Power off circuit system

Abstract

The invention relates to a power-off circuit system. A power-off circuitry for a controller of a process control system is provided. The power-off circuitry comprises: at least one snubber capacitor for buffering sufficient energy to complete a power-off sequence; a power voter configured to select at least one snubber capacitor as an energy source in response to detection of a power failure; a non-volatile memory for holding process data after the detection of the power failure; and logic circuitry configured to coordinate transfer of process data to the non-volatile memory during the power down sequence.

Description

Technical Field

[0001] The present invention relates to a power-off circuit system and method for a process control system. Background Art

[0002] In the field of industrial process automation, controllers are typically provided with power-off functionality that can operate to hold the process values measured immediately before a power failure for reuse upon power-up. One example involves a conveyor belt for loading a ship with bulk materials. When restarting after a power failure, the control application should continue to use exactly the same load count value as before the power failure. As the complexity of process control systems increases, the challenge of implementing power-off functionality in a cost-effective manner becomes more challenging. Summary of the Invention

[0003] To better solve one or more of these problems, in a first aspect of the present invention, a power-off circuit system for a controller of a process control system is provided, the power-off circuit system comprising:

[0004] At least one buffer capacitor for buffering sufficient energy to complete a power-off sequence;

[0005] A power voter configured to select at least one buffer capacitor as an energy source in response to the detection of a power failure;

[0006] A non-volatile memory for holding process data after the detection of a power failure; and

[0007] Logic circuitry configured to coordinate the transfer of process data to the non-volatile memory during the power-off sequence.

[0008] In this way, the power-off circuit system can be implemented using cost-effective, small-sized, and / or readily available components. A battery is not required, and the process control execution task is not hindered by the cyclic storage of data in the non-volatile memory. The data storage time of the process data to be held is effectively infinite. A large amount of data can be held at a moderate hardware cost.

[0009] The power voter may include a plurality of inputs, each input being configured to receive power from a corresponding power source, wherein at least one power source includes at least one capacitor bank. Another power source may include an external power source, such as a cabinet power supply. The power voter may include a plurality of diodes having a common output and connected in a reverse series configuration. The power voter may be configured to select the highest voltage present at the inputs of the power voter to provide to the controller circuitry at the output of the power voter. In this way, the power voter can operate to provide a disturbance-free bridge between the power sources.

[0010] The power-off circuit system may include a DC / DC converter configured to convert an input voltage provided by an external power source into a primary intermediate voltage to supply power to a controller during normal operation. Meanwhile, at least one buffer capacitor provides a secondary intermediate voltage for supplying power to the controller in the event of a failure of the external power source. The level of the secondary intermediate voltage may be selected to be lower than the primary intermediate voltage such that the primary intermediate voltage is selected by a power voter during normal operation. In the event of a power failure, the reduction of the primary intermediate voltage causes the power voter to select the secondary intermediate voltage.

[0011] The power-off circuit system may include a power failure detection circuit system configured to generate a power failure detection signal upon power-off. The power failure detection signal may be used by a logic circuit system to initiate a power-off sequence. In one example, the logic circuit system is configured to directly initiate the power-off sequence in response to receiving the power failure detection signal. In another example, the logic circuit system is configured to directly delay the initiation of the power-off sequence after receiving the power failure detection signal. By delaying the power-off sequence, normal operation can continue for a certain amount of time using the energy from at least one buffer capacitor to bridge a voltage dip from the external power source, thereby enabling the process control system to operate more reliably. The power failure detection circuit system may include a comparator configured to detect that an input voltage provided by the external power source is lower than a predefined threshold voltage level and correspondingly generate the power failure detection signal. In one example, the power failure detection circuit system and / or the comparator form part of the DC / DC converter.

[0012] The power-off circuit system may include a boost converter configured to boost an input voltage provided by the external power source and / or a primary intermediate voltage provided by the DC / DC converter to a higher voltage and supply the higher voltage to at least one capacitor. The power-off circuit system may include a buck converter configured to reduce the higher voltage to a secondary intermediate voltage level for input to a power voter. Boosting to a higher voltage in this way can reduce the necessary size of at least one capacitor.

[0013] The power-off circuit system may include a switch that can be operated by the logic circuit system to cut off power to one or more components during the power-off sequence to conserve energy. Once the logic circuit system has completed coordinating the power-off sequence roll, the components to have power cut off may include the logic circuit system itself. The switch may receive a control signal from the logic circuit system. The control signal may be default-set to turn on the switch.

[0014] The logic circuitry can be configured to coordinate the transfer of process data to a non-volatile memory in a block-wise manner. The logic circuitry can be configured to classify process data for transfer to the non-volatile memory. The logic circuitry can be configured to classify and transfer process data in parallel. The logic circuitry can be configured to transfer a first block of process data to the non-volatile memory while classifying a different second block of process data in parallel to reduce the time and energy costs of data transfer.

[0015] According to a second aspect, there is provided a controller for a process control system, the controller including the power-off circuitry of the first aspect. The controller can be configured to execute a control application for controlling an industrial process. In one example, the logic circuitry of the power-off circuitry can be implemented by the same logic circuitry that executes the control application. The control application can generate process data, which can be obtained or extracted by the controller for retention in the event of a power failure. The controller can be configured to store the process data in a non-volatile storage device for a predetermined amount of time, such as at least one hour after a power failure. The controller can frequently update the process data to be retained during normal operation until a power failure occurs. For example, before writing the process data to a non-volatile storage device (such as F-RAM, M-RAM, or nvSRAM) during a power-off, the controller can periodically place the process data to be retained in a static / dynamic RAM that has an infinite number of write cycles and fast access times.

[0016] According to a third aspect, there is provided a process control system including the power-off circuitry of the first aspect and / or the controller of the second aspect.

[0017] According to a fourth aspect, there is provided an industrial automation system including the power-off circuitry of the first aspect and / or the controller of the second aspect and / or the process control system of the third aspect.

[0018] According to a fifth aspect, there is provided a power-off method. The method includes:

[0019] using at least one buffer capacitor to buffer sufficient energy to complete a power-off sequence;

[0020] selecting at least one buffer capacitor as an energy source in response to detection of a power failure;

[0021] coordinating the transfer of process data to a non-volatile memory during the power-off sequence; and

[0022] retaining the process data in a non-volatile memory after detection of the power failure.

[0023] The method of the fifth aspect may be (at least partially) computer-implemented. Optional features of the first aspect may, with necessary modifications in details, form part of any one of the second to fifth aspects.

[0024] According to the sixth aspect, there is provided a computing system configured to perform the method of the fifth aspect.

[0025] According to the seventh aspect, there is provided a computer program (product) comprising instructions which, when executed by a computing system, cause the computing system to perform the method of the fifth aspect or cause the computing system to perform the method of the fifth aspect.

[0026] According to the eighth aspect, there is provided a computer-readable (storage) medium comprising instructions which, when executed by a computing system, cause the computing system to perform the method of the fifth aspect or cause the computing system to perform the method of the fifth aspect. The computer-readable medium may be transient or non-transient, volatile or non-volatile.

[0027] By "sufficient" is meant that the energy stored in at least one buffer capacitor is at least the amount of energy required for the power-off sequence and preferably greater than the amount of energy necessary for the power-off sequence.

[0028] By "(process) automation system" is meant an industrial plant or a production plant, including one or more pipelines, production lines and / or assembly lines for transforming one or more educts into products and / or assembling one or more components into a final product.

[0029] By "process data" is meant any data related to the production process used by the automation system. In particular, the process data may include process values used in one or more control loops. Usually, during normal operation, such process values are stored in volatile memory. The process data may additionally or alternatively include other data generated and / or used during operation, such as I / O signals, log data, configuration data, management data and / or error counters.

[0030] As used herein, the term "obtain" may include, for example, receiving from another system, device or process; receiving via interaction with a user; loading or retrieving from a storage device or memory; measuring or capturing using a sensor or other data acquisition device.

[0031] As used herein, the term "determine" encompasses a variety of actions and may include, for example, arithmetic operations, calculations, processing, derivation, investigation, finding (e.g., finding in a table, database or another data structure), ascertaining, etc. Moreover, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Moreover, "determine" may include parsing, selecting, picking, establishing, etc.

[0032] The indefinite articles "a" or "an" do not exclude a plurality. Additionally, the articles "a" and "an" as used herein shall generally be construed to mean "one or more", unless otherwise specified or clearly apparent from the context to refer to the singular form.

[0033] Unless otherwise specified or clearly apparent from the context, the phrases "one or more of A, B, and C", "at least one of A, B, and C", and "A, B, and / or C" as used herein are intended to represent all possible permutations of one or more of the listed items. That is, the phrase "A and / or B" means (A), (B), or (A and B), and the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0034] The term "comprising" does not exclude other elements or steps. Additionally, the terms "comprising", "including", "having", etc. may be used interchangeably herein.

[0035] The present invention may include one or more aspects, examples, or features, whether combined or separately, specifically disclosed or not. Any optional feature or sub - aspect of one aspect among the above aspects is suitably applicable to any other aspect.

[0036] The above aspects will become apparent and be elucidated by reference to the specific embodiments provided below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The specific embodiments will now be given by way of example only with reference to the drawings, wherein:

[0038] Figure 1 illustrates a process control system for controlling an industrial process;

[0039] Figure 2 represents Figure 1 a block diagram of a controller of the process control system that uses a capacitor to buffer energy for power failure handling;

[0040] Figure 3 illustrates Figure 1 another example of a controller;

[0041] Figure 4 illustrates an example of a power - off sequence; and

[0042] Figure 5 illustrates yet another example of a power - off sequence rationalized for accelerated execution. DETAILED DESCRIPTION

[0043] Figure 1FIG. illustrates a process control system 100 for controlling an industrial process performed by an automation system (not shown). The process control system 100 includes a plurality of controllers 102-A, 102-B, 102-C, 102-D, collectively referred to as controllers 102, which are physically and communicatively coupled to each other via a mounting terminal unit (MTU) 110 (commonly referred to as a backplane). The controllers 102 are configured to communicate with other components of the automation system, such as field devices or engineering tools described herein. Engineering tools (commonly implemented as software packages) are used to create configuration data for the process control system 100, which can be downloaded to the controllers 102. For such communication, the controllers 102 are provided with Ethernet ports (such as those illustrated at 114) and associated communication interface circuitry. In addition, each of the controllers 102 includes its own network switch.

[0044] Each of the controllers 102 is configured to control a corresponding process performed by the automation system (not shown). The process control system 100 can find applications in any industrial field that requires process automation, such as energy, oil and gas, chemical, petrochemical, etc. By receiving input signals from sensors and instruments and outputting control signals to control plant equipment such as pumps, valves, conveyors, mixers, and heaters, the controllers 102 handle the process control and monitoring of the automation system. Any such sensor, instrument, or plant equipment can form part of one or more field devices. The controllers 102 are configured to execute process control applications to generate control signals based on the input signals. Each control application can include control logic that indicates how the corresponding controller should respond to all input signals with appropriate control signals to maintain the normal operation of the process. In one non-limiting example, the control application conforms to the international standard IEC 61131. Each of the controllers 102 includes logic circuitry configured to execute the corresponding control application. The logic circuitry can include a CPU, MCU, SoC, FPGA, DSP, and / or AI engine, as well as any memory for processing signals. The logic circuitry can also be configured to execute any one or more of the other operations described herein.

[0045] One or more of the controllers 102 are additionally provided with power-off functionality that is capable of operating to hold the process values measured immediately before a power failure for reuse upon power-on. It is desirable to implement the power-off circuitry in a cost-effective manner using small-sized components that are easy to maintain and not subject to usage or transportation constraints.

[0046] According to the present disclosure, the power-down circuitry of controller 102 is implemented using cost-effective components, including at least one buffer capacitor (e.g., a standard capacitor) for buffering sufficient energy to complete a power-down sequence and a non-volatile memory (e.g., an eMMC card or flash memory) for storing application data after the power-down circuitry detects a power failure. During normal operation, at least one capacitor (e.g., a capacitor bank) is charged to a default voltage (e.g., 45V). In the event of a power failure, the energy stored in at least one capacitor is used to move the process data to be retained from the DRAM of controller 102 to the non-volatile storage device. The power-down circuitry may also be configured to perform a power-up sequence after power is restored to continue the execution of the control application, thereby moving the process data retained in the non-volatile storage device back into the DRAM of controller 102.

[0047] Figure 2 is a block diagram illustrating the power-down circuitry 200 of controller 102. It is to be understood that only those components of controller 102 related to power failure handling are illustrated.

[0048] The DC / DC converter 202 receives an input voltage (e.g., 24V) from an external power supply (referred to herein as the cabinet power supply 150), and converts the input voltage to a stable intermediate voltage (e.g., 5.1V), which is referred to as the primary or cabinet-side intermediate voltage. In one non-limiting example, the DC / DC converter includes electrical insulation, current limiters, fuses, and voltage monitoring circuitry.

[0049] The capacitor bank 204 stores energy for power failure handling. In one limiting example, the stored energy is approximately 5 to 10 joules. The charged capacitor bank 204 generates an intermediate voltage (e.g., 5.0V), which is referred to as the secondary or capacitor-side intermediate voltage.

[0050] The power voter 206 selects one of the two intermediate voltages to supply to the circuitry of controller 102, including at least its logic circuitry and memory and optionally certain peripherals. The power voter 206 is configured to select the highest voltage present at the input of the power voter to provide to the controller circuitry. In Figure 2In the illustrated example, the power voter 206 includes two diodes connected in a reverse series configuration. Thus, the power voter 206 is capable of operating to seamlessly bridge a voltage drop in the cabinet-side intermediate voltage (e.g., 5.1V) by selecting the capacitor-side intermediate voltage (e.g., 5.0V). In yet another example, the power voter 206 includes a power FET with low on-resistance to keep the losses due to voltage drop low (e.g., in the mV range). By selecting a capacitor-side intermediate voltage lower than the cabinet-side intermediate voltage, the power-off circuitry system 200 operates in normal operation to supply power to the controller circuitry from the cabinet power supply 150 rather than from the capacitor bank 204.

[0051] In this example, the logic circuitry 208 of the controller 102 includes a central processing unit (CPU) that communicates with a dynamic random access memory (DRAM) 210 via a data bus 212.

[0052] The non-volatile memory 214 provides storage capacity for data to be retained during a power-off. In one example, the non-volatile memory 214 includes an eMMC flash card. The CPU 208 communicates with the non-volatile memory via a data bus 216.

[0053] The power-off sequence performed by the power-off circuitry system 200 is as follows.

[0054] Starting from normal operation in step 1, the energy of the controller 102 is supplied by the cabinet power supply 150. The capacitor bank 204 is charged with sufficient energy to complete the power-off sequence. The CPU 208 executes control applications during each control loop to generate and change process data. At least some of the process data are retention data that will be used for the next control loop or are very important for recording the history of the control applications. The retention data are stored in the DRAM but not necessarily within a linear address range, but rather are scattered across a wide address range of the DRAM.

[0055] Step 2 of the power-off sequence includes detecting a power failure. The DC / DC converter 202 detects that the input voltage has dropped to a certain voltage level, e.g., a critical input voltage at which the DC / DC converter 202 may no longer reliably or safely generate the cabinet-side intermediate voltage, and generates a power failure detection signal. To this end, the DC / DC converter 202 may be provided with a voltage monitor. The power failure detection signal may be low-pass filtered (e.g., about 20 ms) for robustness against fluctuations in the input voltage. The power failure detection signal triggers the CPU 208 to start power failure processing.

[0056] In step 3, normal operation is completed. The CPU 208 ensures that the ongoing controller tasks terminate quickly and that no data inconsistency occurs.

[0057] In step 4, optionally turn off peripheral devices such as Ethernet switches, physical layer components, redundant CPU cores or FPGAs, oscillators, and interfaces to increase the amount of energy stored in capacitors available for storing retention data. By "peripheral device" is meant any component that does not participate in transferring retention data to the non-volatile storage device.

[0058] In step 5, optionally classify the scattered retention data. The retention data scattered in the DRAM 210 is classified and stored in the linear address space of the DRAM 210, which also contains management data for correctly assigning the retention data in order to reconstruct the application when power returns. For data integrity, a CRC checksum can be calculated for segments / blocks of the retention data stored compactly (linearly). To utilize resources more efficiently, hardware-supported checksum calculation can be performed.

[0059] In step 6, the retention data is transferred from the DRAM 210 to the non-volatile memory 214. For example, a block of compactly stored retention data is moved from the DRAM to the non-volatile memory 214 via the data bus 216, which can be a serial bus. Since the data transfer rate between the CPU 208 and the non-volatile memory 214 is limited, regardless of the technology used to implement them, the controller circuitry involved in the transfer must remain powered during this time.

[0060] In step 7, after transferring the retention data, turn off any remaining controller circuitry other than the non-volatile storage device 214. To conserve energy, the CPU 208 can operate a switch to disconnect itself and the DRAM 210 from external power. In the case where the CPU 208 and the DRAM 214 form part of a core or system-on-chip, it may be this component that is turned off. At the same time, the CPU 208 can reset its internal power supply (not shown) in preparation for the power-on sequence performed when external power returns. Additionally or alternatively, the CPU 208 can prepare an external reset circuit that supplies power to the CPU / core when external power returns.

[0061] Accordingly, the power - off sequence is completed by the hold value stored in the non - volatile memory 214, and optionally, data integrity is ensured by one or more error detection and / or correction codes (such as CRC checksum). The non - volatile memory 214 is kept powered by the capacitor bank 204. In one example, the non - volatile memory 214 remains powered for a predetermined amount of time (e.g., 0.5 s) after receiving the last data transfer. During this period, the power consumption of the non - volatile memory 214 is lower than that of the CPU 208, enabling energy savings by separating the power supply to the non - volatile memory 214 from the power supply to the CPU 208.

[0062] In a variant, the data to be held is not directly transferred to the non - volatile memory 214 itself but is first stored in a cache belonging to the non - volatile memory 214, which has a faster access time than the non - volatile memory 214.

[0063] Figure 3 The controller 102 is illustrated including another example of a power - off circuit system 300 according to the present disclosure. The same reference numerals are used to indicate the same components as described with reference to Figure 2 The power - off circuit system 300 differs from the power - off circuit system 200 in the following aspects.

[0064] The boost converter 318 raises the cabinet - side intermediate voltage to a higher level (e.g., 45 V) and supplies this voltage to the capacitor bank 204. Alternatively, the input of the boost converter 318 can be tapped from the input voltage (e.g., 24 V) provided by the cabinet power supply 150. Accordingly, the capacitor bank 204 is charged to a voltage higher than the discharge voltage (e.g., 8 to 9 times higher), which helps to utilize a high proportion of the stored energy. In other words, at the same energy storage conditions, boosting to a higher voltage reduces the necessary size of the capacitor.

[0065] The buck converter 320 reduces the higher capacitor voltage to the aforementioned capacitor - side intermediate voltage (e.g., 5 V).

[0066] The switch 322 can be operated by the CPU 208 to turn off the CPU 208 and the DRAM 210 to save energy. The switch 322 receives a control signal 324 from the CPU 208. After power - on, the control signal 324 is default - set to turn on the switch 322.

[0067] The power - failure detection signal 326 is output by the DC / DC converter 202 to initiate the power - off sequence. The signal 326 indicates that the energy supplied to the controller 102 may no longer be delivered by the external power supply 150. In one example, a comparator is used to detect that the input voltage is lower than a predefined threshold voltage level.

[0068] Example 1

[0069] Figure 4 Illustrates an example of a power-off sequence in which the steps are executed sequentially, with each step starting after the previous step is completed.

[0070] Example 2

[0071] Figure 5 Illustrates yet another example of a power-off sequence that is rationalized for accelerated execution. Figure 5 The sequence of Figure 4 differs from that of Figure 4 in that steps 5 and 6 are executed in parallel rather than serially. In other words, Figure 5 step 6 of

[0072] does not start until step 6 of Figure 3 is completed, and in

[0073] Figure 5 a portion or block of the retained data is sorted in step 5 and then immediately transferred in step 6, while other blocks are sorted in step 5 to save time and energy. The energy savings allow for the use of smaller capacitors.

[0072] In any of the examples described herein, a power-on sequence can be executed when external power returns to restore the retained data. Figure 3 The power-on sequence in the example of

[0073] can start after the boost voltage on the capacitor bank 204 reaches a setpoint voltage, such that the controller 102 is prepared for further power failures. Alternatively, the control application may not generate new retained data until the capacitor bank 204 is fully charged. The lifespan of the restored retained data can be checked to determine if the retained values are still available.

[0074] If implemented in software, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. The computer-readable medium includes computer-readable storage media. The computer-readable storage media can be any available storage media accessible by a computer. By way of example and not limitation, such computer-readable storage media can include flash storage media, RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and optical disk include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk and Blu-ray disk (BD), where disks typically reproduce data magnetically, while optical disks typically reproduce data optically using lasers. Further, propagated signals can be included within the scope of computer-readable storage media. The computer-readable medium also includes communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. For example, a connection can be a communication medium. For example, if software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology such as infrared, radio and microwave are included in the definition of communication media. Combinations of the above should also be included within the scope of computer-readable media.

[0075] The applicant hereby independently discloses each individual feature described herein and any combination of two or more such features, provided that such feature or combination is capable of being carried out based on the present specification as a whole in view of the common general knowledge of those skilled in the art, regardless of whether such feature or combination of features solves any of the problems disclosed herein, and without limiting the scope of the claims. The applicant indicates that various aspects of the invention can consist of any such individual feature or combination of features.

[0076] It must be noted that the embodiments of the present invention are described with reference to different categories. Specifically, some examples are described with reference to methods, while other examples are described with reference to apparatuses. However, those skilled in the art will infer from the description that, unless otherwise notified, any combination between features related to different categories is also considered to be disclosed by this application, in addition to any combination of features belonging to one category. However, all features can be combined to provide synergistic effects, rather than just a simple sum of the features.

[0077] Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered exemplary and not restrictive. The present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and achieved by those skilled in the art by studying the drawings, the disclosure, and the appended claims.

[0078] The fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used advantageously.

[0079] Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A power-off circuit system for a controller in a process control system, the power-off circuit system comprising: At least one buffer capacitor for buffering sufficient energy to complete a power-off sequence; A power voter configured to select the at least one buffer capacitor as an energy source in response to detection of a power failure; A non-volatile memory for holding process data after the detection of the power failure; And A logic circuit system configured to coordinate transfer of the process data to the non-volatile memory during the power-off sequence.

2. The power-off circuit system according to claim 1, wherein the power voter includes a plurality of inputs, each input being configured to receive power from a corresponding power source, wherein at least one of the power sources includes at least one capacitor bank.

3. The power-off circuit system according to claim 2, wherein another of the power sources includes an external power source.

4. The power-off circuit system according to claim 2 or 3, wherein the power voter is configured to select the highest voltage present at the inputs of the power voter to provide at the output of the power voter to power the controller.

5. The power-off circuit system according to any one of the preceding claims, wherein the power voter includes a plurality of diodes having a common output and connected in a reverse series configuration.

6. The power-off circuit system according to any one of the preceding claims, further comprising a DC / DC converter configured to convert an input voltage provided by an external power source into a primary intermediate voltage for powering the controller during normal operation, wherein the at least one buffer capacitor provides a secondary intermediate voltage for powering the controller in the event of a failure of the external power source.

7. The power-off circuit system according to claim 6, wherein the secondary intermediate voltage is selected to be lower than the primary intermediate voltage such that the primary intermediate voltage is selected by the power voter during normal operation, and wherein in the event of a power failure, a reduction in the primary intermediate voltage causes the power voter to select the secondary intermediate voltage.

8. The power-off circuit system according to any one of the preceding claims, further comprising a power failure detection circuit system configured to generate a power failure detection signal at power-off, wherein the power failure detection signal is used by the logic circuit system to initiate the power-off sequence.

9. The power-off circuit system according to any one of the preceding claims, further comprising a boost converter configured to boost an input voltage provided by an external power source and / or a primary intermediate voltage provided by the DC / DC converter to a higher voltage and provide the higher voltage to the at least one capacitor.

10. The power-off circuit system according to claim 9, further comprising a buck converter configured to reduce the higher voltage to a secondary intermediate voltage level for input to the power voter.

11. The power-off circuit system according to any one of the preceding claims further includes a switch, and the switch can be operated by the logic circuit system to cut off the power supply to one or more components during the power-off sequence to save energy.

12. A controller for a process control system, the controller including the power-off circuit system according to any one of the preceding claims.

13. A process control system, including the power-off circuit system according to any one of claims 1 to 11.

14. A power-off method, including: using at least one buffer capacitor to buffer sufficient energy to complete the power-off sequence; selecting the at least one buffer capacitor as an energy source in response to the detection of a power failure; coordinating the transfer of process data to non-volatile memory during the power-off sequence; and holding the process data in non-volatile memory after the detection of the power failure.

15. A computer-readable medium, including instructions that, when executed by a computing system, cause the computing system to perform the method according to claim 14.

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