Digital filter circuit and method of sigma-delta analog-to-digital converter

Abstract

The invention provides a digital filter circuit and method of a sigma-delta analog-to-digital converter. Relates to the technical field of digital decimation filters, and solves the problems that in the prior art, the line decimation rate is single, and output of a first data is delayed. The input data of the sigma-delta analog-to-digital converter is sent to one of the integrator comb filter and the low-delay filter, and the filter receiving the input data is used as a decimation filter; and the decimation filter is used for opening the enabling of the decimation filter according to the configuration information, adjusting the decimation rate of the decimation filter according to the configuration information, and filtering and sampling the input data according to the decimation rate to obtain filter output data. The digital decimation filtering circuit is suitable for the requirements of low time delay and multiple decimation rates, the time delay for outputting the first data can be reduced by selecting the filter path, and the digital decimation filtering with multiple decimation rates and low time delay can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of digital decimation filters, and in particular, to a digital filtering circuit and method for a Σ-Δ analog-to-digital converter. Background Art

[0002] At present, most decimation filters of Σ-Δ analog-to-digital converters adopt CIC (Cascaded integrator–comb) filters. However, the traditional CIC filters have the following problems:

[0003] 1. The decimation rate of the CIC filter is a single decimation rate, and the structure is mostly single. Due to its single decimation rate and fixed structure, the applicable scenarios of the Σ-Δ analog-to-digital converter are relatively single and limited.

[0004] 2. The current CIC filter outputs the first data relatively slowly, and it requires 3 times the decimation rate of clock cycles for the first data.

[0005] 3. The current CIC filter occupies more system resources.

[0006] For the above reasons, a filter and method capable of achieving multiple decimation rates are required for the Σ-Δ analog-to-digital converter. Summary of the Invention

[0007] A brief overview of the present invention is given below to provide a basic understanding of certain aspects of the present invention. It should be understood that this overview is not an exhaustive overview of the present invention. It is not intended to identify the key or important parts of the present invention, nor is it intended to limit the scope of the present invention. Its purpose is merely to present some concepts in a simplified form as a prelude to a more detailed description to be presented later.

[0008] In view of this, in order to solve the above problems, the present invention proposes a digital filtering circuit and method for a Σ-Δ analog-to-digital converter, which can achieve configurable decimation rate and reduce the delay of the first output data.

[0009] The present invention provides a digital filtering circuit for a Σ-Δ analog-to-digital converter, including:

[0010] A main controller, a cascaded integrator–comb filter, and a low-delay filter;

[0011] The main controller is configured to receive configuration information, and according to the configuration information, send the input data of the Σ-Δ analog-to-digital converter to one of the cascaded integrator–comb filter and the low-delay filter, and use the filter that receives the input data as the decimation filter;

[0012] The extraction filter is used to enable the extraction filter according to the configuration information, adjust the extraction rate of the extraction filter according to the configuration information, and filter and sample the input data at the extraction rate to obtain filter output data.

[0013] In a possible implementation, the integrator-comb filter is a third-order integrator-comb filter, and the low-latency filter is a non-recursive filter.

[0014] In a possible implementation, the integrator-comb filter includes: a third-order integrator, a variable extraction rate regulator, and a third-order differentiator connected in sequence;

[0015] For each clock cycle, the third-order integrator performs cascaded integration processing on the input data and outputs third-order accumulated data; the variable extraction rate regulator determines the extraction rate according to the configuration information, samples and transfers the third-order accumulated data at the extraction rate, and outputs intermediate transfer data; the third-order differentiator performs delay processing on the intermediate transfer data and outputs filter output data.

[0016] In a possible implementation, the low-latency filter includes:

[0017] A variable-length shift register, a variable-length Hanning window coefficient controller, a multiplier, and an accumulator. The output end of the variable-length shift register and the output end of the variable-length Hanning window coefficient controller are respectively connected to two input ends of the multiplier, and the output end of the multiplier is connected to the input end of the accumulator;

[0018] For each clock cycle, the variable-length shift register performs shift processing on the input data and outputs shift-processed data; the variable-length Hanning window coefficient controller determines the sampling rate of the Hanning window at intervals according to the configuration information and outputs the Hanning window coefficient; the shift-processed data and the Hanning window coefficient are multiplied by the multiplier and then summed up by the accumulator to output filter output data.

[0019] In a possible implementation, the digital filter circuit further includes a first multiplexer and a second multiplexer;

[0020] The first output end of the integrator-comb filter and the first output end of the low-latency filter are respectively connected to the input ends of the first multiplexer;

[0021] The second output end of the integrator-comb filter and the second output end of the low-latency filter are respectively connected to the input ends of the second multiplexer;

[0022] The first multiplexer is configured to output, according to configuration information, an external observation output data output by the integrator comb filter or an external observation output data output by the low-latency filter as a pulse signal with a pulse width of one clock cycle for obtaining the filter output data.

[0023] The second multiplexer is configured to output, according to configuration information, a quantization voltage value within a reference voltage range from the output data of the integrator comb filter or the output data of the low-latency filter.

[0024] In a second aspect, the present invention further provides a digital filtering method for a Σ-Δ analog-to-digital converter, including:

[0025] Receiving configuration information, and according to the configuration information, sending the input data of the Σ-Δ analog-to-digital converter to one of the integrator comb filter and the low-latency filter, and using the filter that receives the input data as a decimation filter;

[0026] The decimation filter enables the decimation filter according to the configuration information, adjusts the decimation rate of the decimation filter according to the configuration information, and filters and samples the input data at the decimation rate to obtain filter output data.

[0027] In a possible implementation, when the decimation filter is an integrator comb filter, filtering and sampling the input data at the decimation rate to obtain filter output data includes:

[0028] For each clock cycle,

[0029] Performing cascaded integration processing on the input data to output third-order accumulated data;

[0030] Determining the decimation rate according to the configuration information, and sampling and transmitting the third-order accumulated data at the decimation rate to output intermediate transmitted data;

[0031] Performing delay processing on the intermediate transmitted data to output filter output data.

[0032] In a possible implementation, when the decimation filter is a low-latency filter, filtering and sampling the input data at the decimation rate to obtain filter output data includes:

[0033] For each clock cycle,

[0034] Performing shift processing on the input data to output shift-processed data;

[0035] Determining the sampling rate of the Hann window at intervals according to the configuration information, and outputting the Hann window coefficients;

[0036] Multiply the shifted processed data by the Hamming window coefficients, and perform cumulative summation calculation to output the filter output data.

[0037] In a possible implementation, obtaining the filter output data includes:

[0038] According to the configuration information, output a pulse signal with a pulse width of one clock cycle for the external observation output data output by the integrator comb filter or the external observation output data output by the low-latency filter to obtain the filter output data; according to the configuration information, output a quantization voltage value within the reference voltage range for the output data of the integrator comb filter or the output data of the low-latency filter.

[0039] The digital filtering circuit and method of the Σ-Δ analog-to-digital converter of the present invention add a path of FIR filter on the basis of the traditional CIC filter, and adopt a structure of two filters in parallel to balance the requirements for high efficiency or low latency in different scenarios. Multiple decimation rates can be configured in this application, which is applicable to scenarios where the sampling rate of the signal needs to be reduced, and the decimation rate can be controlled through corresponding registers. Further, the Hamming window is used in the FIR filter of this application to prevent spectral leakage, improve the ENOB (Effective number of bits) of the data, and suppress high-frequency and power-frequency interference.

[0040] These and other advantages of the present invention will become more apparent through the following detailed description of the best embodiments of the present invention in conjunction with the accompanying drawings. Description of the Drawings

[0041] The present invention can be better understood by referring to the descriptions given in the following in conjunction with the accompanying drawings, in which the same or similar reference numerals are used in all the drawings to represent the same or similar components. The accompanying drawings, together with the following detailed description, are included in this specification and form a part of this specification, and are used to further illustrate the preferred embodiments of the present invention and explain the principles and advantages of the present invention. In the drawings:

[0042] Figure 1 is a schematic diagram showing the digital filtering circuit of the Σ-Δ analog-to-digital converter according to an embodiment of the present invention;

[0043] Figure 2 is a diagram showing the delay timing diagram according to an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram showing the integrator comb filter according to an embodiment of the present invention;

[0045] Figure 4 is a schematic diagram showing the low-latency filter according to an embodiment of the present invention;

[0046] Figure 5 It is a flowchart showing the digital filtering method of the Σ-Δ analog-to-digital converter according to an embodiment of the present invention.

[0047] Those skilled in the art should understand that the elements in the drawings are shown only for simplicity and clarity, and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the embodiments of the present invention. Detailed implementation manners

[0048] Hereinafter, exemplary embodiments of the present invention will be described in conjunction with the drawings. For clarity and conciseness, not all features of the actual implementation manners are described in the specification. However, it should be understood that many implementation-specific decisions must be made during the development of any such actual implementation to achieve the specific goals of the developer, for example, to comply with those system- and business-related constraints, and such constraints may vary with different implementation manners. In addition, it should be understood that although the development work may be very complex and time-consuming, for those skilled in the art who benefit from the present disclosure, such development work is merely a routine task.

[0049] Here, it should also be noted that, in order to avoid obscuring the present invention with unnecessary details, only the device structures closely related to the solution according to the present invention are shown in the drawings, and other details less related to the present invention are omitted. As Figure 1 shown, an embodiment of the present invention provides a digital filtering circuit for a Σ-Δ analog-to-digital converter, including: a main controller, an integrator-comb filter, and a low-latency filter.

[0050] Among them, the main controller is configured to receive configuration information, and according to the configuration information, send the input data of the Σ-Δ analog-to-digital converter to one of the integrator-comb filter and the low-latency filter, and use the filter that receives the input data as a decimation filter; the decimation filter is configured to enable the decimation filter according to the configuration information, adjust the decimation rate of the decimation filter according to the configuration information, and filter and sample the input data at the decimation rate to obtain filter output data.

[0051] As Figure 1As shown, in the embodiment of the present invention, en is the enable signal, clk is the clock signal, rst is the reset signal, opt is the decimation rate selection signal, and din is the input data of the Σ-Δ analog-to-digital converter. The enable control terminal en of the main controller is connected to the enable terminal en of the integrator comb filter. At the same time, the enable control terminal en of the main controller is connected to the enable terminal en of the low-delay filter through a NOT gate. That is, the enable signals en received by the integrator comb filter and the low-delay filter are opposite. When the integrator comb filter enables, the low-delay filter disables, and when the integrator comb filter disables, the low-delay filter enables. The clock signal output terminal clk and the enable control terminal en of the main controller are respectively connected to the two input terminals of the gated clock unit. The output terminal of the gated clock unit is connected to the clock terminal clk of the integrator comb filter. The clock signal output terminal clk and the enable control terminal en of the main controller are respectively connected to the two input terminals of the gated clock unit through a NOT gate. The output terminal of the gated clock unit is connected to the clock terminal clk of the low-delay filter. That is, the integrator comb filter and the low-delay filter alternately receive the clock signal clk. When the integrator comb filter enables, it can receive the clock signal clk. At this time, the low-delay filter disables and cannot receive the clock signal clk. When the integrator comb filter disables, it cannot receive the clock signal clk. At this time, the low-delay filter enables and can receive the clock signal clk. The reset signal output terminal rst of the main controller is respectively connected to the reset terminal rst of the integrator comb filter and the reset terminal rst of the low-delay filter. The decimation rate selection signal output terminal opt of the main controller is respectively connected to the selection terminal opt of the integrator comb filter and the selection terminal opt of the low-delay filter. The input data terminal din of the main controller is respectively connected to the input data terminal din of the integrator comb filter and the input data terminal din of the low-delay filter.

[0052] The digital filter circuit of the Σ-Δ analog-to-digital converter in the embodiment of the present invention is applied to the digital decimation filtering of the Σ-Δ analog-to-digital converter, as Figure 1As shown, there are two filters, namely the CIC (Cascaded Integrator Comb) filter and the low-latency filter. Optionally, the low-latency filter can be an FIR (Finite Impulse Response) filter. The switching path is selected through the enable signal en. Among them, opt is the decimation rate selection signal, which can adjust the decimation filter to work at different decimation rates. For example, 8 decimation rates can be set with 3 bits, so as to realize that the decimation rate of the decimation filter is configurable. Eight decimation rates of 64, 128, 256, 512, 1024, 2048, 4096, and 8192 can be selected respectively, or eight decimation rates of 2, 4, 8, 16, 32, 64, 128, and 256 can be selected, etc. The decimation rate is controllable through the corresponding register. It is also possible to set 4 decimation rates with 2 bits, or 16 decimation rates with 4 bits, etc.

[0053] In the embodiment of the present invention, different decimation rates are configured for the decimation filter, so that it is applicable to the scenario where the sampling rate of the signal needs to be reduced, and it has a certain inhibitory effect on high-frequency and power-frequency interference.

[0054] As Figure 1 shown, the working process of the digital filter circuit of the Σ-Δ analog-to-digital converter in the embodiment of the present invention is as follows:

[0055] When the digital filter circuit is used for the first time or powered on and restarted, initialization is performed. At this time, wait for the clock to stabilize and the reset has been completed.

[0056] Determine which filter to select as the decimation filter according to the enable signal. For example: when the enable signal is 0, it is determined to select the CIC filter; when the enable signal is 1, it is determined to select the FIR filter. Specifically:

[0057] 1. Wait for the enable signal en input by the main controller to be 0, the CIC filter enters the active state, and the input data of the Σ-Δ analog-to-digital converter enters the CIC filter from the din port;

[0058] 2. Wait for the enable signal en input by the main controller to be 1, the FIR filter enters the active state, and the input data of the Σ-Δ analog-to-digital converter enters the FIR filter from the din port;

[0059] 3. Observe the value of the external output valid. When the value of valid is 1, the multi-bit quantization value of the digital decimation filter is obtained.

[0060] The low-latency filter has a faster response time compared to the CIC filter. As Figure 2As shown, the shaded part represents the output delay of the filter. The CIC filter requires the fourth data to produce a valid output, while the low-delay filter reduces this time to 1 / 3.

[0061] In the embodiments of the present invention, for scenarios with high requirements for time delay, especially scenarios with low time delay requirements in the initial stage of data transmission, the main controller can be configured to use a low-delay filter as the channel for data transmission and processing. For scenarios with low requirements for time delay, especially scenarios without low time delay requirements in the initial stage of data transmission, the main controller can be configured to use an integrator-comb filter as the channel for data transmission and processing.

[0062] In the embodiments of the present invention, the integrator-comb filter is a third-order integrator-comb filter, and the low-delay filter is a non-recursive filter.

[0063] The CIC filter is a digital filter, especially suitable for signal preprocessing during the decimation or interpolation process. It is an efficient digital filter structure and is widely used in communication, signal processing, and multi-stage sampling rate conversion.

[0064] The embodiments of the present invention employ a third-order CIC filter, as Figure 3 shown, the basic structure of the third-order CIC filter is composed of a third-order integrator, a variable decimation rate regulator, and a third-order comb filter in cascade. The third-order CIC filter in the embodiments of the present invention does not require multiplication operations, only addition operations and delay operations. Therefore, the calculation efficiency is very high and it is suitable for implementing systems with high decimation ratios or high interpolation ratios.

[0065] Specifically, for each clock cycle, the third-order integrator performs cascaded integration processing on the input data and outputs third-order accumulated data; the variable decimation rate regulator determines the decimation rate according to the configuration information, samples and transfers the third-order accumulated data according to the decimation rate, and outputs intermediate transfer data; the third-order comb filter performs delay processing on the intermediate transfer data and outputs the filter output data.

[0066] The third-order integrator includes a first-stage integrator, a second-stage integrator, and a third-stage integrator; the third-order comb filter includes a first-stage comb filter, a second-stage comb filter, and a third-stage comb filter.

[0067] For each clock cycle, the third-order CIC filter obtains the input data x(n) of a 1-bit Σ-Δ analog-to-digital converter.

[0068] Input x(n) into the first-stage integrator to obtain the output I1(n), and the output formula is I1(n) = x(n) + x(n - 1);

[0069] Input I1(n) into the second - stage integrator to obtain the output I2(n), and the output formula is I2(n) = I1(n)+I1(n - 1);

[0070] Input I2(n) into the third - stage integrator to obtain the output I3(n), and the output formula is I3(n) = I2(n)+I2(n - 1);

[0071] Perform variable decimation rate on I3(n), configure the decimation rate D, to obtain the output T(n), and the output formula is T(n) = I3(Dn);

[0072] Input T(n) into the first - stage differentiator to obtain the output D1(n), and the output formula is D1(n) = T(n)-T(n - 1);

[0073] Input D1(n) into the second - stage differentiator to obtain the output D2(n), and the output formula is D2(n) = D1(n)-D1(n - 1);

[0074] Input D2(n) into the third - stage differentiator to obtain the output y(n), and the output of the third - order CIC filter is y(n) = D2(n)-D2(n - 1).

[0075] Where n is the serial number of the current clock cycle, and n - 1 is the serial number of the previous clock cycle.

[0076] The FIR (Finite Impulse Response) filter is a digital filter used for multi - rate signal processing, which reduces the sampling rate of the signal through filtering and decimation operations. It is widely used in fields such as communication and audio processing.

[0077] The embodiment of the present invention adopts a first - order CIC filter. The first - order CIC filter can be regarded as a special FIR filter, such as Figure 4 As shown, the serial first - order CIC filter adopted in the embodiment of the present invention includes:

[0078] A variable - length shift register, a variable - length Hanning window coefficient controller, a multiplier, and an accumulator. The output end of the variable - length shift register and the output end of the variable - length Hanning window coefficient controller are respectively connected to the two input ends of the multiplier, and the output end of the multiplier is connected to the input end of the accumulator;

[0079] For each clock cycle, the variable-length shift register shifts the input data and outputs the shifted data; the variable-length Hanning window coefficient controller determines the decimation sampling rate of the Hanning window according to the configuration information and outputs the Hanning window coefficients; the shifted data and the Hanning window coefficients are multiplied by the multiplier and then summed up by the accumulator to output the filter output data.

[0080] The function expression of the first-order CIC filter is:

[0081]

[0082] n is the current clock cycle number, D is the configured decimation rate, and i is a positive integer with a range of 0 to D-1.

[0083] Since a low decimation rate will cause filter spectrum leakage and a low ENOB, in the embodiments of the present invention, based on the FIR filter, a Hanning window is added, and combined with the characteristics of the FIR filter, the FIR filter structure is optimized. Among them, the expression of the Nth-order Hanning window is:

[0084]

[0085] N is the Hanning window length.

[0086] The head and tail values of the Hanning window coefficients gradually tend to 0, and the main lobe width of the Hanning window is twice that of the side lobe. In the embodiments of the present invention, the Hanning window used maximally suppresses spectrum leakage while increasing the frequency. To sum up, the output expression of the filter is:

[0087]

[0088] In the embodiments of the present invention, in order to reduce the burden on the circuit overhead caused by the operation of the Hanning window coefficients, the symmetric characteristics of the Hanning window coefficients are fully utilized, and the Hanning window coefficients with a longer decimation are downsampled to shorter-length Hanning window coefficients. L is the decimation sampling rate:

[0089] ω2(n) = ω1(Ln).

[0090] In this way, a variable-length Hanning window can be realized with a limited number of coefficients.

[0091] For each clock cycle, the decimation rate D is configured, and through downsampling, the Hanning window coefficients are matched; through Figure 4 the serial first-order CIC filter shown, the output value of the filter is calculated.

[0092] In the embodiments of the present invention, both the integrator-comb filter and the low-latency filter are downsampled according to the rate. Therefore, every D clock cycles, a filtered data is output.

[0093] As Figure 1 shown, in an embodiment of the present invention, the digital filter circuit further includes a first multiplexer and a second multiplexer;

[0094] A first output end of the integral comb filter and a first output end of the low-delay filter are respectively connected to an input end of the first multiplexer;

[0095] A second output end of the integral comb filter and a second output end of the low-delay filter are respectively connected to an input end of the second multiplexer;

[0096] The first multiplexer is configured to output a pulse signal with a pulse width of one clock cycle based on configuration information, where the pulse signal is either the external observation output data output by the integral comb filter or the external observation output data output by the low-delay filter, for obtaining the filter output;

[0097] The second multiplexer is configured to output a quantization voltage value within the reference voltage range based on configuration information, where the quantization voltage value is either the output data of the integral comb filter or the output data of the low-delay filter.

[0098] In a second aspect, as Figure 5 shown, the present invention further provides a digital filtering method for a Σ-Δ analog-to-digital converter, where the method includes:

[0099] S100. Receive configuration information, and based on the configuration information, send the input data of the Σ-Δ analog-to-digital converter to either the integral comb filter or the low-delay filter, and use the filter that receives the input data as the decimation filter;

[0100] S200. The decimation filter enables the decimation filter according to the configuration information, adjusts the decimation rate of the decimation filter according to the configuration information, and filters and samples the input data at the decimation rate to obtain filter output data.

[0101] In an embodiment of the present invention, in step S200, when the decimation filter is an integral comb filter, filtering and sampling the input data at the decimation rate to obtain filter output data includes:

[0102] For each clock cycle,

[0103] Perform cascaded integration processing on the input data to output third-order accumulated data;

[0104] Determine the decimation rate according to the configuration information, and sample and transfer the third-order accumulated data at the decimation rate to output intermediate transfer data;

[0105] Perform delay processing on the intermediate transmitted data and output the filter output data.

[0106] In the embodiment of the present invention, in step S200, when the decimation filter is a low-latency filter, filtering and sampling the input data according to the decimation rate to obtain the filter output data includes:

[0107] For each clock cycle,

[0108] Perform shift processing on the input data and output the shift-processed data;

[0109] Determine the skip-point sampling rate of the Hanning window according to the configuration information and output the Hanning window coefficients;

[0110] Multiply the shift-processed data by the Hanning window coefficients, and perform cumulative summation calculation to output the filter output data.

[0111] In the embodiment of the present invention, in step S200, obtaining the filter output data includes:

[0112] According to the configuration information, output a pulse signal with a pulse width of one clock cycle for the external observation output data output by the integrator-comb filter or the external observation output data output by the low-latency filter to obtain the filter output; according to the configuration information, output a quantization voltage value within the reference voltage range for the output data of the integrator-comb filter or the output data of the low-latency filter.

[0113] The digital filtering circuit and method of the Σ-Δ analog-to-digital converter in the embodiment of the present application can better meet the requirements of low latency and multiple decimation rates, and can reduce the delay of the first output data by selecting the filter path, and can implement digital decimation filtering with multiple decimation rates and low latency.

[0114] It should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0115] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0116] In this application, unless otherwise clearly specified and defined, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0117] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application also intends to include these changes and modifications.

[0118] Although the present invention has been described based on a limited number of embodiments, those skilled in the art in this technical field will understand, based on the above description, that other embodiments can be conceived within the scope of the present invention thus described. In addition, it should be noted that the language used in this specification is mainly selected for readability and teaching purposes, rather than for the purpose of explaining or limiting the subject matter of the present invention. Therefore, many modifications and changes are obvious to those of ordinary skill in this technical field without departing from the scope and spirit of the appended claims. For the scope of the present invention, the disclosure of the present invention is illustrative rather than restrictive, and the scope of the present invention is defined by the appended claims.

Claims

1. A digital filtering circuit of a Σ-Δ analog-to-digital converter, characterized in that, Comprising: A main controller, an integrator comb filter, and a low-latency filter; The main controller is configured to receive configuration information, and based on the configuration information, send the input data of the Σ-Δ analog-to-digital converter to one of the integrator comb filter and the low-latency filter, and use the filter that receives the input data as the decimation filter; The decimation filter is configured to enable the decimation filter according to the configuration information, adjust the decimation rate of the decimation filter according to the configuration information, and filter and sample the input data at the decimation rate to obtain the filter output data.

2. The digital filter circuit according to claim 1, wherein The integrator comb filter is a third-order integrator comb filter, and the low-latency filter is a non-recursive filter.

3. The digital filter circuit according to claim 2, wherein The integrator comb filter includes: a third-order integrator, a variable decimation rate regulator, and a third-order differentiator connected in sequence; For each clock cycle, the third-order integrator performs cascaded integration processing on the input data and outputs third-order accumulated data; the variable decimation rate regulator determines the decimation rate according to the configuration information, samples and transfers the third-order accumulated data at the decimation rate, and outputs intermediate transfer data; the third-order differentiator performs delay processing on the intermediate transfer data and outputs the filter output data.

4. The digital filter circuit according to claim 2, wherein, The low-latency filter includes: A variable-length shift register, a variable-length Hanning window coefficient controller, a multiplier, and an accumulator. The output end of the variable-length shift register and the output end of the variable-length Hanning window coefficient controller are respectively connected to two input ends of the multiplier, and the output end of the multiplier is connected to the input end of the accumulator; For each clock cycle, the variable-length shift register performs shift processing on the input data and outputs shift-processed data; the variable-length Hanning window coefficient controller determines the sampling rate of the Hanning window at intervals according to the configuration information and outputs the Hanning window coefficient; the shift-processed data and the Hanning window coefficient are multiplied by the multiplier and then summed up by the accumulator to output the filter output data.

5. The digital filter circuit according to claim 1, wherein It further includes a first multiplexer and a second multiplexer; The first output end of the integrator comb filter and the first output end of the low-latency filter are respectively connected to the input ends of the first multiplexer; The second output end of the integrator comb filter and the second output end of the low-latency filter are respectively connected to the input ends of the second multiplexer; The first multiplexer is configured to output a pulse signal with a pulse width of one clock cycle based on the configuration information, either the external observation output data output by the integrator comb filter or the external observation output data output by the low-latency filter, for obtaining the filter output data; The second multiplexer is configured to output a quantization voltage value within the reference voltage range, either the output data of the integrator comb filter or the output data of the low-latency filter, based on the configuration information.

6. A digital filtering method for a Σ-Δ analog-to-digital converter, characterized in that, Comprising: Receive configuration information, and according to the configuration information, send the input data of the Σ-Δ analog-to-digital converter to one of the integrator-comb filter and the low-latency filter, and use the filter that receives the input data as the decimation filter; The decimation filter enables the decimation filter according to the configuration information, adjusts the decimation rate of the decimation filter according to the configuration information, and filters and samples the input data at the decimation rate to obtain the filter output data.

7. The digital filtering method according to claim 6, characterized in that When the decimation filter is an integrator-comb filter, filtering and sampling the input data at the decimation rate to obtain the filter output data includes: For each clock cycle, Perform cascaded integration processing on the input data and output third-order accumulated data; Determine the decimation rate according to the configuration information, sample and transfer the third-order accumulated data at the decimation rate, and output intermediate transfer data; Perform delay processing on the intermediate transfer data and output the filter output data.

8. The digital filtering method according to claim 6, wherein When the decimation filter is a low-latency filter, filtering and sampling the input data at the decimation rate to obtain the filter output data includes: For each clock cycle, Perform shift processing on the input data and output the shift-processed data; Determine the skip-point sampling rate of the Hanning window according to the configuration information and output the Hanning window coefficients; Multiply the shift-processed data by the Hanning window coefficients and perform cumulative summation calculation to output the filter output data.

9. The digital filtering method according to any one of claims 6-8, characterized in that, Obtaining the filter output data includes: According to the configuration information, output a pulse signal with a pulse width of one clock cycle from the external observation output data output by the integrator-comb filter or the external observation output data output by the low-latency filter to obtain the filter output data; According to the configuration information, output a quantization voltage value within the reference voltage range from the output data of the integrator-comb filter or the output data of the low-latency filter.

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