Manufacturing method of PNM IGBT
Through hard mask technology and multiple etching processes, the problem of tabletop control in PNM IGBT manufacturing is solved, high-precision and low-cost production is achieved, and large-scale production of PNM IGBT is promoted.
Patent Information
- Application Number
- CN202510509754.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-22
- Publication Date
- 2025-07-25
AI Technical Summary
The prior art is difficult to accurately control the mesa width and shape of a PNM IGBT on the micron or even nanoscale, making it difficult to manufacture and to ensure the perpendicularity of the sidewall of the top channel area.
Hard mask technology is used to combine multiple etching technology of anisotropic and isotropic etching to achieve high-precision mesa control through a low-cost way, including making a hard mask dielectric layer on the surface of the substrate, lithography and etching, anisotropic etching and isotropic etching to form a bottom mesa.
It realizes high-precision countertop control, reduces production costs, improves the manufacturing feasibility of PNM IGBT devices, and can be mass-produced on a 6-inch semiconductor production line, replacing the 8-inch production line, and improving economic benefits.
Smart Images
Figure CN120379283A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of IGBTs, and particularly to a manufacturing method of a PNM IGBT. Background Art
[0002] PNM (Partially Narrow Mesa) IGBT, that is, a partially narrow mesa insulated gate bipolar transistor, as a new generation of power semiconductor devices, due to its excellent high-frequency characteristics, high voltage withstand capacity, low on-state loss, and excellent thermal stability, shows great application potential in fields such as new energy vehicles, high-efficiency energy conversion systems, smart grids, and industrial automation control. However, the manufacturing process of PNM IGBT is a highly complex and technically difficult task, and its challenges are mainly reflected in its processing and manufacturing.
[0003] The core feature of PNM IGBT lies in its unique "partially narrow mesa" design, which requires precise control of the mesa width and shape at the micron or even nanometer scale to achieve optimized electric field distribution and current density management. If a direct etching process is used, its manufacturing difficulty is extremely high, and it is difficult to ensure the sidewall perpendicularity of the top channel region.
[0004] Therefore, the existing technology has defects and needs to be improved. Summary of the Invention
[0005] The technical problem to be solved by the present invention is: to provide a manufacturing method of a PNM IGBT, aiming to overcome the limitations in the existing technology and achieve low-cost, high-efficiency, and high-precision production of PNM IGBT.
[0006] The technical solution of the present invention is as follows: to provide a manufacturing method of a PNM IGBT, including the following steps.
[0007] S1: Use an N-type doped substrate, and the substrate is a single crystal substrate or an epitaxial wafer.
[0008] S2: Fabricate a hard mask dielectric layer on the surface of the substrate, and the thickness of the mask dielectric layer ≥ 0.1 μm.
[0009] S3: Perform photolithography and etching on the surface of the hard mask dielectric to make an operation window appear on the hard mask dielectric layer, so that the surface of the substrate at the operation window is exposed.
[0010] S4: Perform anisotropic etching on the exposed substrate at the operation window, and the depth of the etched trench ≥ 1.8 μm, and the width of the etched trench ≥ 0.8 μm.
[0011] S5: Deposit a dielectric on the surface of the trench to deposit a trench dielectric layer on the surface of the trench; the thickness of the trench dielectric layer ≥ 0.05 μm.
[0012] S6: Etch the bottom surface of the trench dielectric layer to expose the lower surface of the trench.
[0013] S7: Use isotropic etching on the exposed lower surface of the trench to etch out a bottom mesa, and the bottom mesa is spherical or quasi-spherical.
[0014] S8: Remove the hard mask dielectric layer and the remaining trench dielectric layer to obtain a substrate with a bottom mesa.
[0015] S9: Fabricate a PNM IGBT on the substrate with a bottom mesa using a standard IGBT process.
[0016] Furthermore, the materials of the hard mask dielectric layer and the trench dielectric layer are one or a combination of at least two of silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride.
[0017] Furthermore, the hard mask dielectric layer is a multi-layer structure.
[0018] Furthermore, the fabrication method of the hard mask dielectric layer and the trench dielectric layer adopts any one of LPCVD, PECVD, and ALD.
[0019] Furthermore, the width of the spacing between adjacent trenches is 2.0 ± 0.2 μm - 20.0 ± 2.0 μm; the spacing between two adjacent bottom mesas in the substrate with a bottom mesa is between 0.3 μm and 10 μm.
[0020] Furthermore, in step S6, during the etching of the bottom surface of the trench dielectric layer, over-etching is performed to ensure that the trench dielectric layer at the bottom of the trench is etched clean without residue. Preferably, over-etch by 0.1 μm.
[0021] Furthermore, dry etching is used to etch out the trench, and dry etching is used to etch the bottom surface of the trench dielectric layer.
[0022] Furthermore, wet etching is used for isotropic etching, and a mixed solution of hydrofluoric acid and nitric acid is selected as the etching solution for isotropic etching.
[0023] Wet etching is used to remove the hard mask dielectric layer and the remaining trench dielectric layer.
[0024] Adopting the above solution, the present invention provides a manufacturing method of a PNM IGBT, which adopts an innovative technological process and combines multiple etching techniques of anisotropic and isotropic etching through a hard mask technology. It can achieve high-precision mesa control in a low-cost manner, enabling better production control and large-scale mass production. Through the method of the present invention, the feasibility of manufacturing PNM IGBT devices is significantly improved. With its excellent performance and extremely high cost-effective advantages, it has opened up a new path for the development of manufacturing processes in the field of power semiconductor devices. IGBT products with narrow channel widths can be manufactured through a 6-inch semiconductor production line, replacing the micro-trench IGBT products of an 8-inch production line, achieving lower manufacturing costs and higher economic benefits. Brief Description of the Drawings
[0025] Figure 1 Schematic diagram of the N-type doped substrate of the present invention;
[0026] Figure 2 Schematic diagram of the substrate for making the operation window;
[0027] Figure 3 Schematic diagram of the substrate after anisotropic etching;
[0028] Figure 4 Schematic diagram of the substrate after depositing the trench dielectric layer;
[0029] Figure 5 Schematic diagram of the substrate after etching the bottom surface of the trench dielectric layer;
[0030] Figure 6 Schematic diagram of the substrate after isotropic etching;
[0031] Figure 7 Schematic diagram of the substrate with a bottom mesa;
[0032] Figure 8 Schematic diagram of the PNM IGBT. Detailed Description of the Preferred Embodiments
[0033] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0034] The present invention provides a manufacturing method of a PNM IGBT, including the following steps.
[0035] S1: Refer to Figure 1 , and use an N-type doped substrate, where the substrate is a single crystal substrate or an epitaxial wafer; in this embodiment, a 90-ohm doped single crystal or epitaxial silicon material is selected.
[0036] S2: Refer to Figure 2, a hard mask dielectric layer is fabricated on the surface of the substrate, and the thickness of the mask dielectric layer is ≥ 0.1 μm; in this embodiment, the hard mask dielectric layer is a two-layer structure of a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is on the surface of the silicon dioxide layer; that is, the hard mask dielectric layer is a multi-layer structure.
[0037] S3: Lithography and etching are performed on the surface of the hard mask dielectric to form an operation window in the hard mask dielectric layer, exposing the surface of the substrate at the operation window; in this embodiment, silicon dioxide and silicon nitride dielectric thin films can be deposited by CVD to form a hard mask, and then lithography and etching are carried out to make an operation window appear in the hard mask dielectric layer, exposing the surface of the substrate at the operation window.
[0038] S4: Refer to Figure 3 , perform anisotropic etching on the exposed substrate at the operation window, the depth of the etched trench is ≥ 1.8 μm, and the width of the etched trench is ≥ 0.8 μm. In this embodiment, by dry etching, trenches with a width of 1 μm and a depth of 2 μm are etched on the substrate surface, and the spacing between adjacent two trenches is 4 μm.
[0039] S5: Refer to Figure 4 , deposit a dielectric layer on the surface of the trench to deposit a trench dielectric layer on the surface of the trench; the thickness of the trench dielectric layer is ≥ 0.05 μm; in this embodiment, the trench dielectric layer is a silicon nitride layer. In this embodiment, a silicon nitride layer is deposited by CVD.
[0040] S6: Refer to Figure 5 , etch the bottom surface of the trench dielectric layer to expose the lower surface of the trench; perform back etching by dry etching, and the etching thickness over-etch to ensure that the silicon nitride layer at the bottom of the trench is etched clean without residue.
[0041] S7: Refer to Figure 6 , isotropically etch the exposed lower surface of the trench to etch out a bottom mesa, and the bottom mesa is spherical or quasi-spherical; in this embodiment, silicon etching is carried out by wet etching, and the etching solution is a mixed solution of hydrofluoric acid and nitric acid for isotropic etching. A spherical or quasi-spherical morphology is formed at the bottom, and the spacing between adjacent spherical or quasi-spherical morphologies is 1 μm, thereby reducing the mesa spacing from 4 μm to 1 μm.
[0042] S8: Refer to Figure 7 , remove the hard mask dielectric layer and the remaining trench dielectric layer to obtain a substrate with a bottom mesa; remove the silicon nitride layer and the silicon dioxide layer of the hard mask layer by wet etching.
[0043] S9: Fabricate a PNM IGBT on a substrate with a bottom mesa using the standard IGBT process. The standard IGBT process includes: gate oxide, poly backfill, P+ implantation, N+ implantation, via etching, via implantation, metal layer, passivation layer, thinning, backside implantation, and backside metal. Finally, a PNM IGBT is obtained, and its specific structure is as shown in Figure 8 .
[0044] Gate Oxide process. Purpose: To form the gate insulating layer and control the conduction and cutoff of the channel. The process is as follows:
[0045] Cleaning: The wafer surface needs to be thoroughly cleaned to remove impurities to ensure the quality of the gate oxide layer.
[0046] Thermal oxidation: Grow a silicon dioxide layer by dry oxidation at a temperature of about 1000°C. The gate oxide grown by dry oxidation is denser and more reliable.
[0047] Lithography and etching: Define the gate oxide region through a mask and retain the oxide layer in the medium / low voltage device region.
[0048] Special treatment: For trench gates, sacrificial oxidation is required to remove the etched damage layer, and then the gate oxide layer is regrown. The thickness at the bottom may be uneven due to limited oxygen diffusion.
[0049] Poly (Polysilicon) backfill. Purpose: To form the gate conductive structure. The process is as follows:
[0050] Trench etching: Form a vertical trench structure by dry etching.
[0051] Poly deposition: Chemically vapor deposit (CVD) polysilicon to ensure no voids in the trenches.
[0052] Etchback: Remove the excess Poly on the surface and only retain the gate structure in the trenches.
[0053] P+ implantation, N+ implantation
[0054] P+ implantation: Used to form the P-body (base region) and the collector region.
[0055] Implant ions: Boron (B) or Aluminum (Al), dose 1E13 - 1E14 cm -2 .
[0056] Well push: High-temperature annealing to activate impurities and control the junction depth.
[0057] N+ implantation: Used for the emitter (source region) and the field stop layer.
[0058] Implant ions: Phosphorus (P) or Arsenic (As), dose 1E14 - 5E20 cm -2 .
[0059] Contact Hole Etching and Implantation
[0060] Hole Etching: Metal contact holes are formed through photolithography and dry / wet etching, with a depth that needs to penetrate from the emitter to the base region.
[0061] Hole Implantation: Heavy doping (such as B or As) is carried out below the holes to reduce contact resistance and improve ohmic contact performance.
[0062] Metal Layer and Passivation
[0063] Metal Layer:
[0064] Front Metal: Aluminum or copper is sputtered (1 - 5 μm thick), and electrode interconnections are formed through photolithography.
[0065] Back Metal: After thinning, a stack of aluminum / titanium / nickel / silver (AL / Ti / Ni / Ag) is sputtered to improve thermal conductivity and solderability.
[0066] Passivation Layer: Silicon nitride (SiN) or silicon dioxide (SiO2) is deposited, with a thickness Protect the chip surface and prevent moisture.
[0067] Wafer Thinning, and available thinning processes such as:
[0068] Mechanical Grinding: The wafer is thinned from the initial thickness (such as 800 μm) to the target value (such as 50 - 300 μm).
[0069] Chemical Mechanical Polishing (CMP): Optimize the surface flatness and reduce stress.
[0070] Back Implantation, including: Buffer Layer and Collector.
[0071] Buffer Layer: Hydrogen or phosphorus is implanted to form an N+ field stop layer to optimize the electric field distribution.
[0072] Collector: Boron is implanted to form a P+ layer, and after activation, hole injection is achieved.
[0073] Back Metallization: Evaporate or sputter multiple layers of metal (such as Ti / Ni / Ag) to improve the conductivity of the collector and the welding reliability.
[0074] In summary, the present invention provides a manufacturing method for a PNM IGBT, which adopts an innovative process. Through a hard mask technology and a multiple etching technology combining anisotropic and isotropic etching, high-precision mesa control can be achieved in a low-cost manner, enabling better production control and large-scale mass production. Through the method of the present invention, the feasibility of manufacturing PNM IGBT devices is significantly improved. With its excellent performance and extremely high cost performance advantages, it has opened up a new path for the development of manufacturing processes in the field of power semiconductor devices. IGBT products with a narrow channel width can be manufactured through a 6-inch semiconductor production line, replacing the micro-groove IGBT products of an 8-inch production line, achieving lower manufacturing costs and higher economic benefits.
[0075] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A manufacturing method of a PNM IGBT, characterized in that, It includes the following steps: S1: Use an N-type doped substrate, and the substrate is a single crystal substrate or an epitaxial wafer; S2: Fabricate a hard mask dielectric layer on the surface of the substrate, and the thickness of the mask dielectric layer ≥ 0.1 μm; S3: Perform photolithography and etching on the surface of the hard mask dielectric to make an operation window appear on the hard mask dielectric layer, so that the surface of the substrate at the operation window is exposed; S4: Perform anisotropic etching on the substrate exposed at the operation window, the depth of the etched trench ≥ 1.8 μm, and the width of the etched trench ≥ 0.8 μm; S5: Deposit a dielectric on the surface of the trench to deposit a trench dielectric layer on the trench surface; The thickness of the trench dielectric layer ≥ 0.05 μm; S6: Etch the bottom surface of the trench dielectric layer to expose the lower surface of the trench; S7: Use isotropic etching to etch the exposed lower surface of the trench to etch out a bottom mesa, and the bottom mesa is spherical or quasi-spherical; S8: Remove the hard mask dielectric layer and the remaining trench dielectric layer to obtain a substrate with a bottom mesa; S9: Fabricate a PNM IGBT on the substrate with a bottom mesa using a standard IGBT process.
2. The manufacturing method of a PNM IGBT according to claim 1, characterized in that, The materials of the hard mask dielectric layer and the trench dielectric layer are one or a combination of at least two of silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride.
3. The manufacturing method of a PNM IGBT according to claim 2, characterized in that, The hard mask dielectric layer is a multi-layer structure.
4. The manufacturing method of a PNM IGBT according to claim 1, characterized in that, The fabrication methods of the hard mask dielectric layer and the trench dielectric layer adopt any one of LPCVD, PECVD, and ALD.
5. The manufacturing method of a PNM IGBT according to claim 1, characterized in that, The width of the adjacent trench spacing is 2.0 ± 0.2 μm - 20.0 ± 2.0 μm; the spacing between two adjacent bottom mesas in the substrate with a bottom mesa is between 0.3 μm and 10 μm.
6. The manufacturing method of a PNM IGBT according to claim 1, characterized in that, In step S6, during the etching of the bottom surface of the trench dielectric layer, over-etching is performed to ensure that the trench dielectric layer at the bottom of the trench is etched clean without residue.
7. The manufacturing method of a PNM IGBT according to claim 6, characterized in that, Over-etch by 0.1 μm.
8. The manufacturing method of a PNM IGBT according to claim 1, characterized in that, Dry etching is used to etch the trench, and dry etching is used to etch the bottom surface of the trench dielectric layer.
9. The manufacturing method of a PNM IGBT according to claim 1, characterized in that, Wet etching is used for isotropic etching, and the etching solution is selected as a mixed solution of hydrofluoric acid and nitric acid for isotropic etching.
10. The manufacturing method of a PNM IGBT according to claim 1, characterized in that, Wet etching is used to remove the hard mask dielectric layer and the remaining trench dielectric layer.