Integrated circuit providing power gating and method of designing same

Abstract

An integrated circuit providing power gating and a method of designing the same are disclosed. The integrated circuit includes a device disposed on a substrate; a first back-side pattern and a second back-side pattern, the second back-side pattern extending parallel to the first back-side pattern in the first direction, the first back-side pattern and the second back-side pattern disposed in the back-side wiring layer under the substrate and configured to receive a first power supply voltage provided to the device; and a third backside pattern extending in the first direction between the first backside pattern and the second backside pattern and configured to receive a source power supply voltage, in which at least one of the devices is configured to provide or block a first power supply voltage based on the source power supply voltage.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0010998, filed with the Korean Intellectual Property Office on January 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] An apparatus and method consistent with example embodiments relate to integrated circuits, and more particularly, to an integrated circuit providing power gating and a method of designing an integrated circuit. Background Art

[0003] To reduce power consumption of an integrated circuit, power gating may be used to cut off power supply to a block included in the integrated circuit when the block is not in use. Due to the demand for high integration and the development of semiconductor processes, the width, pitch, and / or height of wirings in the integrated circuit may be reduced, and the influence of parasitic elements of the wirings may increase. In addition, when high parasitic elements occur in power gating, a high IR drop may occur, and devices included in the block may not operate normally due to a reduced power supply voltage. Summary of the Invention

[0004] One or more example embodiments provide an integrated circuit and a method of designing an integrated circuit, the integrated circuit providing power gating with a reduced influence of parasitic elements.

[0005] According to an aspect of the present disclosure, there is provided an integrated circuit including: devices disposed on a substrate; a first backside pattern and a second backside pattern extending parallel to each other in a first direction, the first backside pattern and the second backside pattern being disposed in a backside wiring layer below the substrate and configured to receive a first power supply voltage supplied to the devices; and a third backside pattern extending in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and configured to receive a source power supply voltage, wherein at least one of the devices is configured to provide or block the first power supply voltage from the source power supply voltage.

[0006] According to another aspect of the present disclosure, there is provided an integrated circuit including a plurality of units, including: at least one power gating unit configured to provide or block a first power supply voltage supplied to the plurality of units from a source power supply voltage; a first backside pattern and a second backside pattern extending parallel to each other in a first direction, the first backside pattern and the second backside pattern being disposed in a backside wiring layer below the substrate and configured to receive the first power supply voltage; and a third backside pattern extending in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and configured to receive the source power supply voltage.

[0007] According to another aspect of the present disclosure, a method of manufacturing an integrated circuit including a plurality of cells is provided, including: laying out at least one power gating cell configured to provide or block a first power voltage from a source power voltage to the plurality of cells; laying out a first backside pattern and a second backside pattern that extend parallel to each other in a first direction, the first backside pattern and the second backside pattern being disposed in a backside wiring layer below a substrate and configured to receive the first power voltage; and laying out a third backside pattern that extends in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and is configured to receive the source power voltage.

[0008] According to another aspect of the present disclosure, an integrated circuit may include: a plurality of target circuits; a plurality of power gating cells configured to receive a source power voltage and, based on a power control signal, apply the power voltage to active target circuits among the plurality of target circuits and block the power voltage from being applied to inactive target circuits among the plurality of target circuits; a first backside wiring pattern extending along a longitudinal boundary of a first row and configured to receive the power voltage; a second backside wiring pattern extending along a longitudinal boundary of a second row and configured to receive the power voltage; and a third backside wiring pattern disposed between the first backside wiring pattern and the second backside wiring pattern and configured to receive the source power voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1A and Figure 1B is a diagram showing a layout of an integrated circuit according to some embodiments.

[0011] Figures 2A to 2D is a diagram showing an example of a device according to some embodiments.

[0012] Figure 3 is a block diagram showing an integrated circuit according to one or more embodiments.

[0013] Figure 4 is a diagram showing a layout of an integrated circuit according to one or more embodiments.

[0014] Figure 5 is a diagram showing a layout of an integrated circuit according to one or more embodiments.

[0015] Figure 6A and Figure 6B is a diagram showing a layout of an integrated circuit according to one or more embodiments.

[0016] Figure 7 is a diagram showing the layout of an integrated circuit according to one or more embodiments.

[0017] Figures 8A to 8C is a diagram showing the layout of an integrated circuit according to some embodiments.

[0018] Figure 9 is a diagram showing the layout of an integrated circuit according to one or more embodiments.

[0019] Figure 10 is a diagram showing the layout of an integrated circuit according to one or more embodiments.

[0020] Figure 11A and 11B is a diagram showing the layout of an integrated circuit according to one or more embodiments.

[0021] Figure 12 is a diagram showing the layout of an integrated circuit according to one or more embodiments.

[0022] Figure 13 is a flowchart showing a method of manufacturing an integrated circuit according to one or more embodiments.

[0023] Figure 14 is a flowchart showing a method of designing an integrated circuit according to one or more embodiments.

[0024] Figure 15 is a flowchart showing a method of designing an integrated circuit according to one or more embodiments.

[0025] Figure 16 is a block diagram showing a system-on-chip (SoC) according to one or more embodiments.

[0026] Figure 17 is a block diagram showing a computing system including a memory storing a program according to one or more embodiments. Detailed Description

[0027] Example embodiments are described in more detail below with reference to the accompanying drawings.

[0028] In the following description, even in different drawings, the same reference numerals are used for the same elements. Matters defined in the description (such as detailed configurations and elements) are provided to assist in a comprehensive understanding of example embodiments. However, it is apparent that example embodiments can be practiced without those specific defined matters. In addition, since well-known functions or configurations would obscure the description with unnecessary detail, they are not described in detail.

[0029] Although terms such as "first", "second", etc. may be used to describe various elements, such elements are not necessarily limited to the above terms. The above terms may be used only to distinguish one element from another.

[0030] Figure 1A and Figure 1B is a diagram showing the layout of an integrated circuit according to some embodiments Figure 10 of 10a and 10b. Figure 1A is the layout Figure 10 a plan view of a and a cross-sectional view of a taken along the line X1-X1', and Figure 10 a cross-sectional view of a taken along the line X1-X1', and Figure 1B is the layout Figure 10 b plan view of b and a cross-sectional view of b taken along the line Y1-Y1'. Figure 10 b cross-sectional view of b taken along the line Y1-Y1'.

[0031] Here, the X-axis direction and the Y-axis direction may be referred to as the first direction and the second direction, respectively, and the Z-axis direction may be referred to as the vertical direction or the third direction. The plane including the X-axis and the Y-axis may be referred to as the horizontal plane. A component disposed in the +Z direction with respect to another component may be referred to as being above the other component, and a component disposed in the -Z direction with respect to another component may be referred to as being below the other component. In addition, the area of a component may refer to the size occupied by the component on a surface parallel to the horizontal plane, and the width of a component may refer to the length in a direction perpendicular to the direction in which the component extends. A surface exposed in the +Z direction may be referred to as the top surface, a surface exposed in the -Z direction may be referred to as the bottom surface, and a surface exposed in the ±X direction or the ±Y direction may be referred to as the side surface. In the drawings, only some layers may be shown for ease of illustration, and even if a via connecting a top pattern and a bottom pattern is located below the top pattern, the via may be shown for ease of understanding. In addition, a pattern including a conductive material (such as a pattern of a wiring layer) may be referred to as a conductive pattern or may be simply referred to as a pattern.

[0032] An integrated circuit may include semiconductor devices (such as transistors) disposed on a substrate SUB. Examples of semiconductor devices disposed on the substrate SUB will be described below with reference to Figures 2A to 2D In addition, an integrated circuit may include a wiring pattern extending above an element and a wiring pattern extending below the substrate SUB. For example, as shown in Figure 1A shown in, the layout Figure 10a may include a wiring pattern (e.g., M11) extending in the front-side wiring layer M1 above the substrate SUB, and a wiring pattern (e.g., BM11) extending in the back-side wiring layer BM1 below the substrate SUB. In some embodiments, the wiring pattern extending below the substrate SUB may be used to supply power to the device. Thus, the back-side pattern for supplying power to the device may be referred to as a back-side power rail. Since the pattern extends below the substrate SUB, available wiring resources can be increased in the front-side wiring layer, and the integrated circuit may have a reduced area and / or an efficient structure. In particular, when the back-side pattern is used for power supply, a power supply voltage that does not drop due to a reduced IR drop can be provided to the device.

[0033] Referring to Figure 1A , the cloth Figure 10 a may include a gate (or gate electrode) extending in the Y-axis direction and an active pattern AP extending in the X-axis direction. For example, as Figure 1A shown, a p-channel field-effect transistor (PFET) active pattern and an n-channel field-effect transistor (NFET) active pattern may extend in the X-axis direction and may intersect a gate extending in the Y-axis direction. Source / drain SD may be formed on both sides of the gate, and a channel may be formed between the source / drain SD. The first back-side pattern BM11 may extend in the back-side wiring layer BM1 along the X-axis direction, and a back-side interlayer dielectric (BILD) may be disposed between the back-side patterns in the back-side wiring layer BM1. In some embodiments, the first back-side pattern BM11 may supply a negative power supply voltage to the NFET.

[0034] The cloth Figure 10 a may include a through-silicon via (TSV, or through-silicon via) penetrating the substrate SUB between the pattern of the back-side wiring layer and the pattern of the front-side wiring layer. For example, as Figure 1A shown, the first through-silicon via TSV1 may extend from the top surface of the first back-side pattern BM11 to the bottom surface of the first front-side pattern M11. Thus, the first front-side pattern M11 and the first back-side pattern BM11 may be (electrically) connected to each other through the first through-silicon via TSV1.

[0035] The first front-side surface pattern M11 can be connected to the first source / drain SD1 through the first contact CA1. Thus, the first source / drain SD1 of the NFET can receive a negative power supply voltage from the first back-side pattern BM11 through the first through-silicon via TSV1, the first front-side pattern M11, and the first contact CA1. Additionally, the first front-side pattern M11 can be connected to the second source / drain SD2 through the second contact CA2. Thus, the second source / drain SD2 of the NFET can receive a negative power supply voltage from the second back-side pattern BM12 through the first through-silicon via TSV1, the first front-side pattern M11, and the second contact CA2. In some embodiments, vias can be additionally arranged between the first front-side pattern M11 and the first contact CA1 and / or between the first front-side pattern M11 and the first through-silicon via TSV1.

[0036] Referring Figure 1B , the layout Figure 10 b can include a gate extending in the Y-axis direction and an active pattern extending in the X-axis direction. For example, as Figure 1B shown, the PFET active pattern and the NFET active pattern can extend in the X-axis direction and intersect with the gate extending in the Y-axis direction. Source / drains SD can be formed on both sides of the gate, and a channel can be formed between the source / drains SD. The first back-side pattern BM11 and the second back-side pattern BM12 can extend along the X-axis direction in the back-side wiring layer BM1, and the back-side interlayer dielectric BILD can be arranged between the first back-side pattern BM11 and the second back-side pattern BM12. In some embodiments, the first back-side pattern BM11 can supply a positive power supply voltage to the PFET, and the second back-side pattern BM12 can supply a negative power supply voltage to the NFET.

[0037] The layout Figure 10 b can include back-side contacts BC that penetrate the substrate SUB between the source / drains SD and the patterns of the back-side wiring layer. For example, as Figure 1B shown, the first back-side contact BC1 can extend from the top surface of the first back-side pattern BM11 to the bottom surface of the first source / drain SD1. Thus, the first source / drain SD1 of the PFET can receive a positive power supply voltage from the first back-side pattern BM11 through the first back-side contact BC1. Additionally, the second back-side contact BC2 can extend from the top surface of the second back-side pattern BM12 to the bottom surface of the second source / drain SD2. Thus, the second source / drain SD2 of the NFET can receive a negative power supply voltage from the second back-side pattern BM12 through the second back-side contact BC2. As Figure 1B shown, the first front-side pattern M11 can be connected to the second source / drain SD2 through the first contact CA1.

[0038] Power gating may refer to removing unnecessary power consumption by blocking the power supply to a specific block included in an integrated circuit when the block is not in use. For example, when the block is in use or active, a power supply voltage may be provided from a power supply to devices included in the block. Conversely, when the block is not in use or inactive, the power supply voltage from the power supply may be blocked or cut off. As shown in the accompanying drawings, power gating may be implemented using a structure in which power is supplied through a pattern of a backside wiring layer. Power gating according to an embodiment of the present disclosure may reduce or minimize IR drop and enable devices to receive a stable power supply voltage consistently. Therefore, power gating may enhance the reliability of an integrated circuit.

[0039] Figures 2A to 2D is a diagram showing an example of a device according to some embodiments. For example, Figure 2A shows a fin field-effect transistor (FinFET) 20a, Figure 2B shows a gate-all-around field-effect transistor (GAAFET) 20b, Figure 2C shows a multi-bridge-channel field-effect transistor (MBCFET) 20c, and Figure 2D shows a vertical field-effect transistor (VFET) 20d. For ease of illustration, Figures 2A to 2C shows that one of two source / drain regions is removed, and Figure 2D shows a cross-sectional view of the VFET 20d taken by a plane parallel to the plane formed by the Y-axis and the Z-axis and passing through the channel CH of the VFET 20d.

[0040] Referring to Figure 2A , the FinFET 20a may include a fin-shaped active pattern extending in the X-axis direction between shallow trench isolation (STI) and a gate G extending in the Y-axis direction. Source / drain SD may be formed on both sides of the gate G, and thus, the source and the drain may be spaced apart from each other in the X-axis direction. An insulating film may be formed between the channel CH and the gate G. In some embodiments, the FinFET 20a may be formed of a plurality of active patterns spaced apart from each other in the X-axis direction and the gate G.

[0041] Referring to Figure 2B , the GAAFET 20b may include active patterns (specifically, nanowires) extending in the X-axis direction and spaced apart from each other in the Z-axis direction. The GAAFET 20b may also include a gate G extending in the Y-axis direction. Source / drain SD may be formed on both sides of the gate G, and thus, the source and the drain may be spaced apart from each other in the X-axis direction. An insulating film may be formed between the channel CH and the gate G. Note that the number of nanowires included in the GAAFET 20b is not limited to Figure 2B the number shown in

[0042] Referring toFigure 2C , the MBCFET 20c may include active patterns (specifically, nanosheets) extending in the X-axis direction and spaced apart from each other in the Z-axis direction. The MBCFET 20c may also include a gate G extending in the Y-axis direction. Source / drain SDs may be formed on both sides of the gate G, and thus, the source and the drain may be spaced apart from each other in the X-axis direction. An insulating film may be formed between the channel CH and the gate G. Note that the number of nanosheets included in the MBCFET 20c is not limited to Figure 2C the number shown in

[0043] Referring to Figure 2D , the VFET 20d includes a top source / drain T_SD and a bottom source / drain B_SD, which are spaced apart from each other in the Z-axis direction and have a channel CH therebetween. The VFET 20d may include a gate G surrounding the outer periphery of the channel CH between the top source / drain T_SD and the bottom source / drain B_SD. An insulating film may be formed between the channel CH and the gate G.

[0044] Hereinafter, an integrated circuit including the FinFET 20a or the MBCFET 20c will be mainly described, but note that the devices included in the integrated circuit are not limited to Figures 2A to 2D the examples of

[0045] Figure 3 is a block diagram showing an integrated circuit 30 according to one or more embodiments. Referring to Figure 3 , the integrated circuit 30 may include a power gating unit 31 and a functional block 32. In some embodiments, the power gating unit 31 may be considered as a part of the functional block 32.

[0046] Integrated circuit 30 may include cells. The cells may be standardized logic cells (e.g., logic gates (AND, OR, NOT), flip-flops, multiplexers, and other basic logic operations) included in the layout of the integrated circuit, and may be referred to as standard cells. The cells may include transistors and may be configured to perform predefined functions. In the integrated circuit, the cells may be arranged in rows. For example, the cells may be aligned and arranged in multiple rows extending along a first direction. The cells laid out in one row may be referred to as single-height cells, and the cells laid out in two or more consecutive rows may be referred to as multi-height cells.

[0047] Function block 32 may operate based on a positive power supply voltage VDD and a negative power supply voltage VSS. For example, function block 32 may include multiple cells, the multiple cells may receive the positive power supply voltage VDD and the negative power supply voltage VSS, and may include devices that operate based on the power supplied according to the positive power supply voltage VDD and the negative power supply voltage VSS.

[0048] Power gating unit 31 may be a circuit component in integrated circuit 30 for managing power consumption by selectively disconnecting the power supply to a specific part of integrated circuit 30 when the specific part is not in use. Power consumption management may be achieved by using a switch (e.g., a transistor) that controls the connection between the power supply and a target circuit block (e.g., function block 32) by using a power control signal (e.g., a power-off signal PD). Specifically, power gating unit 31 may receive the power-off signal PD and may include a switch SW that is turned on or off according to the power-off signal PD. For example, switch SW may be turned on in response to a deactivated power-off signal PD and may supply a positive power supply voltage VDD based on a source power supply voltage VDDG to function block 32. Thus, function block 32 may operate in an active mode and may be referred to as an active function block or an active target circuit block. Additionally, switch SW may be turned off in response to an activated power-off signal PD and may block the positive power supply voltage VDD based on the source power supply voltage VDDG. Thus, function block 32 may be set to a power-saving mode, and the power consumption may be eliminated by function block 32. Function block 32 in the power-saving mode may be referred to as an inactive function block or an inactive target circuit block. The source power supply voltage VDDG may be received from outside integrated circuit 30, or may be generated by integrated circuit 30 from a voltage received from outside integrated circuit 30.

[0049] In some embodiments, the switch SW may include at least one transistor. For example, the switch SW may include a PFET including a gate receiving a power-off signal PD, a source receiving a source power supply voltage VDDG, and a drain generating a positive power supply voltage VDD. In some embodiments, in order to reduce the on-resistance of the switch SW, the switch SW may include a plurality of PFETs connected in parallel to each other. In some embodiments, the integrated circuit 30 may include a plurality of power gating units. Hereinafter, as shown in FIG. 3 , a power gating unit 31 providing a positive power supply voltage VDD from a source power supply voltage VDDG will be mainly described, but it is noted that some embodiments are not limited thereto. For example, the integrated circuit 30 may include a power gating unit that controls a negative power supply voltage VSS and includes at least one NFET.

[0050] Figure 4 4 is a diagram showing a layout 40 of an integrated circuit according to one or more embodiments. For example, Figure 4 The pattern of the backside wiring layer BM1 and the power gating cell C40 is shown. Figure 1A and Figure 1B As described above, the pattern of the backside wiring layer BM1 can be used to provide a positive power voltage and a negative power voltage to the device.

[0051] Reference Figure 4 , the layout 40 may include a first backside pattern BM11, a second backside pattern BM12, and a third backside pattern BM13 extending along the X-axis direction in the backside wiring layer BM1. Figure 4 As shown in , the first backside pattern BM11 may extend in the X-axis direction along the (longitudinal) boundary of the first row R1, the second backside pattern BM12 may extend in the X-axis direction along the (longitudinal) boundary between the first row R1 and the second row R2, and the third backside pattern BM13 may extend in the X-axis direction along the (longitudinal) boundary of the second row R2. A positive power supply voltage VDD may be applied to the first backside pattern BM11 and the third backside pattern BM13, and a source power supply voltage VDDG may be applied to the second backside pattern BM12 between the first backside pattern BM11 and the third backside pattern BM13.

[0052] Layout 40 may include power gating cell C40. Figure 3As described above, the power gating unit C40 can provide or block the positive power supply voltage VDD based on the source power supply voltage VDDG. The power gating unit C40 can be continuously arranged in the first row R1 and the second row R2 extending in the X-axis direction, and can be a multi-height unit. The power gating unit C40 can receive the source power supply voltage VDDG from the second backside pattern BM12, and provide the positive power supply voltage VDD to the first backside pattern BM11 and the third backside pattern BM13 or block the positive power supply voltage VDD. For example, the source power supply voltage VDDG provided from outside the integrated circuit can be applied to the second backside pattern BM12, and the power gating unit C40 can receive the source power supply voltage VDDG applied to the second backside pattern BM12. In addition, the first backside pattern BM11 and the third backside pattern BM13 can be electrically connected to the units included in the layout 40, and the units can receive the positive power supply voltage VDD from the power gating unit C40 through the first backside pattern BM11 and / or the third backside pattern BM13.

[0053] Figure 5 is a diagram showing a layout 50 of an integrated circuit according to one or more embodiments. As Figure 5 shown, the layout 50 can include a first backside pattern BM11, a second backside pattern BM12, a third backside pattern BM13, a fourth backside pattern BM14, a fifth backside pattern BM15, a sixth backside pattern BM16, and a seventh backside pattern BM17 of the backside wiring layer BM1, as well as a first power gating unit C51, a second power gating unit C52, a third power gating unit C53, and a fourth power gating unit C54. In some embodiments, Figure 5 each of the first power gating unit C51, the second power gating unit C52, the third power gating unit C53, and the fourth power gating unit C54 can correspond to Figure 4 the power gating unit C40.

[0054] The first backside pattern BM11, the second backside pattern BM12, the third backside pattern BM13, the fourth backside pattern BM14, the fifth backside pattern BM15, the sixth backside pattern BM16, and the seventh backside pattern BM17 can extend parallel to each other in the X-axis direction in the backside wiring layer BM1. For example, as Figure 5As shown, the first dorsal pattern BM11, the second dorsal pattern BM12, the third dorsal pattern BM13, the fourth dorsal pattern BM14, the fifth dorsal pattern BM15, the sixth dorsal pattern BM16, and the seventh dorsal pattern BM17 can extend in the X-axis direction along the boundaries of the first row R1, the second row R2, the third row R3, the fourth row R4, the fifth row R5, and the sixth row R6. The positive power supply voltage VDD can be applied to the first dorsal pattern BM11, the third dorsal pattern BM13, the fifth dorsal pattern BM15, and the seventh dorsal pattern BM17, the negative power supply voltage VSS can be applied to the second dorsal pattern BM12 and the sixth dorsal pattern BM16, and the source power supply voltage VDDG can be applied to the fourth dorsal pattern BM14. As Figure 5 shown, the dorsal patterns corresponding to the positive power supply voltage VDD and the dorsal patterns corresponding to the negative power supply voltage VSS can be alternately arranged, while the fourth dorsal pattern BM14 can receive the source power supply voltage VDDG instead of the negative power supply voltage VSS under the first power gating unit C51, the second power gating unit C52, the third power gating unit C53, and the fourth power gating unit C54.

[0055] The first power gating unit C51, the second power gating unit C52, the third power gating unit C53, and the fourth power gating unit C54 can be arranged continuously. For example, as Figure 5 shown, the first power gating unit C51, the second power gating unit C52, the third power gating unit C53, and the fourth power gating unit C54 can be arranged continuously in the third row R3 and the fourth row R4. As referred to above Figure 4 The first power gating unit C51, the second power gating unit C52, the third power gating unit C53, and the fourth power gating unit C54 can each provide the positive power supply voltage VDD to the third dorsal pattern BM13 and the fifth dorsal pattern BM15 or block the positive power supply voltage VDD, and the positive power supply voltage VDD comes from the source power supply voltage VDDG received from the fourth dorsal pattern BM14. The first power gating unit C51, the second power gating unit C52, the third power gating unit C53, and the fourth power gating unit C54 can correspond to switches connected in parallel between the source power supply voltage VDDG and the positive power supply voltage VDD, so that the on-resistance of the power gating can be reduced.

[0056] Figure 6A and Figure 6B are diagrams showing the layouts 60a and 60b of an integrated circuit according to one or more embodiments. For example, Figure 6A and Figure 6B show the first end unit C61 and the second end unit C62 arranged adjacent to the power gating unit. In some embodiments, the end unit can be as described below with reference to Figure 8CThe described power tap unit (PTC) is adjacently arranged. Figure 6A and Figure 6B Descriptions redundant to the above description with reference to the accompanying drawings are omitted.

[0057] Referring to Figure 6A , layout 60a may include a first backside pattern BM11, a second backside pattern BM12, a third backside pattern BM13, and a first end unit C61. The first backside pattern BM11, the second backside pattern BM12, and the third backside pattern BM13 may extend in the X-axis direction, and the second backside pattern BM12 may include a first partial backside pattern BM12_1 and a second partial backside pattern BM12_2 that are spaced apart from each other in the X-axis direction. As Figure 6A shown, a positive power supply voltage VDD may be applied to the first backside pattern BM11 and the third backside pattern BM13, a negative power supply voltage VSS may be applied to the first partial backside pattern BM12_1, and a source power supply voltage VDDG may be applied to the second partial backside pattern BM12_2. Accordingly, the power gating unit may be arranged on the right side of the first end unit C61 (i.e., adjacent to the second partial backside pattern BM12_2) in the first row R1 and the second row R2. Additionally, the backside pattern to which the negative power supply voltage VSS is applied may extend in the X-axis direction along the boundary adjacent to the left side of the first end unit C61 in the first row R1 and the second row R2 (i.e., the first partial backside pattern BM12_1).

[0058] Referring to Figure 6B , layout 60b may include a first backside pattern BM11, a second backside pattern BM12, a third backside pattern BM13, and a second end unit C62. The first backside pattern BM11, the second backside pattern BM12, and the third backside pattern BM13 may extend in the X-axis direction, and the second backside pattern BM12 may include a first partial backside pattern BM12_1 and a second partial backside pattern BM12_2 that are spaced apart from each other in the X-axis direction. As Figure 6B shown, a positive power supply voltage VDD may be applied to the first backside pattern BM11 and the third backside pattern BM13, a source power supply voltage VDDG may be applied to the first partial backside pattern BM12_1, and a negative power supply voltage VSS may be applied to the second partial backside pattern BM12_2. Accordingly, the power gating unit may be arranged on the left side of the second end unit C62 (i.e., adjacent to the first partial backside pattern BM12_1) in the first row R1 and the second row R2. Additionally, the backside pattern to which the negative power supply voltage VSS is applied may extend in the X-axis direction along the boundary adjacent to the right side of the second end unit C62 in the first row R1 and the second row R2 (i.e., the second partial backside pattern BM12_2).

[0059] Figure 7is a diagram showing a layout 70 of an integrated circuit according to one or more embodiments. As Figure 7 shown, the layout 70 may include a first backside pattern BM11, a second backside pattern BM12, a third backside pattern BM13, a fourth backside pattern BM14, a fifth backside pattern BM15, a sixth backside pattern BM16, and a seventh backside pattern BM17 in a backside wiring layer BM1, as well as a first cell C71, a second cell C72, a third cell C73, and a fourth cell C74. Figure 7 Descriptions redundant with the above description with reference to the drawings are omitted.

[0060] The first backside pattern BM11, the second backside pattern BM12, the third backside pattern BM13, the fourth backside pattern BM14, the fifth backside pattern BM15, the sixth backside pattern BM16, and the seventh backside pattern BM17 may extend parallel to each other in the X-axis direction in the backside wiring layer BM1. For example, as Figure 7 shown, the first backside pattern BM11, the second backside pattern BM12, the third backside pattern BM13, the fourth backside pattern BM14, the fifth backside pattern BM15, the sixth backside pattern BM16, and the seventh backside pattern BM17 may extend in the X-axis direction along the boundaries of the first row R1, the second row R2, the third row R3, the fourth row R4, the fifth row R5, and the sixth row R6. A positive power supply voltage VDD may be applied to the first backside pattern BM11, the third backside pattern BM13, the fifth backside pattern BM15, and the seventh backside pattern BM17, and a negative power supply voltage VSS may be applied to the second backside pattern BM12 and the sixth backside pattern BM16. The fourth backside pattern BM14 may include a first partial backside pattern BM14_1, a second partial backside pattern BM14_2, and a third partial backside pattern BM14_3 aligned in the X-axis direction. A negative power supply voltage VSS may be applied to the first partial backside pattern BM14_1 and the third partial backside pattern BM14_3, and a source power supply voltage VDDG may be applied to the second partial backside pattern BM14_2.

[0061] The first cell C71, the second cell C72, the third cell C73, and the fourth cell C74 may be arranged continuously in the X-axis direction in the third row R3 and the fourth row R4. Each of the second cell C72 and the third cell C73 may be a power-gated cell and may correspond, for example, to Figure 4 the power-gated cell C40. The first cell C71 and the fourth cell C74 may be end cells and may correspond, for example, to Figure 6A the first end cell C61 and Figure 6B the second end cell C62, respectively. As Figure 7As shown, the second part of the backside pattern BM14_2 to which the source power supply voltage VDDG is applied may terminate respectively below the first cell C71 and the fourth cell C74. Additionally, the first part of the backside pattern BM14_1 and the third part of the backside pattern BM14_3 to which the negative power supply voltage VSS is applied may terminate respectively below the first cell C71 and the fourth cell C74. Accordingly, in the region where the power gating cells are laid out, the backside pattern to which the source power supply voltage VDDG is applied can replace the backside pattern to which the negative power supply voltage VSS is applied. In some embodiments, different from that shown in Figure 7 the end cells may be laid out on both sides of a power gating cell, or the end cells may be laid out on both sides of more than two consecutively laid out power gating cells.

[0062] Figures 8A to 8C FIGS. 80a, 80b, and 80c are diagrams showing the layout of an integrated circuit according to some embodiments. For example, Figures 8A to 8C show layouts 80a, 80b, and 80c each including a structure in which the backside pattern and the front side pattern are connected to each other through through-silicon vias TSVs that penetrate the substrate as described above with reference to Figure 1A . Hereinafter, Figures 8A to 8C the redundant description therebetween will be omitted.

[0063] Referring to Figure 8A , the backside patterns may extend parallel to each other in the X-axis direction in the backside wiring layer. The positive power supply voltage VDD, the negative power supply voltage VSS, or the source power supply voltage VDDG may be applied to the backside patterns, and the power gating cells may be laid out on the backside patterns to which the source power supply voltage VDDG is applied. For example, as Figure 8A shown, the cells C01, C03, C04, C05, C07, C08, C09, C11, C18, C20, C21, C22, C24, C25, C26, and C28 laid out on the backside patterns to which the source power supply voltage VDDG is applied may correspond to the power gating cells.

[0064] The front side patterns may extend parallel to each other in the X-axis direction in the front side wiring layer. For example, as Figure 8A shown, the front side patterns may extend in the X-axis direction along the backside patterns (e.g., along the boundaries of the rows). The front side patterns may similarly receive the positive power supply voltage VDD, the negative power supply voltage VSS, or the source power supply voltage VDDG applied to the underlying backside patterns. To this end, layout 80a may include such a cell (i.e., a power tap cell PTC): the cell includes through-silicon vias TSVs that extend in the Z-axis direction between the backside pattern and the front side pattern. For example, as Figure 8AAs shown, the units C02, C06, C10, C12, C13, C14, C15, C16, C17, C19, C23, and C27 may each include a through-silicon via (TSV) and be arranged and aligned in the Y-axis direction. The following may be referred to Figure 9 to describe a cross-sectional view of the unit C02, which is a power tap unit PTC, taken along the line Y2 - Y2'. As will be referred to below Figure 12 The power gating unit can supply the positive power supply voltage VDD to the front-side pattern from the source power supply voltage VDDG applied to the front-side pattern, or block the positive power supply voltage VDD.

[0065] Referring to Figure 8B , the back-side patterns may extend parallel to each other in the X-axis direction in the back-side wiring layer. The positive power supply voltage VDD, the negative power supply voltage VSS, or the source power supply voltage VDDG may be applied to the back-side patterns, and the power gating unit may be disposed on the back-side pattern to which the source power supply voltage VDDG is applied. For example, as Figure 8B shown, the units C01, C03, C05, C07, C09, C11, C18, C20, C22, C24, C26, and C28 disposed on the back-side pattern to which the source power supply voltage VDDG is applied may correspond to the power gating units.

[0066] The front-side patterns may extend parallel to each other in the X-axis direction in the front-side wiring layer. For example, as Figure 8B shown, the front-side patterns may extend in the X-axis direction along the back-side patterns (e.g., along the boundaries of the rows). The front-side patterns may similarly receive the positive power supply voltage VDD, the negative power supply voltage VSS, or the source power supply voltage VDDG applied to the underlying back-side patterns. To this end, the layout 80b may include such units (i.e., the power tap units PTC) that contain through-silicon vias (TSVs) extending in the Z-axis direction between the back-side patterns and the front-side patterns. For example, as Figure 8B shown, the units C02, C04, C06, C08, C10, C12, C13, C14, C15, C16, C17, C19, C21, C23, C25, and C27 may each include a through-silicon via (TSV). Compared with Figure 8A the layout 80a, Figure 8B the layout 80b may further include the power tap units PTC C04, C08, C21, and C25 that include only one through-silicon via (TSV). As will be referred to below Figure 12 The power gating unit can supply the positive power supply voltage VDD to the front-side pattern from the source power supply voltage VDDG applied to the front-side pattern, or block the positive power supply voltage VDD.

[0067] Referring to Figure 8C, the dorsal patterns may extend parallel to each other in the X-axis direction in the dorsal wiring layer. A positive power supply voltage VDD, a negative power supply voltage VSS, or a source power supply voltage VDDG may be applied to the dorsal patterns, and a power gating unit may be arranged on the dorsal pattern to which the source power supply voltage VDDG is applied. For example, as shown in Figure 8C , the units C03, C04, C05, C18, C19, and C20 arranged on the dorsal pattern to which the source power supply voltage VDDG is applied may correspond to the power gating unit.

[0068] The front-side patterns may extend parallel to each other in the X-axis direction in the front-side wiring layer. For example, as shown in Figure 8C , the front-side patterns may extend in the X-axis direction along the dorsal patterns (e.g., extend along the boundaries of the rows). The front-side patterns may similarly receive the positive power supply voltage VDD, the negative power supply voltage VSS, or the source power supply voltage VDDG applied to the underlying dorsal patterns. To this end, the layout 80c may include such units (i.e., power tap units PTC): the units include through-silicon vias TSVs extending in the Z-axis direction between the dorsal patterns and the front-side patterns. For example, as shown in Figure 8C , the units C02, C06, C08, C09, C10, C11, C12, C13, C14, C15, C17, and C21 may respectively include through-silicon vias TSVs and be aligned and arranged in the Y-axis direction. As will be described below with reference to Figure 12 , the power gating unit may supply the positive power supply voltage VDD from the source power supply voltage VDDG applied to the front-side patterns to the front-side patterns, or block the positive power supply voltage VDD. The layout 80c may include end units. For example, the units C01 and C16 may correspond to the Figure 6A first end unit C61 in Figure 6B , and the units C07 and C22 may correspond to the

[0069] Figure 9 is a diagram showing a layout 90 of an integrated circuit according to one or more embodiments. For example, Figure 9 shows a cross-sectional view of the layout 80a of Figure 8A taken along the line Y2 - Y2'. It will be explained below with reference to Figure 8A Figure 9 .

[0070] Referring to Figure 9 ​, the first backside pattern BM11, the second backside pattern BM12, and the third backside pattern BM13 may extend in the X-axis direction in the backside wiring layer BM1. The first frontside pattern M11, the second frontside pattern M12, and the third frontside pattern M13 may extend in the X-axis direction in the frontside wiring layer M1. The source power supply voltage VDDG may be applied to the second backside pattern BM12, and the second through-silicon via TSV2 may penetrate the substrate SUB from the top surface of the second backside pattern BM12 and extend to the bottom surface of the second frontside pattern M12. Thus, as will be described below with reference to Figure 12 , the power gating unit (e.g., Figure 8A 's C03) may receive the source power supply voltage VDDG through the second frontside pattern M12 and output the positive power supply voltage VDD to the first frontside pattern M11 and the third frontside pattern M13 of the frontside pattern. The first through-silicon via TSV1 may pass through the substrate SUB from the top surface of the first backside pattern BM11 and extend to the bottom surface of the first frontside pattern M11. Thus, the positive power supply voltage VDD may be applied to the first backside pattern BM11. Additionally, the third through-silicon via TSV3 may pass through the substrate SUB from the top surface of the third backside pattern BM13 and extend to the bottom surface of the third frontside pattern M13. Thus, the positive power supply voltage VDD may be applied to the third backside pattern BM13.

[0071] Figure 10 is a diagram showing the layout 100 of an integrated circuit according to one or more embodiments. For example, Figure 10 shows the layout 100 including the power gating unit C100, and the power gating unit C100 includes the backside contacts as described above with reference to Figure 1B . As shown in Figure 10 , the layout 100 may include the first backside pattern BM11, the second backside pattern BM12, the third backside pattern BM13, and the power gating unit C100.

[0072] The first backside pattern BM11, the second backside pattern BM12, and the third backside pattern BM13 may extend in the X-axis direction. A positive power supply voltage VDD may be applied to the first backside pattern BM11 and the third backside pattern BM13, and a source power supply voltage VDDG may be applied to the second backside pattern BM12. The power gating unit C100 may be sequentially arranged in the first row R1 and the second row R2. The power gating unit C100 may include a gate G101 extending in the Y-axis direction and may include a first PFET active pattern AP1 and a second PFET active pattern AP2 extending in the X-axis direction. Accordingly, the power gating unit C100 may include a first PFET formed by the gate G101 and the first PFET active pattern AP1 and a second PFET formed by the gate G101 and the second PFET active pattern AP2. In some embodiments, the power gating unit may include two or more gates and may include more than two transistors.

[0073] The first PFET may include a drain connected to the first backside pattern BM11 through a backside contact and a source connected to the second backside pattern BM12 through a backside contact. Additionally, the second PFET may include a source connected to the second backside pattern BM12 through a backside contact and a drain connected to the third backside pattern BM13 through a backside contact. A cross-sectional view taken along line X2-X2' will be described below, and a cross-sectional view taken along line X3-X3' will be described below with reference to Figure 11A and a cross-sectional view taken along line X3-X3' will be described below with reference to Figure 11B

[0074] Figure 11A and Figure 11B are diagrams showing layouts 110a and 110b of an integrated circuit according to one or more embodiments. For example, Figure 11A shows a cross-sectional view of layout 100 taken along line X2-X2' of Figure 10 , and Figure 11B shows a cross-sectional view of layout 100 taken along line X3-X3' of Figure 10 . That is, Figure 11A and Figure 11B show cross-sectional views of the first PFET included in the power gating unit C100 of Figure 10 taken at different positions.

[0075] Refer to Figure 11A, the first PFET active pattern AP1 may extend in the X-axis direction and intersect the gate G101. The first source / drain SD1 and the second source / drain SD2 may be disposed on both sides of the gate G101. The first backside pattern BM11 may extend in the X-axis direction, and the first backside contact BC1 may extend from the top surface of the first backside pattern BM11 to the bottom surface of the second source / drain SD2. Thus, the drain of the first PFET may be connected to the first backside pattern BM11, and the positive power supply voltage VDD may be applied to the first backside pattern BM11.

[0076] Referring to Figure 11B , the first PFET active pattern AP1 may extend in the X-axis direction and intersect the gate G101. The first source / drain SD1 and the second source / drain SD2 may be disposed on both sides of the gate G101. The second backside contact BC2 may extend from the top surface of the second backside pattern BM12 to the bottom surface of the first source / drain SD1. Thus, the source of the first PFET may be connected to the second backside pattern BM12, and the source power supply voltage VDDG may be applied to the source of the first PFET.

[0077] Figure 12 is a diagram showing the layout 120 of an integrated circuit according to one or more embodiments. For example, as referred to above Figures 8A to 8C above, Figure 12 shows the layout 120 including the power gating unit C120, and the power gating unit C120 receives the source power supply voltage VDDG from one front-side pattern and provides the positive power supply voltage VDD to two front-side patterns. As Figure 12 shown, the layout 120 may include the first backside pattern BM11, the second backside pattern BM12, the third backside pattern BM13, and the power gating unit C120.

[0078] The first backside pattern BM11, the second backside pattern BM12, and the third backside pattern BM13 may extend in the X-axis direction. The positive power supply voltage VDD may be applied to the first backside pattern BM11 and the third backside pattern BM13, and the source power supply voltage VDDG may be applied to the second backside pattern BM12. Additionally, the first front-side pattern M11, the second front-side pattern M12, and the third front-side pattern M1 may extend in the X-axis direction. As referred to above Figures 8A to 8C and Figure 9 above, the first front-side pattern M11, the second front-side pattern M12, and the third front-side pattern M13 may be connected to the first backside pattern BM11, the second backside pattern BM12, and the third backside pattern BM13 respectively through the silicon vias.

[0079] The power gating unit C120 may be sequentially arranged in the first row R1 and the second row R2. The power gating unit C120 may include a gate G121 extending in the Y-axis direction, and may include a first PFET active pattern AP1 and a second PFET active pattern AP2 extending in the X-axis direction. Accordingly, the power gating unit C120 may include a first PFET formed by the gate G121 and the first PFET active pattern AP1, and a second PFET formed by the gate G121 and the second PFET active pattern AP2. In some embodiments, the power gating unit may include two or more gates, and may include more than two transistors.

[0080] The source of the first PFET may be connected to the second front-side pattern M12 through a third contact CA3, and thus, the source of the first PFET may receive a source power supply voltage VDDG through the second front-side pattern M12. Additionally, the drain of the first PFET may be connected to the first front-side pattern M11 through a first contact CA1, and thus, the first back-side pattern BM11 may receive a positive power supply voltage VDD through the first front-side pattern M11. The source of the second PFET may be connected to the second front-side pattern M12 through a third contact CA3, and thus, the source of the second PFET may receive a source power supply voltage VDDG through the second front-side pattern M12. Additionally, the drain of the second PFET may be connected to the third front-side pattern M13 through a second contact CA2, and thus, the third back-side pattern BM13 may receive a positive power supply voltage VDD through the third front-side pattern M13.

[0081] Figure 13 is a flowchart illustrating a method of manufacturing an integrated circuit IC according to one or more embodiments. Specifically, Figure 13 The flowchart of... illustrates an example of a method of manufacturing an integrated circuit IC including cells. As Figure 13 shown, the method of manufacturing an integrated circuit IC may include a plurality of operations S10, S30, S50, S70, and S90.

[0082] The cell library (or standard cell library) D12 may include information about cells (such as information about functions, characteristics, layouts, etc.). In some embodiments, the cell library D12 may define power gating units, end cells, power tap cells PTC, etc. The power gating unit may provide power gating in such a structure: in which power is supplied through a back-side pattern extending from a back-side wiring layer, and thus, the voltage drop caused by power gating may be minimized.

[0083] Design rule D14 may include requirements that the layout of an integrated circuit IC needs to meet. For example, design rule D14 may include requirements for the distance (spacing) between patterns in the same layer, the minimum width of a pattern, the line direction of a wiring layer, etc. In some embodiments, design rule D14 may define the minimum width of an active pattern, the minimum separation distance between active patterns, etc.

[0084] In operation S10, a logic synthesis operation may generate netlist data D13 from register transfer level (RTL) data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) may generate a bitstream or netlist data D13 including a netlist by performing a logic synthesis operation using a cell library D12 and RTL data D11, where the cell library D12 and RTL data D11 are prepared using a hardware description language (HDL) (such as Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) or Verilog). The netlist data D13 can be used as an input for placement and routing (P&R), which will be described below. Here, the netlist data D13 may be referred to as input data.

[0085] In operation S30, cells may be placed. For example, a semiconductor design tool (e.g., a P&R tool) may place the cells used in the netlist data D13 with reference to the cell library D12 and design rule D14. In some embodiments, the semiconductor design tool may place power gating cells and place back patterns in a backside wiring layer. Examples of operation S30 will be described below with reference to Figure 14 and Figure 15 Describe examples of operation S30.

[0086] In operation S50, the pins of the cells may be routed. For example, a semiconductor design tool may generate interconnections that electrically connect the output pins and input pins of the placed functional cells. Additionally, the semiconductor design tool may generate interconnections connected to a node to which a positive power supply voltage is applied or a node to which a negative power supply voltage is applied to supply power to the functional cells. The interconnections may include vias in a via layer and / or patterns in a wiring layer. The semiconductor design tool may generate layout data D15 that defines the placed cells and the generated interconnections. The layout data D15 may have a format such as Graphic Design System II (GDSII) and may include geometric information of the cells and interconnections. The semiconductor design tool may refer to design rule D14 when routing the pins of the cells. The layout data D15 may correspond to the output of P&R. Operation S50 alone or operations S30 and S50 together may be referred to as a method of designing an integrated circuit IC.

[0087] In operation S70, an operation of manufacturing a mask may be performed. For example, optical proximity correction (OPC) for correcting distortion (such as refraction due to the characteristics of light in lithography) may be applied to the layout data D15. A pattern on the mask may be defined based on the data to which OPC has been applied to form patterns arranged on multiple layers, and at least one mask (or photomask) may be manufactured to form patterns on each of the multiple layers. In some embodiments, the layout of the integrated circuit IC may be restrictively modified in operation S70, and the restrictive modification of the integrated circuit IC in operation S70 (which is a post-processing for optimizing the structure of the integrated circuit IC) may be referred to as design polishing.

[0088] In operation S90, an operation of manufacturing an integrated circuit IC may be performed. For example, the integrated circuit IC may be manufactured by patterning multiple layers using at least one mask manufactured in operation S70. The front-end-of-line (FEOL) may include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, and forming source and drain electrodes. Through the FEOL, separate devices (such as transistors, capacitors, resistors, etc.) may be formed on the substrate. Additionally, the back-end-of-line (BEOL) may include, for example, siliciding the gate region, source region, and drain region, adding dielectrics, planarizing, forming vias, adding metal layers, forming through-holes, forming a passivation layer, etc. Through the BEOL, separate devices (such as transistors, capacitors, resistors, etc.) may be interconnected. In some embodiments, a middle-of-line (MOL) process may be performed between the FEOL and the BEOL, and contacts may be formed on the separate devices. Then the integrated circuit IC may be packaged in a semiconductor package and used as a component in various applications.

[0089] Figure 14 is a flowchart showing a method of designing an integrated circuit according to one or more embodiments. For example, Figure 14 the flowchart in Figure 13 shows an example of operation S30. As referred to above with respect to Figure 13 it may be possible to layout cells in operation S30' of Figure 14 . As shown in Figure 14 , operation S30' may include multiple operations S32, S34, and S36. In some embodiments, the multiple operations S32, S34, and S36 may be performed in a different order than that shown in Figure 14 .

[0090] In conjunction with Figure 14 referring together with Figure 8A , Figure 8B and Figure 8C, in operation S32, the power gating unit can be placed. For example, a semiconductor design tool can regularly place the power gating unit before placing the functional units. As described above with reference to the accompanying drawings, the power gating unit can provide or block the positive power supply voltage VDD based on the source power supply voltage VDDG.

[0091] In operation S34, the first backside pattern and the second backside pattern can be placed. For example, a semiconductor design tool can place the first backside pattern and the second backside pattern that extend parallel to each other in the X-axis direction in the backside wiring layer. As described above with reference to the accompanying drawings, the power gating unit can be a multi-height unit continuously arranged in two rows, and the first backside pattern and the second backside pattern can extend in the X-axis direction along the boundary of the power gating unit placed in operation S32. The positive power supply voltage VDD provided by the power gating unit can be applied to the first backside pattern and the second backside pattern.

[0092] In operation S36, the third backside pattern can be placed. For example, a semiconductor design tool can place the third backside pattern in the backside wiring layer between the first backside pattern and the second backside pattern placed in operation S34. As described above with reference to the accompanying drawings, the third backside pattern can extend in the X-axis direction along the boundary between the two rows in which the power gating unit is placed. The source power supply voltage VDDG applied to the third backside pattern can be provided to the power gating unit.

[0093] Figure 15 is a flowchart showing a method for designing an integrated circuit according to one or more embodiments. For example, Figure 15 The flowchart in Figure 13 shows an example of operation S30 in Figure 13 As described above with reference to Figure 15 units can be placed in operation S30'' of Figure 15 As shown in Figure 15 operation S30' can include multiple operations S32', S33', S34', S35' and S36'. In some embodiments, the multiple operations S32', S33', S34', S35' and S36' can be executed in a different order than that shown in

[0094] In operation S32', the power gating units can be placed continuously. For example, as described above with reference to Figure 7 the semiconductor design tool can place the power gating units sequentially in the X-axis direction. The power gating units can correspond to switches connected in parallel with each other, thereby reducing the on-resistance of the power gating.

[0095] In operation S33', the first end unit and the second end unit can be placed. For example, Figure 13The cell library D12 can not only define power gating cells, but also define end cells that are layout-proximate to the power gating cells. In operation S33', the semiconductor design tool can layout a first end cell on one side of the continuously arranged power gating cells, and can layout a second end cell on the other side.

[0096] In operation S34', a first backside pattern and a second backside pattern can be layout. For example, the semiconductor design tool can layout the first backside pattern and the second backside pattern that extend parallel to each other in the X-axis direction in the backside wiring layer. As described above with reference to the drawings, the power gating cells can be multi-height cells that are continuously arranged in two rows, and the first backside pattern and the second backside pattern can extend in the X-axis direction along the boundaries of the power gating cells layout in operation S32'. The positive power supply voltage VDD provided by the continuously layout power gating cells can be applied to the first backside pattern and the second backside pattern. As described above with reference to Figure 7 etc., the first backside pattern and the second backside pattern can extend without terminating at the first end cell and the second end cell layout in operation S33'.

[0097] In operation S35', a third backside pattern can be layout. For example, the semiconductor design tool can layout the third backside pattern in the backside wiring layer between the first backside pattern and the second backside pattern layout in operation S34'. As described above with reference to the drawings, the third backside pattern can extend in the X-axis direction along the boundary between the two rows in which the power gating cells are layout. The source power supply voltage VDDG applied to the third backside pattern can be provided to the power gating cells. As described above with reference to Figure 7 etc., the third backside pattern can terminate at the first end cell and the second end cell layout in operation S33'.

[0098] In operation S36', a fourth backside pattern and a fifth backside pattern can be layout. For example, the semiconductor design tool can layout the fourth backside pattern and the fifth backside pattern that extend in the X-axis direction in the backside wiring layer such that the third backside pattern layout in operation S35' is between the fourth backside pattern and the fifth backside pattern. The negative power supply voltage VSS can be applied to the fourth backside pattern and the fifth backside pattern, and thus, in the regions where the power gating cells layout in operation S32' and the first end cell and the second end cell layout in operation S33' are not layout, the backside patterns applied with the positive power supply voltage VDD and the backside patterns applied with the negative power supply voltage VSS can be alternately layout.

[0099] Figure 16is a block diagram showing a system-on-chip (SoC) 160 according to one or more embodiments. The SoC 160 is a semiconductor device including an integrated circuit according to one or more embodiments. The SoC 160 can be a single chip on which complex functional blocks (such as intellectual property (IP) blocks) configured to perform various functions are provided and can be designed by using a method of designing an integrated circuit according to one or more embodiments, thereby providing high-reliability power gating. Referring to Figure 16 , the SoC 160 may include a modem 162, a display controller 163, a memory 164, an external memory controller 165, a central processing unit (CPU) 166, a transaction unit 167, a power management integrated circuit (PMIC) 168, and a graphics processing unit (GPU) 169, and the functional blocks of the SoC 160 may communicate with each other through a system bus 161.

[0100] The CPU 166 capable of controlling the operation of the SoC 160 at the top level may control the operations of the other functional blocks 162 to 169. The modem 162 may demodulate signals received from outside the SoC 160, or may modulate signals generated in the SoC 160 and send the signals to the outside of the SoC 160. The external memory controller 165 may control operations of sending data to and receiving data from an external memory device connected to the SoC 160. For example, programs and / or data stored in the external memory device may be provided to the CPU 166 or the GPU 169 under the control of the external memory controller 165. The GPU 169 may execute program instructions related to graphics processing. The GPU 169 may receive graphics data through the external memory controller 165, and may send the graphics data processed by the GPU 169 to the outside of the SoC 160 through the external memory controller 165. The transaction unit 167 may monitor data transactions in each functional block, and the PMIC 168 may control the power supplied to each functional block under the control of the transaction unit 167. The display controller 163 may control a display (or display device) outside the SoC 160 to send data generated in the SoC 160 to the display. The memory 164 may include non-volatile memory (such as electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), and may include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.).

[0101] Figure 17FIG. is a block diagram of a computing system 170 including a memory storing a program according to one or more embodiments. At least some of the operations included in a method of designing an integrated circuit (e.g., the above flowchart) according to some embodiments may be performed by the computing system 170 (or a computer).

[0102] The computing system 170 may be a stationary computing system (such as a desktop computer, a workstation, or a server), or may be a portable computing system (such as a laptop computer). As Figure 17 shown, the computing system 170 may include a processor 171, an input / output device 172, a network interface 173, a random access memory (RAM) 174, a read-only memory (ROM) 175, and a storage device 176. The processor 171, the input / output device 172, the network interface 173, the RAM 174, the ROM 175, and the storage device 176 may be connected to a bus 177 and communicate with each other through the bus 177.

[0103] The processor 171 may be referred to as a processing unit and may include at least one core (such as a microprocessor, an application processor (AP), a digital signal processor (DSP), or a GPU) capable of executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, the processor 171 may access a memory (i.e., the RAM 174 or the ROM 175) through the bus 177 and execute instructions stored in the RAM 174 or the ROM 175.

[0104] The RAM 174 may store a program PGM for a method of manufacturing an integrated circuit according to one or more embodiments or at least a part thereof, and the program PGM may cause the processor 171 to perform some of the operations included in a method of designing an integrated circuit (e.g., Figure 13 the method). That is, the program PGM may include a plurality of instructions executable by the processor 171, and the plurality of instructions included in the program PGM may cause the processor 171 to perform at least some of the operations included in, for example, the above flowchart.

[0105] Even when the computing system 170 is powered off, the storage device can store data without losing it. For example, the storage device 176 can include a non-volatile memory device or storage medium (such as magnetic tape, optical disc, or magnetic disk). Additionally, the storage device 176 can be removable from the computing system 170. The storage device 176 can store the program PGM according to one or more embodiments, and the program PGM or at least a portion of the program PGM can be loaded into the RAM 174 from the storage device 176 before being executed by the processor 171. Optionally, the storage device 176 can store files written in a programming language, and the program PGM or at least a portion of the program PGM generated from such files by a compiler, etc., can be loaded into the RAM 174. Additionally, as Figure 17 shown, the storage device 176 can store the database DB, and the database DB can include information required for designing an integrated circuit (e.g., information about the designed blocks and the cell library D12 and / or design rules D14 described with reference Figure 13 .

[0106] The storage device 176 can store data to be processed by the processor 171 or data processed by the processor 171. That is, the processor 171 can generate data by processing the data stored in the storage device 176 according to the program PGM, and can store the generated data in the storage device 176. For example, the storage device 176 can store the RTL data D11, netlist data D13, and / or layout data D15 described with reference Figure 13 .

[0107] The input / output device 172 can include an input device (such as a keyboard or a pointing device) and an output device (such as a display device or a printer). For example, a user can use the input / output device 172 to trigger the execution of the program PGM by the processor 171, input the RTL data D11 and / or netlist data D13 described with reference Figure 13 , or check the layout data D15 described with reference Figure 13 .

[0108] The network interface 173 can provide access to a network external to the computing system 170. For example, the network can include multiple computing systems and multiple communication links, and the communication links can include wired links, optical links, wireless links, or any other type of link.

[0109] The foregoing exemplary embodiments are merely exemplary and should not be construed as restrictive. The present teachings can be easily applied to other types of devices. Moreover, the description of the exemplary embodiments is intended to be illustrative and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An integrated circuit, comprising: a plurality of devices disposed on a substrate; a first backside pattern and a second backside pattern extending parallel to each other in a first direction, the first backside pattern and the second backside pattern being disposed in a backside wiring layer below the substrate and configured to receive a first power supply voltage supplied to the plurality of devices; and a third backside pattern extending in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and configured to receive a source power supply voltage, wherein at least one of the plurality of devices is configured to provide or block the first power supply voltage based on the source power supply voltage.

2. The integrated circuit according to claim 1, further comprising: a fourth backside pattern and a fifth backside pattern extending in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and configured to receive a second power supply voltage supplied to the plurality of devices, wherein the third backside pattern is aligned with the fourth backside pattern and the fifth backside pattern in the first direction between the fourth backside pattern and the fifth backside pattern.

3. The integrated circuit according to claim 1, further comprising: a sixth backside pattern and a seventh backside pattern extending parallel to each other in a first direction, the sixth backside pattern and the seventh backside pattern being disposed in the backside wiring layer and configured to receive a second power supply voltage supplied to the plurality of devices, wherein the first backside pattern and the second backside pattern are adjacent to the sixth backside pattern and the seventh backside pattern respectively and are disposed between the sixth backside pattern and the seventh backside pattern.

4. The integrated circuit according to claim 1, further comprising: a first frontside pattern and a second frontside pattern extending in the first direction along the first backside pattern and the second backside pattern respectively in a frontside wiring layer on the substrate and configured to receive the first power supply voltage; a first through-silicon via extending between the first backside pattern and the first frontside pattern; and a second through-silicon via extending between the second backside pattern and the second frontside pattern.

5. The integrated circuit according to claim 4, further comprising: a third frontside pattern extending in the first direction along the third backside pattern in the frontside wiring layer and configured to receive the source power supply voltage; and a third through-silicon via extending between the third backside pattern and the third frontside pattern.

6. The integrated circuit according to claim 1, wherein at least one of the plurality of devices includes a first transistor, the first transistor including a gate configured to receive a power-off signal, the integrated circuit further comprising: a first backside contact extending between the first backside pattern and the drain of the first transistor; and a second backside contact extending between the third backside pattern and the source of the first transistor.

7. The integrated circuit according to claim 6, wherein at least one of the plurality of devices includes a second transistor, the second transistor including a gate configured to receive a power-off signal, the integrated circuit further comprising: a third backside contact extending between the second backside pattern and the drain of the second transistor.

8. An integrated circuit including a plurality of units, the integrated circuit comprising: At least one power gating unit configured to provide or block a first power voltage based on a source power voltage supplied to the plurality of units; A first backside pattern and a second backside pattern extending parallel to each other in a first direction, the first backside pattern and the second backside pattern being disposed in a backside wiring layer below the substrate and configured to receive the first power voltage; And A third backside pattern extending in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and configured to receive the source power voltage.

9. The integrated circuit according to claim 8, wherein The plurality of units are aligned in a plurality of rows extending in the first direction, The first backside pattern extends in the first direction along the boundary of the first row, The second backside pattern extends in the first direction along the boundary of the second row, and The third backside pattern extends in the first direction along the boundary between the first row and the second row.

10. The integrated circuit according to claim 9, wherein The at least one power gating unit includes two power gating units continuously arranged in the first row and the second row.

11. The integrated circuit according to claim 8, wherein The integrated circuit further includes: A first end unit and a second end unit continuously arranged in the first direction and arranged adjacent to the at least one power gating unit in the first direction, and The third backside pattern terminates below each of the first end unit and the second end unit.

12. The integrated circuit according to claim 11, further including: A fourth backside pattern and a fifth backside pattern extending in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and configured to receive a second power voltage supplied to the plurality of units, Wherein the fourth backside pattern terminates below the first end unit, and The fifth backside pattern terminates below the second end unit.

13. The integrated circuit according to claim 8 further comprises: A sixth backside pattern and a seventh backside pattern extending parallel to each other in the first direction, the sixth backside pattern and the seventh backside pattern being disposed in the backside wiring layer and configured to receive the second power voltage supplied to the plurality of units, Wherein the first backside pattern and the second backside pattern are adjacent to the sixth backside pattern and the seventh backside pattern respectively between the sixth backside pattern and the seventh backside pattern.

14. The integrated circuit according to claim 8, further including: A first frontside pattern and a second frontside pattern extending in the first direction along the first backside pattern and the second backside pattern respectively in a frontside wiring layer on the substrate and configured to receive the first power voltage; A first power tap unit including a through-silicon via extending between the first backside pattern and the first frontside pattern; And A second power tap unit including a through-silicon via extending between the second backside pattern and the second frontside pattern.

15. The integrated circuit according to claim 14, further including: A third frontside pattern extending in the first direction along the third backside pattern in the frontside wiring layer and configured to receive the source power voltage; And A third power tap unit including a through-silicon via extending between the third backside pattern and the third frontside pattern.

16. The integrated circuit according to claim 8, wherein, The at least one power gating unit includes: A first transistor, including a gate configured to receive a power-off signal; A first backside contact extending between a first backside pattern and a drain of the first transistor; and A second backside contact extending between a third backside pattern and a source of the first transistor.

17. The integrated circuit according to claim 16, wherein, The at least one power gating unit further includes: A second transistor, including a gate configured to receive a power-off signal; A third backside contact extending between a second backside pattern and a drain of the second transistor.

18. A method of manufacturing an integrated circuit including a plurality of cells, the method including: Layout at least one power gating unit configured to provide or block a first power voltage based on a source power voltage supplied to the plurality of cells; Layout a first backside pattern and a second backside pattern, the first backside pattern and the second backside pattern extending parallel to each other in a first direction, the first backside pattern and the second backside pattern being disposed in a backside wiring layer below a substrate and configured to receive the first power voltage; And Layout a third backside pattern extending in the first direction between the first backside pattern and the second backside pattern in the backside wiring layer and configured to receive the source power voltage.

19. The method according to claim 18, wherein The at least one power gating unit includes two power gating units, The step of laying out the at least one power gating unit includes: laying out the two power gating units continuously in the first direction, The method further includes: laying out a first end unit and a second end unit adjacent to the at least one power gating unit in the first direction, and The third backside pattern terminates below each of the first end unit and the second end unit.

20. The method according to claim 18, further including: Generating layout data defining a layout of the integrated circuit; Manufacturing a mask based on the layout data; And Manufacturing the integrated circuit based on the mask.

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