Upper tube driving circuit of voltage converter and power supply chip

Abstract

The embodiment of the invention provides an upper tube driving circuit of a voltage converter and a power supply chip. The upper tube driving circuit comprises an upper tube driver, a working state detection module and a driving adjusting module, the working state detection module detects the working state of a voltage converter, and when the voltage converter works in a first state, the driving adjusting module adjusts the driving adjusting module in the upper tube closing process. The driving adjustment module adjusts the control voltage of the upper tube driver according to the voltage amplitude and the voltage change rate of the switch node voltage signal so as to reduce the driving speed of the upper tube driver, when the voltage converter works in the second state, the driving adjustment module stops working, the target parameter in the first state is larger than the target parameter in the second state, and the driving speed of the upper tube driver is reduced. The target parameter includes at least one of an input voltage and a load current. The upper tube driving circuit can improve the conversion efficiency of the voltage converter while ensuring that the voltage converter has low damage risk.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and in particular, to an upper transistor driving circuit of a voltage converter and a power supply chip. Background Art

[0002] With the increasing number of thin, light, and convenient application scenarios, the operating frequency and load of the power supply system are required to be larger and larger, and the requirement for switching loss is also higher and higher. At the same driving speed, the switching loss will increase with the increase of the operating frequency, resulting in a decrease in the conversion efficiency of the voltage converter, and the overvoltage of the upper transistor will increase with the increase of the load, making the voltage converter easily damaged.

[0003] In the prior art, the conversion efficiency of the voltage converter at a high operating frequency can be improved by increasing the driving speed of the upper transistor. However, an overshoot voltage will be generated by too fast driving speed, which will damage the upper transistor. In order to ensure the normal operation of the circuit, the driving speed is usually limited by the highest input voltage and the maximum load, resulting in a low damage risk of the voltage converter while being unable to ensure a high conversion efficiency. Summary of the Invention

[0004] Embodiments of the present disclosure provide an upper transistor driving circuit of a voltage converter and a power supply chip, which can improve the conversion efficiency of the voltage converter while ensuring a low damage risk of the voltage converter.

[0005] In a first aspect, the present disclosure provides an upper transistor driving circuit of a voltage converter. The voltage converter includes an upper transistor and a lower transistor, and the connection point of the upper transistor and the lower transistor is a switching node. The upper transistor driving circuit includes an upper transistor driver, a working state detection module, and a driving adjustment module.

[0006] The working state detection module is configured to detect the working state of the voltage converter. The working state includes a first state and a second state, and the target parameter in the first state is greater than the target parameter in the second state. The target parameter includes at least one of an input voltage and a load current.

[0007] The driving adjustment module is configured to, when the voltage converter operates in the first state, during the turn-off process of the upper transistor, adjust the control voltage of the upper transistor driver according to the voltage amplitude and the voltage change rate of the switching node voltage signal, so as to reduce the driving speed of the upper transistor driver; when the voltage converter operates in the second state, stop working.

[0008] In some embodiments of the present disclosure, the drive adjustment module includes a differential unit and a voltage adjustment unit. The first input terminal of the differential unit is connected to the voltage input terminal of the voltage converter. The second input terminal of the differential unit is connected to the switching node. The control terminal of the differential unit is connected to the output terminal of the operating state detection module. The output terminal of the differential unit is connected to the control terminal of the voltage adjustment unit. The output terminal of the voltage adjustment unit is connected to the control terminal of the upper transistor driver. The input terminal of the voltage adjustment unit is connected to the switching node.

[0009] The differential unit is configured to detect the voltage change rate of the switching node voltage signal during the process of turning off the upper transistor, and obtain a switching node voltage change rate detection signal. The voltage adjustment unit is configured to adjust the control voltage of the upper transistor driver according to the voltage difference between the switching node voltage change rate detection signal and the switching node voltage signal when the voltage converter operates in the first state.

[0010] In some embodiments of the present disclosure, the differential unit includes a first transistor, a first resistor, a second resistor, and a capacitor. The first plate of the capacitor is connected to the voltage input terminal. The second plate of the capacitor is connected to the first end of the first resistor and the control terminal of the voltage adjustment unit. The second end of the first resistor is connected to the first end of the second resistor and the second end of the first transistor. The second end of the second resistor is connected to the first end of the first transistor and the switching node. The control terminal of the first transistor is connected to the output terminal of the operating state detection module.

[0011] In some embodiments of the present disclosure, the voltage adjustment unit includes a second transistor. The control terminal of the second transistor is connected to the output terminal of the differential unit. The first end of the second transistor is connected to the switching node. The second end of the second transistor is connected to the control terminal of the upper transistor driver.

[0012] In some embodiments of the present disclosure, when the voltage converter operates in the first state, the voltage difference is greater than the threshold voltage of the second transistor; when the voltage converter operates in the second state, the voltage difference is less than the threshold voltage of the second transistor.

[0013] In some embodiments of the present disclosure, the working state detection module includes a detection unit and a logic unit. A first input terminal of the detection unit is connected to a load current, a second input terminal of the detection unit is connected to a reference current, a third input terminal of the detection unit is connected to a voltage input terminal of the voltage converter, a fourth input terminal of the detection unit is connected to a reference voltage, a first output terminal of the detection unit is connected to a first input terminal of the logic unit, a second output terminal of the detection unit is connected to a second input terminal of the logic unit, and an output terminal of the logic unit is connected to a control terminal of the drive adjustment module.

[0014] The detection unit is configured to determine a load detection signal according to the load current and the reference current, and determine a voltage detection signal according to the input voltage and the reference voltage. The logic unit is configured to determine a working state detection signal according to the load detection signal and the voltage detection signal.

[0015] In some embodiments of the present disclosure, the detection unit includes a first comparator and a second comparator. A non-inverting input terminal of the first comparator is connected to the load current, an inverting input terminal of the first comparator is connected to the reference current, and an output terminal of the first comparator is connected to the first input terminal of the logic unit; a non-inverting input terminal of the second comparator is connected to the voltage input terminal, an inverting input terminal of the second comparator is connected to the reference voltage, and an output terminal of the second comparator is connected to the second input terminal of the logic unit.

[0016] In some embodiments of the present disclosure, the logic unit includes a NAND gate. A first input terminal of the NAND gate is connected to the first output terminal of the detection unit, a second input terminal of the NAND gate is connected to the second output terminal of the detection unit, and an output terminal of the NAND gate is connected to the control terminal of the drive adjustment module.

[0017] In some embodiments of the present disclosure, the upper transistor driver includes a pull-up transistor and a pull-down transistor. A first end of the pull-up transistor is connected to a power supply voltage, a second end of the pull-up transistor and a second end of the pull-down transistor are connected to a control terminal of the upper transistor, a first end of the pull-down transistor is connected to the switch node, and a control terminal of the pull-up transistor and a control terminal of the pull-down transistor are connected to an output terminal of the drive adjustment module.

[0018] In a second aspect, the present disclosure provides a power chip including any of the drive circuits provided in the first aspect.

[0019] In the technical solution of the embodiments of the present disclosure, the upper transistor driving circuit includes an upper transistor driver, a working state detection module, and a driving adjustment module. The working state detection module detects the working state of the voltage converter. When the voltage converter works in the first state, during the process of turning off the upper transistor, the driving adjustment module adjusts the control voltage of the upper transistor driver according to the voltage amplitude and voltage change rate of the switching node voltage signal to reduce the driving speed of the upper transistor driver. When the voltage converter works in the second state, the driving adjustment module stops working. Since the target parameter in the first state is greater than the target parameter in the second state, and the target parameter includes at least one of the input voltage and the load current, therefore, in the high working voltage and / or high load state, the voltage drop speed of the switching node voltage signal can be reduced, thereby reducing the damage risk of the voltage converter caused by overvoltage of the upper transistor, so as to ensure that the voltage converter has a low damage risk. At the same time, in the low working voltage and / or low load state, the switching loss caused by the driving adjustment module can be avoided, thereby improving the conversion efficiency of the voltage converter.

[0020] The above description is only an overview of the technical solution of the embodiments of the present application. In order to be able to understand the technical means of the embodiments of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and understandable, the following specifically illustrates the embodiments of the present application. Brief Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of the curve of the switching loss and conversion efficiency of the Buck converter provided by the prior art changing with the working frequency.

[0023] Figure 2 It is a schematic diagram of the overvoltage of the upper transistor of the Buck converter provided by the prior art changing with the load.

[0024] Figure 3 It is a schematic diagram of the response curve of the upper transistor of the voltage converter provided by the prior art at different driving speeds.

[0025] Figure 4 It is a schematic structural diagram of a voltage converter provided by an embodiment of the present disclosure.

[0026] Figure 5 It is a schematic structural diagram of an upper transistor driving circuit provided by an embodiment of the present disclosure.

[0027] Figure 6 Schematic diagram of a top - tube driving circuit provided by an embodiment of the present disclosure.

[0028] Figure 7 Schematic diagram of the response curve of the voltage converter provided by an embodiment of the present disclosure during the top - tube turn - off process.

[0029] Figure 8 (a) and Figure 8 (b) Schematic diagram of simulation of each signal of the voltage converter provided by an embodiment of the present disclosure under different input voltages.

[0030] Figure 9 Schematic diagram of the curve of the conversion efficiency of the voltage converter provided by an embodiment of the present disclosure varying with the input voltage.

[0031] Figure 10 Schematic diagram of the curve of the conversion efficiency of the voltage converter provided by an embodiment of the present disclosure varying with the load.

[0032] Figure 11 Schematic diagram of the curve of the over - voltage of the top - tube of the voltage converter provided by an embodiment of the present disclosure varying with the input voltage. Detailed implementation manners

[0033] In order to make the purposes, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts also belong to the scope of protection of the present disclosure.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure pertains. Further, it will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless explicitly defined otherwise herein. As used herein, the statement of connecting two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0035] References to "embodiments" in this disclosure mean that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase "embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0036] In addition, the terms "first", "second", etc. in the specification and claims of this disclosure or in the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order, and may explicitly or implicitly include one or more of such features.

[0037] The term "and / or" in this disclosure is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: the existence of A, the simultaneous existence of A and B, and the existence of B. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0038] In the description of this disclosure, unless otherwise specified, the meanings of "a plurality" and "at least two" refer to more than two (including two). Similarly, "multiple groups" and "at least two groups" refer to more than two groups (including two groups).

[0039] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0040] Figure 1 The schematic diagram of the curves of the switching loss and conversion efficiency of the Buck converter provided by the prior art changing with the operating frequency is as Figure 1 shown. As the operating frequency increases, the proportion of the switching loss becomes higher and higher at the same driving speed, and the conversion efficiency of the Buck converter becomes lower and lower. Figure 2 The schematic diagram of the overvoltage of the upper transistor of the Buck converter provided by the prior art changing with the load is as Figure 2 shown. The greater the load, the greater the overvoltage of the upper transistor at the same driving speed, and the easier the upper transistor is to be damaged, that is, the easier the Buck converter is to be damaged.

[0041] It should be noted that Figure 1 and Figure 2 only the Buck type voltage converter is used for exemplary illustration. In actual applications, the Buck-Boost converter, Boost converter, or other types of DC / DC converters also have the same problems.

[0042] To improve the conversion efficiency of a voltage converter at high operating frequencies, a faster driving speed is required. However, due to the presence of parasitic inductance in the PCB board and packaging, an overly fast driving speed will generate overcharge voltage, causing damage to the upper transistor, that is, the circuit of the voltage converter is damaged, such as Figure 3 shown Figure 3 is a schematic diagram of the response curve of the upper transistor of the voltage converter provided by the prior art at different driving speeds.

[0043] When turning off the upper transistor at three driving speeds of fast, medium, and slow, the voltage of the switching node voltage signal VSW starts to drop, the gate-source voltage VGS_HS of the upper transistor starts to drop, and different overvoltages will be generated in the drain-source voltage VDS_HS of the upper transistor. When quickly turning off the upper transistor, the switching loss is the smallest, but at the same time, the overvoltage of the drain-source voltage VDS_HS of the upper transistor is the largest, and the upper transistor is most easily damaged by overvoltage. To ensure the safe operation of the circuit, the driving speed is usually limited by the highest input voltage and the operating state of the maximum load, so that the driving speed of the upper transistor is relatively low under low operating voltage and low load application conditions, thereby reducing the conversion efficiency. While the voltage converter has a low damage risk, it cannot guarantee a high conversion efficiency.

[0044] In view of this, the present disclosure provides an upper transistor driving circuit, including an upper transistor driver, a working state detection module, and a driving adjustment module. The working state detection module detects the working state of the voltage converter. When the voltage converter operates in the first state, during the process of turning off the upper transistor, the driving adjustment module adjusts the control voltage of the upper transistor driver according to the voltage amplitude and voltage change rate of the switching node voltage signal to reduce the driving speed of the upper transistor driver. When the voltage converter operates in the second state, the driving adjustment module stops working. Since the target parameter in the first state is greater than the target parameter in the second state, and the target parameter includes at least one of the input voltage and the load current, therefore, at high operating voltage and / or high load state, the voltage drop speed of the switching node voltage signal can be reduced, thereby reducing the damage risk of the voltage converter caused by upper transistor overvoltage, to ensure that the voltage converter has a low damage risk. At the same time, at low operating voltage and / or low load state, the switching loss caused by the driving adjustment module can be avoided, thereby improving the conversion efficiency of the voltage converter.

[0045] The following describes in detail the technical solutions provided by the present disclosure with several specific embodiments.

[0046] Figure 4 is a schematic diagram of the structure of a voltage converter provided by an embodiment of the present disclosure, such as Figure 4 shown, the voltage converter 10 is a Buck converter, including an upper transistor driving circuit 100, an upper transistor HS, a lower transistor LS, an inductor L, an output capacitor Cout, and a load Iout.

[0047] The output terminal of the upper transistor driving circuit 100 is connected to the control terminal of the upper transistor HS. The upper transistor HS and the lower transistor LS are connected in series between the voltage input terminal of the voltage converter 10 and the ground. The connection point of the upper transistor HS and the lower transistor LS is the switching node SW, and the voltage signal of the switching node SW is the switching node voltage signal VSW. The switching node SW is connected to the voltage output terminal of the voltage converter 10 through an inductor L, and the output capacitor Cout and the load Iout are connected in parallel between the voltage output terminal and the ground.

[0048] It should be noted that Figure 4 Only the Buck converter is taken as an example to exemplarily illustrate the voltage converter 10. In practical applications, the voltage converter 10 can also be a Buck-Boost converter, a Boost converter or other types of DC / DC converters, and the present disclosure does not make specific limitations thereto.

[0049] Figure 5 The figure is a schematic structural diagram of an upper transistor driving circuit provided by an embodiment of the present disclosure. As Figure 5 shown, the upper transistor driving circuit 100 includes an upper transistor driver 110, a working state detection module 120, and a driving adjustment module 130.

[0050] Among them, the output terminal of the working state detection module 120 is connected to the control terminal of the driving adjustment module 130. The first input terminal of the driving adjustment module 130 is connected to the voltage input terminal of the voltage converter 10 to receive the input voltage VIN. The second input terminal of the driving adjustment module 130 is connected to the switching node SW to receive the switching node voltage signal VSW. The output terminal of the driving adjustment module 130 is connected to the control terminal of the upper transistor driver 110, and the output terminal of the upper transistor driver 110 is connected to the control terminal of the upper transistor HS to provide the control voltage VG_HS to the upper transistor HS.

[0051] The working state detection module 120 is configured to detect the working state of the voltage converter 10. The working state includes a first state and a second state, and the target parameter in the first state is greater than the target parameter in the second state. The target parameters include the input voltage VIN and the load current ILOAD.

[0052] The driving adjustment module 130 is configured to, when the voltage converter 10 works in the first state, during the process of turning off the upper transistor HS, adjust the upper transistor driver control voltage VDRV according to the voltage amplitude and voltage change rate of the switching node voltage signal VSW to reduce the driving speed of the upper transistor driver 110; when the voltage converter 10 works in the second state, stop working.

[0053] Exemplarily, Figure 6 The figure is a circuit schematic diagram of an upper transistor driving circuit provided by an embodiment of the present disclosure. As Figure 6As shown, the working state detection module 120 includes a detection unit 121 and a logic unit 122. The first input terminal of the detection unit 121 is connected to the load current ILOAD, the second input terminal of the detection unit 121 is connected to the reference current IREF, the third input terminal of the detection unit 121 is connected to the voltage input terminal of the voltage converter 10, the fourth input terminal of the detection unit 121 is connected to the reference voltage VREF, the first output terminal of the detection unit 121 is connected to the first input terminal of the logic unit 122, the second output terminal of the detection unit 121 is connected to the second input terminal of the logic unit 122, and the output terminal of the logic unit 122 is connected to the control terminal of the drive adjustment module 130.

[0054] The detection unit 121 can compare the magnitudes of the load current ILOAD and the reference current IREF to obtain a load detection signal VLOAD_DET. When the load current ILOAD is greater than the reference current IREF, it indicates that the voltage converter 10 is in a high-load state, and then the load detection signal VLOAD_DET is at a high level. When the load current ILOAD is less than the reference current IREF, it indicates that the voltage converter 10 is in a low-load state, and then the load detection signal VLOAD_DET is at a low level.

[0055] The detection unit 121 can also compare the magnitudes of the input voltage VIN and the reference voltage VREF to obtain a voltage detection signal VIN_DET. When the input voltage VIN is greater than the reference voltage VREF, it indicates that the voltage converter 10 is in a high operating voltage state, and then the voltage detection signal VIN_DET is at a high level. When the input voltage VIN is less than the reference voltage VREF, it indicates that the voltage converter 10 is in a low operating voltage state, and then the voltage detection signal VIN_DET is at a low level.

[0056] In this way, the detection unit 121 can determine the load detection signal VLOAD_DET based on the load current ILOAD and the reference current IREF, and determine the voltage detection signal VIN_DET based on the input voltage VIN and the reference voltage VREF.

[0057] The logic unit 122 can receive the voltage detection signal VIN_DET and the load detection signal VLOAD_DET output by the detection unit 121, and determine a working state detection signal VSTATE_DET based on the load detection signal VLOAD_DET and the voltage detection signal VIN_DET. Among them, the working state detection signal VSTATE_DET is used to represent whether the voltage converter 10 is operating in the first state or the second state. The first state can be understood as a state of high operating voltage and / or high load, and the second state can be understood as a state of low operating voltage and / or low load.

[0058] For example, when at least one of the load detection signal VLOAD_DET and the voltage detection signal VIN_DET is at a high level, the operating state detection signal VSTATE_DET is at a low level, indicating that the voltage converter 10 is operating in the first state. When both the load detection signal VLOAD_DET and the voltage detection signal VIN_DET are at a low level, the operating state detection signal VSTATE_DET is at a high level, indicating that the voltage converter 10 is operating in the second state.

[0059] Alternatively, when the load detection signal VLOAD_DET and the voltage detection signal VIN_DET are at a high level, the operating state detection signal VSTATE_DET is at a low level, indicating that the voltage converter 10 is operating in the first state. When at least one of the load detection signal VLOAD_DET and the voltage detection signal VIN_DET is at a low level, the operating state detection signal VSTATE_DET is at a high level, indicating that the voltage converter 10 is operating in the second state.

[0060] It should be noted that, in the embodiments of the present disclosure, only the target parameters including the input voltage VIN and the load current ILOAD are taken as examples for illustrative purposes. In practical applications, the target parameters may only include the input voltage VIN. Correspondingly, the detection unit 121 only needs to determine the voltage detection signal VIN_DET according to the input voltage VIN and the reference voltage VREF. The first state is the high operating voltage state, and the second state is the low operating voltage state. Alternatively, the target parameters only include the load current ILOAD. Correspondingly, the detection unit 121 only needs to determine the load detection signal VLOAD_DET according to the load current ILOAD and the reference current IREF. The first state is the high load state, and the second state is the low load state.

[0061] Continuing to refer to Figure 6 , the drive adjustment module 130 includes a differential unit 131 and a voltage adjustment unit 132. The first input terminal of the differential unit 131 is connected to the voltage input terminal, the second input terminal of the differential unit 131 is connected to the switch node SW, the control terminal of the differential unit 131 is connected to the output terminal of the operating state detection module 120, the output terminal of the differential unit 131 is connected to the control terminal of the voltage adjustment unit 132, the output terminal of the voltage adjustment unit 132 is connected to the control terminal of the high-side driver 110, and the input terminal of the voltage adjustment unit 132 is connected to the switch node SW.

[0062] Exemplarily, as Figure 6As shown, the differential unit 131 includes a first transistor M1, a first resistor R1, a second resistor R2, and a capacitor C. The first plate of the capacitor C is connected to the voltage input terminal to receive the input voltage VIN. The second plate of the capacitor C is connected to the first end of the first resistor R1 and the control terminal of the voltage regulation unit 132. The second end of the first resistor R1 is connected to the first end of the second resistor R2 and the second end of the first transistor M1. The second end of the second resistor R2 is connected to the first end of the first transistor M1 and the switch node SW. The control terminal of the first transistor M1 is connected to the output terminal of the working state detection module 120.

[0063] Figure 7 The figure is a schematic diagram of the response curve of the voltage converter provided by the embodiment of the present disclosure during the turn-off process of the upper switch. As Figure 7 shown, during the turn-off process of the upper switch HS, the voltage amplitude of the switch node voltage signal VSW first decreases, then increases, and finally remains stable. Correspondingly, the drain-source voltage VDS_HS of the upper switch HS first increases, then decreases, and finally remains stable.

[0064] When the working state detection signal VSTATE_DET is at a low level, the voltage converter 10 operates in the first state. The first transistor M1 is in the off state. The first resistor R1 and the second resistor R2 are connected in series between the second plate of the capacitor C and the switch node SW. Then, the first resistor R1, the second resistor R2, and the capacitor C form a differential circuit. When the working state detection signal VSTATE_DET is at a high level, the voltage converter 10 operates in the second state. The first transistor M1 is in the on state. The second resistor R2 is short-circuited. The first resistor R1 is connected between the second plate of the capacitor C and the switch node SW. Then, the first resistor R1 and the capacitor C form a differential circuit.

[0065] During the turn-off process of the upper switch HS, regardless of whether the voltage converter 10 operates in the first state or the second state, the differential unit 131 can detect the voltage change rate of the switch node voltage signal VSW during the turn-off process of the upper switch HS, and obtain the switch node voltage change rate detection signal VSW_DET. Among them, the voltage amplitude of the switch node voltage change rate detection signal VSW_DET is positively correlated with the resistance value of the resistor in the differential circuit. The resistance value of the resistor in the differential circuit in the first state is the sum of the resistance values of the first resistor R1 and the second resistor R2. The resistance value of the resistor in the differential circuit in the second state is the resistance value of the first resistor R1. Then, the voltage amplitude of the switch node voltage change rate detection signal VSW_DET in the first state is greater than the voltage amplitude of the switch node voltage change rate detection signal VSW_DET in the second state.

[0066] Exemplarily, continue to refer to Figure 6, the voltage regulation unit 132 includes a second transistor M2. The gate of the second transistor M2 is connected to the output terminal of the differential unit 131 to receive the switching node voltage change rate detection signal VSW_DET. The source of the second transistor M2 is connected to the switching node SW to receive the switching node voltage signal VSW. The drain of the second transistor M2 is connected to the control terminal of the high-side driver 110, and the drain voltage of the second transistor M2 is the high-side driver control voltage VDRV.

[0067] The voltage difference VSW_DET - VSW between the switching node voltage change rate detection signal VSW_DET and the switching node voltage signal VSW is the gate-source voltage of the second transistor M2. When the voltage converter 10 operates in the second state, during the turn-off process of the high-side switch HS, the voltage difference VSW_DET - VSW is less than the threshold voltage of the second transistor M2, and the second transistor M2 is in the off state. The drive regulation module 130 is not connected to the control terminal of the high-side driver 110, so the high-side driver control voltage VDRV remains unchanged, which can avoid the switching loss caused by the drive regulation module 130.

[0068] When the voltage converter 10 operates in the first state, during the turn-off process of the high-side switch HS, the voltage difference VSW_DET - VSW is greater than the threshold voltage of the second transistor M2, and the second transistor M2 is in the on state, and the gate-source voltage of the second transistor M2 is positively correlated with the current I_M2 flowing through the second transistor M2. Specifically, during the turn-off process of the high-side switch HS, when the voltage of the switching node voltage signal VSW drops rapidly, the voltage difference VSW_DET - VSW is large, and the current I_M2 flowing through the second transistor M2 is high, then the second transistor M2 can reduce the high-side driver control voltage VDRV, thereby reducing the drive current IDRV of the high-side switch HS. When the voltage of the switching node voltage signal VSW drops slowly, the voltage difference VSW_DET - VSW is small, and the current I_M2 flowing through the second transistor M2 is small, then the second transistor M2 can increase the high-side driver control voltage VDRV, thereby increasing the drive current IDRV of the high-side switch HS, as Figure 7 shown.

[0069] Exemplarily, continue to refer to Figure 6 , the high-side driver 110 includes a pull-up transistor MU and a pull-down transistor MD. The first end of the pull-up transistor MU is connected to the power supply voltage VDD. The second end of the pull-up transistor MU and the second end of the pull-down transistor MD are connected to the control terminal of the high-side switch HS. The first end of the pull-down transistor MD is connected to the switching node SW. The control terminals of the pull-up transistor MU and the pull-down transistor MD are connected to the output terminal of the drive regulation module 130.

[0070] When the control voltage VDRV of the upper transistor driver remains unchanged, the control voltages of the pull-up transistor MU and the pull-down transistor MD remain unchanged, the drive current IDRV of the upper transistor HS remains unchanged, and the driving speed of the upper transistor driver 110 for the upper transistor HS remains unchanged, that is, the voltage drop speed of the switching node voltage signal VSW remains unchanged. When the control voltage VDRV of the upper transistor driver decreases, the control voltages of the pull-up transistor MU and the pull-down transistor MD decrease, the drive current IDRV of the upper transistor HS decreases, and the driving speed of the upper transistor driver 110 for the upper transistor HS can be reduced to reduce the voltage drop speed of the switching node voltage signal VSW.

[0071] Figure 8 (a) and Figure 8 (b) are simulation schematic diagrams of various signals of the voltage converter provided by the embodiments of the present disclosure under different input voltages. When the input voltage VIN is 12V, during the turn-off process of the upper transistor HS, the drive adjustment module 130 is not connected, and the current I_M2 flowing through the second transistor M2 is zero, thereby reducing the switching loss of the voltage converter 10, as Figure 8 (a) shows. When the input voltage VIN is 24V, during the turn-off process of the upper transistor HS, the drive adjustment module 130 adaptively adjusts the voltage drop speed of the switching node voltage signal VSW to reduce the overvoltage of the upper transistor HS, thereby reducing the damage risk of the voltage converter 10, as Figure 8 (b) shows.

[0072] Exemplarily, Figure 9 is a schematic diagram of the curve of the conversion efficiency of the voltage converter provided by the embodiments of the present disclosure changing with the input voltage. The output voltage of the voltage converter 10 is 0.77V, the load is 12A, and the operating frequency is 1MHz, as Figure 9 shown. When the input voltage VIN is 20V, compared with the traditional voltage converter, in the second state, the conversion efficiency of the voltage converter 10 provided by the present disclosure can be increased by 3.3%.

[0073] Figure 10 is a schematic diagram of the curve of the conversion efficiency of the voltage converter provided by the embodiments of the present disclosure changing with the load. The output voltage of the voltage converter 10 is 0.77V, and the operating frequency is 1MHz, as Figure 10 shown. When the load is 12A, compared with the traditional voltage converter, in the second state, the conversion efficiency of the voltage converter 10 provided by the present disclosure can be increased by 3.5%.

[0074] Figure 11 is a schematic diagram of the curve of the overvoltage of the upper transistor of the voltage converter provided by the embodiments of the present disclosure changing with the input voltage, as Figure 11As shown, in the first state, the voltage converter 10 provided by the present disclosure can achieve an effect similar to that of a conventional voltage converter, that is, it can reduce the risk of damage.

[0075] In summary, when the voltage converter 10 operates in the first state, the voltage converter 10 is in a high operating voltage and / or high load state. During the process of turning off the high-side transistor HS, when the voltage drop rate of the switch node voltage signal VSW is relatively high, the driving speed of the high-side transistor HS by the high-side driver 110 can be reduced to lower the voltage drop rate of the switch node voltage signal VSW, playing a role in protecting the high-side transistor HS.

[0076] When the voltage converter 10 operates in the second state, the voltage converter 10 is in a low operating voltage and / or low load state. During the process of turning off the high-side transistor HS, the drive adjustment module 130 stops working and does not affect the voltage drop rate of the switch node voltage signal VSW, which can avoid switch losses caused by the drive adjustment module 130.

[0077] In this way, the high-side drive circuit 100 can reduce the voltage drop rate of the switch node voltage signal VSW in a high operating voltage and / or high load state, thereby reducing the risk of damage to the voltage converter 10 caused by overvoltage of the high-side transistor HS, ensuring that the voltage converter 10 has a low risk of damage. At the same time, in a low operating voltage and / or low load state, it can avoid switch losses caused by the drive adjustment module 130, thereby improving the conversion efficiency of the voltage converter 10.

[0078] In some embodiments, referring further to Figure 6 , the detection unit 121 includes a first comparator CMP1 and a second comparator CMP2. The positive input terminal of the first comparator CMP1 is connected to the load current ILOAD, the negative input terminal of the first comparator CMP1 is connected to the reference current IREF, and the output terminal of the first comparator CMP1 is connected to the first input terminal of the logic unit 122. The positive input terminal of the second comparator CMP2 is connected to the voltage input terminal of the voltage converter 10, the negative input terminal of the second comparator CMP2 is connected to the reference voltage VREF, and the output terminal of the second comparator CMP2 is connected to the second input terminal of the logic unit 121.

[0079] Exemplarily, the positive input current of the first comparator CMP1 is the load current ILOAD, the negative input current is the reference current IREF. The first comparator CMP1 can compare the magnitudes of the load current ILOAD and the reference current IREF. When the load current ILOAD is greater than the reference current IREF, the output load detection signal VLOAD_DET is at a high level. When the load current ILOAD is less than the reference current IREF, the output load detection signal VLOAD_DET is at a low level.

[0080] The positive input voltage of the second comparator CMP2 is the input voltage VIN, and the negative input voltage is the reference voltage VREF. The second comparator CMP2 can compare the magnitudes of the input voltage VIN and the reference voltage VREF. When the input voltage VIN is greater than the reference voltage VREF, the output voltage detection signal VIN_DET is at a high level; when the input voltage VIN is less than the reference voltage VREF, the output voltage detection signal VIN_DET is at a low level.

[0081] In some embodiments, referring further to Figure 6 , the logic unit 122 includes a NAND gate NOR. The first input terminal of the NAND gate NOR is connected to the first output terminal of the detection unit 121, the second input terminal of the NAND gate NOR is connected to the second output terminal of the detection unit 121, and the output terminal of the NAND gate NOR is connected to the control terminal of the drive adjustment module 130.

[0082] Exemplarily, the first input terminal of the NAND gate NOR is connected to the output terminal of the first comparator CMP1, the second input terminal of the NAND gate NOR is connected to the output terminal of the second comparator CMP2. The NAND gate NOR can receive the load detection signal VLOAD_DET and the voltage detection signal VIN_DET, and perform a NAND operation on the load detection signal VLOAD_DET and the voltage detection signal VIN_DET to obtain the working state detection signal VSTATE_DET.

[0083] For example, when the load detection signal VLOAD_DET and / or the voltage detection signal VIN_DET is at a high level, the working state detection signal VSTATE_DET is at a low level; when the load detection signal VLOAD_DET and the voltage detection signal VIN_DET are at a low level, the working state detection signal VSTATE_DET is at a high level.

[0084] The embodiments of the present disclosure also provide a power chip, including the upper transistor drive circuit 100 provided in any of the above embodiments.

[0085] The power chip provided by the embodiments of the present disclosure includes the upper transistor drive circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the upper transistor drive circuit 100, which will not be elaborated here.

[0086] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when reference is made to the singular, it generally includes the plural of the corresponding term. Similarly, the phrases "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "exemplary" is used herein, particularly when it is after a list of terms, the "exemplary" is merely illustrative and explanatory and should not be considered exclusive or exhaustive.

[0087] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that the various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific embodiments are for illustrative purposes only and are not intended to limit the scope of the present application.

[0088] The above has described in detail several embodiments of the present disclosure. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. An upper transistor driving circuit of a voltage converter, characterized in that, The voltage converter includes an upper transistor and a lower transistor, and the connection point of the upper transistor and the lower transistor is a switching node. The upper transistor driving circuit includes an upper transistor driver, a working state detection module, and a driving adjustment module; The working state detection module is configured to detect the working state of the voltage converter. The working state includes a first state and a second state, and the target parameter in the first state is greater than the target parameter in the second state. The target parameter includes at least one of an input voltage and a load current; The driving adjustment module is configured to, when the voltage converter operates in the first state, during the process of turning off the upper transistor, adjust the control voltage of the upper transistor driver according to the voltage amplitude and voltage change rate of the switching node voltage signal, so as to reduce the driving speed of the upper transistor driver; when the voltage converter operates in the second state, stop working.

2. The upper tube drive circuit according to claim 1, wherein The driving adjustment module includes a differential unit and a voltage adjustment unit; The first input end of the differential unit is connected to the voltage input end of the voltage converter, the second input end of the differential unit is connected to the switching node, the control end of the differential unit is connected to the output end of the working state detection module, the output end of the differential unit is connected to the control end of the voltage adjustment unit, the output end of the voltage adjustment unit is connected to the control end of the upper transistor driver, and the input end of the voltage adjustment unit is connected to the switching node; The differential unit is configured to, during the process of turning off the upper transistor, detect the voltage change rate of the switching node voltage signal to obtain a switching node voltage change rate detection signal; The voltage adjustment unit is configured to, when the voltage converter operates in the first state, adjust the control voltage of the upper transistor driver according to the voltage difference between the switching node voltage change rate detection signal and the switching node voltage signal.

3. The upper tube drive circuit according to claim 2, wherein, The differential unit includes a first transistor, a first resistor, a second resistor, and a capacitor; The first plate of the capacitor is connected to the voltage input end, the second plate of the capacitor is connected to the first end of the first resistor and the control end of the voltage adjustment unit, the second end of the first resistor is connected to the first end of the second resistor and the second end of the first transistor, the second end of the second resistor is connected to the first end of the first transistor and the switching node, and the control end of the first transistor is connected to the output end of the working state detection module.

4. The upper tube driving circuit according to claim 2, wherein The voltage adjustment unit includes a second transistor; The control end of the second transistor is connected to the output end of the differential unit, the first end of the second transistor is connected to the switching node, and the second end of the second transistor is connected to the control end of the upper transistor driver.

5. The upper tube driving circuit according to claim 4, wherein When the voltage converter operates in the first state, the voltage difference is greater than the threshold voltage of the second transistor; when the voltage converter operates in the second state, the voltage difference is less than the threshold voltage of the second transistor.

6. The upper tube drive circuit according to claim 1, wherein The working state detection module includes a detection unit and a logic unit; The first input terminal of the detection unit is connected to the load current, the second input terminal of the detection unit is connected to the reference current, the third input terminal of the detection unit is connected to the voltage input terminal of the voltage converter, the fourth input terminal of the detection unit is connected to the reference voltage, the first output terminal of the detection unit is connected to the first input terminal of the logic unit, the second output terminal of the detection unit is connected to the second input terminal of the logic unit, and the output terminal of the logic unit is connected to the control terminal of the drive adjustment module; The detection unit is configured to determine a load detection signal according to the load current and the reference current, and determine a voltage detection signal according to the input voltage and the reference voltage; The logic unit is configured to determine a working state detection signal according to the load detection signal and the voltage detection signal.

7. The upper tube driving circuit according to claim 6, wherein, The detection unit includes a first comparator and a second comparator; The non-inverting input terminal of the first comparator is connected to the load current, the inverting input terminal of the first comparator is connected to the reference current, and the output terminal of the first comparator is connected to the first input terminal of the logic unit; the non-inverting input terminal of the second comparator is connected to the voltage input terminal, the inverting input terminal of the second comparator is connected to the reference voltage, and the output terminal of the second comparator is connected to the second input terminal of the logic unit.

8. The upper tube drive circuit according to claim 6, characterized in that, The logic unit includes a NAND gate; The first input terminal of the NAND gate is connected to the first output terminal of the detection unit, the second input terminal of the NAND gate is connected to the second output terminal of the detection unit, and the output terminal of the NAND gate is connected to the control terminal of the drive adjustment module.

9. The upper tube driving circuit according to any one of claims 1-8, characterized in that The upper transistor driver includes a pull-up transistor and a pull-down transistor; The first end of the pull-up transistor is connected to the power supply voltage, the second end of the pull-up transistor and the second end of the pull-down transistor are connected to the control terminal of the upper transistor, the first end of the pull-down transistor is connected to the switch node, and the control terminals of the pull-up transistor and the pull-down transistor are connected to the output terminal of the drive adjustment module.

10. A power chip, characterized in that, Comprising the upper transistor drive circuit according to any one of claims 1-9.

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