Neuron circuit based on multi-neuromorphic behavior and brain-like computing system

Abstract

The invention discloses a neuron circuit and brain-like computing system based on multi-neuromorphic behaviors, and the neuron circuit maps an appreciation-Ross model to the field of physical circuits through a capacitance dynamic response mechanism and the cross-interval nonlinear characteristics of a metal-oxide semiconductor field effect transistor. Then the expanded appreciation-Ross model is realized through the design of a metal-oxide semiconductor field effect transistor; the neuron circuit comprises a membrane voltage circuit, a slow variable circuit and a recovery variable circuit. The membrane voltage circuit is used for receiving an input signal and accumulating membrane voltage; the slow variable circuit is used for accumulating a slow variable according to the membrane voltage and enabling the neuron circuit to enter a hyperpolarization stage after the slow variable is greater than a preset threshold value; the recovery variable circuit is used for outputting a recovery variable according to the film voltage delay and resetting the film voltage to a resting potential through the recovery variable.

Description

Technical Field

[0001] The present invention belongs to the technical field of brain-inspired computing and bionic circuits, and particularly relates to a neuron circuit and a brain-inspired computing system based on multi-neuromorphic behaviors. Background Art

[0002] Currently, artificial intelligence shows broad application prospects in fields such as pattern recognition, intelligent perception, and automatic control, posing higher requirements for high-efficiency, low-power, and integrable computing hardware. Traditional computing systems based on the von Neumann architecture face the storage wall and energy consumption bottleneck when dealing with brain-inspired tasks, and it is difficult to meet the requirements for real-time performance and energy efficiency ratio. Therefore, the brain-inspired computing system based on neuron circuits, as an effective implementation method of brain-inspired information processing, has become an important research direction to support neuromorphic intelligent computing systems.

[0003] At present, there are various implementation schemes for neuron circuits, but all of them have significant technical limitations. Traditional neuron circuits have obvious deficiencies in behavior patterns and usually can only simulate a single firing mode. This makes it impossible to dynamically adapt to diverse information processing requirements when dealing with complex neuromorphic computing tasks, severely restricting their application effects in scenarios such as intelligent perception and edge computing. In addition, for neuron circuits that can generate multiple neuromorphic behaviors, their circuit structures are complex and a large number of transistors are required to implement basic functions, significantly increasing the chip area and power consumption cost, further limiting the overall performance improvement of brain-inspired chips.

[0004] The traditional integrate-and-fire (IF) neuron circuit has a simple structure and is easy to integrate, but it can only simulate the accumulation and discharge of membrane voltage, with a single output behavior, and it is difficult to meet the requirements for diverse firing patterns in cognitive computing. The improved leaky integrate-and-fire (LIF) circuit, although introducing a leakage mechanism and enhancing biological plausibility, is still based on a simplified first-order model and cannot express key dynamic behaviors such as adaptive firing, bursting firing, and hyperpolarization, nor can it reflect physiological mechanisms such as sodium-potassium channels, with limited functions. Although complex models such as the Hodgkin–Huxley model (HH) and the Hindmarsh–Rose model (HR) can reproduce various neural activities, their mathematical expressions are complex and there is no direct correspondence with hardware circuit elements, making it difficult to achieve efficient and low-power integrated design. Summary of the Invention

[0005] In view of the deficiencies of existing neuron circuits in behavior diversity and hardware efficiency, the purpose of the present invention is to provide a neuron circuit and a brain-inspired computing system based on multi-neuromorphic behaviors, providing a solution with richer dynamic characteristics and higher energy efficiency ratio for the development of brain-inspired computing systems to meet the urgent needs of artificial intelligence applications for complex neuromorphic computing.

[0006] In a first aspect, the present invention provides a neuron circuit based on multi-neuromorphic behaviors, which includes a membrane voltage circuit, a slow variable circuit, and a recovery variable circuit; the membrane voltage circuit is used to receive an input signal and accumulate membrane voltage; the slow variable circuit is used to accumulate slow variables according to the membrane voltage and make the neuron circuit enter a hyperpolarization stage after the slow variable is greater than a preset threshold; the recovery variable circuit is used to delay the output of the recovery variable according to the membrane voltage and reset the membrane voltage to the resting potential through the recovery variable.

[0007] The membrane voltage circuit includes a membrane capacitor Cm and a positive feedback circuit; the positive feedback circuit includes three field effect transistors M1, M2, and M3; the gate of field effect transistor M1 is connected to the gate of field effect transistor M2, the drain of field effect transistor M1, and the drain of field effect transistor M3; one end of the membrane capacitor Cm is connected to the drain of field effect transistor M2, the gate of field effect transistor M3, and the input signal; the other end of the membrane capacitor Cm is grounded; the sources of field effect transistors M1 and M2 are connected to the power supply voltage; the source of field effect transistor M3 is grounded.

[0008] Preferably, the slow variable circuit includes an integrating capacitor Cu, a leakage resistor R, and two field effect transistors M4 and M5; the gate of field effect transistor M5 is connected to the gate of field effect transistor M1; the drain of field effect transistor M5 is connected to the gate of field effect transistor M4, one end of the integrating capacitor Cu, and one end of the leakage resistor R; the source of field effect transistor M4, the other end of the integrating capacitor Cu, and the other end of the leakage resistor R are all grounded; the drain of field effect transistor M4 is connected to the input signal; the source of field effect transistor M5 is connected to the power supply voltage.

[0009] Preferably, the recovery variable circuit includes a capacitor Ck and a cascaded push-pull feedback circuit; the cascaded push-pull feedback circuit includes five field effect transistors M6, M7, M8, M9, and M10; the drain of field effect transistor M6 is connected to the gates of field effect transistors M3, M7, and M8; the gate of field effect transistor M6 is connected to the drain of field effect transistor M9, the drain of field effect transistor M10, and one end of the capacitor Ck; the other end of the capacitor Ck is grounded; the drains of field effect transistors M7 and M8 are both connected to the gates of field effect transistors M9 and M10; the sources of field effect transistors M6, M8, and M10 are all grounded; the sources of field effect transistors M7 and M9 are both connected to the power supply voltage.

[0010] Preferably, the working process of this neuron circuit is as follows:

[0011] The membrane voltage circuit activates the positive feedback circuit when the input current is input and accumulates the membrane voltage ; when the membrane voltage increases, the recovery variable circuit delays the output of the recovery variable based on the membrane voltage ​ , and by restoring the variable to control the drain current of the field effect transistor M6 , so that the membrane voltage is reset to the resting potential; the slow variable circuit accumulates the slow variable of the action potential pulse through the current mirror when the membrane voltage is released , until the neuron circuit enters the hyperpolarization stage, the membrane voltage is at the resting potential, and the slow variable is released to the initial accumulation value through the leakage resistor R for the next cycle.

[0012] Preferably, the condition for determining that the neuron circuit enters the hyperpolarization stage is that the gate voltage of the field effect transistor M4 is greater than the threshold voltage of the field effect transistor M4.

[0013] Preferably, the width-to-length ratio of the field effect transistor M5 matches that of the field effect transistor M1 to form a current mirror.

[0014] Preferably, by adjusting the current mirror ratio and the parameters of the integration capacitor Cu and the leakage resistor R to control the duration of the resting state and the hyperpolarization period.

[0015] Preferably, the field effect transistors M1, M2, M5, M7, and M9 are P-type metal-oxide semiconductor field effect transistors; the field effect transistors M3, M4, M6, M8, and M10 are N-type metal-oxide semiconductor field effect transistors.

[0016] Preferably, the neuron model constituted by this neuron circuit is as follows:

[0017]

[0018] Wherein, is the membrane capacitance in the membrane voltage circuit; is the membrane voltage of the neuron; is the input current; is the drain current of the field effect transistor M2; is the drain current of the field effect transistor M6; is the drain current of the field effect transistor M4; and are the drain currents of the field effect transistors M9 and M10 respectively; is the restoration variable; is the slow variable; and are the energy storage capacitors of the restoration variable and the slow variable respectively; is the current mirror ratio value; is the derivative of the resistor R.

[0019] In a second aspect, the present invention provides a brain-inspired computing system, which includes a plurality of the above-mentioned neuron circuits; the brain-inspired computing system realizes the output of pulse sequences of various neuromorphic behaviors by adjusting the input current and leakage resistance R of each neuron circuit.

[0020] The beneficial effects of the present invention are as follows:

[0021] 1. By adjusting the input current and leakage resistance of the neuron circuit, the present invention can realize multiple neuromorphic behaviors, breaking through the limitations of existing circuits that only support single-behavior circuits, and improving the expression ability and functional flexibility of the neuromorphic computing system; at the same time, the present invention effectively simulates the firing process of the neuron membrane voltage through the switching of MOS transistors between multiple working intervals, meeting the computational requirements of the non-linear higher-order terms in neurons.

[0022] 2. The present invention can realize complex neural behaviors only by using fewer capacitors, resistors and MOS transistors. Compared with existing circuits with complex implementation and a large number of devices, the hardware implementation complexity is greatly reduced, and the complexity of the neuron circuit structure is reduced.

[0023] 3. Through the effective regulation of the working state of MOS transistors by capacitors and resistors, the present invention realizes the hyperpolarization process in biological neurons, improving the biological feature simulation ability of the circuit; at the same time, by adjusting the resistance parameters, the hyperpolarization duration can be flexibly controlled, thereby adjusting the output mode of neuromorphic behaviors, enabling the neuron circuit to have stronger input adaptation ability and improving the flexibility of behavior regulation. Description of the Drawings

[0024] Figure 1 is the circuit structure diagram of the present invention.

[0025] Figure 2 is the schematic diagram of the changes in membrane voltage, recovery variable and slow variable at different times in the present invention; among them, (a) is the schematic diagram of the change in membrane voltage; (b) is the schematic diagram of the change in recovery variable; (c) is the schematic diagram of the change in slow variable.

[0026] Figure 3 is the schematic diagram of the slow variable changing with the input current in the present invention.

[0027] Figure 4 is the schematic diagram of the membrane voltage changing with the input current in the present invention.

[0028] Figure 5 is the schematic diagram of the fast firing mode in the present invention.

[0029] Figure 6 is the schematic diagram of the slow firing mode in the present invention.

[0030] In the accompanying drawings: 1. Membrane voltage circuit; 2. Slow variable circuit; 3. Input signal; 4. Recovery variable circuit. Specific embodiments

[0031] The present invention will be further described below in conjunction with the accompanying drawings.

[0032] As Figure 1 shown, a neuron circuit based on multi-neuromorphic behavior includes a membrane voltage circuit 1, a slow variable circuit 2, and a recovery variable circuit 4. The membrane voltage circuit 1 is used to receive an input signal 3 and accumulate a membrane voltage, and accelerate the rise of the membrane voltage through a positive feedback mechanism to form a pulse spike; the membrane voltage circuit 1 includes a membrane capacitor Cm and a positive feedback circuit; the positive feedback circuit includes a field effect transistor M1, a field effect transistor M2, and a field effect transistor M3; the gate of the field effect transistor M1 is connected to the gate of the field effect transistor M2, the drain of the field effect transistor M1, and the drain of the field effect transistor M3; one end of the membrane capacitor Cm is connected to the drain of the field effect transistor M2, the gate of the field effect transistor M3, and the input signal, and the other end of the membrane capacitor Cm is grounded; the sources of the field effect transistors M1 and M2 are connected to the power supply voltage VDD; the source of the field effect transistor M3 is grounded.

[0033] In this embodiment, the field effect transistors M1 and M2 are PMOS transistors (P-type metal-oxide semiconductor field effect transistors); the field effect transistor M3 is an NMOS transistor (N-type metal-oxide semiconductor field effect transistor).

[0034] The slow variable circuit 2 is used to convert the action potential pulse (the drain current of the field effect transistor M5) into a charging current for the integration capacitor Cu, realize the step-by-step accumulation of the slow variable, and set the decay time constant through a leakage resistor; the slow variable circuit 2 includes an integration capacitor Cu, a leakage resistor R, a field effect transistor M4, and a field effect transistor M5. The field effect transistor M5 and the field effect transistor M1 form a current mirror, whose gates are interconnected and the aspect ratios are matched, and both operate in the saturation region to achieve accurate replication of the reference current; the drain of the field effect transistor M5 is connected to the gate of the field effect transistor M4, one end of the integration capacitor Cu, and one end of the leakage resistor R; the drain of the field effect transistor M4 is connected to the input signal; the source of the field effect transistor M4, the other end of the integration capacitor Cu, and the other end of the leakage resistor R are all grounded; the source of the field effect transistor M5 is connected to the power supply voltage VDD.

[0035] In this embodiment, the field effect transistor M4 is an NMOS transistor; the field effect transistor M5 is a PMOS transistor.

[0036] The recovery variable circuit 4 is used to receive the output signal of the membrane voltage circuit 1 and delay the output of the recovery variable, and reset the membrane voltage to the resting potential by controlling the drain current of the field effect transistor M6; the recovery variable circuit 4 includes a capacitor Ck and a cascaded push-pull feedback circuit; the cascaded push-pull feedback circuit includes field effect transistors M6, M7, M8, M9 and M10; the drain of the field effect transistor M6 is connected to the gates of the field effect transistors M3, M7 and M8; the gate of the field effect transistor M6 is connected to the drain of the field effect transistor M9, the drain of the field effect transistor M10, and one end of the capacitor Ck; the other end of the capacitor Ck is grounded; the drains of the field effect transistors M7 and M8 are both connected to the gates of the field effect transistors M9 and M10; the sources of the field effect transistors M6, M8 and M10 are all grounded; the sources of the field effect transistors M7 and M9 are both connected to the power supply voltage VDD.

[0037] In this embodiment, the field effect transistors M6, M8 and M10 are NMOS transistors; the field effect transistors M7 and M9 are PMOS transistors.

[0038] The HR neuron mathematical model is as follows:

[0039] (1)

[0040] (2)

[0041] (3)

[0042] Wherein, is the membrane potential; is the fast current; is the slow current; is the external stimulus current; is a constant for adjusting the discharge mode.

[0043] Formula (1) is the dynamic change of the membrane voltage, formula (2) is the recovery variable for resetting the pulse, and formula (3) is the slow variable for rhythmic modulation and pulse burst, thereby using the variables 、 and It is divided into the dynamic variables on the left side of the equation, representing the change of neuron state over time, and the functional variables on the right side of the equation, describing the mechanisms driving these changes. This separation directly corresponds to the basic electrical behavior. The time derivative operation in the dynamic variables is inherently consistent with the dynamic characteristics of the capacitor voltage, while the non-linear behavior in the functional variables can be achieved through the non-linear current characteristics of the transistor. Therefore, the dynamic variables can be mapped to capacitors, and the functional variables can be mapped to transistors, realizing the correspondence between the HR neuron mathematical model and the physical extended model. The specific mapping method is as follows:

[0044] The term in Equation (1) can be realized by the drain current generated by the field effect transistor M2 controlled by the membrane voltage . The operating state (subthreshold, saturation, linear) of the field effect transistor M2 causes the drain current to change exponentially, quadratically, and linearly, enabling the membrane voltage to quickly respond and drive the formation of spikes. In the extended HR model, due to the amplitude limitation of the hardware voltage supply, the non-linear term as the amplitude-limiting term is no longer needed. The non-linear current (drain current ) generated by the field effect transistor M6 replaces the in Equation (1). In the HR mathematical model, since itself is a negative value, a negative sign needs to be added before the drain current , that is . At the same time, the drain current of the field effect transistor M4 replaces the in Equation (1). According to the above replacements, the first-order dynamic response equation composed of the drain current of the field effect transistor and the membrane capacitor Cm in the membrane voltage circuit 1 realizes the mapping from Equation (1) to Equation (4). The equations are as follows:

[0045] (4)

[0046] The constant of the recovery variable in Equation (2) is replaced by GND, indicating that the baseline is 0. is replaced by the drain current of the field effect transistor M9. At the same time, the drain current of the field effect transistor M10 replaces the fast current . Based on the above replacements, the first-order dynamic response equation composed of the drain current and the capacitor Ck in the recovery variable circuit 4 realizes the mapping from (2) to (5). The equations are as follows:

[0047] (5)

[0048] The constant in formula (3) Replace it with a capacitor value to adjust the response speed of slow variables. Using GND instead means the resting potential is 0. use Replacement; among them, Represents the current mirror ratio value. Constant This is achieved through a linear resistor structure. This structure combines the recovery variable and resistors To achieve the function of slow-changing dynamic attenuation. Based on the above substitution, the first-order dynamic response equation composed of the drain current of the field effect transistor in the slow-variable circuit 2 and the capacitor Cu realizes the mapping from (3) to (6), and the formula is as follows:

[0049] (6)

[0050] Therefore, the HR neuron model is extended as follows:

[0051] (7)

[0052] in, is the membrane capacitance in the membrane voltage circuit; is the membrane voltage of the neuron; is the input current; is the drain current of field effect transistor M2; is the drain current of field effect transistor M6; is the drain current of field effect transistor M4; and are the drain currents of field effect transistor M9 and field effect transistor M10 respectively; To restore the variables; is a slow variable; and They are the energy storage capacitors for recovery variables and slow variables respectively; is the current mirror ratio value; is the derivative of resistance and is used to implement the leakage function.

[0053] The neuron circuit works as follows:

[0054] Membrane voltage circuit 1 at input current The positive feedback circuit is activated when input is applied, causing the membrane voltage to Rapid accumulation and accelerated membrane voltage through a positive feedback mechanism The membrane voltage circuit 1 achieves a rapid response to the input signal and an efficient generation of pulse spikes through the synergistic effect of membrane capacitance integration and positive feedback.

[0055] Recovery variable circuit 4 in membrane voltage When it increases rapidly, the output signal of the membrane voltage circuit is received through the cascaded push-pull feedback circuit, and the received signal is delayed and output to restore the variable through the cascaded push-pull feedback circuit ; Restoring variable By controlling the drain current of the field effect transistor M6 Reset the membrane voltage to the resting potential. The membrane voltage circuit 1 starts to accumulate the membrane voltage again.

[0056] The slow variable circuit 2 converts the action potential pulse into the charging current of the capacitor Cu through the current mirror every time the membrane voltage is released, realizing the slow variable (the gate voltage of the field effect transistor M4) The stepped accumulation of; At the same time, a leakage circuit is formed by juxtaposing the integration capacitor Cu and the leakage resistor R, and the decay time constant is set to realize the leakage and energy storage of the slow variable Of the slow variable When the slow variable accumulates to the threshold voltage of the field effect transistor M4, the hyperpolarization mechanism of the neuron is triggered, and the resting state duration and hyperpolarization period can be controlled by adjusting the current mirror ratio And the parameters of the integration capacitor Cu and the leakage resistor R to realize the dynamic regulation of the periodic accumulation-discharge process of the neuron membrane voltage.

[0057] Use multiple neuron circuits to form a brain-like computing system, and realize the pulse sequence output of various neuromorphic behaviors by adjusting the input current of each neuron circuit and the leakage resistor R.

[0058] Such as Figure 2 As shown, when the input signal is , the membrane capacitor Cm accumulates charge, and the membrane voltage Rises and serves as a control signal to drive the field effect transistor M3, triggering the positive feedback loop to accelerate the rise of the membrane voltage Of the rising process; The membrane voltage Cooperates with the capacitor Ck through the cascaded push-pull circuit to generate a hysteretic restored variable signal , the restored variable signal Reset the rapidly rising membrane voltage to the resting potential by controlling the gate of the field effect transistor M6; The slow variable circuit 2 accumulates the integration capacitor Cu through the current mirror during each membrane voltage release process. After three accumulations, the slow variable Accumulates to the threshold voltage of the field effect transistor M4, and the neuron circuit enters the hyperpolarization stage, then the membrane voltage is in the long-term resting potential until the slow variable is slowly released to the initial value of the accumulation through the leakage resistor R, and a new round of cycle begins.

[0059] Such as Figure 3 As shown, the slow variable With the input current rises steadily, and this rise has a clear mapping relationship. Specifically, under different input current conditions, the slow variable gradually increases during the membrane voltage accumulation period. Each time the membrane voltage is released, the slow variable rises by one step, and when the threshold voltage is reached, the hyperpolarization mechanism is triggered to make the neuron enter the long-term resting potential state.

[0060] As Figure 4 shown, when the input signals are respectively , , , , , , , , the neuron circuit receives the input current. The positive feedback circuit is quickly activated with the accumulation of the membrane voltage and accelerates the increase of the membrane voltage; the increased membrane voltage is reset to the resting state by the hysteresis signal generated by the recovery variable; the slow variable circuit 2 accumulates the capacitor Cu through the current mirror during each membrane voltage release process. Once the threshold voltage of the field effect transistor M4 is reached, the neuron circuit immediately enters the hyperpolarization stage, making the membrane voltage in the long-term resting potential state until the slow variable slowly releases to the initial accumulation value through the leakage resistor R, and so on in a cycle. As the input signal increases, the longer the slow variable hyperpolarization process leads to the long-term resting state time and the lower the dissipated energy, resulting in the change of the membrane voltage burst firing behavior with the stimulus intensity and presenting 8 different neural morphological behaviors.

[0061] As Figure 5 shown, when the resistance value in the slow variable circuit 2 is 0.5 MΩ and the input current is 30 μA, the neuron circuit is in the fast emission mode. The membrane capacitance starts to accumulate, and the accumulated membrane voltage acts as a control signal to control the field effect transistor M3, and then activates the positive feedback circuit to accelerate the increase of the membrane voltage; the recovery variable signal resets the rapidly rising membrane voltage to the resting potential through the control of the field effect transistor M6; the slow variable accumulates to the threshold voltage of the field effect transistor M4, making the neuron circuit enter the hyperpolarization stage.

[0062] As Figure 6 shown, when the resistance value in the slow variable circuit 2 is 2 MΩ and the input current is 30 μA, the neuron circuit is in the slow emission mode; increasing the resistance value increases the time constant of the slow variable circuit 2, making the slow variable dissipate at a lower speed through the resistor and increasing the time of the hyperpolarization stage of the neuron circuit. By adjusting the resistance value, the continuous adjustment of the emission frequency is realized, constituting the frequency modulation characteristic of the neuron circuit.

[0063] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively detailed to clearly explain the inventor's invention verification process, but it is not to be construed as a limitation on the protection scope of the present invention patent. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and optimizations can be made, and these all fall within the protection scope of the present application.

Claims

1. A neuron circuit based on multi-neuromorphic behavior, comprising a membrane voltage circuit (1), a slow variable circuit (2) and a recovery variable circuit (4); the membrane voltage circuit (1) is used to receive an input signal (3) and accumulate a membrane voltage; the slow variable circuit (2) is used to accumulate a slow variable according to the membrane voltage, and make the neuron circuit enter a hyperpolarization phase after the slow variable is greater than a preset threshold value; The recovery variable circuit (4) is used to delay the output of the recovery variable according to the membrane voltage, and reset the membrane voltage to the resting potential through the recovery variable; It is characterized in that: The membrane voltage circuit includes a membrane capacitor Cm and a positive feedback circuit; the positive feedback circuit includes three field effect transistors M1, M2, and M3; the gate of field effect transistor M1 is connected to the gate of field effect transistor M2, the drain of field effect transistor M1, and the drain of field effect transistor M3; one end of the membrane capacitor Cm is connected to the drain of field effect transistor M2, the gate of field effect transistor M3, and the input signal; the other end of the membrane capacitor Cm is grounded; the sources of field effect transistors M1 and M2 are connected to the power supply voltage; The source of field effect transistor M3 is grounded.

2. A neuron circuit based on multi-neuromorphic behavior according to claim 1, characterized in that: The slow variable circuit includes an integration capacitor Cu, a leakage resistor R, and two field effect transistors M4, M5; the gate of field effect transistor M5 is connected to the gate of field effect transistor M1; the drain of field effect transistor M5 is connected to the gate of field effect transistor M4, one end of the integration capacitor Cu, and one end of the leakage resistor R; the source of field effect transistor M4, the other end of the integration capacitor Cu, and the other end of the leakage resistor R are all grounded; the drain of field effect transistor M4 is connected to the input signal; the source of field effect transistor M5 is connected to the power supply voltage.

3. The neuron circuit based on multi-neuromorphic behavior according to claim 2, characterized in that: The recovery variable circuit includes a capacitor Ck and a cascaded push-pull feedback circuit; the cascaded push-pull feedback circuit includes five field effect transistors M6, M7, M8, M9, and M10; the drain of field effect transistor M6 is connected to the gates of field effect transistors M3, M7, and M8; the gate of field effect transistor M6 is connected to the drains of field effect transistors M9 and M10, and one end of the capacitor Ck; the other end of the capacitor Ck is grounded; the drains of field effect transistors M7 and M8 are both connected to the gates of field effect transistors M9 and M10; the sources of field effect transistors M6, M8, and M10 are all grounded; the sources of field effect transistors M7 and M9 are both connected to the power supply voltage.

4. A neuron circuit based on multi-neuromorphic behavior according to claim 3, characterized in that: The working process of this neuron circuit is as follows: The membrane voltage circuit activates the positive feedback circuit upon input of an input current to accumulate the membrane voltage ; The recovery variable circuit delays the output of the recovery variable based on the membrane voltage when the membrane voltage increases, and controls the drain current of the field effect transistor M6 through the recovery variable, so as to reset the membrane voltage to the resting potential; when increasing, based on the membrane voltage delays the output of the recovery variable and through the recovery variable controls the drain current of the field effect transistor M6 to reset the membrane voltage to the resting potential; The slow variable circuit accumulates the action potential pulse slow variable through a current mirror when the membrane voltage is released , until the neuron circuit enters the hyperpolarization phase and the membrane voltage is at the resting potential, and the slow variable is released to the initial accumulation value through the leakage resistor R for the next cycle.

5. A neuron circuit based on multi-neuromorphic behavior according to claim 4, characterized in that: The condition for determining that the neuron circuit enters the hyperpolarization stage is that the gate voltage of field effect transistor M4 is greater than the threshold voltage of field effect transistor M4.

6. A neuron circuit based on multi-neuromorphic behavior according to claim 2, characterized in that: The field effect transistor M5 and the field effect transistor M1 have a matching width-to-length ratio and form a current mirror.

7. A neuron circuit based on multi-neuromorphic behavior according to claim 6, characterized in that: By adjusting the current mirror ratio and controlling the parameters of the integration capacitor Cu and the leakage resistor R to control the resting state duration and the hyperpolarization period.

8. A neuron circuit based on multi-neuromorphic behavior according to claim 3, characterized in that: Field effect transistors M1, M2, M5, M7, and M9 are P-type metal-oxide-semiconductor field effect transistors; field effect transistors M3, M4, M6, M8, and M10 are N-type metal-oxide-semiconductor field effect transistors.

9. A neuron circuit based on multi-neuromorphic behavior according to claim 3, characterized in that: The neuron model constituted by this neuron circuit is as follows: ； Among them, is the membrane capacitance in the membrane voltage circuit; is the membrane voltage of the neuron; is the input current; is the drain current of the field effect transistor M2; is the drain current of the field effect transistor M6; is the drain current of the field effect transistor M4; and are the drain currents of the field effect transistors M9 and M10 respectively; is the recovery variable; is the slow variable; and are the energy storage capacitors of the recovery variable and the slow variable respectively; is the current mirror ratio value; is the derivative of the resistor R.

10. A brain-inspired computing system, characterized in that, It includes multiple neuron circuits with multiple neuromorphic behaviors as described in any one of claims 2-9; this type of brain computing system realizes the output of pulse sequences with multiple neuromorphic behaviors by adjusting the input current and leakage resistor R of each neuron circuit.

Images