Silver-gold alloy bump structure and forming method thereof

Abstract

The embodiment of the invention provides a silver-gold alloy bump structure and a forming method thereof. The method comprises the following steps: providing a semiconductor device; sequentially forming a first seed layer and a second seed layer on the functional surface of the semiconductor device, wherein the second seed layer is an Au seed layer; forming a silver-gold alloy bump on the second seed layer; carrying out annealing treatment on the silver-gold alloy bump and the second seed layer; and removing a part of the first seed layer and a part of the second seed layer through an etching process, so that the first seed layer and the second seed layer are only located between the silver-gold alloy bump and the semiconductor device. Before the seed layer is etched, the silver-gold alloy bump and the Au seed layer are subjected to annealing treatment, so that the hardness of the silver-gold alloy bump is ensured, the lattice structure of Au in the Au seed layer is changed through annealing treatment, the etching rate and effect are improved, the problem of gold residue is solved, and the electrical property and reliability of the silver-gold bump structure are improved.

Description

Technical Field

[0001] Embodiments of the present disclosure belong to the technical field of semiconductor packaging, and particularly relate to a silver-gold alloy bump structure and a method for forming the same. Background Art

[0002] In advanced packaging technologies, silver-gold alloy bumps are widely used in the interconnection of integrated circuits due to their good electrical conductivity and stable performance. During the manufacturing process of silver-gold alloy bumps, Ti+Au or TiW+Au is usually used as the seed layer to enhance the adhesion between the electroplating solution and the wafer substrate and ensure the uniformity and quality of the electroplated layer. However, after electroplating, the photoresist and the seed layer need to be stripped and etched to form the final bump structure.

[0003] During the stripping and etching process, due to the high stability and corrosion resistance of Au (gold), it is often difficult to completely etch it clean, resulting in the problem of Au residue. The Au residue not only affects the electrical performance and reliability of the bump structure, but may also have an adverse impact on subsequent packaging processes. In addition, since the Au seed layer is a dense metal film deposited by PVD sputtering, the electroplated silver-gold bump structure is relatively more porous, and the etching rates of Au and Ag in the silver-gold bump are much higher than that of Au in the Au seed layer, resulting in over-etching of the silver-gold bump or incomplete etching of the Au seed layer. The Au residue not only affects the electrical performance and reliability of the bump structure, but may also have an adverse impact on subsequent packaging processes.

[0004] In view of the above problems, it is necessary to propose a silver-gold alloy bump structure and a method for forming the same that are reasonably designed and effectively solve the above problems. Summary of the Invention

[0005] Embodiments of the present disclosure aim to at least solve one of the technical problems existing in the prior art, and provide a silver-gold alloy bump structure and a method for forming the same.

[0006] One aspect of the embodiments of the present disclosure provides a method for forming a silver-gold alloy bump structure, the method comprising:

[0007] Providing a semiconductor device;

[0008] Successively forming a first seed layer and a second seed layer on the functional surface of the semiconductor device, wherein the second seed layer is an Au seed layer;

[0009] Forming a silver-gold alloy bump on the second seed layer;

[0010] Performing an annealing treatment on the silver-gold alloy bump and the second seed layer;

[0011] Remove a part of the first seed layer and a part of the second seed layer through an etching process, such that the first seed layer and the second seed layer are only located between the silver-gold alloy bump and the semiconductor device.

[0012] Optionally, the annealing treatment of the silver-gold alloy bump structure and the second seed layer includes:

[0013] Continuously heat the silver-gold alloy bump and the second seed layer to a preset annealing time at a preset annealing temperature;

[0014] Cool the heated silver-gold alloy bump and the second seed layer.

[0015] Optionally, the range of the preset annealing temperature is 270 °C to 300 °C, and the preset annealing time is greater than 15 min.

[0016] Optionally, the cooling method adopts natural cooling or rapid cooling.

[0017] Optionally, a wet etching method is adopted to remove a part of the first seed layer and a part of the second seed layer.

[0018] Optionally, the time range of the wet etching is 5 min to 10 min.

[0019] Optionally, the time interval between the completion of the annealing treatment and the start of the etching process is less than 8 hours.

[0020] Optionally, the forming of the silver-gold alloy bump on the second seed layer includes:

[0021] Form a photoresist layer on the second seed layer;

[0022] Pattern the photoresist layer to form an opening window on the photoresist layer;

[0023] Adopt an electroplating process to form the silver-gold alloy bump in the opening window.

[0024] Optionally, the forming of the first seed layer and the second seed layer in sequence on the functional surface of the semiconductor device includes:

[0025] Adopt a sputtering process to form the first seed layer and the second seed layer in sequence on the functional surface of the semiconductor device; wherein, the first seed layer is a Ti seed layer or a TiW seed layer.

[0026] Another aspect of the embodiments of the present disclosure provides a silver-gold alloy bump structure, which is prepared and formed by the method described above.

[0027] The silver-gold alloy bump structure and its forming method according to the embodiments of the present disclosure anneal the silver-gold alloy bump and the Au seed layer before etching the seed layer. While ensuring the hardness of the silver-gold alloy bump, the annealing treatment changes the lattice structure of Au in the Au seed layer, improving the etching rate and effect, solving the problem of gold residue, and thus improving the electrical performance and reliability of the silver-gold bump structure. Compared with the method of forming a silver-gold alloy bump structure in the prior art, this method does not require significant modification of the existing process or additional equipment investment. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. is a schematic flow chart of a method for forming a silver-gold alloy bump structure according to an embodiment of the present disclosure;

[0029] Figures 2 to 8 FIG. is a process schematic diagram of a method for forming a silver-gold alloy bump structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the following further describes the embodiments of the present disclosure in detail with reference to the drawings and specific embodiments.

[0031] The main process of conventionally forming a silver-gold alloy bump structure is: sputtering a seed layer → photoresist coating, exposure, and development → gold electroplating → photoresist stripping → etching → annealing, etc. Since the Au seed layer is denser than the silver-gold alloy coating, the etching solution is more difficult to penetrate into the metal layer, resulting in an overly slow etching rate of the Au seed layer by the etching solution, and it is often difficult to completely etch it clean, leading to the problem of gold residue.

[0032] In response to this, as Figure 1 shown, one aspect of the embodiments of the present disclosure provides a method S100 for forming a silver-gold alloy bump structure, and the method S100 includes:

[0033] S110. Provide a semiconductor device.

[0034] As Figure 2 shown, provide a semiconductor device 200. Specifically, in this embodiment, the semiconductor device 200 is described by taking a chip as an example. As Figure 2 shown, a solder pad 210 and a passivation layer 220 are provided on the functional surface of the chip, and among them, the passivation layer 220 has an opening corresponding to the solder pad 210.

[0035] S120. Sequentially form a first seed layer and a second seed layer on the functional surface of the semiconductor device, where the second seed layer is an Au seed layer.

[0036] Specifically, as Figure 3As shown, a first seed layer 110 and a second seed layer 120 are sequentially sputtered on the functional surface of the semiconductor device 200 through a PVD sputtering process. The two formed seed layers are electrically connected to the bonding pads 210 of the chip.

[0037] Among them, in this embodiment, the first seed layer 110 can adopt a Ti seed layer or a TiW seed layer, and the second seed layer 120 can adopt an Au seed layer. The thickness of the first seed layer 110 is 0.32 μm, and the thickness of the second seed layer 120 is 0.08 μm.

[0038] S130. Form silver-gold alloy bumps on the second seed layer.

[0039] As Figure 4 shown, first, a photoresist layer 130 is coated on the second seed layer 120. Among them, the photoresist layer 130 can adopt a positive photoresist or a negative photoresist, which can be selected according to actual needs, and this embodiment does not make specific limitations.

[0040] Secondly, the photoresist layer 130 is patterned to form an opening 131 on the photoresist layer 130.

[0041] Specifically, as Figure 5 shown, a mask plate is provided, and the mask plate is placed above the photoresist layer 130. Using the mask plate as a mask, the photoresist layer 130 is exposed and developed to form an opening 131 at the position corresponding to the bonding pad 210 on the photoresist layer 130.

[0042] Thirdly, as Figure 6 shown, an electroplating process is used to electroplate a silver-gold alloy bump 140 in the opening 131. After that, the remaining photoresist layer 130 is removed.

[0043] S140. Anneal the silver-gold alloy bumps and the second seed layer.

[0044] Specifically, as Figure 7 shown, the silver-gold alloy bump 140 and the second seed layer 120 are continuously heated to a preset annealing time at a preset annealing temperature.

[0045] The heated silver-gold alloy bump 140 and the second seed layer 120 are cooled. Among them, the cooling method can adopt natural cooling or rapid cooling. Preferably, in order to meet the hardness requirements of the silver-gold alloy bump 140, a rapid cooling method can be adopted for cooling, such as cooling methods such as inert gas purging, water cooling, and freezing.

[0046] Further, in this embodiment, the range of the preset annealing temperature is 270°C to 300°C, and the preset annealing time is greater than 15 min. Preferably, in this embodiment, the preset annealing temperature is set to 280°C, and the specific reasons are as follows:

[0047] 1) The annealing process has temperature requirements for improving the etching effect. When the temperature is lower than 270°C, the effect of improving etching cannot be achieved well; 2) Since the silver-gold alloy bump structure has hardness requirements, setting the preset annealing temperature to 280°C can meet the hardness requirements of the silver-gold alloy bump structure; 3) The existing machine can withstand a temperature of 290°C. According to the window conditions, the preset annealing temperature is set to 280°C.

[0048] Etching preferentially proceeds along grain boundaries. If the Au grain size is larger, the etching rate is slower. The silver-gold alloy bumps 140 formed by the electroplating process originally have smaller grains. High-temperature annealing of the silver-gold alloy bumps 140 can cause the silver-gold alloy bumps 140 to recrystallize, and the grains gradually grow. The larger the grains, the fewer the grain boundaries (the gaps between particles), and it is more difficult for the etching solution to penetrate and corrode. Therefore, after high-temperature annealing and then etching, the etching rate of the silver-gold alloy bumps 140 becomes slower.

[0049] The Au seed layer is formed by the sputtering process. The Au seed layer itself has larger grains. During the high-temperature annealing process, the base material (such as the TiW layer) will interfere with the crystal growth of Au, resulting in the Au grains being forced to "follow" the base structure to rearrange (epitaxial crystallization), and the grains become smaller instead. The smaller the grains, the more grain boundaries, and the easier it is for the etching solution to penetrate and corrode. Therefore, when etching the Au seed layer after high-temperature annealing, the etching rate becomes faster.

[0050] In this embodiment, the preset annealing temperature is set to 270°C to 300°C, and the preset annealing time is set to be greater than 15 min. While ensuring the hardness of the silver-gold alloy bumps, the lattice structure of Au in the Au seed layer is changed by annealing treatment, improving the etching rate and effect, and solving the problem of gold residue.

[0051] S150. Remove part of the first seed layer and part of the second seed layer through an etching process, so that the first seed layer and the second seed layer are only located between the silver-gold alloy bump and the semiconductor device.

[0052] Specifically, as Figure 8 shown, in this embodiment, a wet etching method is used to remove part of the first seed layer 110 and part of the second seed layer 120, so that the first seed layer 110 and the second seed layer 120 are only located between the silver-gold alloy bump 140 and the semiconductor device 200, preventing short circuits. Among them, the wet etching method can adopt the commonly used existing wet etching method, which will not be elaborated here.

[0053] Exemplarily, in this embodiment, the time range of wet etching is 5 min to 10 min. Preferably, the time of wet etching is 5 min.

[0054] Exemplarily, in this embodiment, the time interval between the completion of the annealing process and the start of the etching process is less than 8 hours. Specifically, if the sample is left standing for a long time after annealing, the Au seed layer will recrystallize, resulting in a larger grain size, a slower etching rate of the Au seed layer, and Au residue.

[0055] As shown in Table 1, it is the etching condition of the Au seed layer when the time interval between annealing and etching is different. It can be seen from Table 1 that under the condition of annealing at 280 °C and etching for 5 min, there is no Au residue in the Au seed layer when the time interval between annealing and etching is 1 h, there is slight Au residue in the Au seed layer when the time interval between annealing and etching is 8 h, and there is obvious Au residue in the Au seed layer when the time interval between annealing and etching is 12 h. It can be seen from Table 1 that in order to ensure no Au residue in the etched Au seed layer, the time interval between the completion of the annealing process and the start of the etching process needs to be set to less than 8 hours.

[0056] Table 1 Etching condition of Au seed layer when the time interval between annealing and etching is different

[0057]

[0058] For the silver-gold alloy bump structure and its forming method according to the embodiments of the present disclosure, when forming the silver-gold alloy bump structure, the silver-gold alloy bump and the Au seed layer are annealed before etching the seed layer. While ensuring the hardness of the silver-gold alloy bump, the lattice structure of Au in the Au seed layer is changed by the annealing process, improving the etching rate and effect, solving the problem of Au residue, thereby improving the electrical performance and reliability of the silver-gold bump structure; compared with the method of forming a silver-gold alloy bump structure in the prior art, this method does not require a large modification of the existing process or an additional investment in equipment.

[0059] Another aspect of the embodiments of the present disclosure provides a silver-gold alloy bump structure, which is prepared by using a method S100 for forming a silver-gold alloy bump structure described above. The specific steps of the method S100 for forming a silver-gold alloy bump structure have been described in detail above and will not be elaborated here.

[0060] The silver-gold alloy bump structure according to the embodiments of the present disclosure is prepared by using the method for forming a silver-gold alloy bump structure described above, solving the problem of Au residue in the silver-gold alloy bump structure, thereby improving the electrical performance and reliability of the silver-gold bump structure.

[0061] It is understandable that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the embodiments of the present disclosure.

Claims

1. A method for forming a silver-gold alloy bump structure, characterized in that, The method includes: providing a semiconductor device; successively forming a first seed layer and a second seed layer on a functional surface of the semiconductor device, wherein the second seed layer is an Au seed layer; forming a silver-gold alloy bump on the second seed layer; annealing the silver-gold alloy bump and the second seed layer; removing a part of the first seed layer and a part of the second seed layer by an etching process, such that the first seed layer and the second seed layer are only located between the silver-gold alloy bump and the semiconductor device.

2. The method according to claim 1, characterized in that The annealing of the silver-gold alloy bump structure and the second seed layer includes: continuously heating the silver-gold alloy bump and the second seed layer to a preset annealing time at a preset annealing temperature; cooling the heated silver-gold alloy bump and the second seed layer.

3. The method according to claim 2, wherein The range of the preset annealing temperature is 270°C to 300°C, and the preset annealing time is greater than 15 min.

4. The method according to claim 2, wherein The cooling method adopts natural cooling or rapid cooling.

5. The method according to any one of claims 1 to 4, characterized in that, A wet etching method is adopted to remove a part of the first seed layer and a part of the second seed layer.

6. The method according to claim 5, wherein The time range of the wet etching is 5 min to 10 min.

7. The method according to any one of claims 1 to 4, characterized in that, The time interval between the completion of the annealing treatment and the start of the etching process is less than 8 hours.

8. The method according to any one of claims 1 to 4, characterized in that, The forming of the silver-gold alloy bump on the second seed layer includes: forming a photoresist layer on the second seed layer; patterning the photoresist layer to form a window opening on the photoresist layer; forming the silver-gold alloy bump in the window opening by an electroplating process.

9. The method according to any one of claims 1 to 4, characterized in that, The successively forming of the first seed layer and the second seed layer on the functional surface of the semiconductor device includes: successively forming the first seed layer and the second seed layer on the functional surface of the semiconductor device by a sputtering process; wherein the first seed layer is a Ti seed layer or a TiW seed layer.

10. A silver-gold alloy bump structure, characterized in that, Prepared and formed by the method according to any one of claims 1 to 9.

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