FPGA-based strong current system real-time monitoring fault intelligent processing system

Abstract

The invention relates to the technical field of power system monitoring and protection, and discloses an FPGA (Field Programmable Gate Array)-based strong current system real-time monitoring fault intelligent processing system, which comprises a pulse coding module used for converting a monitored voltage or current signal into a time domain pulse sequence; the hardware pulse neural network module is used for processing the pulse sequence to generate a local early warning state vector; the distributed consensus engine module is used for generating a global early warning state vector through consensus in combination with the local vectors of the plurality of nodes; the parameter adaptive adjustment module is used for adjusting the response characteristics of the neural network according to the global vector feedback; and the collaborative decision-making and intelligent control module is used for executing a collaborative strategy to process potential faults when the global early warning reaches a threshold value. According to the invention, weak fault precursor can be detected with extremely low delay and high sensitivity, and the global reliability and intelligent processing capability for coping with systematic risks are improved through distributed cooperation.

Description

Technical Field

[0001] The present invention relates to the technical field of power system monitoring and protection, and specifically to a real-time monitoring and fault intelligent processing system for high-voltage power systems based on FPGA. Background Art

[0002] The security and stability of high-voltage power networks are of utmost importance. In the power grid, the precursor signals of early faults caused by equipment aging and the like are weak and fleeting. If not captured in real time and accurately identified, they are extremely likely to evolve into cascading faults.

[0003] Existing technical solutions generally adopt architectures based on digital signal processors (DSPs) or general-purpose processors (CPUs), perform feature analysis and fault judgment through high-speed sampling and relying on software algorithms. In some advanced applications, data from multiple monitoring points is uploaded to a central server for comprehensive analysis.

[0004] However, this technical path has inherent defects. Its software-based serial processing mode brings significant delays and is difficult to meet the real-time response requirements for microsecond-level transient disturbances. At the same time, its analysis method focuses on signal amplitudes and is not sensitive enough to complex time-series dynamic information that can better characterize the fault evolution process. More critically, existing devices are mostly deployed in a centralized or isolated manner, lacking an efficient real-time information sharing and consensus mechanism among monitoring points, resulting in difficulty in correlatively analyzing multi-point anomalies from a global perspective and making rapid collaborative judgments and controls on global risks.

[0005] Compared with the prior art:

[0006] After retrieval, the invention patent with the Chinese publication number CN118377644B discloses a method and system for quickly improving CPU fault diagnosis based on FPGA. This technology uses FPGA as an external monitoring unit, and judges whether the CPU is stuck or faulty by real-time monitoring of the watchdog signal interval, temperature, utilization rate of the CPU, and core dump logs received through the UART port. When a fault is detected, the FPGA is responsible for transferring detailed log information from the internal BRAM to the external SPI FLASH for permanent storage, then safely resetting the CPU by controlling the watchdog chip, and providing the fault log for analysis to the CPU after restart.

[0007] The technical comparison between the above application and the present application is as follows:

[0008] This application discloses a method and system for quickly improving CPU fault diagnosis based on FPGA in the field of computer hardware and system diagnosis technology. Its core is to use FPGA as an external monitoring unit for the CPU, and the problem to be solved is how to effectively save the on-site log and perform a safe restart after the CPU gets stuck or crashes. The object of this technology is the operating state of the CPU, and the data processed are digital logic signals such as watchdog signals and system logs. Its technical means are based on state machine logic and the caching and transfer of logs.

[0009] This application is a fault prevention and intelligent processing system for high-voltage power systems. Its core is to utilize the parallel computing ability of FPGA and the pulse neural network module technology to solve the problem that weak and transient early fault precursor signals in the power grid are difficult to be captured in real time and accurately identified. The objects of this application are physical analog signals such as voltage and current in the power grid, and complex time-series pattern recognition is carried out through pulse coding and hardware pulse neural networks. More importantly, this application proposes a distributed consensus mechanism, aiming to fuse information from multiple monitoring points to form a global judgment and perform predictive collaborative control, belonging to the category of active prevention and system-level collaboration.

[0010] Although both use FPGA, there are essential differences in the application field, technical problems solved, core technical means, and system objectives. This application is a passive and reactive fault diagnosis for a single computing unit; this application is a predictive and active fault precursor analysis and collaborative processing system for the entire high-voltage power network.

[0011] After retrieval, the invention patent with Chinese publication number CN114610551A discloses a method for implementing a dual-machine hot standby system based on FPGA fault detection. This technology integrates FPGA modules on the main and slave computers respectively to achieve millisecond-level rapid detection of hardware states such as voltage, temperature, power-on timing, and software states such as operating system interrupt response and key processes. When the host fails, its FPGA or the slave FPGA can quickly judge and trigger an IP address migration, enabling the slave to take over the work, thus realizing a faster system hot standby switch than the traditional software heartbeat scheme.

[0012] The technical comparison between the above application and this application is as follows:

[0013] This application discloses a dual-machine hot standby solution applied in the field of fault detection. Its technical core is to use FPGA as a hardware monitoring unit to solve the problem of how to quickly switch to the backup server after the main server in the computer system has a hardware or software crash. This solution realizes millisecond-level fault judgment and service takeover by monitoring deterministic signals such as interrupt response and hardware sensor values, and its goal is to ensure the continuity of services.

[0014] This application is a fault precursor monitoring and intelligent processing system applied to the high-voltage power system. Its technical core is to use FPGA to implement a pulsed neural network module to deeply analyze complex analog waveforms such as voltage and current in the power grid, aiming to identify weak and uncertain precursor characteristics before a fault occurs. This application does not focus on backup switching after equipment downtime, but rather on predicting and locating potential faults in the power grid through collaborative analysis and consensus judgment of distributed monitoring points, belonging to an active and predictive security guarantee technology.

[0015] Therefore, there are essential differences between the two in terms of application scenarios, technical contradictions to be solved, and core implementation mechanisms. That application is oriented to the high availability of information systems and is a rapid response mechanism after a fault occurs; this application is oriented to the power physical system and is a precursor warning and collaborative prevention mechanism before a fault occurs.

[0016] After retrieval, the invention patent with Chinese publication number CN112101517B discloses an FPGA implementation method based on a piecewise linear pulsed neuron network. The core of this technology lies in solving how to minimize the loss of the biodynamic characteristics of the neuron model while maintaining low hardware resource consumption and high computing efficiency when hardwareizing a general pulsed neural network. For this purpose, it proposes to adopt a two-dimensional piecewise linear pulsed neuron model and elaborates on the specific circuit implementation scheme of mapping this specific neuron model and its network topology to FPGA through discretization processing, designing pipeline arithmetic logic, etc. Its essence is a basic method for the hardware implementation of neural networks.

[0017] The technical solution of this application is a fault precursor monitoring and intelligent processing system applied to the high-voltage power system. Its technical core is a pulsed neural network implemented using FPGA to deeply analyze and identify features of complex analog waveforms such as voltage and current in the power system. The focus of this application is not the implementation method of the neural network itself, but rather to construct a collaborative monitoring system composed of distributed monitoring points, and through data analysis and consensus judgment of each monitoring point, to achieve the prediction and location of weak and non-deterministic precursor characteristics before potential faults occur in the power grid, which is a predictive security guarantee technology.

[0018] Therefore, there are essential differences between the two in terms of technical levels and problems to be solved. That application belongs to the field of neural network hardware implementation, and it is committed to providing a more efficient and realistic general pulsed neural network hardware construction module, focusing on the mapping method from the model to the circuit. This application is a specific engineering application system that uses the pulsed neural network as the core analysis tool and applies it to the specific scenario of power physical system security monitoring. Its innovation lies in the overall architecture of the system and the application mode of using the pulsed neural network for fault precursor analysis.

[0019] Therefore, the present invention proposes a real-time monitoring and fault intelligent processing system for high-voltage systems based on FPGA to solve the deficiencies of the prior art. Summary of the Invention

[0020] In view of the deficiencies of the prior art, the present invention provides a real-time monitoring and fault intelligent processing system for high-voltage systems based on FPGA, which solves the problems of high processing delay, insufficient feature extraction, and insufficient multi-node collaborative decision-making ability in the existing FPGA-based high-voltage system monitoring when facing non-linear and transient complex fault precursors.

[0021] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0022] The first aspect of the present invention provides a real-time monitoring and fault intelligent processing system for high-voltage systems based on FPGA, which includes:

[0023] A pulse coding module, a hardware pulse neural network module, a distributed consensus engine module, a parameter adaptive adjustment module, and a collaborative decision-making and intelligent control module;

[0024] The pulse coding module serves as the signal input stage, and its output is connected to the hardware pulse neural network module. The output of the hardware pulse neural network module is connected to the distributed consensus engine module. The output of the distributed consensus engine module is divided into two paths, which are respectively connected to the parameter adaptive adjustment module and the collaborative decision-making and intelligent control module. The output of the parameter adaptive adjustment module is fed back to the hardware pulse neural network module to form a closed-loop adjustment circuit;

[0025] The pulse coding module is used to monitor the high-voltage system in real time, receive the monitored voltage or current signal, and then convert it into a time-domain pulse sequence representing the dynamic change of the signal;

[0026] The hardware pulse neural network module is used to process the time-domain pulse sequence in real time to identify a preset fault precursor pattern and generate a local warning state vector accordingly;

[0027] The distributed consensus engine module is used to receive the local warning state vector generated by the hardware pulse neural network module, and combine it with the local warning state vectors received from at least one other node to generate a global warning state vector through a consensus protocol;

[0028] The parameter adaptive adjustment module receives the global warning state vector and dynamically adjusts the internal parameters of the hardware pulse neural network module according to the global warning state vector, so as to adjust the response characteristics of the hardware pulse neural network module to the corresponding time-domain pulse sequence;

[0029] The collaborative decision-making and intelligent control module is used to execute a preset collaborative control strategy to intelligently handle potential faults when the global warning state vector reaches a preset control execution threshold.

[0030] In an optional embodiment, the pulse coding module adopts a time contrast coding mechanism. When the change amount of the received signal at adjacent sampling moments is Exceeds the preset encoding sensitivity threshold When , pulses are emitted, where ;

[0031] Where, Indicates that at the current discrete sampling moment The sampled value of the voltage or current signal is obtained; Indicates that at the previous discrete sampling moment The sampled value of the voltage or current signal obtained; Represents the sampling point index of discrete time; Represents absolute value operation.

[0032] In an optional embodiment, the hardware spiking neural network module is composed of a plurality of leaky integration and release neurons, specifically configured to:

[0033] receiving the time-domain pulse train and weighting the received pulses based on preset synaptic weights to accumulate a membrane potential within the leaky integrate-and-send neuron, wherein the preset synaptic weights are determined by offline training on sample data including known prefault patterns;

[0034] When the membrane potential of any neuron in the leaky integration and firing neurons reaches a preset firing threshold, the neuron fires an output pulse, and the firing behavior of the corresponding output neuron in the hardware pulse neural network module represents the recognition of a preset fault precursor pattern;

[0035] The initial value of the preset release threshold is determined based on the offline training;

[0036] The preset fault precursor mode is at least one of the following:

[0037] Partial discharge patterns associated with insulation aging in power equipment;

[0038] transient disturbance modes associated with mechanical loosening of electrical connection points;

[0039] Ultra-high frequency noise patterns associated with switching anomalies in power electronics devices.

[0040] In an optional embodiment, the membrane potential of the leaky integrated firing neuron The dynamic changes satisfy the following relationship:

[0041] ;

[0042] wherein, is the membrane time constant; is the instantaneous change rate of the membrane potential; is the resting potential; is the membrane resistance; represents the total synaptic input current received by the neuron with index at consecutive time points .

[0043] In an optional embodiment, the distributed consensus engine module is specifically configured to:

[0044] Receive the local warning state vector generated by the hardware spiking neural network module;

[0045] Receive the local warning state vectors of at least one other node through communication with the at least one other node;

[0046] Based on the local warning state vector generated by receiving the hardware spiking neural network module and the local warning state vectors of the at least one other node, execute a deterministic consensus protocol to reach a consistent judgment on the warning state among all participating nodes, thereby generating the global warning state vector.

[0047] In an optional embodiment, the distributed consensus engine module communicates with the other nodes through a high-speed fiber optic network to receive the local warning state vectors from the other nodes.

[0048] In an optional embodiment, the parameter adaptive adjustment module is specifically configured to:

[0049] Receive the global warning state vector;

[0050] According to the received global warning state vector, determine a parameter adjustment strategy, and accordingly generate an adjustment instruction for adjusting the internal parameters of the hardware spiking neural network module. The adjustment instruction is specifically a modulation matrix for adjusting the synaptic weights, or an adjustment value for adjusting the neuron firing threshold;

[0051] Apply the generated adjustment instruction to the hardware spiking neural network module, update the synaptic weights by performing matrix multiplication or matrix addition operations on the original synaptic weight matrix and the modulation matrix, or update the firing threshold by applying the adjustment value to the original firing threshold, thereby adjusting the response characteristics of the hardware spiking neural network module to the corresponding time-domain pulse sequence.

[0052] The second aspect of the present invention provides a real-time monitoring and fault intelligent processing method for a high-voltage system based on FPGA, which includes the following steps:

[0053] Perform real-time monitoring on the high-voltage system, receive the monitored voltage or current signal, and then convert it into a time-domain pulse sequence representing the dynamic change of the signal.

[0054] Perform real-time processing on the time-domain pulse sequence to identify a preset fault precursor pattern, and generate a local warning state vector accordingly.

[0055] Receive the local warning state vector generated by the hardware pulse neural network module, and combine it with the local warning state vectors received from at least one other node to generate a global warning state vector through a consensus protocol.

[0056] Receive the global warning state vector, and dynamically adjust the internal parameters of the hardware pulse neural network module according to the global warning state vector, so as to adjust the response characteristics of the hardware pulse neural network module to the corresponding time-domain pulse sequence.

[0057] When the global warning state vector reaches a preset control execution threshold, execute a preset cooperative control strategy to intelligently process potential faults.

[0058] The present invention provides a real-time monitoring and fault intelligent processing system for a high-voltage system based on FPGA. It has the following beneficial effects:

[0059] 1. By deploying functional units such as a pulse coding module, a hardware pulse neural network module, and a cooperative decision-making and intelligent control module in the hardware logic of FPGA, the present invention utilizes its inherent parallel processing ability to achieve a pipelined processing of high-voltage network signals. This hardware architecture avoids the overhead of instruction execution and task scheduling in software processing. Combining with the event-driven characteristics of the hardware pulse neural network, it greatly reduces the data processing delay and ensures the real-time monitoring ability of fault precursors.

[0060] 2. By directly analyzing the time-domain pulse sequence with a hardware pulse neural network, the present invention can effectively capture the time dynamic information contained in the transient disturbance signals related to equipment insulation aging or mechanical looseness in the high-voltage network, and achieve an accurate identification of fault precursor patterns. In addition, by setting a parameter adaptive adjustment module, the internal parameters of the neural network can be dynamically adjusted according to the global warning state, enabling the monitoring device to adaptively adjust its response characteristics, thereby significantly improving the intelligent processing level of fault identification in a complex electromagnetic environment.

[0061] 3. By setting up a distributed consensus engine module, the present invention allows multiple monitoring nodes deployed at different locations to fuse their locally generated early warning state vectors, and generates a more reliable and comprehensive global early warning state vector by executing a consensus protocol. This method effectively avoids misjudgment caused by information deviation of a single node. Based on this global state, the collaborative decision-making and intelligent control module can execute collaborative control strategies, realizing the transformation from single-point response to multi-point collaborative intelligent processing, and thus being able to more effectively respond to and suppress potential cascading failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is the architecture diagram of the real-time monitoring and fault intelligent processing system for the high-voltage power system based on FPGA of the present invention;

[0063] Figure 2 is the schematic diagram of the content structure of the pulse coding module of the present invention;

[0064] Figure 3 is the schematic diagram of the structure of the hardware pulse neural network module of the present invention;

[0065] Figure 4 is the schematic diagram of the structure of the distributed consensus engine module of the present invention;

[0066] Figure 5 is the schematic diagram of the structure of the parameter adaptive adjustment module of the present invention;

[0067] Figure 6 is the schematic diagram of the structure of the collaborative decision-making and intelligent control module of the present invention;

[0068] Figure 7 is the flowchart of the real-time monitoring and fault intelligent processing method for the high-voltage power system based on FPGA of the present invention.

[0069] Among them, 10. Pulse coding module; 20. Hardware pulse neural network module; 30. Distributed consensus engine module; 40. Parameter adaptive adjustment module; 50. Collaborative decision-making and intelligent control module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0070] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0071] Refer to the attached Figure 1 , Figure 1It is an architecture diagram of a real-time monitoring and fault intelligent processing system for a high-voltage power system based on FPGA according to an embodiment of the present invention. The present invention provides a real-time monitoring and fault intelligent processing system for a high-voltage power system based on FPGA, which may include: a pulse coding module 10, a hardware pulse neural network module 20, a distributed consensus engine module 30, a parameter adaptive adjustment module 40, and a collaborative decision-making and intelligent control module 50. In one embodiment, all the above modules are implemented through the hardware logic of FPGA.

[0072] A complete data processing and feedback path is formed among the system modules. The pulse coding module 10 serves as the signal input stage, and its output is connected to the hardware pulse neural network module 20. The output of the hardware pulse neural network module 20 is connected to the distributed consensus engine module 30. The output of the distributed consensus engine module 30 is divided into two paths, which are respectively connected to the parameter adaptive adjustment module 40 and the collaborative decision-making and intelligent control module 50. Among them, the output of the parameter adaptive adjustment module 40 is fed back to the hardware pulse neural network module 20 to form a closed-loop regulation loop.

[0073] The overall working process of the system is as follows: First, the signals of the monitored high-voltage power system are converted into a pulse sequence by the pulse coding module 10. Then, the hardware pulse neural network module 20 processes the sequence to generate local early warning information. Next, the distributed consensus engine module 30 fuses the early warning information of multiple nodes to form a global state judgment. Finally, based on this global state, the collaborative decision-making and intelligent control module 50 executes external control, and at the same time, the parameter adaptive adjustment module 40 performs internal optimization on the hardware pulse neural network module 20.

[0074] Refer to the appendix Figure 2 , Figure 2 It is a schematic diagram of the content structure of the pulse coding module according to an embodiment of the present invention. The pulse coding module 10 is the data input and preprocessing unit of the entire real-time monitoring and fault intelligent processing system for a high-voltage power system based on FPGA. Its core function is to receive a sequence of discrete sampling values representing the voltage or current of the high-voltage power system from an external ADC (analog-to-digital converter), and convert it into a time-domain pulse sequence with less data volume and more capable of characterizing the dynamic changes of the signal.

[0075] In a specific embodiment, the pulse coding module 10 adopts a time comparison coding mechanism. The principle of this mechanism is that only when the change amplitude between the current sampling value and the previous sampling value of the monitored signal is large enough, is it considered that an effective event occurs, and thus a pulse is issued. This event-driven coding method provides highly sparse input data for subsequent fault intelligent processing, significantly reducing the computational load of subsequent modules.

[0076] The pulse coding module 10 calculates the absolute value of the signal sampling values at adjacent sampling moments , and compare it with the coding sensitivity threshold to determine whether to issue a pulse. This calculation process is determined by the following relational expression:

[0077] ;

[0078] In the formula, represents the sampling value of the voltage or current signal obtained at the current discrete sampling moment ; represents the sampling value of the voltage or current signal obtained at the previous discrete sampling moment ; represents the sampling point index of discrete time, which is a positive integer; represents the absolute value operation.

[0079] The coding sensitivity threshold is a key parameter, and its value is used to define the significance of signal changes. The setting of this threshold enables the module to effectively ignore low-amplitude and informationless signal fluctuations such as the background noise of the power system, and only respond to drastic signal changes such as partial discharges and transient disturbances that may indicate potential faults. In one embodiment, the value of this threshold can be determined based on the statistical analysis of the background noise signal under historical normal operating conditions (for example, calculating three or five times its standard deviation), and can be configured in a dedicated parameter register.

[0080] At the implementation level of the FPGA hardware logic, the pulse coding module 10 can be composed of the following units:

[0081] An input data interface for receiving the sampling value from the ADC ; A data register for latching the current sampling value at the end of each clock cycle , so as to be used as the sampling value at the previous moment in the next clock cycle ; A fixed-point subtractor for calculating ; A logic judgment unit for obtaining the absolute value of the difference; and a digital comparator for comparing the calculated with the threshold stored in the parameter register. When the comparison result is , a time-domain pulse sequence with a width of one clock cycle is generated at the output end of this module.

[0082] Refer to Appendix Figure 3 , Figure 3It is a schematic structural diagram of a hardware spiking neural network module according to an embodiment of the present invention. The hardware spiking neural network module 20 undertakes the core pattern recognition function in the real-time monitoring and fault intelligent processing system of the high-voltage system based on FPGA. Its input end receives the time-domain pulse sequence from the pulse coding module 10, and through internal parallel computing, processes this sequence in real time to identify the preset fault precursor patterns, and finally generates a local warning state vector at its output end.

[0083] In a specific embodiment, the hardware spiking neural network module 20 is composed of multiple Leaky Integrate-and-Fire (LIF) neurons, and these neurons are organized into a feedforward network structure inside the FPGA, for example, including an input layer, one or more hidden layers, and an output layer. The connections between neurons are defined by a preset synaptic weight matrix. When a pulse from a previous neuron or the pulse coding module 10 arrives at a neuron, the pulse will be weighted based on the corresponding synaptic weight and used to update the membrane potential inside the neuron.

[0084] The initial values of the synaptic weights and the firing thresholds of the neurons are not randomly set, but are determined through offline training on sample data including known fault precursor patterns. These sample data may include: partial discharge patterns related to the insulation aging of power equipment; transient disturbance patterns related to the mechanical looseness of electrical connection points; ultra-high frequency noise patterns related to abnormal switching of power electronic devices. Through this training process, the network learns to map specific input time-domain pulse sequence patterns to the firing behaviors of specific output neurons. Therefore, the firing of a specific output neuron in the hardware spiking neural network module 20 represents the successful recognition of a preset fault precursor pattern.

[0085] At the physical model level, the membrane potential of each Leaky Integrate-and-Fire neuron The dynamic change process satisfies the following relationship:

[0086] ;

[0087] where is the membrane time constant, which determines the rate at which the membrane potential leaks to the resting potential; is the instantaneous change rate of the membrane potential; is the resting potential, which is the stable membrane potential value of the neuron when there is no input; is the membrane resistance, which characterizes the amplitude of the influence of synaptic input current on the membrane potential; represents the total synaptic input current received by the neuron with index at consecutive time points .

[0088] This formula describes two core processes: the leakage of the membrane potential (represented by the term ), and the integration that accumulates through the integration process until a preset firing threshold is reached. At this time, the neuron will emit an output pulse, and then its membrane potential is reset to the reset potential (for example, reset to ), entering the next integration cycle. This mechanism enables the neuron to not only respond to the presence or absence of the input, but also to the temporal dynamics of the input pulses, thus providing a basis for accurately identifying the precursors of transient faults in the high-voltage system.

[0089] To be implemented in the discrete-time digital logic of the FPGA, the above continuous-time differential equation is discretized by numerical methods such as the Euler method. Inside the FPGA, each LIF neuron can be implemented by a dedicated computing unit, which includes: registers for storing the current membrane potential , the resting potential and the firing threshold ; a memory (such as BRAM) for storing synaptic weights; and a fixed-point arithmetic logic unit (adders, multipliers, etc.) for performing the calculations of the discretized equation; as well as a digital comparator for comparing the membrane potential with the threshold. Thanks to the parallel characteristics of the FPGA, the membrane potential update, threshold comparison, and pulse firing processes of all neurons in the network can be synchronously completed within each clock cycle, which ensures extremely low-latency processing of the input pulse sequence and is the key to realizing real-time fault monitoring and intelligent processing.

[0090] Referring to Appendix Figure 4 , Figure 4 is a schematic structural diagram of a distributed consensus engine module according to an embodiment of the present invention. The distributed consensus engine module 30 is a key unit for realizing multi-node information fusion and global situation awareness in the entire real-time monitoring and fault intelligent processing system of the high-voltage system based on the FPGA. Its function is to upgrade the localized warning information generated by a single node to a global state judgment that is consistent among all participating nodes.

[0091] In a specific embodiment, the input end of this module receives the local warning state vector generated by the hardware pulse neural network module 20 inside the system. At the same time, this module integrates a high-speed communication interface. In a preferred embodiment, this interface communicates with the distributed consensus engine modules of at least one other monitoring node with the same configuration deployed at other locations in the high-voltage system through a high-speed optical fiber network to receive the local warning state vectors of the other party. Selecting a high-speed optical fiber network for inter-node communication is to ensure the high bandwidth and low latency of vector data transmission, which is the basis for realizing fast consensus and ensuring the real-time performance of the system.

[0092] The core function of the distributed consensus engine module 30 is to execute a deterministic consensus protocol. The execution of this protocol aims to reach a consistent judgment on the power grid warning state among all participating nodes based on the local warning state vector of this node and the local warning state vectors of all other nodes received, thereby eliminating misjudgments or missed judgments that may be caused by sensor noise of a single node, local electromagnetic interference, or model deviation.

[0093] This consensus protocol is implemented inside the FPGA through a dedicated state machine and computing unit. Its working process may include the following steps: First, after receiving the local warning state vector of this node, the module broadcasts this vector to all other participating nodes through a high-speed optical fiber network. At the same time, it also continuously listens for and receives vectors from other nodes and stores them in the internal buffer memory.

[0094] Second, when the local warning state vectors of all participating nodes are collected within a preset synchronization time window, the consensus protocol is triggered. In one embodiment, this deterministic protocol can perform element-level deterministic calculations on all received state vectors (including the vector of this node). For example, for each element in the vector (this element corresponds to the warning level of a specific fault precursor pattern), calculate the arithmetic mean or maximum value of all nodes on this element to generate the value of the corresponding element in the global warning state vector. Since all nodes execute exactly the same input collection and calculation logic, it is ensured that within the same time window, all nodes will generate exactly the same global warning state vector.

[0095] Finally, the module outputs the calculated and unique global warning state vector. This vector can more comprehensively and accurately reflect the macroscopic safety state of the entire high-voltage power system compared to any single local warning state vector.

[0096] Refer to the attached Figure 5 , Figure 5 is a schematic structural diagram of the parameter adaptive adjustment module according to an embodiment of the present invention. The parameter adaptive adjustment module 40 constitutes a key feedback adjustment loop in the entire real-time monitoring and fault intelligent processing system of the high-voltage power system based on FPGA. Its core function is to dynamically adjust the internal parameters of the hardware pulse neural network module 20 according to the global warning state currently sensed by the system, thereby adjusting its response characteristics to a specific time-domain pulse sequence, enabling the system to have an adaptive ability and improving the intelligent processing level of fault recognition.

[0097] In a specific embodiment, the input end of the parameter adaptive adjustment module 40 receives the global early warning status vector generated by the distributed consensus engine module 30. The module internally includes a parameter adjustment strategy determination unit and an adjustment instruction generation unit. The parameter adjustment strategy determination unit monitors the input global early warning status vector in real time. When certain elements or their combinations in the vector meet the preset triggering conditions (for example, the early warning level of a specific fault mode rises continuously for multiple cycles), this unit will determine a corresponding parameter adjustment strategy according to the preset mapping relationship.

[0098] According to the determined parameter adjustment strategy, the adjustment instruction generation unit then generates an adjustment instruction for adjusting the internal parameters of the hardware spiking neural network module 20. In one embodiment, the adjustment instruction is specifically manifested in one of the following two forms: one is a modulation matrix for adjusting the synaptic weights ; the other is an adjustment value for adjusting the neuron firing threshold .

[0099] The adjustment instruction is output to the parameter control end of the hardware spiking neural network module 20 to update its internal parameters in an online manner. The update process is as follows:

[0100] When the adjustment instruction is a modulation matrix , by performing matrix multiplication or matrix addition operations on the original synaptic weight matrix in the hardware spiking neural network module 20 and the modulation matrix , an updated synaptic weight matrix is generated. This process can be represented by the following relational expressions:

[0101] Or ;

[0102] In the formula, is the updated synaptic weight matrix; is the original synaptic weight matrix before update; is the modulation matrix generated by the parameter adaptive adjustment module; represents the Hadamard product of matrices (element - wise multiplication, that is, multiplication of corresponding elements).

[0103] When the adjustment instruction is an adjustment value , the firing threshold is updated by applying this adjustment value to the original firing threshold . For example, for a group or all neurons, the updated firing threshold can be determined by the following relational expression:

[0104] ;

[0105] In the formula, is the updated neuron firing threshold; is the original neuron firing threshold before update; is the adjustment value generated by the parameter adaptive adjustment module. In the hardware implementation of the FPGA, the parameter adaptive adjustment module 40 can be composed of a control logic unit, a look-up table (LUT) or block memory (BRAM) for storing preset adjustment strategies, and a fixed-point arithmetic operation unit. The control logic unit queries the LUT to obtain the corresponding modulation matrix or adjustment value according to the value of the input global warning status vector, and then the arithmetic operation unit performs the above matrix or scalar operation, and writes the result into the corresponding register or memory for storing weights and thresholds in the hardware pulse neural network module 20 through a dedicated data bus to complete the real-time update of the parameters.

[0106] Refer to the appendix Figure 6 , Figure 6 is a schematic structural diagram of the collaborative decision-making and intelligent control module according to an embodiment of the present invention. The collaborative decision-making and intelligent control module 50 is the final execution output unit of the entire real-time monitoring and fault intelligent processing system of the high-voltage system based on the FPGA. Its function is to execute a preset collaborative control strategy to actively intervene and intelligently process potential faults when the global warning status of the system reaches a critical condition.

[0107] In a specific embodiment, the input end of the module receives the global warning status vector generated by the distributed consensus engine module 30. The module internally monitors the global warning status vector in real time and continuously compares it with a preset control execution threshold. The control execution threshold here is not an empirical value, but is determined according to the analysis of the safety and stability margin of the monitored high-voltage network, and its value represents the upper limit of the warning status before the system evolves into an unstable state. The threshold is pre-calculated and stored in a dedicated register or memory inside the module.

[0108] When the value of the global warning status vector reaches the preset control execution threshold, it indicates that one or more key indicators of the system have approached their safety boundaries, and the collaborative decision-making and intelligent control module 50 is immediately triggered, and specific control instructions are generated and output according to the preset collaborative control strategy. The collaborative control strategy is pre-designed to cope with different fault precursors. In one embodiment, the strategy is at least one of the following:

[0109] Predictive power flow reconstruction: When the global warning status vector indicates a potential risk of line overload or voltage violation, the module will execute this strategy. It generates a set of control instructions and sends them to the switching devices (such as circuit breakers, disconnectors) in the power grid. By changing the operating topology of the power grid, the power flow is transferred from high-risk lines to other lines with larger margins, thereby actively avoiding the occurrence of faults.

[0110] Active damping injection: When the global warning status vector indicates precursors of stability problems such as low-frequency oscillations in the system, the module will execute this strategy. It generates control instructions and sends them to the Flexible Alternating Current Transmission System (FACTS) devices or energy storage systems in the system, controlling them to inject or absorb power with specific phases and amplitudes into the power grid to generate a damping torque opposite to the system oscillation, thereby quickly suppressing the oscillation and improving the dynamic stability of the system.

[0111] Online adjustment of protection settings: When the global warning status vector clearly identifies precursors of a specific type of fault (such as partial discharge related to insulation aging), the module can execute this strategy. It generates new protection setting parameters and sends them to the digital protection relays in the relevant line or equipment area through the communication network, online adjusting their protection settings (such as starting thresholds or delays), so that the protection system responds more sensitively and precisely to the upcoming specific type of fault, ensuring that the fault can be quickly and selectively cleared when it occurs.

[0112] At the hardware implementation level of the FPGA, the collaborative decision-making and intelligent control module 50 can be composed of a digital comparator array, a control logic state machine (FSM), and a block memory (BRAM) for storing the collaborative control strategy instruction set. The digital comparator array continuously compares the input global warning status vector with the stored control execution thresholds. Once the comparison condition is met, the FSM is triggered, reads the corresponding preset control instruction sequence from the BRAM according to the specific content of the global vector, and sends it to the external control execution unit through the output interface of the module.

[0113] Refer to Appendix Figure 7 , Figure 7 is a flowchart of a real-time monitoring and fault intelligent processing method for a high-voltage power system based on FPGA according to an embodiment of the present invention. The method aims to provide a complete processing flow from signal acquisition to intelligent control implemented on the FPGA hardware. The method specifically includes the following steps:

[0114] S1. Real-time monitor the high-voltage power system, receive the monitored voltage or current signals, and then convert them into time-domain pulse sequences representing the dynamic changes of the signals;

[0115] In one embodiment, this step is performed by the aforementioned pulse coding module 10. This module performs time-contrast coding on consecutive signal sample values and generates pulses only when the signal change amplitude exceeds a preset coding sensitivity threshold, thereby converting the original dense data stream into a sparse, event-driven pulse sequence.

[0116] S2. Perform real-time processing on the time-domain pulse sequence to identify a preset fault precursor pattern, and generate a local warning status vector accordingly;

[0117] In one embodiment, this step is performed by the aforementioned hardware pulse neural network module 20. This module uses an internal leaky integrate-and-fire neuron network to perform weighted summation and integration on the input pulse sequence. The firing behavior of specific output neurons in the network represents the recognition of a specific fault precursor pattern, and the comprehensive firing status of these neurons constitutes the local warning status vector.

[0118] S3. Receive the local warning status vector generated by the hardware pulse neural network module, and combine it with the local warning status vectors received from at least one other node to generate a global warning status vector through a consensus protocol;

[0119] In one embodiment, this step is performed by the aforementioned distributed consensus engine module 30. This module exchanges local warning status vectors with other nodes through a high-speed communication network and executes a deterministic consensus protocol to calculate a globally consistent global warning status vector among all participating nodes, thereby obtaining a unified judgment on the overall system state.

[0120] After generating the global warning status vector, the method performs the following two steps, S4 and S5, in parallel:

[0121] S4. Receive the global warning status vector and dynamically adjust the internal parameters of the hardware pulse neural network module according to the global warning status vector, thereby adjusting the response characteristics of the hardware pulse neural network module to a specific time-domain pulse sequence;

[0122] In one embodiment, this step is performed by the aforementioned parameter adaptive adjustment module 40. This module generates adjustment instructions such as a modulation matrix or adjustment values according to the global warning status vector and based on a preset adjustment strategy. These instructions are used to online update the synaptic weights or neuron firing thresholds of the hardware pulse neural network module, thereby forming a closed-loop feedback to enable the recognition performance of the system to adapt to changes in the power grid operation state.

[0123] S5. When the global warning status vector reaches a preset control execution threshold, execute a preset cooperative control strategy to intelligently handle potential faults.

[0124] In one embodiment, this step is executed by the aforementioned collaborative decision-making and intelligent control module 50. This module compares the global early warning state vector with a control execution threshold determined based on the analysis of the safety and stability margin. Once the threshold is reached, collaborative control strategies such as predictive power flow reconstruction, active damping injection, or online adjustment of protection settings are immediately triggered and executed, and control instructions are output to the external execution unit to achieve active intervention in potential faults.

[0125] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A real-time monitoring and intelligent fault processing system for high-voltage power systems based on FPGA, characterized in that Including: A pulse coding module, a hardware spiking neural network module, a distributed consensus engine module, a parameter adaptive adjustment module, and a collaborative decision-making and intelligent control module; The pulse coding module serves as the signal input stage, and its output is connected to the hardware spiking neural network module. The output of the hardware spiking neural network module is connected to the distributed consensus engine module. The output of the distributed consensus engine module is divided into two paths, which are respectively connected to the parameter adaptive adjustment module and the collaborative decision-making and intelligent control module. The output of the parameter adaptive adjustment module is fed back to the hardware spiking neural network module to form a closed-loop adjustment circuit; The pulse coding module is used to monitor the strong power system in real time, receive the monitored voltage or current signal, and then convert it into a time-domain pulse sequence representing the dynamic change of the signal; The hardware spiking neural network module is used to process the time-domain pulse sequence in real time to identify a preset fault precursor pattern and generate a local warning state vector accordingly; The distributed consensus engine module is used to receive the local warning state vector generated by the hardware spiking neural network module, and combine it with the local warning state vectors received from at least one other node to generate a global warning state vector through a consensus protocol; The parameter adaptive adjustment module receives the global warning state vector and dynamically adjusts the internal parameters of the hardware spiking neural network module according to the global warning state vector, thereby adjusting the response characteristics of the hardware spiking neural network module to the corresponding time-domain pulse sequence; The collaborative decision-making and intelligent control module is used to execute a preset collaborative control strategy to intelligently process potential faults when the global warning state vector reaches a preset control execution threshold; 2. The real-time monitoring and fault intelligent processing system for the high-voltage system based on FPGA according to claim 1, characterized in that The pulse coding module adopts a time comparison coding mechanism. When the change amount of the received signal at adjacent sampling moments exceeds a preset coding sensitivity threshold , it emits a pulse. Among them, ; Wherein, represents the sampling value of the voltage or current signal obtained at the current discrete sampling moment; represents the sampling value of the voltage or current signal obtained at the previous discrete sampling moment; represents the sampling point index of the discrete time; represents the absolute value operation.

3. The real-time monitoring and fault intelligent processing system for the high-voltage power system based on FPGA according to claim 1, wherein The hardware spiking neural network module is composed of multiple leaky integrate-and-fire neurons, and is specifically used for: Receiving the time-domain pulse sequence and weighting the received pulses based on a preset synaptic weight to accumulate the membrane potential inside the leaky integrate-and-fire neuron. The preset synaptic weight is determined through offline training including sample data of known fault precursor patterns; When the membrane potential of any neuron in the leaky integrate-and-fire neuron reaches a preset firing threshold, the any neuron fires an output pulse, and the firing behavior of the corresponding output neuron in the hardware spiking neural network module represents the recognition of a preset fault precursor pattern; The initial value of the preset firing threshold is determined according to the offline training; The preset fault precursor pattern is at least one of the following: A partial discharge pattern related to the insulation aging of power equipment; A transient disturbance pattern related to the mechanical looseness of electrical connection points; A ultra-high frequency noise pattern related to the abnormal switching of power electronic devices.

4. The real-time monitoring and fault intelligent processing system for the high-voltage system based on FPGA according to claim 3, characterized in that The membrane potential of the leaky integral - emitting neuron has a dynamic change that satisfies the following relationship: ； wherein, is the membrane time constant; is the instantaneous change rate of the membrane potential; is the resting potential; is the membrane resistance; represents the total synaptic input current received by the neuron with index at consecutive time points .

5. The real-time monitoring and fault intelligent processing system for high-voltage power systems based on FPGA according to claim 1, characterized in that, The distributed consensus engine module is specifically used for: Receiving the local warning state vector generated by the hardware spiking neural network module; Receiving the local warning state vectors of the at least one other node through communication with at least one other node; Execute a deterministic consensus protocol based on the generated local warning state vector of the hardware spiking neural network module and the local warning state vectors of the at least one other node to reach a consistent judgment on the warning state among all participating nodes, thereby generating the global warning state vector.

6. The real-time monitoring and fault intelligent processing system for the high-voltage system based on FPGA according to claim 5, characterized in that, The distributed consensus engine module communicates with the other nodes through a high-speed fiber optic network to receive the local warning state vectors from the other nodes.

7. The real-time monitoring and fault intelligent processing system for the high-voltage system based on FPGA according to claim 1, wherein The parameter adaptive adjustment module is specifically configured to: Receive the global warning state vector; Determine a parameter adjustment strategy based on the received global warning state vector, and accordingly generate an adjustment instruction for adjusting the internal parameters of the hardware spiking neural network module. The adjustment instruction is specifically a modulation matrix for adjusting synaptic weights, or an adjustment value for adjusting the neuron firing threshold; Apply the generated adjustment instruction to the hardware spiking neural network module, update the synaptic weights by performing matrix multiplication or matrix addition operations on the original synaptic weight matrix and the modulation matrix, or update the firing threshold by applying the adjustment value to the original firing threshold, thereby adjusting the response characteristics of the hardware spiking neural network module to the corresponding time-domain pulse sequence.

8. The real-time monitoring and fault intelligent processing system for the high-voltage system based on FPGA according to claim 1, characterized in that, The collaborative decision-making and intelligent control module is specifically configured to: Monitor the global warning state vector in real time; Compare the global warning state vector with a preset control execution threshold, where the control execution threshold is a value determined based on the security and stability margin analysis of the high-voltage power network and representing the upper limit of the warning state; When the global warning state vector reaches the preset control execution threshold, execute a preset collaborative control strategy, and the collaborative control strategy is at least one of the following: Predictive power flow reconstruction; Active damping injection; Online adjustment of protection setting values.

9. The real-time monitoring fault intelligent processing method for a high-voltage power system based on FPGA is applied to the real-time monitoring fault intelligent processing system for a high-voltage power system based on FPGA as described in any one of claims 1-8, and is characterized in that Includes the following steps: Monitor the high-voltage power system in real time, receive the monitored voltage or current signals, and then convert them into time-domain pulse sequences representing the dynamic changes of the signals; Perform real-time processing on the time-domain pulse sequences to identify preset fault precursor patterns, and accordingly generate local warning state vectors; Receive the local warning state vectors generated by the hardware spiking neural network module, and combine them with the local warning state vectors received from at least one other node to generate a global warning state vector through a consensus protocol; Receive the global warning state vector, and dynamically adjust the internal parameters of the hardware spiking neural network module according to the global warning state vector, thereby adjusting the response characteristics of the hardware spiking neural network module to the corresponding time-domain pulse sequence; When the global warning state vector reaches the preset control execution threshold, execute a preset collaborative control strategy to intelligently process potential faults.

Images