Optical interconnection link assembly, training method of optical interconnection link and acceleration cluster system

Abstract

The invention discloses an optical interconnection link assembly, an optical interconnection link training method and an acceleration cluster system, and relates to the technical field of optical interconnection, and the method comprises the steps: allowing an optical interconnection link to enter a training process when a switching assembly successfully receives a detection character sequence sent by an opposite side, so as to guarantee the normal communication of the optical interconnection link, the success rate and the reliability of link establishment are improved, only when the bidirectional communication link of the optical interconnection link is successfully established, the actual data transmission function can be performed through the optical interconnection link, the limitation of traditional copper cable interconnection is solved, an efficient and stable data transmission link based on PCIe optical interconnection is provided, and the data transmission efficiency is improved. And low-loss and long-distance transmission is realized.

Description

Technical Field

[0001] The present application relates to the field of optical interconnection technology, and in particular to an optical interconnection link component, a training method for an optical interconnection link, and an acceleration cluster system. Background Art

[0002] With the development of artificial intelligence, 5G, and cloud computing, data centers are facing extreme challenges in bandwidth, latency, and energy efficiency. Traditional copper cables suffer from severe attenuation and distance limitations (≤3 meters) at the high-frequency signals of PCIe Gen4 / 5 (above 16 GT / s), making them difficult to support new architectures such as GPU clusters and storage-computing separation. Traditional copper cable interconnect solutions restrict PCIe interconnect system design to zero-access, making it difficult to meet the scale-up requirements of GPU cluster applications.

[0003] In related technologies, the implementation principle of the PCIe (Peripheral Component Interconnect Express) electrical interconnect detection device (controlled end detection) identification logic is to determine the presence of the controlled end by detecting the DC common-mode input impedance of the receiving logic of the opposite device. However, due to the presence of optoelectronic conversion devices, the switching components at both ends of the PCIe optical interconnect cannot directly detect the presence of the controlled end device. The link DC common-mode input impedance is much greater than the normal value, and the opposite device on the optical interconnect link cannot be directly detected. As a result, PCIe link training fails and subsequent PCIe link training processes cannot be carried out. Summary of the Invention

[0004] The present application provides an optical interconnect link component, an optical interconnect link training method, an acceleration cluster system, an optical interconnect computing unit, an optical interconnect switching unit, an optical interconnect acceleration unit, a medium and a program product, so as to at least solve the problem in the related art that the photoelectric conversion process changes the form of the signal, causing the DC common-mode input impedance of the link to be much greater than the normal value. Therefore, the optical interconnect link cannot directly detect the opposite end device like the electrical interconnection, thereby causing the link training to fail.

[0005] The present application provides an optical interconnection link component, comprising: a first photoelectric converter, a second photoelectric converter, a first switching component, and a second switching component, wherein the first photoelectric converter and the second photoelectric converter constitute an optical interconnection link, and the first switching component and the second switching component interact with each other via the optical interconnection link; the first switching component is configured to continuously send a first detection character sequence and send a first response character sequence upon receiving a second detection character sequence; the second switching component is configured to continuously send a second detection character sequence and send a second response character sequence upon receiving the first detection character sequence; after the first switching component and the second switching component complete the interaction, the optical interconnection link enters a training process.

[0006] The present application provides a training method for an optical interconnection link. The method is applied to the first switching component of the optical interconnection link component in the above embodiment. The method includes: controlling the first optoelectronic converter to continuously send a first detection character sequence, identifying the first electrical signal output by the first optoelectronic device, and determining whether a second response character sequence is received within a preset duration, where the second switching component outputs the second response character sequence after receiving the first detection character sequence; after determining that the second response character sequence is received within the preset duration, controlling the internal state machine of the first switching component to be set to an effective state, where the effective state indicates that the optical interconnection link is allowed to enter the training process.

[0007] The present application provides a training method for an optical interconnection link. The method is applied to the second switching component of the optical interconnection link component in the above embodiment. The method includes: controlling the second optoelectronic converter to continuously send a second detection character sequence, identifying the second electrical signal output by the second optoelectronic device, and determining whether a first response character sequence is received within a preset duration, where the first switching component outputs the first response character sequence after receiving the second detection character sequence; after determining that the first response character sequence is received within the preset duration, controlling the internal state machine of the second switching component to be set to an effective state, where the effective state indicates that the optical interconnection link is allowed to enter the training process.

[0008] The present application provides an acceleration cluster system. The acceleration cluster system is composed of the optical interconnection link components in the above embodiment. The system includes: at least one optical interconnection computing unit and at least one optical interconnection acceleration unit, where the optical interconnection computing unit provides computing resources and the optical interconnection acceleration unit provides acceleration resources; at least one optical interconnection switching unit, where at least one of the optical interconnection switching unit and the optical interconnection computing unit and the optical interconnection acceleration unit is connected by an optical interconnection link, and / or, the optical interconnection acceleration unit and at least one optical interconnection computing unit are connected by an optical interconnection link.

[0009] The present application provides an optical interconnection computing unit. The optical interconnection computing unit is composed of the optical interconnection link components in the above embodiment and includes: at least one central processing unit and at least one switching component, where the central processing unit is connected to at least one switching component, the switching component is connected to at least one optoelectronic converter, and an optical interconnection link is formed between the optoelectronic converter inside the computing unit and the optoelectronic converter outside the computing unit.

[0010] The present application provides an optical interconnection switching unit, which is composed of the optical interconnection link components in the above embodiments of the optical interconnection computing unit, and includes: at least one optical interconnection switching board, wherein the optical interconnection switching board includes: a substrate connector and at least one switching component, and the substrate connector is connected to at least one switching component; the switching component is connected to at least one high-speed connector and at least one optoelectronic converter, wherein the optical interconnection switching board performs data communication with other optical interconnection switching boards through the high-speed connector, and an optical interconnection link is formed between the optoelectronic converters inside the optical interconnection switching board and the optoelectronic converters outside the optical interconnection switching board.

[0011] The present application also provides an optical interconnection acceleration unit, which is composed of the optical interconnection link components in the above embodiments of the optical interconnection computing unit, and includes: at least one graphics processor and at least one switching component, wherein the switching component is connected to at least one graphics processor, the switching component is connected to at least one optoelectronic converter, an optical interconnection link is formed between the optoelectronic converters inside the optical interconnection acceleration unit and the optoelectronic converters outside the optical interconnection acceleration unit, and at least one graphics processor provides acceleration resources through the optical interconnection link.

[0012] The present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned training method of the optical interconnection link are implemented.

[0013] The present application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned training method of the optical interconnection link are implemented.

[0014] When the switching components in the present application successfully receive the detection character sequences sent by each other, the optical interconnection link is allowed to enter the training process to ensure the normal communication of the optical interconnection link, improve the success rate and reliability of link establishment. Only when the bidirectional communication link of the optical interconnection link is successfully established can actual data transmission functions be carried out through the optical interconnection link. It not only solves the limitations of traditional copper cable interconnection, but also provides an efficient and stable data transmission link based on PCIe optical interconnection, realizing low-loss and long-distance transmission. Description of the Drawings

[0015] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 It is a schematic block diagram of the optical interconnection link components in the embodiments of the present application; Figure 2A flow chart of RX detection for PCIe optical interconnection link training provided by an embodiment of the present application; Figure 3 A flow chart of a training method for an optical interconnection link provided by an embodiment of the present application; Figure 4 A flow chart of a training method for an optical interconnection link provided by another embodiment of the present application; Figure 5 A schematic block diagram of an acceleration cluster system according to an embodiment of the present application; Figure 6 A connection topology diagram of a thousand-calorie GPU acceleration cluster PCIe optical interconnection switch unit according to an embodiment of the present application; Figure 7 A connection topology diagram of a single PCIe optical interconnection switch unit according to an embodiment of the present application; Figure 8 A schematic diagram of the connection topology of a GPU acceleration cabinet provided by an embodiment of the present application; Figure 9 A connection topology diagram of a PCIe optical interconnection computing unit provided by an embodiment of the present application; Figure 10 An explanatory diagram of a PCIe optical interconnection switch board provided by an embodiment of the present application; Figure 11 A connection topology diagram of a PCIe optical interconnection acceleration unit provided by an embodiment of the present application; Figure 12 A topology diagram of a thousand-calorie GPU acceleration cluster provided by an embodiment of the present application; Figure 13 A schematic block diagram of an optical interconnection computing unit provided by an embodiment of the present application; Figure 14 A schematic block diagram of an optical interconnection switch unit provided by an embodiment of the present application; Figure 15 A schematic block diagram of an optical interconnection acceleration unit provided by an embodiment of the present application; Figure 16 A connection topology diagram of a GPU acceleration cabinet provided by an embodiment of the present application.

[0017] Reference numerals: optical interconnection link component 10, first optoelectronic converter 110, second optoelectronic converter 120, first switching component 130, second switching component 140, acceleration cluster system 20, optical interconnection computing unit 210, optical interconnection acceleration unit 220, and optical interconnection switch unit 230. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0019] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0020] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0021] Due to the design defects of copper cables, the industry is actively promoting the research on related technologies and the implementation of cases of PCIe optical interconnection technology. The core of PCIe optical interconnection technology lies in converting PCIe electrical signals into PCIe optical signals. After converting PCIe electrical signals into PCIe optical signals, the PCIe optical signals can be transmitted through optical fibers. The attenuation coefficient of optical fibers is low. The typical attenuation of single-mode optical fibers at a wavelength of 1310 nm is 0.35 dB / km, which is much lower than that of copper cables at 10 dB / m @ 10 GHz. At the same time, the optical signals are propagated by total internal reflection in the optical fibers, which can avoid the skin effect, dielectric loss, and electromagnetic interference in the process of electrical signal transmission. Based on these characteristics, PCIe optical signals can achieve low-loss and long-distance transmission in optical fibers.

[0022] Existing optical interconnection technologies are mostly applied to data transmission in network switches. The PCIe optical interconnection solution is in its infancy. Current applications mainly focus on application scenarios such as data transmission of a single PCIe optical-electrical conversion device, establishment of a single PCIe optical interconnection link, and functional verification of a single board or single system supporting optical interconnection. There is no related technology application of the PCIe optical interconnection solution in cross-resource pool interconnection. In the application scenario of cross-resource pool interconnection, copper cable interconnection or network interconnection technology solutions are still mostly adopted.

[0023] To solve the problems that the above copper cable interconnection solution is limited by the PCIe transmission distance, and the network interconnection solution is limited by the increase in the number of data hops, resulting in high communication latency, the present invention relates to an accelerated cluster system based on PCIe optical interconnection technology. Among them, the accelerated cluster system includes an optical interconnection computing resource pool, an optical interconnection switching unit, and an optical interconnection acceleration unit. The resource pools are based on a switching component that supports an optical interconnection link. Among them, the switching component includes a Retimer chip and a Switch chip. The switching component itself can be used as a USP device or a DSP device. That is, when both ends of the optical interconnection link are switching components, the switching component can skip the process of monitoring the USP device or the DSP device and directly send a device signal to the optoelectronic converter. The optoelectronic conversion device and the optical fiber form multiple PCIe optical interconnection links, which can support low-power, long-distance, and low-latency PCIe data transmission between resource pools within / between cabinets, and can flexibly expand the scale of the GPU accelerated cluster based on PCIe communication.

[0024] The optical interconnection computing resource pool, the optical interconnection switching unit, and the optical interconnection acceleration unit are all composed of optical interconnection link components. Among them, the PCIe optical interconnection solution is mainly implemented by a switching component that supports an optical interconnection link and an LPO (Low Power Optical) optoelectronic conversion device. In the PCIe optical interconnection link, the master end of the PCIe signal requires an optoelectronic conversion device to convert the PCIe electrical signal into a PCIe optical signal, and the controlled end of the PCIe signal also requires an optoelectronic conversion device to convert the PCIe optical signal into a PCIe electrical signal. During the optoelectronic conversion process, conversions of the PCIe signal transmission medium, signal nature, signal modulation method, and signal compensation technology are involved. The differences in these conversion methods also determine that the optoelectronic conversion devices applied to network transmission cannot be directly applied to PCIe optical interconnection transmission. For example, the optoelectronic conversion devices applied to 25G and 100G network switches mostly have built-in DSP chips and adopt the NRZ-25G modulation method. Although the PCIeGen5 and lower rates also adopt the NRZ modulation method, different from the NRZ-25G modulation technology that is only optimized for the 25G rate, the PCIe NRZ modulation technology needs to optimize the signal for different communication rates of PCIe Gen1-Gen5. That is, the optoelectronic conversion device used in the PCIe optical interconnection application needs to adjust the internal configuration information according to the PCIe signal characteristics.

[0025] To avoid excessive participation of the internal DSP chip of the traditional optoelectronic conversion device in the PCIe optical signal modulation process, in this solution, an optoelectronic converter and a switching component that supports an optical interconnection link externally are jointly used to form a PCIe optical interconnection link.

[0026] The switching component supporting the optical interconnection link also participates in the PCIe optical interconnection link training process. The differences between the optical interconnection link training and the electrical interconnection link training are concentrated in the Receiver detection stage of the PCIe link training: The implementation principle of the PCIe electrical interconnection detection device to identify logic is to judge whether the controlled end exists by detecting the DC common-mode input impedance of the receiving logic of the peer device. However, due to the existence of optoelectronic conversion devices at both ends of the PCIe optical interconnection, the switching components at both ends of the optical interconnection cannot directly detect the existence of the Receiver device, and the link DC common-mode input impedance is much larger than the normal value, so the peer device on the optical interconnection link cannot be directly detected, resulting in the failure of the PCIe link training and the inability to proceed with the subsequent PCIe link training process.

[0027] To solve this problem, the embodiments of the present application provide an optical interconnection link component, and the system is described in detail in combination with the operation process of the optical interconnection link component.

[0028] Specifically, Figure 1 It is a block diagram of the optical interconnection link component provided by the embodiments of the present application.

[0029] As Figure 1 shown, the optical interconnection link component 10 includes: a first optoelectronic converter 110, a second optoelectronic converter 120, a first switching component 130, and a second switching component 140.

[0030] Among them, an optical interconnection link is formed between the first optoelectronic converter 110 and the second optoelectronic converter 120, and the first switching component 130 and the second switching component 140 interact through the optical interconnection link; the first switching component 130 is used to continuously send a first detection character sequence and send a first response character sequence when receiving the second detection character sequence; the second switching component 140 is used to continuously send a second detection character sequence and send a second response character sequence when receiving the first detection character sequence; after the first switching component 130 and the second switching component 140 complete the interaction, the optical interconnection link enters the training process.

[0031] It can be understood that in the embodiments of the present application, when the switching components successfully receive the detection character sequences sent by each other, the optical interconnection link is allowed to enter the training process to ensure the normal communication of the optical interconnection link, improve the success rate and reliability of link establishment. Only when the two-way communication link of the optical interconnection link is successfully established can the actual data transmission function be carried out through the optical interconnection link, which not only solves the limitations of traditional copper cable interconnection, but also provides an efficient and stable data transmission link based on PCIe optical interconnection, realizing low-loss and long-distance transmission.

[0032] It should be noted that the first optical - electrical converter is close to the first switching component. It is used to convert the electrical signal from the first device into an optical signal for transmission to the opposite end through an optical fiber, and convert the optical signal received from the opposite end back into an electrical signal for the first switching component to process. The second optical - electrical converter is close to the second switching component. It is used to convert the electrical signal from the second device into an optical signal and transmit it to the opposite end through an optical fiber, and convert the optical signal received from the opposite end back into an electrical signal for the second switching component to process. The first switching component is responsible for managing and processing the signals from the first device, and performing the conversion and transmission of optical - electrical signals through the optical - electrical conversion device. The second switching component is responsible for managing and processing the signals from the second device, and performing the conversion and transmission of optical - electrical signals through the optical - electrical conversion device. The first device is the master - control device, which is the device connected to the first switching component. The second device is the controlled device, which is the device connected to the second switching component, and no specific limitations are made.

[0033] In the embodiment of the present application, the structures of the first optical - electrical converter 110 and the second optical - electrical converter 120 are the same. Among them, the structures of the first optical - electrical converter 110 and the second optical - electrical converter 120 include: a linear trans - impedance amplifier and a linear driver. Among them, the linear trans - impedance amplifier is used to convert the optical signal output by the photodetector into an electrical signal with a target linearity, and the linear driver is used to convert the electrical signal received by the photodetector into a continuous modulation current to drive the laser to work in the linear region to obtain an optical signal.

[0034] It can be understood that in the embodiment of the present application, the structures of the optical - electrical converters are the same, making the signal - processing paths of the optical interconnection link completely symmetric in both directions, improving the compatibility and maintainability of the system; the trans - impedance amplifier converts the weak current signal output by the photodetector into a voltage signal and amplifies it, improving the sensitivity of the controlled end, enhancing the detection ability of low - optical - power signals, and improving the data - receiving quality. The driver converts the electrical signal into an optical signal for transmission, ensuring that the optical signal at the transmitting end has sufficient intensity and stability, and can adjust the drive current according to the link requirements to optimize the balance between power consumption and performance, thereby realizing the transceiver of optical signals that conforms to the electrical characteristics of the PCIe protocol and ensuring the smooth progress of link training and data communication.

[0035] In the embodiment of the present application, the first switching component 130 processes the first electrical signal output by the first optical - electrical converter 110 based on the electrical specifications of the optical interconnection protocol; the second switching component 140 processes the second electrical signal output by the second optical - electrical converter 120 based on the electrical specifications of the optical interconnection protocol.

[0036] It can be understood that in the embodiments of the present application, by following the electrical specifications of the optical interconnection protocol, the first switching component and the second switching component can ensure that the electrical signals received from the optical - electrical converters meet the standards, which include functions such as dispersion compensation, error correction, and equalization of the signals. This enables the signals to maintain high quality even after long - distance transmission, reduces the bit error rate, and improves the reliability of data transmission. It not only enhances the quality and transmission efficiency of the signals but also improves the compatibility, flexibility, and stability of the system.

[0037] In the embodiments of the present application, both the first optical - electrical converter 110 and the second optical - electrical converter 120 are connected to the baseboard management controller. When the baseboard management controller detects that the optical interconnection link meets the link establishment conditions, it establishes the optical interconnection link and controls the optical interconnection link to enter the training process.

[0038] It can be understood that in the embodiments of the present application, using the baseboard management controller to detect whether the optical interconnection link meets the establishment conditions and control it to enter the training process not only ensures that the optical - electrical conversion devices can operate in the best state, but also enables the optical - electrical converters based on linear direct drive to adapt to different communication rates, thus better meeting diverse requirements.

[0039] Specifically, as Figure 2 shown, since the internal TIA and Driver of the optical - electrical conversion device need to perform temperature compensation and bias current adjustment after power - on to ensure the stable operation of the optical - electrical conversion device, the on - board management device needs to be connected to both the switching component and the optical - electrical conversion device to control their timing relationship, ensuring that the switching component waits for the optical - electrical conversion device to work stably before establishing the PCIe optical interconnection link. The basis for the on - board management device to judge the stable operation of the optical - electrical conversion device is: (1) monitoring whether the internal state machine of the optical - electrical conversion device reaches the data - link valid state; (2) monitoring whether there are alarms in the internal status register of the optical - electrical conversion device to avoid the influence of internal abnormal states on the optical signal transceiver; (3) monitoring the optical power of the controlled end to ensure that both optical - electrical conversion devices at both ends of the optical fiber are in a stable working state.

[0040] According to the optical interconnection link component proposed in the embodiments of the present application, when the switching components respectively successfully receive the detection character sequences sent by each other, the optical interconnection link is allowed to enter the training process to ensure the normal communication of the optical interconnection link, improving the success rate and reliability of link establishment. Only when the two - way communication link of the optical interconnection link is successfully established can the actual data transmission function be carried out through the optical interconnection link. It not only solves the limitations of traditional copper cable interconnection but also provides an efficient and stable data transmission link based on PCIe optical interconnection, achieving low - loss and long - distance transmission.

[0041] The embodiments of the present application also provide a training method for an optical interconnection link.

[0042] Figure 3It is a flowchart of the training method for the optical interconnection link provided by the embodiments of the present application.

[0043] As Figure 3 shown, the training method of the optical interconnection link is applied to the first switching component 130 in the optical interconnection link component 10. Among them, the method includes: In step S101, control the first optoelectronic converter to continuously send the first detection character sequence, identify the first electrical signal output by the first optoelectronic conversion device, and determine whether the second response character sequence is received within a preset duration. Among them, after receiving the first detection character sequence, the second switching component outputs the second response character sequence.

[0044] Among them, the preset duration can be set according to actual needs without specific limitation.

[0045] It can be understood that in the embodiments of the present application, by controlling the first optoelectronic converter to continuously send the first detection character sequence and identifying the first electrical signal output by the first optoelectronic conversion device, it is determined whether the second response character sequence is received within the preset duration, which not only ensures the existence and normal operation of the devices at both ends of the link, but also significantly improves the success rate of link establishment, and enhances the stability and reliability of the link.

[0046] In step S102, after determining that the second response character sequence is received within the preset duration, control the internal state machine of the first switching component to be set to an effective state, where the effective state indicates that the optical interconnection link is allowed to enter the training process.

[0047] It can be understood that in the embodiments of the present application, by setting the internal state machine of the first switching component to an effective state after receiving the second response character sequence within the preset duration, it is ensured that the training process is allowed to enter only when the link conditions meet the requirements, thereby improving the reliability and efficiency of link establishment, enhancing the stability and robustness of the system, and supporting efficient link training.

[0048] It should be noted that the response character sequence is a series of specific characters generated and sent back to the master control end by the controlled end after receiving the detection character sequence sent by the master control end. These characters are used to verify the communication ability and status between the devices at both ends of the link. The main purpose is to ensure that the devices at both ends of the link can recognize and communicate with each other and are ready to enter the subsequent link training stage. This is achieved by detecting physical layer characteristics (such as DC common mode impedance) in traditional electrical interconnections, but it cannot be directly applied in optical interconnections due to the presence of optoelectronic conversion devices. Therefore, the method of using character sequences is adopted as an alternative solution.

[0049] In the embodiment of the present application, before controlling the internal state machine of the first switching component to be set to the valid state, it further includes: identifying the first continuous reception quantity of the second response character sequence within a preset duration; if the first continuous reception quantity is greater than or equal to the preset quantity, controlling the internal state machine of the first switching component to be set to the valid state; if the first continuous reception quantity is less than the preset quantity, controlling the internal state machine of the first switching component to be set to the invalid state, where the invalid state indicates that the optical interconnection link is not allowed to enter the training process.

[0050] Among them, the preset quantity can be set according to actual requirements without specific limitation.

[0051] It can be understood that before controlling the internal state machine of the first switching component to be set to the valid state, the embodiment of the present application adds the identification of the first continuous reception quantity of the second response character sequence within a preset duration, and determines the state of the state machine according to the comparison result with the preset quantity, which not only enhances the robustness of the system in the face of abnormal situations, but also optimizes the resource usage efficiency and simplifies the fault troubleshooting process.

[0052] In the embodiment of the present application, it further includes: identifying the first electrical signal output by the first optoelectronic conversion device, determining the second detection character sequence output by the second switching component, and controlling the first optoelectronic conversion device to send the first response character sequence.

[0053] It can be understood that the embodiment of the present application can identify the first electrical signal output by the first optoelectronic conversion device, determine the second detection character sequence output by the second switching component, and control the first optoelectronic conversion device to send the first response character sequence, which can determine the existence of the switching component at the other end of the optical interconnection link and can receive the data sent by the switching component at the other end through the optical interconnection link, solves the problem of the failure of the detection device in traditional electrical interconnection, and also provides a reliable basic support for subsequent link training, data transmission and system management.

[0054] In Figure 2 In the shown process, the switching component itself can be used as a USP device or a DSP device, that is, when both ends of the optical interconnection link are switching components, the switching component can skip the process of monitoring the USP device or the DSP device and directly send a device signal to the optoelectronic converter.

[0055] In the embodiment of the present application, before controlling the first optoelectronic converter to continuously send the first detection character sequence, it further includes: determining whether to detect the first device signal of the master control end according to the type of the first switching component; if the type of the first switching component is the switching type, controlling the first optoelectronic converter to continuously send the first detection character sequence; if the type of the first switching component is the relay type, after detecting the first device signal of the master control end, controlling the first optoelectronic converter to continuously send the first detection character sequence.

[0056] It can be understood that the embodiments of the present application can adopt different link establishment strategies according to the switching type of the first switching component, so as to perform differential link initialization control based on different switching component types, realizing the compatibility design for multiple interconnect topologies and improving the flexibility and adaptability of the system architecture.

[0057] According to the training method of the optical interconnection link proposed by the embodiments of the present application, the first switching component sends a detection character sequence, and after the second switching component receives it, it returns a response character sequence. Only after the first switching component confirms the response is it allowed to enter the training process, ensuring that both devices at both ends of the link are ready, avoiding training failures caused by one side not being ready, significantly improving the success rate and stability of link training, constructing an efficient, reliable, and intelligent optical interconnection link establishment mechanism, solving the core problem of detection device failure in PCIe optical interconnection, and significantly improving the success rate of link training and the stability of the system.

[0058] The embodiments of the present application also provide a training method for an optical interconnection link.

[0059] Figure 4 It is a flowchart of the training method for the optical interconnection link provided by the embodiments of the present application.

[0060] As Figure 4 shown, this training method for the optical interconnection link is applied to the second switching component 140 of the optical interconnection link component 10, where the method includes: In step S201, control the second optoelectronic converter to continuously send a second detection character sequence, identify the second electrical signal output by the second optoelectronic conversion device, and determine whether a first response character sequence is received within a preset duration, where the first switching component outputs a first response character sequence after receiving the second detection character sequence.

[0061] Among them, the preset duration can be set according to actual needs and is not specifically limited.

[0062] It can be understood that the embodiments of the present application can control the second optoelectronic converter to continuously send a second detection character sequence and identify the second electrical signal output by it to determine whether a first response character sequence is received within a preset duration, not only ensuring the existence and readiness state of the device at the opposite end of the link, but also significantly improving the success rate of link establishment and the stability of the system.

[0063] In step S202, after determining that the first response character sequence is received within the preset duration, control the internal state machine of the second switching component to be set to an effective state, where the effective state indicates that the optical interconnection link is allowed to enter the training process.

[0064] It can be understood that in the embodiments of the present application, after determining that the first response character sequence is received within a preset duration, the internal state machine of the second switching component is controlled to be set to an effective state. This design ensures that the training process is allowed only when the link condition meets the requirements, not only improving the reliability and efficiency of link establishment, but also enhancing the stability and robustness of the system, supporting efficient link training, and simplifying management and maintenance work.

[0065] In the embodiments of the present application, before controlling the internal state machine of the second switching component to be set to an effective state, it further includes: identifying the second continuous reception quantity of the first response character sequence within the preset duration; if the second continuous reception quantity is greater than or equal to the preset quantity, controlling the internal state machine of the second switching component to be set to an effective state; if the second continuous reception quantity is less than the preset quantity, controlling the internal state machine of the second switching component to be set to an invalid state, where the invalid state means that the optical interconnection link is not allowed to enter the training process.

[0066] Among them, the preset quantity can be set according to actual needs without specific limitation.

[0067] It can be understood that in the embodiments of the present application, before controlling the internal state machine of the second switching component to be set to an effective state, a mechanism for counting and judging the reception quantity of the first response character sequence can be added, which not only enhances the system's ability to resist interference and occasional failures, but also improves the resource utilization efficiency.

[0068] It should be noted that a single successful reception of the response character sequence is not sufficient to determine that the link is stable and reliable. By setting a threshold, it is ensured that the devices at both ends of the link are considered to be in a normal communication state only after continuously and stably receiving the response signal. This method can avoid misjudgment caused by instantaneous interference, noise or occasional errors, and improve the reliability of link establishment. In a complex electromagnetic environment or long-distance transmission, data loss or error codes may occur. By identifying the continuous reception quantity of the response character sequence, the system can distinguish between occasional packet loss and link abnormality. If the reception quantity is insufficient, it is considered that the link quality does not meet the standard and it is prevented from entering the training process, thereby enhancing the anti-interference ability of the system.

[0069] In the embodiments of the present application, it further includes: identifying the second electrical signal output by the second optoelectronic conversion device, determining the first detection character sequence output by the first switching component, and controlling the second optoelectronic conversion device to send the second response character sequence.

[0070] It can be understood that the embodiments of the present application can recognize the second electrical signal output by the second optoelectronic conversion device, determine the first detection character sequence output by the first switching component, and control the second optoelectronic conversion device to send a second response character sequence. Only when the first optoelectronic converter successfully recognizes the first detection character sequence from the peer end and can correctly return the first response character sequence, does it indicate that the link has the basic conditions to enter the training phase. This avoids blindly entering the training process when the link is abnormal or the device is not ready, and significantly improves the success rate and stability of link training.

[0071] In the embodiments of the present application, before controlling the second optoelectronic converter to continuously send the second detection character sequence, it further includes: determining whether to detect the second device signal of the controlled end according to the type of the second switching component; if the type of the second switching component is the switching type, controlling the second optoelectronic converter to continuously send the second detection character sequence; if the type of the second switching component is the relay type, after detecting the second device signal of the master control end, controlling the second optoelectronic converter to continuously send the second detection character sequence.

[0072] It can be understood that the embodiments of the present application can adopt different link establishment strategies according to the switching type of the second switching component, so as to perform differential link initialization control based on different switching component types, realize the compatibility design of various interconnection topologies, and improve the flexibility and adaptability of the system architecture.

[0073] According to the training method of the optical interconnection link proposed by the embodiments of the present application, by detecting the controlled end device signal, sending the detection character sequence, recognizing the response character sequence, and controlling the optoelectronic converter state machine, an optical interconnection link establishment mechanism is constructed. It not only solves the problem that the traditional physical layer detection mechanism fails in optical interconnection, but also significantly improves the reliability, stability and intelligence level of link establishment, and is an important technical support for realizing a high-performance, low-latency, large-scale GPU acceleration cluster system.

[0074] Next, it will be combined with Figure 2 The training method of the optical interconnection link of the present application will be elaborated in detail as follows: When the switching component is working properly and it is detected that the PCIe optical interconnection link is not established, actively monitor whether there are USP (User Services Platform) devices or DSP devices connected to the switching component through the PCIe electrical interconnection link. When USP devices and DSP devices are detected at both ends, the switching components at both ends continuously and actively send a specific detection character sequence to the optical-electric converter to monitor whether the PCIe optical interconnection link can communicate normally. If the controlled end of the switching component at one end of the PCIe optical interconnection link detects N consecutive specific detection character sequences sent by the optical-electric converter within a specific time, it is considered that data sent from the opposite end can be received through this PCIe optical interconnection link; if the specified number of detection character sequences is not received after the timeout, it is considered that the PCIe optical interconnection link is abnormal, stop sending the character sequence, exit the PCIe optical interconnection link training RX detection (detection device, receive detection) process, and wait for the on-board management device to send an instruction before restarting the RX detection process; then, the master control end of the switching component that receives the consecutive specific detection character sequences continuously and actively sends a specific response character sequence to the connected optical-electric converter to inform the opposite-end switching component that the local end can receive data sent through the optical interconnection link; while the switching component is sending the specific response character sequence at the master control end, the controlled end continuously monitors whether the specific response character sequence sent by the optical-electric converter is received. If M consecutive specific response character sequences are received within the specified time, it is considered that the switching components at both ends of the link exist and are working properly and can send data normally through the PCIe optical interconnection link; if the specified number and format of character sequences are not received within the specified time, it is considered that the status of the optical-electric converter / opposite-end switching component is abnormal and the PCIe optical interconnection link cannot be established normally, then return to the stage of sending the specific detection character sequence; to avoid the power supply timing of the switching components at both ends of the link being out of sync, resulting in entering the detection process successively and the detection character sequences received by the chips at both ends being out of sync. If a specific response sequence sent by the opposite end is detected before one end of the switching component has received N specific detection character sequences that meet the requirements, directly enter the stage of judging whether the specific response sequence meets the requirements, and then judge whether the switching components at both ends of the link exist and are working properly and whether data can be sent normally through the PCIe optical interconnection link.

[0075] If it has been confirmed that the switching components at both ends of the PCIe optical interconnection link exist and are working properly and can send data normally through the PCIe optical interconnection link, when the USP device or DSP device actively sends a device signal, the switching component directly informs the USP device or DSP device that the receiving device already exists and the next link training Polling process can be directly carried out.

[0076] Embodiments of the present application provide an acceleration cluster system, and the system is described in detail in combination with the operation process of the acceleration cluster system.

[0077] Specifically, Figure 5 is a block diagram of the acceleration cluster system provided by the embodiments of the present application.

[0078] As Figure 5 shown, the acceleration cluster system 20 is composed of optical interconnection link components 10. Among them, the system includes: an optical interconnection computing unit 210, an optical interconnection acceleration unit 220, and an optical interconnection switching unit 230.

[0079] Among them, the optical interconnection computing unit 210, the optical interconnection acceleration unit 220, and the optical interconnection switching unit 230 include at least one. Among them, the optical interconnection computing unit 210 provides computing resources, and the optical interconnection acceleration unit 220 provides acceleration resources; the optical interconnection switching unit 230 is connected to at least one of the optical interconnection computing unit 210 and the optical interconnection acceleration unit 220 through an optical interconnection link, and the optical interconnection acceleration unit 220 is connected to at least one optical interconnection computing unit 210 through an optical interconnection link.

[0080] It can be understood that in the embodiments of the present application, the optical interconnection computing unit focuses on CPU (Central Processing Unit) resources, the optical interconnection acceleration unit provides GPU resources, and the optical interconnection switching unit independently undertakes data routing. Based on the characteristics of low attenuation, anti-interference, and long-distance transmission of PCIe optical signals in optical fibers, the three can be deployed across cabinets, breaking through the physical limitations of a single cabinet, supporting the on-demand distributed layout of computing resources and acceleration resources; data is transmitted through optical interconnection links within the cabinet, across cabinets, and between the switching board and resources. The number of resource pools can be flexibly adjusted according to the application scenario to achieve the on-demand allocation of computing, switching, and network resources, meeting diverse deployment requirements. The direct connection optical link between the optical interconnection acceleration units realizes microsecond-level latency communication between GPUs, avoiding network congestion and achieving long-distance, low-loss, low-latency, and high-rate PCIe data transmission.

[0081] As Figure 6As shown in the figure, a single optical interconnection switching unit is connected to a GPU acceleration cabinet, and 4 GPU acceleration cabinets are connected to the 4-layer optical interconnection switching unit in the PCIe optical interconnection switching unit in a PCIe switch cabinet. The positions of the GPU acceleration cabinet and the PCIe switch cabinet are decoupled and can be independently distributed at different locations in different computer rooms. The cabinets are connected through optical-electrical converters and optical fibers to realize the data transmission of PCIe optical signals between the cabinets. The single-layer optical interconnection switching unit supports 10 PCIe x16 optical interconnection links externally. Among them, 8 groups of PCIe optical interconnection links are used to connect the GPU acceleration cabinets, and 2 groups of PCIe x16 optical interconnection links are used to connect the top-layer PCIe optical interconnection switching unit to achieve a larger-scale GPU acceleration resource expansion. Internally, the 4 * PCIe x16 interconnection ports of the optical interconnection switching unit can be used for the interconnection of the internal switching components of the switching unit. Based on different cable connection relationships, 1*2, 2*2, 2*3, and 2*4 optical interconnection switching unit interconnection topologies can be realized, and the GPU acceleration cards in different GPU acceleration cabinets can access the GPU acceleration cards in other GPU acceleration cabinets through this interconnection port. When the two groups of PCIe x16 connecting the top-layer PCIe optical interconnection switching unit are changed to connect the optical interconnection computing unit, a single optical interconnection computing unit can support simultaneous communication with 128 GPU acceleration cards.

[0082] In the embodiment of the present application, if there are multiple optical interconnection switching units 230, at least one main switching unit and at least one secondary switching unit are included in the multiple optical interconnection switching units 230. The main switching unit is connected to at least one secondary switching unit through an optical interconnection link, and the main switching units are connected to each other through an optical interconnection link.

[0083] It can be understood that in the embodiment of the present application, through the hierarchical interconnection of the main switching unit and the secondary switching unit, the communication traffic of the large-scale GPU cluster can be layered and diverted, avoiding a single switching unit from becoming a performance bottleneck. The main switching units are directly connected, and the secondary switching units are mounted under the main units to ensure that the GPUs in any acceleration cabinet can access the resources of other cabinets through optical links, realizing the global connection of the cross-unit resource pool. When a secondary switching unit fails, the main switching unit can dynamically switch the routing path. The multi-link interconnection between the main units provides redundancy to avoid the cluster paralysis caused by a single point of failure and enhance the fault tolerance of the system.

[0084] Specifically, as Figure 7As shown in the figure, in a kilocalorie GPU-accelerated cluster, a single PCIe optical interconnection switching unit is connected to the optical interconnection switching unit in the top-layer PCIe optical interconnection switching unit through 8 * PCIe x16 optical interconnection links. A single top-layer PCIe optical interconnection switching unit can support the connection of 4 PCIe optical interconnection switching units, and the 4 PCIe optical interconnection switching units are respectively connected to the optical interconnection switching units on 4 layers in the top-layer PCIe optical interconnection switching unit. In addition to aggregating the 8 * PCIe x16 optical interconnection links connected by the PCIe optical interconnection switching units, the other two groups of PCIe x16 in each layer of the optical interconnection switching unit in the top-layer PCIe optical interconnection switching unit are used for interconnection with the optical interconnection switching unit in the top-layer PCIe switching unit in another PCIe switch cabinet. A single top-layer PCIe optical interconnection switching unit is responsible for the cross-cabinet PCIe data exchange of 512 GPU-accelerated cards in the system, and two top-layer PCIe optical interconnection switching units jointly undertake the data exchange task of 1024 GPU-accelerated cards in the system.

[0085] In an embodiment of the present application, at least one of the main switching unit and the secondary switching unit is connected to at least one optical interconnection computing unit through an optical interconnection link.

[0086] It can be understood that in the embodiment of the present application, connecting the main switching unit and the secondary switching unit to the optical interconnection computing unit through an optical interconnection link can significantly improve the data transmission efficiency and reduce the latency. By optimizing the connection method between the optical interconnection computing unit and the switching unit, the computing resources in the cluster can be utilized more effectively, thereby improving the operating efficiency of the entire system. The optical interconnection technology is adopted to reduce the data communication latency compared with the network interconnection solution, and high-speed and low-latency data transmission can be achieved even in the case of cross-cabinet, which not only enhances the data processing capacity and response speed of the system, but also provides higher flexibility and reliability.

[0087] Specifically, when the interconnection port between two top-layer PCIe optical interconnection switching units is changed to connect to an optical interconnection computing unit, each optical interconnection computing unit can access 512 GPU-accelerated cards distributed at different locations through the top-layer PCIe optical interconnection switching unit, and the 512 GPU-accelerated cards can also perform PCIe data communication through the PCIe optical interconnection switching unit and the top-layer PCIe optical interconnection switching unit.

[0088] In an embodiment of the present application, the optical interconnection switching unit 230 includes at least one optical interconnection switching board. When the optical interconnection switching board is connected to computing resources based on an optical interconnection link, the optical interconnection switching board is connected to at least one optical interconnection computing unit 210.

[0089] It can be understood that in the embodiments of the present application, the optical interconnection switch board can uniformly converge and manage the PCIe data streams from multiple optical interconnection computing units, avoiding the topological chaos caused by the scattered connection of computing resources. When the optical interconnection switch board is connected to the optical interconnection computing unit, direct data exchange is achieved through the PCIe optical interconnection link, significantly improving the communication efficiency and data processing ability.

[0090] In the embodiments of the present application, when the optical interconnection switch board connects to the acceleration resources based on the optical interconnection link, the optical interconnection switch board is connected to at least one optical interconnection acceleration unit 220.

[0091] It can be understood that in the embodiments of the present application, the optical interconnection switch board is connected to at least one optical interconnection acceleration unit through the optical interconnection link, which not only solves the distance limitation problem of traditional electrical interconnection, but also significantly improves the scalability, flexibility and overall performance of the system, enabling large-scale GPU acceleration clusters to operate more efficiently in the data center environment.

[0092] Specifically, as Figure 8 shown, a single GPU acceleration cabinet contains a total of 4 optical interconnection acceleration units and at least one optical interconnection computing unit. A single cabinet contains 32 GPU acceleration cards, and a single optical interconnection computing unit can communicate with 32 GPU acceleration cards. Inside the cabinet, the optical interconnection computing unit outputs 8 groups of PCIe x16, which are respectively connected to 8 switching components in 4 optical interconnection acceleration units, forming 8 PCIe optical interconnection links between the optical interconnection computing unit and the optical interconnection acceleration unit. Each optical interconnection acceleration unit configures the externally connected 2*PCIe x16 as 4*PCIe x8 interconnection ports for use in the interconnection of switching components between acceleration resource pools within the cabinet, enabling high-speed and low-latency communication among 32 GPU acceleration cards in the same cabinet. In addition to the ports for internal interconnection, each switching component outputs 1*PCIe x16 optical signal for cross-cabinet connection to the PCIe optical interconnection switching unit within the PCIe switch cabinet. An 8*PCIe x16 optical signal from a GPU acceleration cabinet is connected to the same layer of PCIe optical interconnection switch board within the PCIe optical interconnection switching unit. The GPU acceleration cards distributed in different optical interconnection acceleration units can not only communicate through the interconnection ports between the internal resource pools of the cabinet, but also transfer data through the switching components on the PCIe optical interconnection switch board for communication. Similar to the above 8-card system, this cabinet can also be used alone as a 32-GPU acceleration card system. At this time, the 1*PCIe x16 connected to the PCIe optical interconnection switch board can be used for internal interconnection within the cabinet to optimize the GPU interconnection topology.

[0093] In the embodiments of the present application, the optical interconnection computing unit 210 includes: at least one central processor and at least one switching component.

[0094] Among them, the central processing unit is connected to at least one switching component, the switching component is connected to at least one optical-electric converter, and an optical interconnection link is formed between the optical-electric converter inside the computing unit and the optical-electric converter outside the computing unit. The central processing unit provides computing resources through the optical interconnection link.

[0095] It can be understood that the central processing unit of the embodiment of the present application is connected to external devices through an optical interconnection link, so that local computing resources can communicate efficiently with other nodes across physical distances, support low-latency and high-bandwidth data interaction between multiple nodes, improve the computing power and scalability of the overall system, thus breaking through the physical limitations of traditional electrical interconnections, and also realizing cross-node sharing and flexible expansion of computing resources, with high stability, low power consumption, easy maintenance, and strong scalability.

[0096] It should be noted that the optical-electric converter is responsible for converting between electrical signals and optical signals. Specifically: at the master control end, the optical-electric converter converts the electrical signal into an optical signal for transmission through an optical fiber; at the controlled end, the optical-electric converter then restores the received optical signal into an electrical signal for subsequent device processing.

[0097] In the embodiment of the present application, the optical interconnection computing unit 210 further includes at least one baseboard management controller, and the baseboard management controller is connected to at least one switching component and at least one optical-electric converter, and is used to manage the timing relationship between the switching component and the optical-electric converter and the establishment of the optical interconnection link.

[0098] It can be understood that in the embodiment of the present application, the baseboard management controller can accurately control the startup sequence of the switching component and the optical-electric converter and the working timing between the switching component and the optical-electric converter, ensuring that the transimpedance amplifier and driver of the optical-electric conversion device can perform PCIe link training after temperature compensation and bias current adjustment are completed, thereby ensuring the stable establishment of the link; reducing link failures caused by timing mismatches and improving system stability.

[0099] In the embodiment of the present application, the baseboard management controller detects the operating parameters of the optical-electric converter, and when it is determined that the optical-electric conversion device is in a stable state based on the operating parameters, an optical interconnection link is established.

[0100] It can be understood that in the embodiment of the present application, the baseboard management controller detects the operating parameters of the optical-electric converter, and when it is determined that the optical-electric conversion device is in a stable state based on the operating parameters, an optical interconnection link is established. Only when all key parameters meet the expected standards, the baseboard management controller will trigger the link establishment process, thus effectively avoiding link instability or failure problems caused by the device not being fully ready. If it is detected that some parameters deviate from the normal range, corresponding correction measures can be automatically executed, such as adjusting the bias current, notifying the administrator for maintenance, etc., to ensure that the optical-electric conversion device is always in the best working state.

[0101] It should be noted that, assuming in a large-scale GPU-accelerated cluster, multiple optical interconnection computing units need to be interconnected to form an efficient data processing network. Each computing unit contains at least one optoelectronic converter for realizing optoelectronic signal conversion. Without a baseboard management controller to monitor the operating state of the optoelectronic converter, link interruptions or data loss may frequently occur at the initial stage of link establishment because the optoelectronic converter has not reached a stable operating state. However, with the intervention of the baseboard management controller, it will only allow link establishment after all key parameters of the optoelectronic converter (such as temperature, bias current, optical power, etc.) meet the requirements, thus ensuring the reliability and stability of data transmission.

[0102] In the embodiment of the present application, the operating parameters include at least one of the state machine state, register state, and controlled-end optical power inside the optoelectronic conversion device. When the baseboard management controller determines that the operating parameters meet the target conditions, it determines that the optoelectronic conversion device is in a stable state, where the target conditions include: the state machine state is an effective state, where the baseboard management controller identifies the effective identification bit of the state machine, then determines that the state machine state is an effective state; the register state is a normal state, where the baseboard management controller identifies the normal identification bit of the register, then determines that the register state is a normal state; the controlled-end optical power is greater than a preset optical power.

[0103] Among them, the preset optical power can be set according to actual needs without specific limitation.

[0104] It can be understood that the embodiment of the present application can identify the effective identification bit of the state machine to confirm whether the state machine is in an effective state; identify the normal identification bit in the register to confirm whether the register is in a normal state without alarms or abnormalities; ensure that the optical power of the controlled end is greater than the preset value to ensure the quality of signal transmission. Only when all target conditions are met, the baseboard management controller will determine that the optoelectronic conversion device is in a stable state and allow the establishment of an optical interconnection link; by strictly checking the key operating parameters of the optoelectronic conversion device, the baseboard management controller can prevent link establishment when the device is not fully ready, thus avoiding potential link instability or failure problems, not only improving the reliability and stability of the system, but also enhancing the flexibility, adaptability, and management convenience of the system.

[0105] It should be noted that during the optoelectronic conversion process, any unstable factor may cause signal distortion and affect the final data transmission quality. By ensuring that the optoelectronic conversion device is in a stable state before establishing the link, signal distortion can be minimized, ensuring high-speed and low-latency data transmission. If the baseboard management controller detects that certain parameters deviate from the normal range (such as too high temperature, insufficient optical power, or register alarms), it can trigger corresponding correction measures, such as adjusting the bias current or notifying the administrator for maintenance, to ensure that the device is always in the best working state. The baseboard management controller can dynamically adjust the working parameters of the optoelectronic conversion device according to changes in the actual operating environment (such as temperature fluctuations, load changes, etc.) so that it can maintain the best performance under different conditions.

[0106] Specifically, as Figure 7 shown, the optical interconnection computing resource pool internally contains two CPU processors. Each CPU processor respectively outputs multiple groups of PCIe X16 electrical signals. Each group of PCIe x16 is connected to a switching component. Each switching component outputs two groups of PCIe x8, which are respectively connected to two optoelectronic converter connectors. At the same time, the on-board management device is connected to all the switching components and optoelectronic conversion devices inside the computing unit to control the initialization and link establishment process of the same PCIe optical interconnection link. On the one hand, the switching component optimizes the PCIe signals sent by the optoelectronic converter, and on the other hand, it can assist the PCIe optical interconnection link training process. The two optoelectronic converters connected to the same switching component can be used as 1*PCIe x16 or 2*PCIe x8, supporting more connection topologies for the system. Based on the above optical interconnection computing unit, multiple groups of PCIe optical interconnection links can be externally extended, which can be respectively connected to the optical interconnection switching unit or the optical interconnection acceleration resource to realize the expansion of computing resources in the form of PCIe optical signals.

[0107] In the embodiment of the present application, the optical interconnection switching unit 230 includes: at least one optical interconnection switching board.

[0108] Among them, the optical interconnection switching board includes a substrate connector and at least one switching component. The substrate connector is connected to the at least one switching component; the switching component is connected to at least one high-speed connector and at least one optoelectronic converter. The optical interconnection switching board communicates with other optical interconnection switching boards through the high-speed connector, and the optoelectronic converters of the optical interconnection switching board form an optical interconnection link with other optoelectronic converters.

[0109] It can be understood that in the embodiments of the present application, data communication between optical interconnection switching boards is carried out through high-speed connectors, which supports high-speed data exchange within and between boards, improves the data transmission efficiency between various modules inside the switching unit, reduces communication latency, and supports the rapid scheduling requirements of computing resources in large-scale GPU clusters; each switching component is connected to at least one optical-electric converter for establishing an optical interconnection link between local and remote devices. The optical-electric converters inside the optical interconnection switching board and those of other external units form an optical interconnection link, enabling data to be transmitted at high speed in the form of optical fibers between different cabinets, breaking the distance limitation of traditional copper cable PCIe connections, supporting flexible deployment across cabinets or even across floors, providing lower signal attenuation and higher anti-interference ability, ensuring stable communication over long distances, and realizing efficient cooperation of resources in large-scale GPU acceleration clusters.

[0110] Specifically, the optical interconnection switching unit mainly consists of 4 optical interconnection switching units, and the connection topology of a single optical interconnection switching unit is as Figure 10 shown. Each optical interconnection switching unit contains two switching components that support optical interconnection links. Each switching component supports connecting 9 groups of PCIe Gen5 x16 ports. Among them, 4 groups of PCIe x16 ports are connected to the MCIO x16 connector for internal interconnection within the switching unit to exchange the data transmitted by the external ports of the switching components with each other, and 5 groups of PCIe x16 are connected to 10 optical-electric converter connectors externally.

[0111] In the embodiments of the present application, the switching component includes multiple internal ports and multiple external ports.

[0112] Among them, the internal ports are connected to high-speed connectors, and the external ports are connected to optical-electric converters.

[0113] It can be understood that in the embodiments of the present application, the internal ports are connected to high-speed connectors, and the external ports are connected to optical-electric converters, which support multi-level network topologies, meet the requirements of efficient communication between large-scale GPU cards, and can achieve seamless interconnection between local and remote resources. This not only improves the bandwidth utilization rate and communication efficiency of the system but also enhances its scalability, stability, and manageability.

[0114] It should be noted that the internal ports are connected to high-speed connectors for high-speed data forwarding inside the optical interconnection switching unit or between different switching boards; the external ports are connected to optical-electric converters for establishing optical interconnection links with external devices such as computing units and acceleration units. According to the needs of application scenarios, the ratio of internal ports to external ports can be flexibly configured to adapt to cluster deployments of different scales.

[0115] In the embodiments of the present application, the configuration type of the external port includes any one of an uplink port, a downlink port, and an interconnection port. Among them, the uplink port is connected to computing resources, the downlink port is connected to acceleration resources, and the interconnection port is connected to other switching components.

[0116] It can be understood that in the embodiments of the present application, each external port can be configured as an uplink, downlink, or interconnection port according to actual deployment requirements to adapt to different application scenarios. Through flexible configuration, the system can build multiple network topologies to meet different requirements for communication paths in heterogeneous computing environments, which not only improves the communication efficiency and resource utilization rate of the system but also enhances its scalability, reliability, and manageability.

[0117] It should be noted that the uplink port is directly connected to computing resources: ensuring that the CPU can access remote GPU acceleration resources with the shortest path and reducing the intermediate forwarding level; the downlink port is directly connected to acceleration resources: avoiding the bandwidth bottleneck caused by the shared bus in the traditional switching component architecture and improving the communication efficiency between GPUs; the interconnection port constructs a high-speed channel: establishing a dedicated link between multiple switching components for internal load balancing or cross-processor data forwarding.

[0118] Specifically, as Figure 11 shown, each external optical-electric converter connector supports PCIe x8. According to the requirements of the usage scenario, the switching component can change the external PCIe x16 port into two independent PCIe x8 ports for use. A single PCIe switching chip can support up to 10 PCIe Gen5 x8 ports externally. Each x8 or x16 port can be flexibly configured as an uplink port (connected to computing resources), a downlink port (connected to acceleration resources), or an interconnection port (interconnection of switching components). If all the external ports of a switching component are configured as PCIe x16, with one being an uplink port and the rest being downlink ports, a group of PCIe x16 optical interconnection links can be extended to 4 groups of PCIe x16 optical interconnection links. When all the external ports are configured as PCIe x8, the expansion performance can be improved proportionally. Based on the differences in application scenarios, the internal port connection topology of the optical interconnection switching unit can be flexibly changed, the configuration type of the external port can be modified, the allocation ratio of the uplink port, downlink port, and interconnection port in the external port can be adjusted, and the data routing method between switching components can be optimized, supporting multiple interconnection topologies of the PCIe optical interconnection system to meet the requirements of the large-scale cluster of GPU acceleration cards for PCIe interconnection resources.

[0119] In the embodiments of the present application, the optical interconnection switching unit 230 further includes at least one clock buffer.

[0120] Among them, the clock buffer is connected to the clock port of the switching component and is used to enhance and distribute the clock signal of the switching component.

[0121] It can be understood that in the embodiments of the present application, the clock buffer is used to enhance and distribute the clock signal of the switching component, which can enhance the amplitude of the original clock signal and improve the integrity of the clock signal and stability.

[0122] It should be noted that assume in a large-scale GPU acceleration cluster, multiple switching components need to work together to achieve efficient distributed computing. Each processor relies on an accurate clock signal for data synchronization and processing scheduling. Without a clock buffer, as the system scale expands and the signal transmission distance increases, problems such as attenuation and distortion of the clock signal may occur, resulting in synchronization failures and data transmission errors. Especially in high-frequency application scenarios, signal attenuation is a common problem. The clock buffer compensates for the attenuation generated during transmission by amplifying the signal, thus ensuring signal quality.

[0123] In the embodiments of the present application, the optical interconnection acceleration unit 220 includes: at least one graphics processor and at least one switching component.

[0124] Among them, the switching component is connected to at least one graphics processor, the switching component is connected to at least one optoelectronic converter, the optoelectronic converters of the optical interconnection acceleration unit and other optoelectronic converters form an optical interconnection link, and at least one graphics processor provides acceleration resources through the optical interconnection link.

[0125] It can be understood that in the embodiments of the present application, by introducing optoelectronic converters and switching components, the GPU can establish a connection with remote computing resources through optical fibers, breaking through the distance limitation of traditional PCIe electrical connections; the optoelectronic converters of multiple optical interconnection acceleration units and other optoelectronic converters form an optical interconnection link to form a large-scale GPU cluster, which can flexibly allocate the number of GPUs according to the business load requirements, meet the elastic resource scheduling requirements in different scenarios, and improve the overall system utilization rate; the switching component is responsible for converting the PCIe protocol signal sent by the GPU into a format suitable for transmission on the optical link and restoring it to the original PCIe signal at the controlled end, reducing communication latency and improving heterogeneous computing efficiency.

[0126] It should be noted that the optical interconnection acceleration units in this application are all optical interconnection acceleration resource pools. The acceleration cards such as GPU / NPU (Graphics Processing Unit / Neural Processing Unit) originally bound to a single server are centrally deployed through optical interconnection links to achieve decoupling of physical resources, build a virtualized acceleration resource pool, and through the combination of high-speed optical interconnection technology and intelligent protocol processors, realize centralized management, on-demand scheduling, and remote transparent access of heterogeneous computing resources. It not only breaks the physical limitations of the traditional PCIe architecture, but also improves resource utilization, system flexibility, and operation and maintenance efficiency, and is the core infrastructure for building the next-generation high-performance and low-latency distributed heterogeneous computing system.

[0127] In the embodiment of this application, the switching component includes multiple ports. Among them, the ports are configured as internal ports and external ports. The internal ports are connected to the graphics processor, and the external ports are connected to the optical-electric converter. The configuration type of the external ports includes interconnection ports, and the interconnection ports are connected to other switching components inside the optical interconnection acceleration unit.

[0128] It can be understood that the embodiment of this application can reasonably configure the ports of the switching component to meet the requirements of communication paths in different application scenarios, realize efficient scheduling and communication management of GPU acceleration resources, and improve the communication efficiency and resource utilization of the system.

[0129] It should be noted that the internal ports are connected to the GPU: to ensure that the GPU can directly access the switching component through the PCIe interface for local data processing; the external ports are connected to the optical-electric converter: to achieve high-speed optical link communication with external computing resources and switching devices; the interconnection ports build an intra-chip / intra-board interconnection channel: to allow efficient data paths to be established between multiple switching components within the same acceleration unit, and realize seamless data flow from a single GPU to multiple GPUs, from local to remote.

[0130] Specifically, the connection topology of the PCIe optical interconnection acceleration unit is as Figure 12As shown in the figure, the resource pool consists of two switching components that support optical interconnection links and eight GPU acceleration cards inside. Each switching component is externally connected to 4 * PCIe x16 to eight optical - electrical converter connectors respectively. Inside, the 4 * PCIe x16 are respectively connected to four GPU acceleration cards. One group of PCIe x16 is configured as an interconnection port for the interconnection of the two internal switching components. The external optical - electrical converter of the PCIe optical interconnection acceleration unit can be directly connected to the optical interconnection computing unit to achieve a one - to - one correspondence between the CPU processor and the GPU acceleration card, ensuring high - speed and low - latency interconnection of PCIe data; it can also be connected to the PCIe optical interconnection switching unit and then connected to the optical interconnection computing unit through the PCIe optical interconnection switching unit. Based on the PCIe resource expansion of the PCIe optical interconnection switching unit and the function of internal PCIe data exchange, it can support the expansion of the scale of GPU acceleration cards that can be accessed by a single CPU processor, and the GPU acceleration cards within the cluster can also achieve high - speed communication through the PCIe optical interconnection switching unit; it can also, according to application requirements, configure some ports as uplink ports and connect them to the optical interconnection computing unit, and the remaining ports as interconnection ports for the interconnection between optical interconnection acceleration units. At this time, a single CPU processor can communicate with more GPU acceleration cards, and the GPU acceleration cards can also transmit PCIe data through the interconnection ports between the switching components, which can improve the communication bandwidth between GPU acceleration cards across resource pools.

[0131] The acceleration cluster system proposed according to the embodiments of the present application uses optical interconnection links to replace traditional copper cables. Utilizing the characteristics of low attenuation and anti - electromagnetic interference of optical fibers, it supports the interconnection of resource pools across cabinets, across floors, and even across regions; the optical interconnection computing unit, optical interconnection acceleration unit, and optical interconnection switching unit are dynamically combined as needed, and the number of resource pools can be freely increased or decreased according to the scenario. The resource pools support low - power, long - distance, and low - latency PCIe data transmission between in - cabinet / across - cabinet resource pools, and can achieve flexible expansion of the scale of the GPU acceleration cluster based on PCIe communication.

[0132] Next, it will be combined with Figure 12 to elaborate on the acceleration cluster system of the present application in detail as follows: This system utilizes the characteristic of the PCIe optical interconnection supporting long - distance transmission to distribute the thousand - card GPU acceleration cluster in 34 cabinets respectively. Among them, 32 cabinets are GPU acceleration card cabinets, and 2 cabinets are PCIe switch cabinets. Each GPU acceleration card cabinet contains four optical interconnection acceleration units. The entire GPU acceleration cluster contains a total of 128 optical interconnection acceleration units, supporting a total of 128 * 8 = 1024 GPU acceleration cards. The cabinets are connected by optical fibers to transmit PCIe optical signals, enabling long - distance and distributed deployment of the thousand - card GPU acceleration cluster based on PCIe interconnection.

[0133] Each resource pool of the present application includes a different number of switching components and connector interfaces for connecting optical - electrical converters externally. The switching components and the connector interfaces are preset with on - board PCIe links. When the resource pools are connected through optical - electrical converters and optical fibers, multiple PCIe optical interconnection links mentioned above can be formed between the resource pools. Based on the characteristics of low attenuation, anti - interference, and long - distance transmission of PCIe optical signals in optical fibers, it can support the distributed deployment of optical interconnection computing resource pools, optical interconnection switching units, and optical interconnection acceleration units across cabinets, floors, and regions, realizing the large - scale expansion of a GPU acceleration card cluster based on the PCIe protocol.

[0134] An embodiment of the present application also provides an optical interconnection computing unit. The system will be described in detail in combination with the operation process of this optical interconnection computing unit.

[0135] Specifically, Figure 13 is a block diagram of the optical interconnection computing unit provided by the embodiment of the present application.

[0136] As Figure 13 shown, the optical interconnection computing unit 210 is composed of an optical interconnection link component 10 and includes: at least one central processing unit and at least one switching component.

[0137] Among them, the central processing unit is connected to at least one switching component, the switching component is connected to at least one optical - electrical converter, and an optical interconnection link is formed between the optical - electrical converters inside the computing unit and the optical - electrical converters outside the computing unit.

[0138] It should be noted that the foregoing explanation of the acceleration cluster system embodiment also applies to the optical interconnection computing unit of this embodiment, and will not be elaborated here.

[0139] According to the optical interconnection computing unit proposed by the embodiment of the present application, an optical interconnection link is formed between the optical - electrical converters of the optical - electrical converter and other external units (such as optical interconnection acceleration units, optical interconnection switching units, etc.) through optical fibers, thereby realizing cross - unit data communication and meeting the high - bandwidth requirements in a large - scale GPU cluster.

[0140] An embodiment of the present application also provides an optical interconnection switching unit. The system will be described in detail in combination with the operation process of this optical interconnection switching unit.

[0141] Specifically, Figure 14 is a block diagram of the optical interconnection switching unit provided by the embodiment of the present application.

[0142] As Figure 14 shown, the optical interconnection switching unit 230 is composed of an optical interconnection link component 10 and includes: at least one optical interconnection switching board.

[0143] Among them, the optical interconnection switch board includes: a substrate connector and at least one switching component, wherein the substrate connector is connected to at least one switching component; the switching component is connected with at least one high-speed connector and at least one optoelectronic converter. The optical interconnection switch board performs data communication with other optical interconnection switch boards through the high-speed connector. An optical interconnection link is formed between the optoelectronic converters inside the optical interconnection switch board and the optoelectronic converters outside the optical interconnection switch board.

[0144] It should be noted that the foregoing explanation of the acceleration cluster system embodiment also applies to the optical interconnection switch unit of this embodiment, and will not be repeated here.

[0145] According to the optical interconnection switch unit proposed in the embodiment of the present application, data transmission between optical interconnection switch boards is carried out through high-speed connectors to ensure high-speed signal integrity. The switching component is connected to a processor responsible for routing and forwarding, and performs intelligent routing of data packets between multiple ports to reduce cross-device communication latency; each switching component is connected to at least one optoelectronic converter for establishing an optical interconnection link between local and remote devices. An optical interconnection link is formed between the optoelectronic converters inside the optical interconnection switch board and the optoelectronic converters of other external units, enabling data to be transmitted at high speed in a fiber optic manner between different cabinets, breaking the distance limitation of traditional copper cable PCIe connections, supporting flexible deployment across cabinets or even across floors, providing lower signal attenuation and higher anti-interference ability, ensuring stable communication over long distances, and realizing efficient coordination of resources in large-scale GPU acceleration clusters.

[0146] The embodiment of the present application also provides an optical interconnection acceleration unit. The system will be described in detail in combination with the operation process of the optical interconnection acceleration unit.

[0147] Specifically, Figure 15 It is a block diagram of the optical interconnection acceleration unit provided by the embodiment of the present application.

[0148] As Figure 15 shown, the optical interconnection acceleration unit 220 is composed based on the optical interconnection link component 10 and includes: at least one graphics processor and at least one switching component.

[0149] Among them, the switching component is connected to at least one graphics processor, the switching component is connected to at least one optoelectronic converter, the optoelectronic converters inside the optical interconnection acceleration unit and the optoelectronic converters outside the optical interconnection acceleration unit form an optical interconnection link, and at least one graphics processor provides acceleration resources through the optical interconnection link.

[0150] Specifically, as Figure 16As shown in the figure, each optical interconnection acceleration resource pool contains 8 GPUs. Each switching component is internally connected to 4 GPUs through 4 * PCIe x16 connections, 1 * PCIe x16 is used for the interconnection of switching components within the resource pool, 1 * PCIe x16 is used for connecting to the computing node externally, 1 * PCIe x16 is used for connecting to the PCIe optical interconnection switching unit, and 4 * PCIe x8 are configured as interconnection ports for the interconnection of optical interconnection acceleration resource pools within the GPU Chassis. Based on the above design method, the external connection method of the optical interconnection acceleration resource pool uses an optical - electrical converter to convert the PCIe electrical signal into an optical signal for transmission in the optical fiber. Each optical - electrical converter can transmit signals of PCIe x8. According to the requirements of the usage scenario, the allocation ratio of the ports connecting the PCIe optical interconnection switching unit and the interconnection ports in the above text can be adjusted to flexibly adapt to the application requirements. Each GPU acceleration resource pool can be independently connected to an optical interconnection computing unit separately from the cluster. At this time, one computing unit can communicate with 8 GPU acceleration cards.

[0151] It should be noted that the foregoing explanation of the acceleration cluster system embodiment also applies to the optical interconnection acceleration unit of this embodiment, and will not be elaborated here.

[0152] According to the optical interconnection acceleration unit proposed in the embodiment of the present application, by introducing an optical - electrical converter and a switching component, the GPU can establish a connection with remote computing resources through an optical fiber, breaking through the distance limitation of traditional PCIe electrical connections; multiple optical interconnection acceleration units can be interconnected through an optical interconnection link to form a large - scale GPU cluster, and the number of GPUs can be flexibly allocated according to the business load requirements to meet the elastic resource scheduling requirements in different scenarios and improve the overall system utilization rate; the switching component is responsible for converting the PCIe protocol signal sent by the GPU into a format suitable for transmission on the optical link and restoring it to the original PCIe signal at the receiving end, reducing the communication delay and enhancing the heterogeneous computing efficiency.

[0153] The embodiment of the present application also provides a non - volatile computer - readable storage medium. A computer program is stored in the non - volatile computer - readable storage medium, and the computer program is configured to execute the steps in any of the above - mentioned optical interconnection link training method embodiments when running.

[0154] In an exemplary embodiment, the above - mentioned computer - readable storage medium may include, but is not limited to: USB flash drive, read - only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk, or optical disc and other media that can store computer programs.

[0155] An embodiment of the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in the embodiment of the training method of the above optical interconnection link.

[0156] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in the embodiment of the method of the above shared memory resource pool.

[0157] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0158] The above has introduced in detail a system of a shared memory resource pool provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An optical interconnect link assembly, characterized in that: Including: A first optoelectronic converter, a second optoelectronic converter, a first switching component, and a second switching component. Among them, an optical interconnection link is formed between the first optoelectronic converter and the second optoelectronic converter, and the first switching component and the second switching component interact through the optical interconnection link; The first switching component is configured to continuously send a first detection character sequence and send a first response character sequence when receiving a second detection character sequence; The second switching component is configured to continuously send a second detection character sequence and send a second response character sequence when receiving a first detection character sequence; After the first switching component and the second switching component complete the interaction, the optical interconnection link enters a training process.

2. The optical interconnection link component according to claim 1, characterized in that, The first optoelectronic converter and the second optoelectronic converter have the same structure. Among them, the structures of the first optoelectronic converter and the second optoelectronic converter include: a linear transimpedance amplifier and a linear driver. The linear transimpedance amplifier is used to convert the optical signal output by the photodetector into an electrical signal with a target linearity, and the linear driver is used to convert the electrical signal received by the photodetector into a continuous modulation current to drive the laser to operate in the linear region to obtain an optical signal.

3. The optical interconnection link component according to claim 1, characterized in that, The first switching component processes the first electrical signal output by the first optoelectronic converter based on the electrical specification of the optical interconnection protocol; The second switching component processes the second electrical signal output by the second optoelectronic converter based on the electrical specification of the optical interconnection protocol.

4. The optical interconnection link component according to claim 1, wherein Both the first optoelectronic converter and the second optoelectronic converter are connected to the baseboard management controller. When the baseboard management controller detects that the optical interconnection link meets the link establishment condition, it establishes the optical interconnection link and controls the optical interconnection link to enter the training process.

5. A training method for an optical interconnection link, characterized in that: The method is applied to the first switching component of the optical interconnection link component according to any one of claims 1-4. Among them, the method includes: Controlling the first optoelectronic converter to continuously send a first detection character sequence, identifying the first electrical signal output by the first optoelectronic conversion device, and determining whether a second response character sequence is received within a preset duration. Among them, the second switching component outputs a second response character sequence after receiving the first detection character sequence; After determining that the second response character sequence is received within the preset duration, controlling the internal state machine of the first switching component to be set to an effective state, where the effective state indicates that the optical interconnection link is allowed to enter the training process.

6. The training method of the optical interconnection link according to claim 5, characterized in that Before controlling the internal state machine of the first switching component to be set to the effective state, it further includes: Identifying the first continuous reception quantity of the second response character sequence within the preset duration; If the first continuous reception quantity is greater than or equal to a preset quantity, controlling the internal state machine of the first switching component to be set to the effective state; If the first continuous reception quantity is less than the preset quantity, controlling the internal state machine of the first switching component to be set to an invalid state, where the invalid state indicates that the optical interconnection link is not allowed to enter the training process.

7. The training method of the optical interconnection link according to claim 6, wherein It also includes: Identify the first electrical signal output by the first photoelectric conversion device, determine the second detection character sequence output by the second switching component, and control the first photoelectric conversion device to send a first response character sequence.

8. The training method of the optical interconnection link according to claim 5, wherein, Before controlling the first photoelectric converter to continuously send the first detection character sequence, the method further includes: determining whether to detect a first device signal at the master end according to the type of the first switching component; If the type of the first switching component is a switching type, controlling the first photoelectric converter to continuously send a first detection character sequence; If the type of the first switching component is a relay type, after detecting the first device signal of the main control end, the first photoelectric converter is controlled to continuously send the first detection character sequence.

9. A training method for an optical interconnection link, characterized in that: The method is applied to the second switching component of the optical interconnect link component according to any one of claims 1 to 4, wherein the method comprises: controlling the second photoelectric converter to continuously transmit a second detection character sequence, identifying a second electrical signal output by the second photoelectric conversion device, and determining whether a first response character sequence is received within a preset time period, wherein the first switching component outputs a first response character sequence after receiving the second detection character sequence; After determining that the first response character sequence is received within a preset time period, controlling the internal state machine of the second switching component to be set to a valid state, wherein the valid state indicates that the optical interconnection link is allowed to enter a training process.

10. The training method of the optical interconnection link according to claim 9, characterized in that, Before controlling the internal state machine of the second switching component to be in a valid state, the method further includes: Identifying a second continuous reception quantity of the first response character sequence within the preset time period; If the second continuously received number is greater than or equal to a preset number, controlling the internal state machine of the second switching component to be set to a valid state; If the second continuous reception quantity is less than a preset quantity, the internal state machine of the second switching component is controlled to be set to an invalid state, wherein the invalid state indicates that the optical interconnection link is not allowed to enter the training process.

11. The training method of the optical interconnection link according to claim 10, wherein Also includes: Identify the second electrical signal output by the second photoelectric conversion device, determine the first detection character sequence output by the first switching component, and control the second photoelectric conversion device to send a second response character sequence.

12. The training method of the optical interconnection link according to claim 9, characterized in that, Before controlling the second photoelectric converter to continuously send the second detection character sequence, the method further includes: determining whether to detect a second device signal of the controlled end according to the type of the second switching component; If the type of the second switching component is a switching type, controlling the second photoelectric converter to continuously send a second detection character sequence; If the type of the second switching component is a relay type, after detecting the second device signal of the master end, the second photoelectric converter is controlled to continuously send the second detection character sequence.

13. An accelerated cluster system, characterized in that, The acceleration cluster system is based on the optical interconnection link component according to any one of claims 1 to 4, wherein the system includes: At least one optical interconnect computing unit and at least one optical interconnect acceleration unit, wherein the optical interconnect computing unit provides computing resources and the optical interconnect acceleration unit provides acceleration resources; At least one optical interconnection switching unit, wherein at least one of the optical interconnection switching unit and the optical interconnection computing unit and the optical interconnection acceleration unit is connected by an optical interconnection link, and / or, the optical interconnection acceleration unit and at least one of the optical interconnection computing units are connected by an optical interconnection link.

14. The acceleration cluster system according to claim 13, wherein When there are multiple optical interconnection switching units, at least one main switching unit and at least one secondary switching unit are included in the multiple optical interconnection switching units. The main switching unit and at least one of the secondary switching units are connected by an optical interconnection link, and the main switching units are connected by an optical interconnection link.

15. The acceleration cluster system according to claim 14, wherein At least one of the main switching unit and the secondary switching unit is connected to at least one optical interconnection computing unit by an optical interconnection link.

16. The acceleration cluster system according to claim 15, characterized in that: The optical interconnection computing unit includes: at least one central processing unit and at least one switching component. Among them, the central processing unit is connected to at least one switching component, the switching component is connected to at least one optoelectronic converter, and an optical interconnection link is formed between the optoelectronic converters inside the computing unit and the optoelectronic converters outside the computing unit. The central processing unit provides computing resources through the optical interconnection link.

17. The accelerated cluster system according to claim 16, wherein The optical interconnection computing unit further includes at least one baseboard management controller, which is connected to the at least one switching component and the at least one optoelectronic converter, and is used to manage the timing relationship between the switching component and the optoelectronic converter and the establishment of the optical interconnection link.

18. The acceleration cluster system according to claim 13, wherein The optical interconnection switching unit includes: at least one optical interconnection switching board, where the optical interconnection switching board includes: A baseboard connector and at least one switching component, where the baseboard connector is connected to the at least one switching component; The switching component is connected to at least one high-speed connector and at least one optoelectronic converter. Among them, the optical interconnection switching board performs data communication with other optical interconnection switching boards through the high-speed connector, and an optical interconnection link is formed between the optoelectronic converters of the optical interconnection switching board and other optoelectronic converters.

19. The accelerated cluster system according to claim 18, wherein The switching component includes a plurality of internal ports and a plurality of external ports, where the internal ports are connected to the high-speed connector, and the external ports are connected to the optoelectronic converter.

20. The acceleration cluster system according to claim 19, wherein The configuration type of the external port includes any one of an upstream port, a downstream port, and an interconnection port. Among them, the upstream port is connected to computing resources, the downstream port is connected to acceleration resources, and the interconnection port is connected to other switching components.

21. The accelerated cluster system according to claim 18, wherein The optical interconnection switching unit further includes at least one clock buffer, which is connected to the clock port of the switching component and is used to enhance and distribute the clock signal of the switching component.

22. The accelerated cluster system according to claim 13, wherein The optical interconnection acceleration unit includes: at least one graphics processing unit and at least one switching component. Among them, the switching component is connected to at least one graphics processing unit, the switching component is connected to at least one optoelectronic converter, and the optoelectronic converters of the optical interconnection acceleration unit and other optoelectronic converters form an optical interconnection link. The at least one graphics processing unit provides acceleration resources through the optical interconnection link.

23. The acceleration cluster system according to claim 22, characterized in that: The switching component includes a plurality of ports, wherein the ports are configured as internal ports and external ports, the internal port is connected to the graphics processor, the external port is connected to the photoelectric converter, and the configuration type of the external port includes an interconnection port, which is connected to other switching components.

24. An optical interconnection computing unit, characterized in that, The optical interconnection computing unit is based on the optical interconnection link component according to any one of claims 1 to 4, and includes: At least one central processing unit and at least one switching component, wherein the central processing unit is connected to at least one switching component, the switching component is connected to at least one photoelectric converter, and an optical interconnection link is formed between the photoelectric converter inside the computing unit and the photoelectric converter outside the computing unit.

25. An optical interconnection switching unit, characterized in that, The optical interconnection switching unit is based on the optical interconnection link component according to any one of claims 1 to 4, and includes: At least one optical interconnection switching board, wherein the optical interconnection switching board comprises: a substrate connector and at least one switching component, wherein the substrate connector is connected to at least one of the switching components; The switching component is connected with at least one high-speed connector and at least one photoelectric converter, wherein the optical interconnection switching board communicates data with other optical interconnection switching boards through the high-speed connector, and the photoelectric converter inside the optical interconnection switching board and the photoelectric converter outside the optical interconnection switching board form an optical interconnection link.

26. An optical interconnection acceleration unit, characterized in that: The optical interconnection acceleration unit is based on the optical interconnection link component according to any one of claims 1 to 4, and includes: At least one graphics processor and at least one switching component, wherein the switching component is connected to the at least one graphics processor, and the switching component is connected to at least one photoelectric converter, the photoelectric converter inside the optical interconnection acceleration unit and the photoelectric converter outside the optical interconnection acceleration unit form an optical interconnection link, and the at least one graphics processor provides acceleration resources through the optical interconnection link.

27. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the optical interconnection link training method according to any one of claims 5 to 12.

28. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the optical interconnection link training method according to any one of claims 5 to 12 are implemented.

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