Data link wireless communication timing synchronization method

Abstract

The invention provides a data link wireless communication timing synchronization method, which comprises the following steps of: adopting a plurality of groups of PN sequences as the basis of synchronous timing, detecting TOD after PN serial numbers when an effective synchronization symbol number is detected, carrying out CRC (cyclic redundancy check) on information contents, adopting RS (Reed-Solomon) coding and decoding, and then carrying out 8-time spectrum spreading; and the demodulation end determines an effective timing position according to serial numbers of different hops by taking the verified correct position as a basis for synchronizing the timing time point. The method has the beneficial effects that the synchronization signal-to-noise ratio can be reduced to be lower than 0db, and meanwhile, the false alarm probability and the missing alarm probability are greatly reduced, so that the frame synchronization performance is improved; and the anti-interference capability of the time domain and the frequency domain is enhanced.

Description

Technical Field

[0001] The present invention belongs to the technical field of data link wireless communication, and in particular relates to a data link wireless communication timing synchronization method. Background Art

[0002] Wireless data links are used to transmit real-time data (such as voice, video, sensor data, or control instructions), and are usually applied to the following scenarios: industrial automation: high-precision time synchronization (such as TSN time-sensitive network); mobile communication (5G / 6G): high-speed movement, millimeter-wave communication, large-scale MIMO. In these application scenarios, timing synchronization is the basis for ensuring the correct demodulation of signals at the receiving end. Timing synchronization is a process in a wireless data link system (such as Link-16, TTNT, industrial Internet of Things, etc.) to ensure that each node (platform, terminal, relay station, etc.) participating in the communication has a highly consistent time reference. Its goal is to make all nodes "know" that they should send or receive specific signals or data at the same moment. The core goal is to eliminate or minimize the time deviation caused by clock differences and signal propagation delays between nodes. If the synchronization fails, the entire frame of information will be lost. If the synchronization timing is inaccurate, it will lead to inter-symbol interference (ISI), an increase in the frequency offset cumulative bit error rate (BER), and even a communication link interruption. In wireless communication, wireless signal interference and anti-interference have always been a contradictory entity. Under such conditions, it is very important how the wireless signal can still decode the synchronization information under interference. Therefore, multi-hop synchronization and multiple timing information per hop are effective ways to solve interference. Summary of the Invention

[0003] In view of this, the present invention aims to propose a data link wireless communication timing synchronization method to solve the problems of high false alarm probability and missed alarm probability at a signal-to-noise ratio of 0 dB and weak anti-interference capabilities in the time domain and frequency domain in the prior art.

[0004] To achieve the above object, the technical solution of the present invention is realized as follows: A data link wireless communication timing synchronization method includes the following steps: S1. Construct synchronization frame information; S2. Send a frequency-hopping synchronization frame information once, and then send another frequency-hopping synchronization frame information; S3. Use the correct position of the TOD check of the synchronization frame information as the basis for the synchronization timing time point, and determine the effective timing synchronization position according to the serial numbers of different hops; In step S1, constructing the synchronization frame includes: S11. Construct a synchronization area; S12. Construct a PN sequence area, and the PN sequence area includes multiple groups of PN sequences; S13. Construct the TOD region, and perform CRC check, RS coding, and 8-fold spread spectrum processing on the TOD region; S14. Construct the idle region, where the idle region includes eight-byte idle bits; In step S12, construct the PN sequence region, including: The PN sequence region includes four groups of 127-bit PN sequences. The four groups of PN sequences are composed of four groups of gold sequences. The gold sequences are obtained by modulo-2 addition of two m-sequences. The four groups of gold sequences are obtained by modulo-2 addition of m-sequences with the same preferred pair and different initial phases. The order of the m-sequence is 7, and the period is 127 bits.

[0005] Furthermore, in step S11, construct the synchronization area, including: The synchronization area is an 8-μs pilot synchronization area, where 2 μs is used for frequency switching and waiting for the frequency switching to stabilize, and 6 μs is used for demodulating the system bit synchronization.

[0006] Furthermore, in step S122, the four groups of PN sequences, including: localparam FRAME_head_m1 = 127'hPN1; localparam FRAME_head_m2 = 127'hPN2; localparam FRAME_head_m3 = 127'hPN3; localparam FRAME_head_m4 = 127'hPN4.

[0007] Furthermore, in step S13, construct the TOD region, including: S131. Perform CRC check on the TOD region information; S132. Perform RS coding based on the TOD region information in step S131; S133. Perform 8-fold spread spectrum based on the TOD region information in step S132.

[0008] Furthermore, in step S131, the CRC check, including: Perform CRC check on the three-byte frequency hopping serial number, one-byte frequency hopping frequency point mask, one-byte synchronization frame number, and one-byte modulation information and rate information of the TOD region to generate one-byte CRC check bits. The polynomial for CRC check is: x 8 + x 5 + x³ + x² + x + 1.

[0009] Furthermore, in step S132, the RS coding, including: Perform RS encoding on the three-byte hopping sequence number, one-byte hopping frequency point mask, one-byte synchronization frame sequence number, one-byte modulation information and rate information, and one-byte CRC check bit in the TOD region. The RS encoding uses the RS(112,56) generated by the IP provided by vivado.

[0010] Further, in step S133, perform 8-fold spreading, including: Perform 8-fold spreading on RS(112,56) to form 896-bit information data.

[0011] Further, in step S2, send the hopping synchronization frame information once, and then send another hopping synchronization frame information, including: The other hopping synchronization frame information uses the same PN sequence group as the previous hopping. The difference from the TOD region of the previous hop is that the hopping sequence number is one less than that of the previous hop. At the same time, the CRC check value and the RS check are recalculated.

[0012] Further, in step S3, determine the effective timing synchronization position, including: S31: Use the end time point of spreading as the synchronization timing time point. According to the sequence position of different hops, use the end time point of spreading of the last hop as the effective timing synchronization position; S32: At the receiving demodulation end, if the CRC check of the last hop is correct, use it as the timing synchronization position. Otherwise, use other synchronization hops with correct CRC checks as the effective timing synchronization position identifiers, and make corresponding delays according to the synchronization sequence number to obtain the final synchronization timing position.

[0013] Compared with the prior art, the data link wireless communication timing synchronization method described in the present invention has the following beneficial effects: (1) Use multiple groups of PN sequences as the basis for synchronization timing. When the number of effective synchronization symbols is detected, then detect the TOD after the PN sequence number. The TOD is 8-fold or other multiple spreading. Use RS encoding and decoding or other encoding and decoding methods to improve the signal-to-noise ratio, perform CRC check or summation check on the information content to improve information security, and use the position with correct check as the basis for the synchronization timing time point, and determine the effective timing position according to the sequence position of different hops.

[0014] (2) Reduce the false alarm probability and missed alarm probability at a signal-to-noise ratio of 0 db, thereby improving the frame synchronization performance.

[0015] (3) Strengthen the anti-interference ability in the time domain and frequency domain. Description of the Drawings

[0016] The accompanying drawings, which form a part of the present invention, are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not unduly limit the present invention. In the drawings: Figure 1 It is a schematic diagram of the theoretical performance curve of the 48-sequence frame synchronization described in the embodiment of the present invention; Figure 2 It is a schematic diagram of the definition of the synchronization frame structure described in the embodiment of the present invention; Figure 3 It is a schematic diagram of the CRC generation logic described in the embodiment of the present invention; Figure 4 It is a schematic diagram of the theoretical performance curve of the 127-sequence frame synchronization with verification described in the embodiment of the present invention. Detailed implementation manners

[0017] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0018] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "mounted", "connected", "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood through specific situations.

[0020] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0021] Glossary: TOD: Time Of Day, is a time synchronization technology based on the clock of a computer system. It synchronizes the computer system clock to the global standard time. Here, this concept is borrowed, and the transmitted information content is the information in the frequency domain (hopping frequency points) and the time domain (hopping sequence numbers).

[0022] As Figures 1 to 4 shown, a data link wireless communication timing synchronization method includes the following steps: including the following steps: S1. Construct synchronization frame information; S2. Send a hopping synchronization frame information once, and then send another hopping synchronization frame information; S3. Use the position where the TOD check of the synchronization frame information is correct as the basis for the synchronization timing time point, and determine the effective timing synchronization position according to the sequence positions of different hops.

[0023] The specific implementation is as follows: I. Ordinary synchronization timing method: The ordinary synchronization timing technology is that the transmitting end sends a PN sequence, and the receiving end uses this PN sequence to perform channel correlation operations. According to the results of the correlation operations, it judges whether the received information is synchronized and generates subsequent receiving timing information of the system. The PN sequence (pseudo-noise sequence) is a special binary sequence, which is often used as a pseudo-random signal in communication systems. It is mainly used in aspects such as spread-spectrum communication, spread-spectrum modulation, synchronization and encryption in wireless communication. The synchronization timing of the PN sequence is an important aspect in its application, especially for the receiving end to correctly synchronize to the signal of the transmitting end to ensure the correctness and reliability of data transmission.

[0024] 1. Basic principle of the PN sequence: Definition: The PN sequence is generated by a specific feedback shift register. Its characteristic is that the autocorrelation function of the sequence is very large when the delay is zero, and has very small values at other delays. This characteristic makes the PN sequence have good autocorrelation and cross-correlation characteristics, and is very suitable for use as a synchronization signal.

[0025] 2. Generation method of the PN sequence: Generally, the PN sequence can be generated by a linear feedback shift register (LFSR). The initial state and feedback polynomial of the LFSR determine the specific form of the sequence.

[0026] For example, the feedback polynomial of a common 8-bit PN sequence can be x^8 + x^4 + x^3 + x^2 + 1.

[0027] 3. Principle of synchronization timing: In a communication system, the receiving end needs to accurately synchronize with the signal of the transmitting end in order to correctly decode the information. For the synchronization timing of the PN sequence, there are mainly the following methods: Correlation detection: The receiving end performs a correlation operation on the received signal and the locally generated PN sequence. If the signal is well synchronized with the clock, the correlation value will be very high, thus triggering the synchronization process.

[0028] A correlation detector is usually used to measure the correlation between the received signal and the locally generated sequence. When a sufficiently high correlation is detected, the correct synchronization point can be considered to be found.

[0029] Phase-locked loop (PLL): The phase-locked loop technology is used to track and lock the phase of the received signal. The PLL can automatically adjust the local clock frequency and phase of the receiving end to synchronize with the clock of the transmitting end. The PLL usually includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector compares the phase of the input signal with the phase of the reference signal, and the loop filter adjusts the output of the VCO to reduce the phase error.

[0030] Timing recovery: In some systems, it may also be necessary to accurately recover the timing of the signal, that is, to determine the exact arrival time of each bit. This can be achieved by sampling and timing analysis of the received signal. Timing recovery usually involves signal sampling and edge detection to accurately know when each data bit starts and ends.

[0031] 4. Implementation steps of ordinary synchronization timing technology: Generate a local PN sequence: Generate the same PN sequence as the transmitting end at the receiving end.

[0032] Correlation operation: Perform a correlation operation on the received signal and the locally generated PN sequence.

[0033] Synchronization decision: Judge whether synchronization is achieved according to the magnitude of the correlation value.

[0034] PLL adjustment: If more accurate synchronization is required, the PLL technology can be used to further adjust the clock.

[0035] Data decoding: Once synchronization is achieved, data decoding can begin.

[0036] Through the above methods, the receiving end can accurately synchronize with the PN sequence of the transmitting end, thus ensuring the accuracy and reliability of data transmission.

[0037] II. Measurement of frame synchronization performance: In a complex electromagnetic environment, a working environment with a relatively high dry signal-to-noise ratio, and a working environment with a relatively low signal-to-noise ratio, how to improve the reliability of synchronization, that is, to ensure a relatively low probability of false synchronization and a relatively low probability of missed detection, is the main issue considered in the present invention. The probability of missed detection ( ) and the probability of false synchronization ( ) are two important indicators for measuring the performance of frame synchronization.

[0038] 1. Calculation of the probability of missed detection: Channel noise and interference can cause some code elements of the frame header synchronization code group in the information code stream to have transmission errors, resulting in incorrect identification by the frame header identifier. This makes it erroneously believe that there is no synchronization code when there is actually a synchronization code. The probability of this situation occurring is called the probability of missed detection, denoted by . Taking a 7-bit synchronization code as an example, if the decision threshold is set to 6, when 1 bit of the synchronization code has an error, the output result of the adder is 5. Since it is less than the decision threshold, a missed decision will occur. If the decision threshold is reduced to 4, no decision error will occur. Therefore, the size of the probability of missed detection is related to the decision threshold. Further, it is related to the number of bits of the synchronization code that allows errors.

[0039] Let be the probability of a code element having an error, be the number of code elements in the synchronization code group, be the maximum number of code elements that allow errors. Then the probability of error-free transmission of the code elements in the synchronization code group is , the probability of having 1 error is , and the probability of having errors is . Since is the maximum number of code elements that allow errors, the probability that the synchronization code identifier can correctly detect is . Correspondingly, the probability of missed detection is ; Among them, is the combination number of taking from . Here, r is the value variable used for traversing the calculation of the combination number, and it has a similar physical meaning to m, indicating the situation of having r errors.

[0040] For common modulations such as BPSK and QPSK, the theoretical bit error rate at different SNRs can be obtained as the probability of a code element having an error. From this, the theoretical probability of missed detection can be calculated.

[0041] 2. Calculation of the probability of false synchronization: In the case of receiving symbol data bitstreams or when there is no signal and only noise exists, since the content-random signal codes or other random interferences are similar to the synchronization code, the recognizer will misidentify it as the synchronization code at this time, thus sending out an incorrect frame synchronization signal. The probability of being misjudged as a valid synchronization is the false alarm probability, denoted by which is

[0042] Similarly, assume is the number of code elements in the synchronization code group, and is the maximum number of code elements allowed to have errors. Since the probability of each code element in the information bitstream taking "0" or "1" is an equiprobable event, the probability that all code elements entering the shift register are the same as the synchronization code is , the probability of having one different is , the probability of having different bits is , then the probability of allowing errors within bits is , that is, in the case of allowing synchronization code errors, the false alarm probability is: [[ID=2⑧]]; The most ideal situation is that both the false alarm probability and the miss detection probability of the correlation peak detection are relatively small, so that a reliable judgment result can be obtained. However, the false alarm probability and the miss detection probability will not decrease simultaneously.

[0043] If a 7-bit synchronization code is used as the synchronization code group, assume the symbol error rate is , when and , the miss detection probability and the false alarm probability are respectively: ; ; and ; ; If a 13-bit synchronization code is used, assume the symbol error rate is , when and , the miss detection probability and the false alarm probability are respectively: ; ; and ; ; It can be seen that when the number of symbol bits is fixed and the symbol error rate remains unchanged, as the number of allowed error symbol bits With the increase of [[ID=]], the probability of missed detection will decrease, but the false alarm probability will increase; on the contrary, if the number of synchronization symbols is increased, the false alarm probability will decrease, but the probability of missed detection will increase. Therefore, the selection of the synchronization code length and the allowable number of error symbols needs to be compromised between the probability of missed detection and the false alarm probability.

[0044] As Figure 1 shown, the figure shows the theoretical false alarm probability and missed detection probability of the synchronization sequence, where the threshold is , that is, the number of correct symbols. It can be seen from the figure that the false alarm probability and the missed detection probability are related to the threshold selection. The higher the threshold, the lower the false alarm probability and the higher the missed detection probability; the SNR affects the missed detection probability, and the lower the SNR, the higher the missed detection probability. In practical applications, the threshold and the synchronization code length should also be selected in combination with the lowest working SNR so that the false alarm probability and the missed detection probability meet the system requirements.

[0045] Example 1: The present invention sets the PN sequence to 128 bits, and there are 4 types of PN sequences, which are composed of 1^28×4 = 512 bits. After the four groups of PN sequences, the TOD area is given. The data information content constituting the TOD is considered according to 7 bytes, where 6 bytes are the information itself and 1 byte is the information CRC check. These 7 bytes are spread spectrum by 8 times, and then encoded according to 1 / 2RS to form 7×8×8×2 = 896 bits of data and sent to the channel.

[0046] In order to improve the anti-interference performance of the system, after the above one-hop information is sent, the information of another hop is given, and the same PN sequence group is sampled, and the content serial number of the TOD is reduced by one to ensure that the next hop can be normally synchronized and timed after the previous hop is interfered.

[0047] 1. Frame structure definition: As Figure 2 shown, at the beginning of the frame, an 8 μs pilot synchronization area is provided, where 2 μs is used for frequency switching and waiting for the frequency switching to be stable, and 6 μs is used for demodulating the system bit synchronization; Four groups of 127-bit PN sequences, and these four groups of PN sequences are composed of 4 groups of gold sequences. The generation process of each PN sequence is: generated by modulo 2 addition of a pair of m-sequence optimal pairs to form a 127-bit PN sequence. In the present invention, 4 groups of PN sequences are obtained by modulo 2 addition of the same optimal pair with different initial phases to obtain 4 groups of gold sequences. In this way, the PN sequence can obtain better cross-correlation characteristics and autocorrelation characteristics; TOD Region: The original information includes the hopping sequence number (3 bytes), the hopping frequency point mask (1 byte), the synchronization frame number, the modulation information and the rate information (2 bytes). The above 6-byte information is CRC-checked (1 byte, TOD check), and the 7-byte information after checking is RS-encoded (112, 56). The 112-bit original information is 56 bits, and the RS check bits are 56 bits. The 112-bit information is spread spectrum by 8 times to form 896-bit information; Idle bits: To meet 100 us per hop, 64 idle bits are added to meet the time requirement.

[0048] 2. PN Sequence: Generated from the m-sequence, a 127-bit periodic m-sequence with a stage number of 7. Its preferred pairs are: 203, 211, 217, 235, 277, 313, 325, 345, 367; Two of them are used as preferred pairs to generate four groups of PN sequences, and the generated PN sequences are: localparam FRAME_head_m1 = 127'hPN1; localparam FRAME_head_m2 = 127'hPN2; localparam FRAME_head_m3 = 127'hPN3; localparam FRAME_head_m4 = 127'hPN4; Four groups of 127-bit PN sequences formed; 3. CRC Check: As Figure 3 shown, the check polynomial used is: x 8 + x 5 + x³ + x² + x + 1, g0 ~ gn are 1 1 1 1 01 0 0 1, where "0" means disconnection and "1" means connection. M(x) is the input information sequence to be checked, CLK is the system working clock, D represents the D flip-flop, Q1~Qn are the output results of the D flip-flop, and the "⊕" symbol represents the exclusive OR of the two input signals and outputs to the next D flip-flop, and the output result of Qn.

[0049] 4. RS Encoding and Decoding: RS encoding and decoding uses the IP provided by vivado to generate RS(112,56). This sequence has good error correction ability. The original information generates 7-byte data after CRC check, a total of 56 bits, and after RS(112,56) encoding, 112-bit data is obtained.

[0050] 5. 8-fold Spread Spectrum: The binary 01110010 is used as the spreading code, and 8-fold spreading is performed on the TOD segment information. The 112-bit information is spread 8 times to generate 112×8 = 896-bit data.

[0051] As Figure 4 shown, it is the effect simulation of the present invention. When the frame synchronization is performed on the 127-bit gold sequence, the false alarm probability and the missed alarm probability curves output under different thresholds (i.e., matching values) are shown. The abscissa is the threshold, and the ordinate is the probability. At the same time, when the signal-to-noise ratio is from -10 db to 4 db, Figure 4 the first blue line on the left is the false alarm probability, and the other 8 lines are the missed alarm probabilities.

[0052] The beneficial effects and advantages of the present invention are as follows: (1) Multiple groups of PN sequences are used as the basis for synchronous timing. When the number of valid synchronization symbols is detected, the TOD after the PN serial number is detected. The TOD is 8-fold or other multiple spreading. RS encoding and decoding or other encoding and decoding methods are used to improve the signal-to-noise ratio. CRC check or sum check is performed on the information content to improve information security. The correct check position is used as the basis for the synchronous timing time point. According to the sequence positions of different hops, the effective timing position is determined.

[0053] (2) Reduce the false alarm probability and the missed alarm probability at a signal-to-noise ratio of 0 db, thereby improving the frame synchronization performance.

[0054] (3) Strengthen the anti-interference ability in the time domain and the frequency domain.

[0055] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data link wireless communication timing synchronization method, characterized in that: It includes the following steps: S1. Construct synchronization frame information; S2. Send a frequency-hopping synchronization frame information once, and then send another frequency-hopping synchronization frame information; S3. Use the correct position of the TOD check of the synchronization frame information as the basis for the synchronization timing time point, and determine the effective timing synchronization position according to the serial numbers of different hops; In step S1, constructing a synchronization frame includes: S11. Construct a synchronization area; S12. Construct a PN sequence area, and the PN sequence area includes multiple groups of PN sequences; S13. Construct a TOD area, and perform CRC check, RS coding and 8-fold spreading processing on the TOD area; S14. Construct an idle area, and the idle area includes eight-byte idle bits; In step S12, constructing a PN sequence area includes: The PN sequence area includes four groups of 127-bit PN sequences. The four groups of PN sequences are composed of four groups of gold sequences. The gold sequence is obtained by modulo-2 addition of two m-sequences. The four groups of gold sequences are obtained by modulo-2 addition of m-sequences with the same preferred pair and different initial phases. The order of the m-sequence is 7 and the period is 127 bits.

2. A data link wireless communication timing synchronization method according to claim 1, characterized in that: In step S11, constructing a synchronization area includes: The synchronization area is an 8-μs pilot synchronization area, where 2 μs is used for frequency switching and waiting for the frequency switching to be stable, and 6 μs is used for demodulating the system bit synchronization.

3. A data link wireless communication timing synchronization method according to claim 1, wherein: In step S122, the four groups of PN sequences include: localparam FRAME_head_m1 = 127'hPN1; localparam FRAME_head_m2 = 127'hPN2; localparam FRAME_head_m3 = 127'hPN3; localparam FRAME_head_m4 = 127'hPN4.

4. A data link wireless communication timing synchronization method according to claim 1, characterized in that: In step S13, constructing a TOD area includes: S131. Perform CRC check on the TOD area information; S132. Perform RS coding based on the TOD area information in step S131; S133. Perform 8-fold spreading based on the TOD area information in step S132.

5. A data link wireless communication timing synchronization method according to claim 4, characterized in that: In step S131, the CRC check includes: Perform CRC check on the three-byte hopping sequence number, one-byte hopping frequency point mask, one-byte synchronization frame sequence number, one-byte modulation information and rate information in the TOD area to generate a one-byte CRC check bit. The polynomial for CRC check is: x 8 + x 5 + x³+ x² + x + 1。 6. A data link wireless communication timing synchronization method according to claim 4, characterized in that: In step S132, the RS coding includes: Perform RS coding on the three-byte frequency-hopping serial number, one-byte frequency-hopping frequency point mask, one-byte synchronization frame serial number, one-byte modulation information and rate information, and one-byte CRC check bit of the TOD area. The RS coding uses the RS(112,56) provided by vivado.

7. A data link wireless communication timing synchronization method according to claim 4, characterized in that: In step S133, the 8-fold spreading includes: Perform 8-fold spreading on RS(112,56) to form 896-bit information data.

8. A data link wireless communication timing synchronization method according to claim 1, characterized in that: In step S2, sending a frequency-hopping synchronization frame information once, and then sending another frequency-hopping synchronization frame information includes: The other frequency-hopping synchronization frame information uses the same PN sequence group as the previous frequency-hopping. The difference from the TOD area of the previous hop is that the frequency-hopping serial number is one less than that of the previous hop, and at the same time, the CRC check value and the RS check are recalculated.

9. A data link wireless communication timing synchronization method according to claim 1, characterized in that: In step S3, determine the effective timing synchronization position, including: S31. Take the spreading end time point as the synchronization timing time point. According to the sequence positions of different hops, take the spreading end time point of the last hop as the effective timing synchronization position; S32. At the receiving demodulation end, if the CRC check of the last hop is correct, take it as the timing synchronization position. Otherwise, take other synchronization hops with correct CRC checks as the effective timing synchronization position identifiers, and make corresponding delays according to the synchronization sequence numbers to obtain the final synchronization timing position.

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