Embedded ReRAM with backside contact

Abstract

There is provided a semiconductor structure including a single transistor single capacitor (1T1R) device including: an embedded resistive random access memory (ReRAM) having a width greater than 1 gate pitch, present at a front side or a back side of the structure; a front side contact structure electrically connected to a source region of the transistor of the 1T1R device; and a backside contact structure electrically connected to the drain region of the transistor of the 1T1R device.

Description

BACKGROUND OF THE INVENTION

[0001] This application relates to semiconductor technology, and more particularly, to a semiconductor structure including an embedded resistive random access memory (ReRAM) having a backside contact for reducing the forming voltage of the ReRAM.

[0002] A non-volatile memory (NVM) or non-volatile storage device is a computer memory that can retain stored information even after the power supply has been removed. In contrast, volatile memory requires a constant power supply to retain data. NVMs, such as, for example, ReRAM (or sometimes just RRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM), are being re-noticed for potential applications in neuromorphic computing with in-memory processing capabilities that significantly reduce power consumption and eliminate the data bus buffering time between a conventional complementary metal oxide semiconductor (CMOS)-based memory and a central processing unit (CPU) for neuromorphic computing. ReRAM is considered a promising technology for electronic synaptic devices or memristors for neuromorphic computing as well as for high density and high speed NVM applications. In neuromorphic computing applications, a resistive memory device such as a ReRAM device can be used as a connection (i.e., synapse) between a pre-neuron and a post-neuron, representing the connection weight in the form of the device resistance. SUMMARY OF THE INVENTION

[0003] A semiconductor structure including a single transistor single capacitor (1T1R) device is provided, comprising: an embedded ReRAM present on a front side or a back side of the structure; a front side contact structure electrically connected to a source region of the transistor of the 1T1R device; and a back side contact structure electrically connected to a drain region of the transistor of the 1T1R device. By placing these two contact structures on opposite sides of the structure, low voltage switching of the ReRAM can be achieved without increasing the size of the ReRAM or the forming voltage itself. The ReRAM can have a width greater than 1 gate pitch. In this application, the term "gate pitch" represents the distance between a point on a gate structure and the exact point on the nearest neighboring gate structure.

[0004] In one embodiment of the present application (i.e., the front-side ReRAM embodiment), the semiconductor structure includes a transistor located in a memory device region, and includes a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, wherein the second side of the gate structure is opposite to the first side of the gate structure. The structure further includes a ReRAM located in the memory device region and positioned above the transistor, a front-side contact structure electrically connecting the ReRAM to the source region of the transistor, and a back-side contact structure electrically connecting the drain region of the transistor to a back-side backend-of-line (BEOL) structure. In this front-side ReRAM embodiment, the ReRAM switching area is effectively increased without increasing the gate pitch.

[0005] In this front-side ReRAM embodiment, the transistor can be a nanosheet transistor including a plurality of vertically stacked and spaced semiconductor channel material nanosheets, wherein the gate structure of the transistor wraps around the middle portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced semiconductor channel material nanosheets. In such an embodiment, the structure may further include a bottom dielectric isolation layer and a back-side interlayer dielectric material layer located below the nanosheet transistor, wherein the back-side contact structure passes through both the back-side interlayer dielectric material layer and the bottom dielectric isolation layer and makes direct physical contact with the drain region of the transistor.

[0006] In this front-side ReRAM embodiment, the structure may further include a source / drain contact structure positioned between the front-side contact structure and the source region of the transistor, wherein the front-side contact structure makes direct physical contact with a first surface of the source / drain contact structure, and a second surface of the source / drain contact structure opposite to the first surface makes direct physical contact with the source region of the transistor.

[0007] In this front-side ReRAM embodiment, the structure may further include a front-side BEOL structure located above the ReRAM, wherein the front-side BEOL structure is electrically connected to the top electrode of the ReRAM through a front-side BEOL-to-ReRAM metal via. In such an embodiment, the front-side BEOL-to-ReRAM metal via passes through a dielectric material layer present on the ReRAM.

[0008] In this front-side ReRAM embodiment, the structure may further include a carrier wafer located on the surface of the front-side BEOL structure.

[0009] In this front-side ReRAM embodiment, the ReRAM is embedded in the front-side interlayer dielectric material layer.

[0010] In this front - side ReRAM embodiment, the structure may further include a logic device region adjacent to the memory device region, where the logic device region includes another transistor. The another transistor includes another gate structure, another source region on a first side of the another gate structure, and another drain region on a second side of the another gate structure, where the second side of the another gate structure is opposite to the first side of the another gate structure. In such an embodiment, the structure may further include another front - side contact structure that electrically connects the another source region of the another transistor to the front - side BEOL structure, and another back - side contact structure that electrically connects the another drain region of the another transistor to the back - side BEOL structure.

[0011] In another embodiment of the present application (i.e., the back - side ReRAM embodiment), the semiconductor structure includes a transistor in the memory device region, and includes a gate structure, a source region on a first side of the gate structure, and a drain region on a second side of the gate structure, where the second side of the gate structure is opposite to the first side of the gate structure. The structure of this back - side ReRAM embodiment further includes a ReRAM in the memory device region and positioned under the transistor, a front - side contact structure that electrically connects the source region of the transistor to the front - side BEOL structure, and a back - side contact structure that electrically connects the drain region of the transistor to the ReRAM. In this back - side ReRAM embodiment, the ReRAM switching region is effectively increased without increasing the gate pitch.

[0012] In this back - side ReRAM embodiment, the transistor is a nanosheet transistor including a plurality of vertically stacked and spaced semiconductor channel material nanosheets, where the gate structure of the transistor wraps the middle portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced semiconductor channel material nanosheets. In such an embodiment, the structure may further include a bottom dielectric isolation layer and a back - side interlayer dielectric material layer under the nanosheet transistor, where the back - side contact structure passes through both the back - side interlayer dielectric material layer and the bottom dielectric isolation layer and makes direct physical contact with the drain region of the transistor.

[0013] In this back - side ReRAM embodiment, the structure may further include a source / drain contact structure positioned between the front - side contact structure and the source region of the transistor, where the front - side contact structure makes direct physical contact with a first surface of the source / drain contact structure, and a second surface of the source / drain contact structure opposite to the first surface makes direct physical contact with the source region of the transistor.

[0014] In this back - side ReRAM embodiment, the structure may further include a front - side metal via positioned between the front - side contact structure and the front - side BEOL structure, where the front - side metal via has a first surface that directly contacts the front - side BEOL structure and a second surface that directly contacts the front - side contact structure and is opposite to the first surface.

[0015] In this backside ReRAM embodiment, the structure may further include a backside BEOL structure located under the ReRAM, where the backside BEOL structure is electrically connected to the bottom electrode of the ReRAM through a backside BEOL-to-ReRAM metal via.

[0016] In this backside ReRAM embodiment, the structure may further include a carrier wafer located on the surface of the frontside BEOL structure.

[0017] In this backside ReRAM embodiment, the ReRAM is embedded in the backside interlayer dielectric material layer.

[0018] In this backside ReRAM embodiment, the structure may further include a logic device region adjacent to the memory device region, where the logic device region includes another transistor, and the another transistor includes another gate structure, another source region located on a first side of the another gate structure, and another drain region located on a second side of the another gate structure, where the second side of the another gate structure is opposite to the first side of the another gate structure. In such an embodiment, the structure may further include another frontside contact structure that electrically connects the another source region of the another transistor to the frontside BEOL structure, and another backside contact structure that electrically connects the another drain region of the another transistor to the backside BEOL structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A is a cross-sectional view of an exemplary structure present in a memory device region of a semiconductor substrate, and the exemplary structure includes a transistor, a ReRAM, a frontside contact structure, a frontside BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate.

[0020] Figure 1B is a cross-sectional view of an exemplary structure present in a logic device region of a semiconductor substrate, and the logic device region is located adjacent to Figure 1A the memory device region shown in, where the exemplary structure in the logic device region includes a transistor, a frontside contact structure, a frontside BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate.

[0021] Figures 2A - 2B are respectively cross-sectional views of the exemplary structure shown in Figures 1A - 1B after removing the semiconductor substrate to allow backside processing in both the memory device region and the logic device region.

[0022] Figures 3A - 3B are respectively cross-sectional views of the exemplary structure shown in Figures 2A - 2BCross-sectional views of exemplary structures as shown.

[0023] Figures 4A - 4B Cross-sectional views after forming backside contact structures in the memory device region and the logic device region, respectively. Figures 3A - 3B Cross-sectional views of exemplary structures as shown.

[0024] Figures 5A - 5B Cross-sectional views after forming the backside BEOL structure, respectively. Figures 4A - 4B Cross-sectional views of exemplary structures as shown.

[0025] Figure 6A A cross-sectional view of another exemplary structure present in the memory device region of a semiconductor substrate, the exemplary structure including a transistor, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate.

[0026] Figure 6B A cross-sectional view of another exemplary structure present in the logic device region of a semiconductor substrate, the logic device region being located adjacent to the Figure 6A memory device region as shown, wherein the other exemplary structure in the logic device region includes a transistor, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate.

[0027] Figures 7A - 7B Cross-sectional views after removing the semiconductor substrate to allow backside processing in both the memory device region and the logic device region, respectively. Figures 6A - 6B Cross-sectional views of exemplary structures as shown.

[0028] Figures 8A - 8B Cross-sectional views after forming a first backside interlayer dielectric material layer in the memory device region and the logic device region, respectively. Figures 7A - 7B Cross-sectional views of exemplary structures as shown.

[0029] Figures 9A - 9B Cross-sectional views after forming backside contact structures in the memory device region and the logic device region, respectively. Figures 8A - 8B Cross-sectional views of exemplary structures as shown.

[0030] Figures 10A - 10B Respectively Figures 9A - 9B Cross-sectional views of the exemplary structures as shown after further backside processing, the backside processing including forming ReRAM in the memory device region and forming a backside BEOL structure. Detailed Description

[0031] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and are therefore not drawn to scale. It should also be noted that the same and corresponding elements are denoted by the same reference numerals.

[0032] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, one of ordinary skill in the art will understand that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

[0033] It should be understood that when an element that is a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element or there can also be an intermediate element. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there is no intermediate element. It will also be understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under or beneath the other element or there can be an intermediate element. In contrast, when an element is referred to as being "directly under" or "directly beneath" another element, there is no intermediate element.

[0034] Conventional filamentary switch ReRAM devices require a forming step to generate a soft breakdown. On the one hand, as the switching area scales down, the forming voltage increases, such that additional external devices are required, which results in power consumption. On the other hand, if the ReRAM switching region is increased to reduce the forming voltage, there is an area penalty. The present application solves the above problems by providing a 1T1R device, where the ReRAM (which serves as the storage element in the 1T1R structure) is present on the front side or the back side of the device, and where the source contact and the drain contact are located on opposite sides of the device. It is noted that in the present application, a front side contact is present on the front side of the device, which is electrically connected to the source region of the transistor, and a back side contact structure is present on the back side of the device, which is electrically connected to the drain region of the transistor. Here, the front side of the device is the region that includes the transistor and is located above the transistor, while the back side of the device is the region that is located below the transistor. In this way, the ReRAM switching region is not limited by the drain contact (as is the case in conventional 1T1R devices). In the present application, the ReRAM size can be greater than 1 gate pitch. This aspect of the present application can reduce the forming voltage without increasing the 1T1R device size.

[0035] In the present application, as Figures 1A - 10BAs shown, there are generally a memory device region 100 and a logic device region 102. The logic device region 102 is located adjacent to the memory device region 100. In the present application, the transistors present in the memory device region 100 and the logic device region 102 are located on the same semiconductor substrate 10. The memory device region 100 includes a 1T1R device, which includes a ReRAM and a transistor T1. The ReRAM can be located on the front side or the back side of the semiconductor substrate 10. The logic device region 102 also includes a transistor T2. In the memory device region 100 and the logic device region 102, a front-side contact is formed with the source region of the transistor present in each respective device region, and a back-side contact is formed with the drain region of the transistor in each respective device region. This provides low-voltage switching of the ReRAM in the memory device region 100 without having to increase the size of the ReRAM.

[0036] In the present application, the term "transistor" refers to a three-terminal device including a gate electrode, a source region, and a drain region; the gate electrode is a component of the gate structure. In the present application, the transistors in the memory device region 100 and the logic device region are both shown as nanosheet transistors. The term "nanosheet transistor" refers to a transistor in which the channel of the transistor is a plurality of vertically stacked and spaced semiconductor channel material nanosheets. In a nanosheet transistor, the gate structure wraps each of the plurality of vertically stacked and spaced semiconductor channel material nanosheets. The nanosheet transistor is advantageous for the present application because such a transistor generally includes a bottom dielectric isolation layer, which will allow back-side processing without negatively affecting the channel of the transistor. In some embodiments, a transistor formed on a semiconductor-on-insulator substrate can be used instead of the nanosheet transistor because the semiconductor-on-insulator substrate includes a buried insulating layer.

[0037] Now refer to Figure 1A, shows an exemplary structure present in the memory device region 100 of the semiconductor substrate 10, the exemplary structure including a transistor T1, ReRAM 34 / 35 / 36, a front-side contact structure 32, a front-side BEOL structure 44, and a carrier wafer 46, all of which are present on the front side of the semiconductor substrate 10. The transistor T1 present in the memory device region 100 includes a plurality of vertically stacked and spaced semiconductor channel material nanosheets 16, a gate structure 22 wrapped around the middle portion of each semiconductor channel material nanosheet 16, a source region 26 located on one side of the gate structure 22, and a drain region 27 located on the opposite side of the gate structure 22. The exemplary structure also shows dummy gates on the left and right sides of the transistor T1. Each dummy gate region further includes at least a gate structure 22 wrapped around the end portion of each semiconductor channel material nanosheet 16; the dummy transistor lacks at least one of the source region or the drain region. Also present in the memory device region 100 are: a shallow trench isolation structure 12, an inner spacer 18, a gate spacer 20, a gate capping layer 24, a front-side source / drain contact structure 28, a first front-side interlayer dielectric material layer 30, a dielectric material layer 38, a second front-side interlayer dielectric material layer 40, and a front-side BEOL to RERAM metal via 42. In the present application, the shallow trench isolation structure 12 is formed in the semiconductor substrate 10 and it can surround the unetched portion of the semiconductor substrate 10. The structure further includes a bottom dielectric isolation layer 14 present between the transistor T1 and the semiconductor substrate 10.

[0038] As Figure 1A illustrated, the ReRAM 34 / 35 / 36 is a front-side ReRAM located above the transistor T1 present in the memory device region 100. As Figure 1A further shown, the front-side contact structure 32 electrically connects the ReRAM 34 / 35 / 36 to the source region 26 of the transistor T1; one of the front-side source / drain contact structures 28 is positioned between the front-side contact structure 32 and the source region 26 of the transistor T1 in the memory device region 100. In the present application, the front-side contact structure 32 has a first surface that physically contacts the front-side source / drain contact structure 28 and a second surface opposite the first surface that physically contacts the first electrode 34 of the ReRAM 34 / 35 / 36. The front-side BEOL to RERAM metal via 42 electrically connects the second electrode 36 of the ReRAM 34 / 35 / 36 to the front-side BEOL structure 44, and the carrier wafer 46 is located on the front-side BEOL structure 44. The dielectric material layer 38 is present along the top surface and the sidewall surface of the ReRAM 34 / 35 / 36; the dielectric material layer is also present between the first front-side interlayer dielectric material layer 30 and the second front-side interlayer dielectric material layer 40. In this embodiment of the present application, as Figure 1AAs shown, the first front-side interlayer dielectric material layer 30 is embedded in the transistor T1 and the dummy transistor, the front-side source / drain contact structure 28, the front-side contact structure 32, the bottom dielectric isolation layer 14, and the second front-side interlayer dielectric material layer 40 is at least embedded in the ReRAM 34 / 35 / 36 and the front-side BEOL to ReRAM metal vias 42.

[0039] Now referring to Figure 1B , an exemplary structure existing in the logic device region 102 of the semiconductor substrate 10 is shown. Note that the logic device region 102 and the memory device region 100 exist on the same substrate, i.e., the semiconductor substrate 10. The logic device region 102 is located Figure 1A near the memory device region 100 shown in, and the exemplary structure in the logic device region 102 includes a transistor T2, a front-side contact structure 32, a front-side BEOL structure 44, and a carrier wafer 46, all of which exist on the front side of the semiconductor substrate 10. The transistor T2 existing in the logic device region 102 includes a plurality of vertically stacked and spaced semiconductor channel material nanosheets 16, a gate structure 22 wrapped around the middle portion of each semiconductor channel material nanosheet 16, a source region 26 located on one side of the gate structure 22, and a drain region 27 located on the opposite side of the gate structure 22. The exemplary structure also shows dummy gate regions on the left and right sides of the transistor T2. Each dummy gate region also at least includes a gate structure 22 wrapped around the end portion of each semiconductor channel material nanosheet 16; the dummy transistor lacks at least one of the source region or the drain region. Also existing in the logic device region 102 are: a shallow trench isolation structure 12, an inner spacer 18, a gate spacer 20, a gate capping layer 24, a front-side source / drain contact structure 28, a first front-side interlayer dielectric material layer 30, a dielectric material layer 38, a second front-side interlayer dielectric material layer 40, and a front-side metal via 43. Figure 1B The structure shown also includes a bottom dielectric isolation layer 14 existing between the transistor T2 and the semiconductor substrate 10.

[0040] As Figure 1B shown, the front-side contact structure 32 electrically connects the front-side BEOL structure 44 to the source region 26 of the transistor T2; one of the front-side source / drain contact structures 28 is positioned between the front-side contact structure 32 and the source region 26 of the transistor T2 in the logic device region 102. In the present application, the front-side contact structure 32 has a first surface physically contacting the front-side source / drain contact structure 28 and a second surface opposite to the first surface, and the second surface physically contacts the metal via 43 positioned between the front-side BEOL structure 44 and the front-side contact structure 32. In the logic device region 102, the dielectric material layer 38 exists between the first front-side interlayer dielectric material layer 30 and the second front-side interlayer dielectric material layer 40. In this embodiment of the present application, as Figure 1BAs shown, the first front-side interlayer dielectric material layer 30 is embedded in the transistor T2 and the dummy transistor, the front-side source / drain contact structure 28, the front-side contact structure 32, and the bottom dielectric isolation layer 14, and the second front-side interlayer dielectric material layer 40 is embedded in at least the metal vias 43.

[0041] The semiconductor substrate 10 present in both the memory device region 100 and the logic device region 102 is composed of at least one semiconductor material having semiconductor characteristics. Examples of semiconductor materials that can be used to provide the semiconductor substrate 12 include, but are not limited to, silicon (Si), silicon-germanium (SiGe) alloy, silicon-germanium-carbon (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors.

[0042] The shallow trench isolation structure 12 present in both the memory device region 100 and the logic device region 102 may include a trench dielectric material and an optional trench liner layer. When present, the trench liner layer is formed along the sidewalls and the bottom wall of the trench dielectric material. The trench dielectric material can be composed of any trench dielectric such as, for example, silicon oxide, and the trench liner layer can be composed of any trench liner material such as, for example, silicon nitride.

[0043] The bottom dielectric isolation layer 14 present in both the memory device region 100 and the logic device region 102 is composed of a spacer dielectric material that includes (but is not limited to) SiN, SiBCN, SiOCN, SiON, or SiOC. Typically, but not always necessarily, the spacer dielectric material providing the bottom dielectric isolation layer 14 is the same in composition as the spacer dielectric material providing the gate spacer 20.

[0044] Each semiconductor channel material nanosheet 16 is composed of one of the semiconductor materials of the above-mentioned semiconductor substrate 10. In one example, each semiconductor channel material nanosheet 16 is composed of Si or SiGe. In some embodiments, each semiconductor channel material nanosheet 16 can be composed of a semiconductor material capable of providing high channel mobility for nFET devices. In other embodiments, each semiconductor channel material nanosheet 16 can be composed of a semiconductor material capable of providing high channel mobility for pFET devices. Each semiconductor channel material nanosheet 16 generally has a width of 6 nm to 100 nm and a vertical height of 4 nm to 15 nm.

[0045] Each inner spacer 18 is located below each semiconductor channel material nanosheet 16. Each inner spacer 18 is composed of a spacer dielectric material including, but not limited to, SiN, SiBCN, SiOCN, SiON, or SiOC.

[0046] Each gate spacer 20 present along the sidewalls of the gate structure 22 may also be composed of a spacer dielectric material. The spacer dielectric material providing the gate spacer 20 may be the same as or different from the dielectric spacer material providing the internal spacer 18 in composition.

[0047] The gate structure 22 includes a gate dielectric material and a gate electrode, neither of which is shown separately but is intended to be within the region defined by the gate structure 22. As is known to those skilled in the art, the gate dielectric material directly contacts the physically exposed surface of each semiconductor channel material structure, and the gate electrode is formed on the gate dielectric material. The gate dielectric material of the gate structure 22 has a dielectric constant of 4.0 or greater. Unless otherwise specified, all dielectric constants mentioned herein are measured in a vacuum. Illustrative examples of the gate dielectric material include, but are not limited to, silicon dioxide, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminate (LaAlO3), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanate (BaO6SrTi2), barium titanate (BaTiO3), strontium titanate (SrTiO3), ytterbium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalate (Pb(Sc,Ta)O3), and / or lead zinc niobate (Pb(Zn,Nb)O). The gate dielectric material may also include dopants such as La, Al, and / or Mg.

[0048] The gate electrode of the gate structure 22 may include a work function metal (WFM) and an optional conductive metal. The WFM can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to achieve an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" means a shift in the effective work function of the work function metal-containing material towards the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicide, or combinations thereof. In other embodiments, the WFM can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that will turn on a semiconductor device (e.g., a transistor) by causing the channel of the device to conduct. As used herein, the term "p-type threshold voltage shift" means a shift in the effective work function of the WFM-containing material towards the valence band of silicon in the silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The optional conductive metal may include, but is not limited to, Al, W, or Co.

[0049] Each gate capping layer 24 present in the memory device region 100 and the logic device region 102 may be composed of a dielectric hard mask material such as, for example, silicon nitride and / or silicon oxynitride. The gate capping layer 24 is present on the topmost surface of the gate structure 22 and is laterally surrounded by the upper portion of the gate spacer 20; the lower portion of the gate spacer 20 laterally surrounds the gate structure 20. At this point in the present application, the topmost surface of the gate capping layer 24 is coplanar with the topmost surface of the gate spacer 20.

[0050] The source regions 26 and the drain regions 27 present in the memory device region 100 and the logic device region 102 include a semiconductor material and a dopant. The dopant can be an n-type dopant or a p-type dopant, both of which are defined below. The semiconductor material providing the source regions 26 and the drain regions 27 includes one of the semiconductor materials providing the semiconductor substrate 10 described above. The semiconductor material providing the source regions 26 and the drain regions 27 may be the same as or different in composition from the semiconductor material providing each semiconductor channel material nanosheet 16. The term "n-type" refers to the addition of an impurity that contributes free electrons to an intrinsic semiconductor. In a silicon-containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor, which creates a deficiency of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of the n-type or p-type dopant in the source regions 26 and the drain regions 27 can be between 1×10 18atoms / cm 3 to 1×10 21 atoms / cm 3 However, dopant concentrations greater than 1×10 21 atoms / cm 3 or less than 1×10 18 atoms / cm 3 are also conceivable.

[0051] The first interlayer dielectric layer 30 present in the memory device region 100 and the logic device region 102 may be composed of a dielectric material, which includes, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" used throughout this application refers to a dielectric material having a dielectric constant less than 4.0. The first interlayer dielectric layer 30 generally includes a plurality of the above dielectric materials.

[0052] Each front-side source / drain contact structure 28 present in the memory device region 100 and the logic device region 102 is located on the surface of the source region 26 and on the surface of the drain region 27. Each front-side source / drain contact structure 28 is at least composed of a contact conductor material. The contact conductor material may include, for example, a silicide liner layer, such as Ni, Pt, NiPt, an adhesion metal liner layer, such as TiN, and a conductive metal, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. Each front-side source / drain contact structure 28 may also include one or more contact liner layers (not shown). In one or more embodiments, the contact liner layer (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, their alloys, or their stacks, such as Ti / TiN and Ti / WC. In one or more embodiments where a contact layer is present, the contact liner layer (not shown) may include a silicide liner layer, such as Ti, Ni, NiPt, etc., and a diffusion barrier material as defined above.

[0053] The front-side contact structure 32 present in the memory device region 100 and the logic device region 102 is at least composed of a contact conductor material, as described above for the front-side source / drain contact structure 28. The front-side contact structure 32 may also include a diffusion barrier material present along the sidewalls and bottom wall of the front-side contact structure 32 as defined above. In the memory device region 100, the front-side contact structure 32 and the front-side source / drain contact structure 28 electrically connect the front-side ReRAM 34 / 35 / 36 to the source region 26 of the transistor T1.

[0054] The front-side ReRAM 34 / 35 / 36 includes a first electrode 34, a filament-formation layer 35 (which may also be referred to herein as a dielectric switching layer), and a second electrode 36. The first electrode 34 may be composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Cu, Co, CoWP, CoN, W, WN, or any combination thereof. The first electrode 34 may have a thickness ranging from 2 nm to 80 nm; other thicknesses are possible and may be used in the present application as the thickness of the first electrode 34. The filament-formation layer 35 is composed of a dielectric material such as a dielectric metal oxide having a dielectric constant of 4.0 or greater. At this point in the present application and during operation, the filament-formation layer 35 is electrically insulating, and conductive filaments may be formed in the filament-formation layer 35. Examples of dielectric metal oxides that may be used as the filament-formation layer 35 include, but are not limited to, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, or combinations thereof. In some embodiments, hydrogen may be present in the dielectric material providing the filament-formation layer 35. The filament-formation layer 35 may have a thickness of 1 nm to 50 nm; however, other thicknesses may also be considered as the thickness of the filament-formation layer 35. The second electrode 36 may include one of the conductive materials described above for the first electrode 34. In some embodiments, the conductive material providing the second electrode 36 is the same in composition as the conductive material providing the first electrode 34. In one example, the conductive materials providing the first electrode 34 and the second electrode 36 are composed of TiN. In other embodiments, the conductive material providing the second electrode 36 is different in composition from the conductive material providing the first electrode 34. In one example, the conductive material providing the first electrode 34 is composed of TaN, and the conductive material providing the second electrode 36 is composed of TiN. The ReRAM lateral width may be greater than 1 gate pitch.

[0055] The dielectric material layer 38 located on the uppermost surface and sidewalls of the ReRAM 34 / 35 / 36 and on the first front-side interlayer dielectric material layer 30 may be composed of a dielectric hard mask material such as, for example, silicon nitride and / or silicon oxynitride. The dielectric material layer 38 present in the memory device region may be referred to as a dielectric encapsulation material layer. The dielectric material layer 38 may have a thickness ranging from 5 nm to 50 nm; although other thicknesses are possible and may be used in the present application as the thickness of the dielectric material layer 38. The dielectric material layer 38 may be a conformal dielectric material layer. "Conformal" means that the material layer has a vertical thickness along a horizontal surface that is substantially the same as the lateral thickness along a vertical surface (i.e., within ±10%).

[0056] The second front-side interlayer dielectric material layer 40 is composed of the dielectric material used for the first front-side interlayer dielectric material layer 30 as described above. The dielectric material provided for the second front-side interlayer dielectric material layer 40 may be the same as or different from the dielectric material provided for the first front-side interlayer dielectric material layer 30 in composition.

[0057] The front-side BEOL to RERAM metal vias 42 present in the memory device region 100 are composed of at least a contact conductor material, as mentioned above for the front-side source / drain contact structure 28. The front-side BEOL to RERAM metal vias 42 may also include a diffusion barrier material present along the sidewalls and bottom wall of the front-side BEOL to RERAM metal vias 42 as defined above. In the memory device region 100, the front-side BEOL to ReRAM metal vias 42 electrically connect the second (i.e., top) electrode 36 of the front-side ReRAM 34 / 35 / 36 to the front-side BEOL structure 44. As shown, the front-side BEOL to ReRAM metal vias 42 pass through the dielectric material layer 38 present on the uppermost surface of the ReRAM 34 / 35 / 36.

[0058] In the logic device region 102, there are front-side metal vias 43 that electrically connect the front-side BEOL structure 44 to the front-side contact structure 32. The front-side metal vias 43 are composed of at least a contact conductor material, as described above for the front-side source / drain contact structure 28. The front-side metal vias 43 may also include a diffusion barrier material present along the sidewalls and bottom wall of the front-side metal vias 43 as defined above.

[0059] The front-side BEOL structure 44 present in the memory device region 100 and the logic device region 102 may include one or more interconnect dielectric material layers (including one of the dielectric materials mentioned above for the first front-side interlayer dielectric material layer 30), which contain one or more wiring regions (the wiring regions may include any conductive metal (e.g., Cu) or metal alloy (e.g., Cu - Al) embedded therein).

[0060] Figures 1A - 1BThe exemplary structures shown can be formed using a combination of front-end-of-line (FEOL) processing, middle-of-line (MOL) processing, and front-side BEOL processing, each of these processing steps being well known to those skilled in the art. FEOL processing can include conventional nanosheet device formation processes well known to those skilled in the art. MOL processing and BEOL processing can include metallization processes, which are also well known to those skilled in the art. Metallization can include forming openings in at least one material layer and then filling the openings with at least one conductive material. Filling can include depositing the conductive material followed by a planarization process such as, for example, chemical mechanical polishing (CMP). BEOL processing also includes ReRAM device processing steps, which are also well known to those skilled in the art. To avoid obscuring the methods of the present application, details of FEOL processing, MOL processing, and BEOL processing are not provided herein.

[0061] Now referring to Figures 2A - 2B , respectively, shown are the Figures 1A - 1B exemplary structures shown in after removing the semiconductor substrate 10 to allow backside processing in the memory device region 100 and the logic device region 102. Before removing the semiconductor substrate 10, the wafer is typically flipped 180° to physically expose the backside of the semiconductor substrate 10; for simplicity, the flipping of the wafer is not shown in the drawings. The backside processing occurs on the side of the wafer opposite the transistors. The flipping of the structure can be performed by hand or by using a mechanical device such as, for example, a robotic arm. The removal of the semiconductor substrate 10 can be performed using a material removal process (e.g., chemical wet etching) that is selective in removing the semiconductor material providing the semiconductor substrate 10. The material removal process can include a single step or can use multiple steps depending on the composition of the semiconductor substrate 10. Note that the material removal process for removing the semiconductor substrate 10 in the memory device region 100 and the logic device region 102 forms gaps 48 that physically expose the bottom dielectric isolation layer 14 between the shallow trench isolation structures 12.

[0062] Now referring to Figures 3A - 3B , respectively, shown are the Figures 2A - 2BThe exemplary structure shown in the figure. The backside interlayer dielectric material layer 50 is formed in each gap 48 formed by removing the semiconductor substrate 10 from the structure. The backside interlayer dielectric material layer 50 has a surface that directly contacts the bottom dielectric isolation layer 14 and another surface opposite to the surface that contacts the bottom dielectric isolation layer 14, and this another surface is coplanar with the physically exposed horizontal surface of the shallow trench isolation structure 12. The backside interlayer dielectric material layer 50 includes the dielectric material for the first frontside interlayer dielectric material layer 30 as described above. The backside interlayer dielectric material layer 50 can be formed by deposition followed by planarization. The deposition of the backside interlayer dielectric material layer 50 can include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or spin coating. Planarization can include CMP and / or polishing.

[0063] Now referring to Figures 4A - 4B , respectively, showing the Figures 3A - 3B exemplary structure shown in the figure after forming the backside contact structures 52 in the memory device region 100 and the logic device region 102. Each backside contact structure 52 makes direct physical contact with the drain region 27 of the corresponding transistor (i.e., T1 or T2) present in a specific device region. Each backside contact structure 52 passes through the backside interlayer dielectric material layer 50 and the bottom dielectric isolation layer 14. Each backside contact structure 52 is at least composed of a contact conductor material, as described above for the frontside source / drain contact structure 28. Each backside contact structure 52 may also include a diffusion barrier material present along the sidewalls and bottom wall of each backside contact structure 52 as defined above. Each backside contact structure 52 can be formed by the metallization process defined above.

[0064] Now referring to Figures 5A - 5B , respectively, showing the Figures 4A - 4B exemplary structure shown in the figure after forming the backside BEOL structure 54 in each of the memory device region 100 and the logic device region 102. The backside BEOL structure 54 includes the materials for the frontside BEOL structure 44 as described above. The backside BEOL structure 54 can be formed using any interconnect device process, including, for example, the damascene process. As shown, the backside contact structure 52 in the memory device region 100 electrically connects the drain region 27 of the transistor T1 to the backside BEOL structure 54, and the backside contact structure 5 in the logic device region 102 electrically connects the drain region 27 of the transistor T2 to the backside BEOL structure 54.

[0065] It is worth noting that Figure 5AA semiconductor structure according to an embodiment of the present application is shown, which includes a transistor T1 located in a memory device region 100. The transistor T1 includes a gate structure 22, a source region 26 located on a first side of the gate structure 22, and a drain region 27 located on a second side of the gate structure 22, wherein the second side of the gate structure 22 is opposite to the first side of the gate structure 22. The structure further includes a front-side ReRAM 34 / 35 / 36 located in the memory device region 100 and positioned above the transistor T1. There is also a front-side contact structure 32 that electrically connects the front-side ReRAM 34 / 35 / 36 to the source region 26 of the transistor T1. There is also a back-side contact structure 52 that electrically connects the drain region 27 of the transistor T1 to a back-side BEOL structure 54. In Figure 5A the structure shown, without increasing the gate pitch, the switching area of the front-side ReRAM 34 / 35 / 36 is effectively increased. As in an embedded memory application, there are wiring benefits for the structures present in the logic device region 102 (see Figure 5B ).

[0066] Now referring to Figure 6A , another example structure present in the memory device region 100 of a semiconductor substrate 10 is shown. The example structure includes a transistor T1, a front-side contact structure 32, a front-side BEOL structure 44, and a carrier wafer 46 as defined above, all of which are present on the front side of the semiconductor substrate 10 and all are composed of the materials for the example structure shown in Figures 1A - 1B . Figure 6A The transistor T1 shown in Figures 1A - 1B is a nanosheet transistor, which includes a bottom dielectric isolation layer 14, semiconductor channel material nanosheets 16, inner spacers 18, gate spacers 20, a gate structure 22, a gate capping layer 24, a source region 26, and a drain region 27, all of which have been defined above in connection with the example structure shown in Figure 6A . Figures 1A - 1B The exemplary structure shown in Figure 6A also includes a source / drain contact structure 28, a first front-side interlayer dielectric material layer 30, and a second front-side interlayer dielectric material layer 40, each of which has been described above with respect to the structure shown in Figure 1BThe materials mentioned for the front-side metal vias 43 in the exemplary structures shown.

[0067] Now refer to Figure 6B , another exemplary structure present in the logic device region 102 of the semiconductor substrate 100 is shown, and the logic device region 102 is located adjacent to Figure 6A the memory device region 100 shown in Figure 6B The another exemplary structure shown includes elements as shown above Figure 1B shown. Note that there is no dielectric material layer 38 separating the first front-side interlayer dielectric material layer 30 from the second front-side interlayer dielectric material layer 40 on the front side of the logic device region 102.

[0068] Figures 6A through 6B The exemplary structure shown can be formed using a combination of FEOL processing, MOL processing, and front-side BEOL processing, and each of these processing steps is well known to those skilled in the art. FEOL processing can include conventional nanosheet device processes well known to those skilled in the art. MOL processing and BEOL processing can include metallization processes (as defined above), which are also well known to those skilled in the art. To avoid obscuring the methods of the present application, details of FEOL processing, MOL processing, and BEOL processing are not provided herein.

[0069] Now refer to Figures 7A - 7B , the exemplary structures shown in Figures 6A - 6B after removing the semiconductor substrate 10 to allow back-side processing in both the memory device region 100 and the logic device region 102 are shown respectively. Before removing the semiconductor substrate 10, the wafer is typically flipped 180° to physically expose the back side of the semiconductor substrate 10; for simplicity, the flipping of the wafer is not shown in the drawings. The back-side processing occurs on the side of the wafer opposite to the transistors. The flipping of the structure can be performed by hand or by using a mechanical device (such as a robotic arm for example). The removal of the semiconductor substrate 10 can be performed using a material removal process (e.g., chemical wet etching), which is selective in removing the semiconductor material providing the semiconductor substrate 10. The material removal process can include a single step or multiple steps depending on the composition of the semiconductor substrate 10. Note that the material removal process for removing the semiconductor substrate 10 in the memory device region 100 and the logic device region 102 forms a gap 48 that physically exposes the bottom dielectric isolation layer 14 between the shallow trench isolation structures 12.

[0070] Now refer to Figures 8A - 8B , the exemplary structures shown in Figures 7A - 7BThe exemplary structure shown in []. The backside interlayer dielectric material layer 50 is formed in each gap 48 formed by removing the semiconductor substrate 10 from the structure. The backside interlayer dielectric material layer 50 has a surface in direct contact with the bottom dielectric isolation layer 14 and another surface opposite to the surface in contact with the bottom dielectric isolation layer 14, and this another surface is coplanar with the physically exposed horizontal surface of the shallow trench isolation structure 12. The backside interlayer dielectric material layer 50 includes the dielectric material for the first frontside interlayer dielectric material layer 30 as described above. The backside interlayer dielectric material layer 50 can be formed by deposition followed by planarization, as defined above for providing Figures 3A through 3B the backside interlayer dielectric material layer 50 shown in [].

[0071] Now referring to Figures 9A - 9B , respectively, show the Figures 8A - 8B exemplary structure shown in [] after forming the backside contact structures 52 in the memory device region 100 and the logic device region 102. Each backside contact structure 52 is in direct physical contact with the drain region of the corresponding transistor (i.e., T1 or T2) present in a particular device region. Each backside contact structure 52 passes through the backside interlayer dielectric material layer 50 and the bottom dielectric isolation layer 14. Each backside contact structure 52 is at least composed of a contact conductor material, as described above for the frontside source / drain contact structure 28. Each backside contact structure 52 may also include a diffusion barrier material present along the sidewalls and bottom wall of each backside contact structure 52 as defined above. Each backside contact structure 52 can be formed by the metallization process defined above.

[0072] Now referring to Figures 10A - 10B , respectively, show the Figures 9A - 9B exemplary structure shown in [] after further backside processing, which further backside processing includes forming ReRAM 56 / 57 / 58 in the memory device region 100 and forming the backside BEOL structure 54. ReRAM 56 / 57 / 58 is a backside ReRAM, which includes a first electrode 56, a filament formation layer 57, and a second electrode 58. The first electrode 56 includes the conductive material for the first electrode 34 of the frontside ReRAM as described above, the filament formation layer 57 includes the dielectric material for the filament formation layer 35 of the frontside ReRAM as described above, and the second electrode 58 includes the conductive material for the second electrode 36 of the frontside ReRAM as described above. The backside ReRAM 56 / 57 / 58 can be formed by depositing various material layers and then lithographically patterning these various deposited material layers; these processing steps can be used to form Figure 1A the frontside ReRAM illustrated in []. As Figure 10AAs shown, the backside ReRAMs 56 / 57 / 58 have a surface in direct physical contact with the backside contact structure 52, which is formed to contact the drain region 27 of the transistor T1 present in the memory device region 100.

[0073] After the backside ReRAMs 56 / 57 / 58 are formed, a dielectric material layer 59 is formed. The dielectric material layer 59 includes the dielectric material for the dielectric material layer 38 as described above. The dielectric material layer 59 encapsulates the backside ReRAMs 56 / 57 / 58; that is, it is present on the physically exposed surface of the backside ReRAMs 56 / 57 / 58.

[0074] Then, a second backside dielectric material layer 60 is formed on the dielectric material layer 59. The second backside dielectric material layer 60 embeds the backside ReRAMs 56 / 57 / 58. The second backside dielectric material layer 60 includes the dielectric material for the first frontside interlayer dielectric material layer 30 as described above, and the second backside dielectric material layer 60 can be formed by a deposition process, such as CVD, PECVD, or spin coating.

[0075] Then, a backside BEOL-to-ReRAM metal via 62 is formed in the memory device region 100, and a backside metal via 63 is formed in the logic device region 102. The backside BEOL-to-ReRAM metal via 62 and the backside metal via 63 are at least composed of a contact conductor material, as described above for the frontside source / drain contact structure 28. These via structures can also include the diffusion barrier material present along the sidewalls and bottom walls of each via structure as defined above. The backside BEOL-to-ReRAM metal via 62 and the backside metal via 63 can be formed by a metallization process, as described above. As shown, the backside BEOL-to-ReRAM metal via 62 passes through the dielectric material layer 59 and contacts the second electrode 58 of the backside ReRAMs 56 / 57 / 58.

[0076] The backside BEOL structure 54 includes the materials for the frontside BEOL structure 44 as described above. The backside BEOL structure 54 can be formed using any interconnect device process, including, for example, a damascene process. As shown, the backside contact structure 52 in the memory device region 100 electrically connects the drain region 27 of the transistor T1 to the backside ReRAMs 56 / 57 / 58, and the backside BEOL-to-ReRAM metal via 62 electrically connects the backside ReRAMs 56 / 57 / 58 to the backside BEOL structure 54, and the backside contact structure 52 and the backside metal via 63 in the logic device region 102 electrically connect the drain region 27 of the transistor T2 to the backside BEOL structure 54.

[0077] It is worth noting that Figure 10AA semiconductor structure according to another embodiment is shown, which includes a transistor T1 located in a memory device region 100. The transistor T1 includes a gate structure 22, a source region 26 located on a first side of the gate structure 22, and a drain region 27 located on a second side of the gate structure 22, wherein the second side of the gate structure 22 is opposite to the first side of the gate structure 22. The structure of this embodiment also includes a ReRAM 56 / 57 / 58 located in the memory device region 100 and positioned below the transistor T1. The structure even includes a front side contact structure 32 that electrically connects the source region 26 of the transistor T1 to the front side BEOL structure 44, and a back side contact structure 52 that electrically connects the drain region 27 of the transistor T1 to the ReRAM 56 / 57 / 58. The back side ReRAM 56 / 57 / 58 is electrically connected to the back side BEOL structure 54 through a back side BEOL to ReRAM metal via 62. Figure 10A In the structure shown, the backside ReRAM 56 / 57 / 58 switching area is effectively increased without increasing the gate pitch. In other words, the ReRAM lateral width can be greater than 1 gate pitch. For example, in embedded memory applications, for structures present in the logic device area 102 (see Figure 10B ) There is a wiring benefit. In this embodiment of the present application, there is no need for Figure 5A The gate contact (not shown) is moved as in the embodiment shown.

[0078] Although the present application has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the scope of the present application. Therefore, the present application should not be limited to the exact forms and details described and shown, but should fall within the scope of the appended claims.

Claims

1. A semiconductor structure, comprising: A transistor, located in a memory device region, and comprising a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, wherein the second side of the gate structure is opposite to the first side of the gate structure; A resistive random access memory (ReRAM), located in the memory device region and positioned above the transistor; A front-side contact structure, electrically connecting the ReRAM to the source region of the transistor; And A back-side contact structure, electrically connecting the drain region of the transistor to a back-end-of-line (BEOL) structure.

2. The semiconductor structure according to claim 1, wherein the transistor is a nanosheet transistor comprising a plurality of vertically stacked and spaced semiconductor channel material nanosheets, and wherein the gate structure of the transistor wraps an intermediate portion of each of the plurality of vertically stacked and spaced semiconductor channel material nanosheets.

3. The semiconductor structure according to claim 2, further comprising a bottom dielectric isolation layer and a back-side interlayer dielectric material layer located below the nanosheet transistor, wherein the back-side contact structure passes through both the back-side interlayer dielectric material layer and the bottom dielectric isolation layer and makes direct physical contact with the drain region of the transistor.

4. The semiconductor structure according to claim 1, further comprising a source contact structure / drain contact structure positioned between the front-side contact structure and the source region of the transistor, wherein the front-side contact structure makes direct physical contact with a first surface of the source contact structure / drain contact structure, and a second surface of the source contact structure / drain contact structure, opposite to the first surface, makes direct physical contact with the source region of the transistor.

5. The semiconductor structure according to claim 1, further comprising a front-side BEOL structure located above the ReRAM, wherein the front-side BEOL structure is electrically connected to a top electrode of the ReRAM through a front-side BEOL-to-ReRAM metal via.

6. The semiconductor structure according to claim 5, wherein the front-side BEOL-to-ReRAM metal via passes through a dielectric material layer present on the ReRAM.

7. The semiconductor structure according to claim 5, further comprising a carrier wafer located on a surface of the front-side BEOL structure.

8. The semiconductor structure according to claim 1, wherein the ReRAM is embedded in a front-side interlayer dielectric material layer.

9. The semiconductor structure according to claim 1, further comprising a logic device region adjacent to the memory device region, wherein the logic device region comprises another transistor, the another transistor comprising another gate structure, another source region located on a first side of the another gate structure, and another drain region located on a second side of the another gate structure, wherein the second side of the another gate structure is opposite to the first side of the another gate structure.

10. The semiconductor structure according to claim 9 further includes another front-side contact structure that electrically connects the other source region of the other transistor to the front-side BEOL structure, and another back-side contact structure that electrically connects the other drain region of the other transistor to the back-side BEOL structure.

11. A semiconductor structure includes: a transistor located in a memory device region and including a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, wherein the second side of the gate structure is opposite to the first side of the gate structure; a resistive random access memory (ReRAM) located in the memory device region and positioned below the transistor; a front-side contact structure that electrically connects the source region of the transistor to a front-side back-end-of-line (BEOL) structure; and a back-side contact structure that electrically connects the drain region of the transistor to the ReRAM.

12. The semiconductor structure according to claim 11, wherein the transistor is a nanosheet transistor including a plurality of vertically stacked and spaced semiconductor channel material nanosheets, and wherein the gate structure of the transistor wraps an intermediate portion of each of the plurality of vertically stacked and spaced semiconductor channel material nanosheets.

13. The semiconductor structure according to claim 12 further includes a bottom dielectric isolation layer and a back-side interlayer dielectric material layer located below the nanosheet transistor, wherein the back-side contact structure passes through both the back-side interlayer dielectric material layer and the bottom dielectric isolation layer and makes direct physical contact with the drain region of the transistor.

14. The semiconductor structure according to claim 11 further includes a source contact structure / drain contact structure positioned between the front-side contact structure and the source region of the transistor, wherein the front-side contact structure makes direct physical contact with a first surface of the source contact structure / drain contact structure, and a second surface of the source contact structure / drain contact structure opposite to the first surface makes direct physical contact with the source region of the transistor.

15. The semiconductor structure according to claim 11 further includes a front-side metal via positioned between the front-side contact structure and the front-side BEOL structure, wherein the front-side metal via has a first surface directly contacting the front-side BEOL structure and a second surface opposite to the first surface directly contacting the front-side contact structure.

16. The semiconductor structure according to claim 11 further includes a back-side BEOL structure located below the ReRAM, wherein the back-side BEOL structure is electrically connected to a bottom electrode of the ReRAM through a back-side BEOL-to-ReRAM metal via.

17. The semiconductor structure according to claim 11 further includes a carrier wafer located on a surface of the front-side BEOL structure.

18. The semiconductor structure according to claim 11, wherein the ReRAM is embedded in a back-side interlayer dielectric material layer.

19. The semiconductor structure according to claim 11 further includes a logic device region adjacent to the memory device region, wherein the logic device region includes another transistor, and the another transistor includes another gate structure, another source region located on a first side of the another gate structure, and another drain region located on a second side of the another gate structure, wherein the second side of the another gate structure is opposite to the first side of the another gate structure.

20. The semiconductor structure according to claim 19 further includes another front-side contact structure that electrically connects the another source region of the another transistor to a front-side BEOL structure, and another back-side contact structure that electrically connects the another drain region of the another transistor to a back-side BEOL structure.

Images