True random number generation circuit and chip

Abstract

The invention relates to a true random number generation circuit and a chip, the true random number generation circuit comprises a clock signal generation module and a sampling module, the output end of the clock signal generation module is connected with one input end of the sampling module; the clock signal generation module is used for randomly switching the input current or voltage of the clock signal generation module according to a random signal so as to generate a jitter clock signal, and the sampling module is used for sampling a target clock signal according to the jitter clock signal so as to generate a true random number. The switching action of switching the input current or voltage can introduce jitter, and the input current or voltage is randomly switched through the random signal, so that the input time of the input current or voltage is random, the jitter degree of the generated jitter clock signal can be effectively increased, and the randomness of the generated true random number can be effectively enhanced; and the quality of the true random number can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a true random number generation circuit and chip. Background Art

[0002] With the rapid development of informatization today, information security has received more and more attention from countries and industries. Information security is mostly based on keys and implemented through different encryption and decryption algorithms, and the generation of keys depends on random number generators.

[0003] Random number generation circuits are divided into true random number generation circuits and pseudo-random number generation circuits. Generating random numbers based on oscillation ring jitter is one of the common implementation methods of true random number generation circuits. It uses the tiny jitter of the clock signal as the entropy source. However, due to the small jitter of the clock signal, the randomness of the true random number is not strong, and the quality of the true random number is poor. Summary of the Invention

[0004] In order to solve the above technical problems, the purpose of this application is to provide a true random number generation circuit and chip, which can effectively increase the jitter degree of the generated jitter clock signal, thereby effectively enhancing the randomness of the generated true random numbers and effectively improving the quality of the true random numbers.

[0005] The technical solutions provided in this application are as follows: A true random number generation circuit comprises a clock signal generation module and a sampling module, wherein an output terminal of the clock signal generation module is connected to an input terminal of the sampling module; The clock signal generating module is used to randomly switch the input current or voltage of the clock signal generating module according to the random signal, thereby generating a jittered clock signal; The sampling module is used to generate a true random number by sampling a target clock signal according to the jittered clock signal.

[0006] Optionally, the control end of the clock signal generating module is connected to the output end of the sampling module, and the random signal is associated with the true random number.

[0007] Optionally, the clock signal generating module includes a dynamic matching module and an oscillation module; The output end of the dynamic matching module is connected to an input end of the oscillation module, and the output end of the oscillation module is connected to the input end of the sampling module; The dynamic matching module is configured to randomly switch the input current or voltage according to the random signal and output a first jittering voltage; The oscillation module is configured to generate the jittered clock signal according to the first jittered voltage.

[0008] Optionally, the clock signal generating circuit further includes a bias module, and each output terminal of the bias module is connected to the input terminal of the dynamic matching module; The bias module is used to output the input current or voltage.

[0009] Optionally, the oscillation module includes an oscillation unit and a first trigger; An input terminal of the oscillation unit is connected to an output terminal of the dynamic matching module, and an output terminal of the oscillation unit is connected to an input terminal of the first trigger; The oscillation unit is configured to output a dithering signal according to the first dithering voltage; The first trigger is configured to generate the jitter clock signal according to the jitter signal.

[0010] Optionally, the oscillation unit includes a comparator, a control unit and a capacitor; The first end of the capacitor, the first end of the control unit, and the first input end of the comparator are connected, and a common end of the three is connected to the output end of the dynamic matching module, the output end of the comparator is connected to the second end of the control unit, and a common end of the two is connected to the one input end of the first trigger; The control unit is used to control the voltage of the first input terminal of the comparator to fluctuate within a preset voltage value range after the capacitor is discharged.

[0011] Optionally, the control unit includes a first MOS tube; The first MOS transistor is used to control the voltage at the first input terminal of the comparator to fluctuate within the preset voltage value range after the capacitor is discharged; wherein the preset voltage value is greater than 0V.

[0012] Optionally, the sampling module includes a second trigger, and another input terminal of the second trigger is used to input the target clock signal; The second trigger is configured to generate the true random number by sampling the target clock signal according to the jittered clock signal.

[0013] Optionally, the input current or voltage includes multiple values, and each two adjacent switches can obtain input currents or voltages with different values.

[0014] The present application also provides a chip, comprising any of the true random number generation circuits described above.

[0015] Compared with the prior art, the present application provides a true random number generation circuit and chip, wherein the true random number generation circuit includes a clock signal generation module and a sampling module, wherein the output end of the clock signal generation module is connected to an input end of the sampling module, the clock signal generation module is used to randomly switch the input current or voltage of the clock signal generation module according to a random signal, thereby generating a jittered clock signal, and the sampling module is used to sample a target clock signal according to the jittered clock signal to generate a true random number. In the present application, since the switching action of switching the input current or voltage will introduce jitter, and the random signal is used to randomly switch the input current or voltage, so that the input time of the input current or voltage is random, the jitter degree of the generated jittered clock signal can be effectively increased, thereby effectively enhancing the randomness of the generated true random number, and effectively improving the quality of the true random number. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A circuit diagram of a true random number generation circuit provided in an embodiment of the present application; Figure 2 A circuit diagram of another true random number generation circuit provided in an embodiment of the present application; Figure 3 A circuit diagram of another true random number generation circuit provided in an embodiment of the present application; Figure 4 A circuit diagram of a dynamic matching module provided in an embodiment of the present application; Reference numerals: 100 - clock signal generating module; 200 - sampling module; 110-dynamic matching module; 120-oscillation module; 130-bias module; 121-oscillation unit; CMP-comparator; C-capacitor; 1211-control unit; FF1-first trigger; 1212 - first inverting unit; INV1 - first inverter; 1213 - second inverting unit; INV2 - second inverter; INV3 - third inverter; 1214 - third inverting unit; INV4 - fourth inverter; INV5 - fifth inverter; MOS1-first MOS tube; FF2-second trigger; 131-bias unit; MOS2-second MOS tube; FF3-third trigger; MOS3-third MOS tube; 111-NOR gate. DETAILED DESCRIPTION

[0018] In order to help those skilled in the art better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0019] It should be noted that when an element is referred to as being “fixed on” or “set on” another element, it can be directly on the other element or indirectly set on the other element; when an element is referred to as being “connected to” another element, it can be directly connected to the other element or indirectly connected to the other element.

[0020] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" or "several" means two or more, unless otherwise specifically defined.

[0022] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which this application can be implemented. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application.

[0023] like Figure 1As shown, an embodiment of the present application provides a true random number generation circuit, including a clock signal generation module 100 and a sampling module 200, wherein the output end of the clock signal generation module 100 is connected to an input end of the sampling module 200; the clock signal generation module 100 is used to randomly switch the input current or voltage of the clock signal generation module 100 according to the random signal CLK_TRNG, thereby generating a jittered clock signal CLK_L; the sampling module 200 is used to sample the target clock signal CLK_H according to the jittered clock signal CLK_L to generate a true random number.

[0024] In this embodiment, the random signal CLK_TRNG can be a signal associated with a true random number, or it can be an external random signal CLK_TRNG; the other input end of the sampling module 200 is used to receive the target clock signal CLK_H, the jittered clock signal CLK_L can be a low-frequency clock signal or a high-frequency clock signal, preferably the jittered clock signal CLK_L is a low-frequency clock signal, the target clock signal CLK_H can be a low-frequency clock signal or a high-frequency clock signal, preferably the target clock signal CLK_H is a high-frequency clock signal.

[0025] In this embodiment, the clock signal generation module 100 randomly switches the input current or input voltage of the clock signal generation module 100 using the received random signal CLK_TRNG, and generates a jittered clock signal CLK_L, which is output to the sampling module 200. The sampling module 200 samples the received target clock signal CLK_H based on the received jittered clock signal CLK_L to generate a true random number. The random signal CLK_TRNG is used to randomly switch the input current or input voltage of the clock signal generation module 100. Since switching the input current or input voltage introduces jitter, the random signal CLK_TRNG is used to randomly switch the input current or input voltage, making the input timing of the input current or input voltage random. This effectively increases the jitter level of the jittered clock signal CLK_L generated by the random signal CLK_TRNG randomly switching the input current or input voltage of the clock signal generation module 100. This effectively enhances the randomness of the true random number generated by sampling the target clock signal CLK_H using the jittered clock signal CLK_L, thereby effectively improving the quality of the true random number.

[0026] Compared with the prior art, the present application provides a true random number generation circuit and chip. The true random number generation circuit includes a clock signal generation module 100 and a sampling module 200. The output end of the clock signal generation module 100 is connected to an input end of the sampling module 200. The clock signal generation module 100 is used to randomly switch the input current or voltage of the clock signal generation module 100 according to the random signal CLK_TRNG, thereby generating a jittered clock signal CLK_L. The sampling module 200 is used to sample the target clock signal CLK_H according to the jittered clock signal CLK_L to generate a true random number. In the present application, since the switching action of switching the input current or voltage introduces jitter, and the random signal CLK_TRNG is used to randomly switch the input current or voltage, so that the input time of the input current or voltage is random, the jitter degree of the generated jittered clock signal CLK_L can be effectively increased, thereby effectively enhancing the randomness of the generated true random number, and effectively improving the quality of the true random number.

[0027] like Figure 2 As shown, as an implementation manner, in the embodiment of the present application, the control end of the clock signal generating module 100 is connected to the output end of the sampling module 200, and the random signal CLK_TRNG is associated with a true random number.

[0028] In this embodiment, the random signal CLK_TRNG being associated with the true random number may mean that the random signal CLK_TRNG is the true random number, or the random signal CLK_TRNG is generated according to the true random number.

[0029] In this embodiment, the input end of the clock signal generation module 100 receives N groups of input currents or input voltages, where N is a positive integer greater than 1. The clock signal generation module 100 is specifically configured to switch the input current or input voltage based on a random signal CLK_TRNG received by the control end to generate a jittered clock signal CLK_L. By feeding back the random signal CLK_TRNG associated with a true random number to the control end of the clock signal generation module 100, and then switching the input current or input voltage based on the random signal CLK_TRNG received by the control end, the input timing of each group of input currents or input voltages is randomized. This can effectively increase the jitter level of the generated jittered clock signal CLK_L, thereby effectively enhancing the randomness of the generated true random number and improving the quality of the true random number.

[0030] like Figure 2As shown, as an implementation manner, in an embodiment of the present application, the clock signal generation module 100 includes a dynamic matching module 110 and an oscillation module 120; the output end of the dynamic matching module 110 is connected to an input end of the oscillation module 120, and the output end of the oscillation module 120 is connected to an input end of the sampling module 200; the dynamic matching module 110 is used to randomly switch the input current or voltage according to the random signal CLK_TRNG and output a first jitter voltage; the oscillation module 120 is used to generate a jitter clock signal CLK_L according to the first jitter voltage.

[0031] In this embodiment, the input end of the dynamic matching module serves as the input end of the clock signal generation module 100 and receives N groups of input currents or input voltages. The control end of the dynamic matching module 110 serves as the control end of the clock signal generation circuit and is connected to the output end of the sampling module 200. The output end of the oscillation module 120 serves as the output end of the clock signal generation module 100 and is connected to an input end of the sampling module 200.

[0032] In this embodiment, the switching action of switching the input current or input voltage itself increases the jitter of the output first jittered voltage. Furthermore, the switching of the input current or input voltage according to the random signal CLK_TRNG results in random input timing for each set of input currents or input voltages. This causes the value of the output first jittered voltage, which is generated by the random switching of the input current or input voltage according to the random signal CLK_TRNG, to vary randomly. Since the values of each of the N sets of input currents or input voltages can be identical or different, or have some values identical and others different, if the values of each of the N sets of input currents or input voltages are different, or have some values identical and some values different, the jitter of the output first jittered voltage will be further increased, causing the degree of jitter of the first jittered voltage to be correlated with the input current or input voltage. Greater jitter in the first jittered voltage results in greater jitter in the jittered clock signal CLK_L generated based on the first jittered voltage. The jitter degree of the jittered clock signal CLK_L is positively correlated with the jitter degree of the first jittered voltage.

[0033] In this embodiment, the dynamic matching module 110 randomly switches the input current or input voltage according to the random signal CLK_TRNG and outputs the first jittering voltage, thereby effectively increasing the jitter of the first jittering voltage. Furthermore, the dynamic matching module is provided with N input terminals for receiving N groups of currents or voltages. Each of the currents or voltages is input to the corresponding input terminal of the dynamic matching module through a corresponding switch tube. The input terminal of the dynamic matching module is connected to the output terminal of the switch tube in a one-to-one correspondence. The switch tube is turned on or off according to the control signal received by its control terminal to control the switching output of the corresponding current or voltage. The control signal includes a random signal. When the control signal is a random signal, the current or voltage received by the input terminal of the dynamic matching module is random each time, and the time of receiving the current or voltage is random. The control signal includes a cyclic control signal. When the control signal is a cyclic control signal, N groups of currents or voltages are cyclically input to the corresponding input terminals of the dynamic matching module in a preset order, with at least one group of currents or voltages input to the corresponding input terminals of the dynamic matching module each time. In this way, the switch tube is turned on or off according to the control signal to control the switching of the corresponding input current, thereby increasing the jitter level of the first jittering voltage output by the dynamic matching module. Because the oscillation module 120 can enhance signal jitter, the jitter of the jittering clock signal CLK_L generated based on the first jittering voltage can be further increased, thereby further enhancing the randomness of the true random number generated based on the jittering clock signal CLK_L sampling the target clock signal CLK_H, thereby further improving the quality of the true random number.

[0034] like Figure 2 As shown, as an implementation method, in an embodiment of the present application, the clock signal generating circuit further includes a bias module 130, and each output end of the bias module 130 is connected to the input end of the dynamic matching module 110; the bias module 130 is used to output input current or voltage.

[0035] In this embodiment, the input end of the bias module is connected to the power supply VDD, and the bias module is provided with N output ends. The dynamic matching module is provided with N input ends. The output ends of the bias module 130 are connected one-to-one with the input ends of the dynamic matching module 110. The bias module 130 is used to output M groups of input currents or input voltages of different values; wherein M is a natural number not greater than N.

[0036] In this embodiment, the dynamic matching module 110 is specifically used to switch the input current or input voltage connected in sequence according to a preset order when the true random number received by the control end is not less than a preset value, and output a first jittering voltage according to the input current or input voltage, wherein the jitter degree of the first jittering voltage is positively correlated with the number of groups of input currents with different current values or the number of groups of input voltages with different voltage values, the preset value is a preset value, the preset order is a preset order, the more the number of groups of input currents with different current values or input voltages with different voltage values is, the greater the jitter degree of the first jittering voltage is, and each group can be The current values of the group input currents or the voltage values of the input voltages are set to be different to enhance the jitter degree of the first jitter voltage. Since the random signal CLK_TRNG received by the control end is not less than (i.e., greater than or equal to) the preset value at random times, the jitter degree of the first jitter voltage output by the dynamic matching module 110 can be further enhanced. The dynamic matching module can also be used to connect the bias current output by the first bias unit when the random signal received by the control end flips to a valid level for the first time, and switch to the bias current output by the next bias control unit when the random signal flips to a valid level for the second time.

[0037] like Figure 2 As shown, as an implementation method, in an embodiment of the present application, the oscillation module 120 includes an oscillation unit 121 and a first trigger FF1; an input end of the oscillation unit 121 is connected to the output end of the dynamic matching module 110, and the output end of the oscillation unit 121 is connected to an input end of the first trigger FF1; the oscillation unit 121 is used to output a jitter signal according to the first jitter voltage; the first trigger FF1 is used to generate a jitter clock signal CLK_L according to the jitter signal.

[0038] In this embodiment, the first flip-flop FF1 can be a D flip-flop. The output end of the first flip-flop FF1 is connected to an input end of the sampling module 200 as the output end of the clock signal generating circuit, and the inverting output end of the first flip-flop FF1 is connected to an input end. Since the oscillation unit 121 can enhance signal jitter, the jitter of the jitter signal output according to the first jitter voltage can be increased, and the jitter of the jitter clock signal CLK_L generated according to the jitter signal can be increased, thereby further enhancing the randomness of the true random number generated based on the sampling target clock signal CLK_H of the jitter clock signal CLK_L, and further improving the quality of the true random number.

[0039] like Figure 2As shown, as an implementation manner, in an embodiment of the present application, the oscillation unit 121 includes a comparator CMP, a control unit 1211 and a capacitor C; the first end of the capacitor C, the first end of the control unit 1211 and the first input end of the comparator CMP are connected, and the common end of the three is connected to the output end of the dynamic matching module 110, the output end of the comparator CMP is connected to the second end of the control unit 1211, and the common end of the two is connected to an input end of the first trigger FF1; the control unit 1211 is used to control the voltage VFB of the first input end of the comparator CMP to jitter within a preset voltage value range after the capacitor C is discharged.

[0040] In this embodiment, the output terminal of the comparator CMP is connected to the second terminal of the control unit 1211, and the common terminal of the two is connected to an input terminal of the first trigger FF1 as the output terminal of the oscillation unit 121. The second terminal of the capacitor C is connected to the third terminal of the control unit 1211, and the common terminal of the two is grounded. The preset voltage value range can be a preset voltage value range. The other input terminal of the comparator CMP is used to input the reference voltage Vref. The output terminal of the dynamic matching module 110 outputs the first jittering voltage to the common terminal of the first terminal of the capacitor C, the first terminal of the control unit 1211 and the first input terminal of the comparator CMP. When the voltage VFB of the first input terminal of the comparator CMP is greater than the reference voltage Vref or less than the reference voltage Vref, the output signal output by the comparator CMP is flipped, so that the control unit 1211 is turned on or off, so that As capacitor C discharges or charges, the operating states of capacitor C and control unit 1211 vary with the jitter of the first jittering voltage. Since the jitter of the first jittering voltage varies randomly, the oscillation loop formed by comparator CMP, control unit 1211, and capacitor C cannot achieve equilibrium and is constantly searching for equilibrium. This effectively increases the jitter of the jittering signal output from the common terminal between the output terminal of comparator CMP and the second terminal of control unit 1211. After capacitor C is discharged, control unit 1211 controls the voltage VFB at the first input terminal of comparator CMP to jitter within a preset voltage range. Since VFB jitters within the preset voltage range, the charge and discharge time of capacitor C varies each time, further increasing the jitter of the jittering signal output from the common terminal between the output terminal of comparator CMP and the second terminal of control unit 1211.

[0041] like Figure 3 As shown, as an implementation manner, in an embodiment of the present application, the control unit 1211 includes a first MOS transistor MOS1; the first MOS transistor MOS1 is used to control the voltage VFB of the first input terminal of the comparator CMP to jitter within a preset voltage value range after the capacitor C is discharged; wherein the preset voltage value is greater than 0V.

[0042] In this embodiment, the preset voltage value may specifically be 50 mV. By setting the on-resistance of the first MOS transistor MOS1 to the preset impedance value, after the capacitor C is discharged, the voltage VFB at the first input terminal of the comparator CMP fluctuates within a preset voltage value range (or near the preset voltage value) corresponding to the preset impedance value. Since the preset voltage value still has room to decrease, the lower limit of the voltage VFB at the first input terminal of the comparator CMP is a floating value, so that the charging and discharging time of the capacitor C varies each time, which can further increase the jitter of the jitter signal output from the common terminal of the output terminal of the comparator CMP and the second terminal of the first MOS transistor MOS1.

[0043] like Figure 3 As shown, in this embodiment, the first MOS transistor MOS1 is an NMOS transistor, the oscillation unit 121 further includes a first inverting unit 1212, one input end of the comparator CMP is an inverting input end, and the other input end of the comparator CMP is a non-inverting input end. The output end of the comparator CMP is connected to the input end of the first inverting unit 1212, and the common end of the connection between the two is connected to an input end of the first trigger FF1 as the output end of the oscillation unit 121, and the output end of the first inverting unit 1212 is connected to the control end of the first MOS transistor MOS1. When the reference voltage Vref is just input to the second input end of the comparator CMP, the voltage VFB of the first input end of the comparator CMP is 0, and the dynamic matching module 110 outputs the first jitter voltage to the first end of the capacitor C to charge the capacitor C, so that the comparator C The voltage VFB at the first input terminal of the comparator CMP rises. When the voltage VFB at the first input terminal of the comparator CMP is greater than the reference voltage Vref, the output signal at the output terminal of the comparator CMP flips (from 1 to 0). After the output signal is inverted by the first inverting unit 1212, the first MOS transistor MOS1 is turned on, the capacitor C is discharged, and the voltage at the first input terminal drops. When the voltage at the first input terminal is less than the reference voltage Vref, the output signal of the comparator CMP flips again (from 0 to 1). After the output signal is inverted by the first inverting unit 1212, the first MOS transistor MOS1 is turned off, and the capacitor C is charged. The operating states of the capacitor C and the first MOS transistor MOS1 change with the jitter of the first jitter voltage. Specifically, the first inverting unit 1212 includes a first inverter INV1.

[0044] like Figure 3As shown, in this embodiment, the oscillation unit 121 further includes a second inverting unit 1213. The output end of the comparator CMP is connected to the input end of the second inverting unit 1213. The output end of the second inverting unit 1213 is connected to the input end of the first inverting unit 1212. The common end of the two is connected as the output end of the oscillation unit 121 to an input end of the first flip-flop FF1. The output end of the first inverting unit 1212 is connected to the control end of the first MOS transistor MOS1. The second inverting unit 1213 is used to shape the waveform of the output signal output by the comparator CMP, improve the waveform quality, and enhance the driving force of the output signal, so that the output signal It can be effectively transmitted to the first trigger FF1 and the first inverting unit 1212. Specifically, the second inverting unit 1213 includes a second inverter INV2 and a third inverter INV3. The output end of the comparator CMP is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, the output end of the third inverter INV3 is connected to the input end of the first inverter INV1, and the common end of the two is connected to an input end of the first trigger FF1 as the output end of the oscillation unit 121, and the output end of the first inverter INV1 is connected to the control end of the first MOS tube MOS1.

[0045] like Figure 3 As shown, in this embodiment, the oscillation unit 121 further includes a third inverting unit 1214, the output end of the first inverter INV1 is connected to the input end of the third inverting unit 1214, and the output end of the third inverting unit 1214 is connected to the control end of the first MOS transistor MOS1. The third inverting unit 1214 is used to shape the waveform of the signal output by the first inverter INV1, improve the waveform quality, and enhance the driving force of the signal, so that the signal can be effectively transmitted to the first MOS transistor MOS1. Specifically, the third inverting unit 1214 includes a fourth inverter INV4 and a fifth inverter INV5, the output end of the first inverter INV1 is connected to the input end of the fourth inverter INV4, the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is connected to the control end of the first MOS transistor MOS1.

[0046] like Figure 3 As shown, as an implementation method, in an embodiment of the present application, the sampling module 200 includes a second trigger FF2, and the other input end of the second trigger FF2 is used to input the target clock signal CLK_H; the second trigger FF2 is used to sample the target clock signal CLK_H according to the jittered clock signal CLK_L to generate a true random number.

[0047] In this embodiment, the second flip-flop FF2 can be a D flip-flop, and the data output end of the first flip-flop FF1 is connected to an input end of the second flip-flop FF2 as the output end of the clock signal generating circuit, and an input end of the second flip-flop FF2 can be a clock input end of the second flip-flop FF2, and the other input end of the second flip-flop FF2 can be a data input end of the second flip-flop FF2. The second flip-flop FF2 is specifically used to sample the target clock signal CLK_H input at the data input end according to the jittered clock signal CLK_L input at the clock input end to generate a true random number and output it.

[0048] As an implementation manner, in the embodiment of the present application, the input current or voltage includes multiple values, and each two adjacent switches can obtain input currents or voltages with different values.

[0049] like Figure 3 As shown, in this embodiment, the bias module 130 includes N bias units 131, each The input end of the bias unit 131 is connected to the power supply VDD, and the output end of each bias unit 131 is connected to each input end of the dynamic matching module 110 in a one-to-one correspondence. The N bias units 131 can be mirror images of each other, and the width-to-length ratio of each bias unit 131 is different, so that the input current or input voltage output by each bias unit 131 has a different value. Alternatively, the input end of each bias unit 131 is connected to each power supply VDD with different values, so that the input current or input voltage output by each bias unit 131 has a different value. Preferably, the N bias units 131 are mirror images of each other, and the width-to-length ratio of each bias unit 131 is different. The dynamic matching module 110 is specifically used to connect the input current or input voltage corresponding to the output of the first bias unit 131 when the random signal CLK_TRNG received by the control end flips to a valid level for the first time. When the random signal CLK_TRNG flips to an active level for the second time, the next bias unit 131 is switched to output the corresponding input current or input voltage. The preset order can be from left to right or from right to left, and the active level can be a high level. Because the N bias units 131 are mirror images of each other and each bias unit 131 has a different width-to-length ratio, the input current or input voltage output by each bias unit 131 to the dynamic matching module 110 has a different value. Therefore, the dynamic matching module 110 can obtain different input currents or input voltages in each adjacent switching. This can effectively enhance the jitter level of the first jitter voltage output by the dynamic matching module 110. Since the random signal CLK_TRNG flips to an active level at a random time, the jitter level of the first jitter voltage output by the dynamic matching module 110 can be further enhanced.

[0050] In this embodiment, the bias unit 131 includes a second MOS transistor MOS2, which is short for Metal-Oxide-Semiconductor Field-Effet Transistor. The second MOS transistor MOS2 may be a PMOS transistor. The N second MOS transistors MOS2 are mirror images of each other, and each second MOS transistor MOS2 has a different width-to-length ratio. By making the N second MOS transistors MOS2 mirror images of each other and making each second MOS transistor MOS2 have a different width-to-length ratio, the second MOS transistors MOS2 are mismatched, so that the input current or input voltage output by each second MOS transistor MOS2 is different. During actual layout (i.e., printed circuit board layout and routing), the mismatch between the second MOS transistors MOS2 can be achieved by making the N second MOS transistors MOS2 mirror images of each other, making each second MOS transistor MOS2 have a different width-to-length ratio, and making the positions of the second MOS transistors MOS2 asymmetric.

[0051] like Figure 3 and Figure 4As shown, in the embodiment of the present application, the dynamic matching module 110 may include N third flip-flops FF3, N third MOS transistors MOS3 and a NOR gate 111. The third MOS transistor MOS3 may be an NMOS transistor, and the third flip-flop FF3 may be a D flip-flop. The number of the third flip-flops FF3 and the third MOS transistors MOS3 is the same as the number of the second MOS transistors MOS2. The clock input end of each third flip-flop FF3 is connected to the output end of the sampling module 200 as the control end of the dynamic matching module 110 and is used to input the random signal CLK_TRNG. The data output end of the first third flip-flop FF3 is connected to the data input end of the next third flip-flop FF3 and the control end of the first third MOS transistor MOS3. The data output terminal of a third flip-flop FF3 is connected to the data input terminal of the next third flip-flop FF3 or the control terminal of the next third MOS transistor MOS3. The input terminals of each third MOS transistor MOS3 are connected to the output terminals of each second MOS transistor MOS2 in a one-to-one correspondence. The output terminals of each third MOS transistor MOS3 are connected to the input terminals of the NOR gate 111. The output terminals of the NOR gate 111 are connected to the data input terminal of the first third flip-flop FF3. Since the initial level state of the output terminals of each third MOS transistor MOS3 is a low level, a high level is output through the NOR gate 111. The value of the data input terminal of the first third flip-flop FF3 is 1. When the random signal CLK_TRN outputted from the output terminal of the sampling module 200 is When the first high level appears on G, the first third trigger FF3 is triggered to output the value 1 at the data input end, so that the first third MOS transistor MOS3 is turned on, and the other third MOS transistors MOS3 are in the off state, so that the output end of the first second MOS transistor MOS2 outputs the input current or input voltage to the first third MOS transistor MOS3. When the random signal CLK_TRNG output by the output end of the sampling module 200 appears at the next high level, the data output end of the first third trigger FF3 is triggered to output 0, so that the first third MOS transistor MOS3 is turned off, and the data output end of the next third trigger FF3 is triggered to output 1, so that the next third MOS transistor MOS3 is turned on, so that the next second MOS transistor M The output terminal of OS2 outputs the input current or input voltage to the next third MOS transistor MOS3. After the input current or input voltage outputted from the output terminal of the last second MOS transistor MOS2 reaches the last third MOS transistor MOS3, when the random signal CLK_TRNG outputted from the output terminal of the sampling module 200 reaches the next high level, the data output terminal of the last third flip-flop FF3 is triggered to output 0, so that the last third MOS transistor MOS3 is turned off, and the data output terminal of the first third flip-flop FF3 is triggered to output 1, so that the first third MOS transistor MOS3 is turned on, so that the input current or input voltage outputted from the output terminal of the first second MOS transistor MOS2 reaches the first third MOS transistor MOS3.This cycle repeats until the true random number generation circuit stops working. The switching action of switching the input current or input voltage output by the two adjacent second MOS transistors MOS2 increases the jitter level of the first jitter voltage output by the dynamic matching module 110. In addition, the random signal CLK_TRNG is at a high level for a random period of time, which can further enhance the jitter level of the first jitter voltage output by the dynamic matching module 110.

[0052] For example, the second MOS transistor MOS2 is a PMOS transistor, the third MOS transistor MOS3 is an NMOS transistor, the third flip-flop FF3 is a D flip-flop, and N is 4. Since the initial level state of the output end of each third MOS transistor MOS3 is a low level, a high level is output through the NOR gate 111, and the value of the data input end of the first third flip-flop FF3 is 1. When the random signal CLK_TRNG has a first high level, the first third flip-flop FF3 is triggered to output the value 1 of the data input end, so that the first third MOS transistor MOS3 is turned on, and all other third MOS transistors MOS3 are in a cut-off state, so that the output end of the first second MOS transistor MOS2 outputs the input current or input voltage to the first third MOS transistor MOS3; when the random signal CLK_TRNG has a second high level, the data output end of the second third flip-flop FF3 is triggered to output 1, so that the second third MOS transistor MOS3 is turned on, and the data output ends of the other third flip-flops FF3 are triggered to output 0, so that the other third MOS transistors MOS3 are turned off, so that the output end of the second second MOS transistor MOS2 outputs the input current or input voltage to the second third MOS transistor MOS3. When the random signal CLK_TRNG has a third high level, The data output terminal of the third third flip-flop FF3 is triggered to output 1, and the data output terminals of the second third flip-flop FF3 and the other flip-flops are triggered to output 0, so that the MOS3s except the third MOS3 are turned off, the third third MOS3 is turned on, and the output terminal of the third second MOS2 outputs the input current or input voltage to the third third MOS3. When the random signal CLK_TRNG reaches a fourth high level, the data output terminal of the fourth third flip-flop FF3 is triggered to output 1, and the data output terminals of the other third flip-flops FF3 are triggered to output 0, so that the fourth third MOS3 is turned on, so that the output terminal of the fourth second MOS2 outputs the input current or input voltage to the fourth third MOS3. When the random signal CLK_TRNG reaches a fifth high level, the data output terminal of the first third flip-flop FF3 is triggered to output 1, and the data output terminals of the other third flip-flops FF3 are triggered to output 0, so that the first third MOS3 is turned on, so that the output terminal of the first second MOS2 outputs the input current or input voltage to the first third MOS3. This cycle repeats until the true random number generation circuit stops operating.

[0053] An embodiment of the present application also provides a chip, comprising any one of the above-mentioned true random number generation circuits.

[0054] The embodiments in this specification are described in a progressive manner, and each embodiment focuses on the following For other differences between the embodiments, reference may be made to the same or similar parts between the embodiments.

[0055] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A true random number generation circuit, characterized in that: It includes a clock signal generating module and a sampling module, wherein the output end of the clock signal generating module is connected to an input end of the sampling module; The clock signal generating module is used to randomly switch the input current or voltage of the clock signal generating module according to the random signal, thereby generating a jittered clock signal; The sampling module is used to generate a true random number by sampling a target clock signal according to the jittered clock signal.

2. The true random number generation circuit according to claim 1, wherein: The control end of the clock signal generating module is connected to the output end of the sampling module, and the random signal is associated with the true random number.

3. The true random number generating circuit according to claim 1, wherein: The clock signal generation module includes a dynamic matching module and an oscillation module; The output end of the dynamic matching module is connected to an input end of the oscillation module, and the output end of the oscillation module is connected to the input end of the sampling module; The dynamic matching module is configured to randomly switch the input current or voltage according to the random signal and output a first jittering voltage; The oscillation module is configured to generate the jittered clock signal according to the first jittered voltage.

4. The true random number generating circuit according to claim 3, wherein: The clock signal generating circuit further includes a bias module, each output terminal of the bias module is connected to the input terminal of the dynamic matching module; The bias module is used to output the input current or voltage.

5. The true random number generating circuit according to claim 3, wherein: The oscillation module includes an oscillation unit and a first trigger; An input terminal of the oscillation unit is connected to an output terminal of the dynamic matching module, and an output terminal of the oscillation unit is connected to an input terminal of the first trigger; The oscillation unit is configured to output a dithering signal according to the first dithering voltage; The first trigger is configured to generate the jitter clock signal according to the jitter signal.

6. The true random number generating circuit according to claim 5, wherein: The oscillation unit includes a comparator, a control unit and a capacitor; The first end of the capacitor, the first end of the control unit, and the first input end of the comparator are connected, and a common end of the three is connected to the output end of the dynamic matching module, the output end of the comparator is connected to the second end of the control unit, and a common end of the two is connected to the one input end of the first trigger; The control unit is used to control the voltage of the first input terminal of the comparator to fluctuate within a preset voltage value range after the capacitor is discharged.

7. The true random number generating circuit according to claim 6, wherein: The control unit includes a first MOS tube; The first MOS transistor is used to control the voltage at the first input terminal of the comparator to fluctuate within the preset voltage value range after the capacitor is discharged; wherein the preset voltage value is greater than 0V.

8. The true random number generating circuit according to claim 1, wherein: The sampling module includes a second trigger, and another input terminal of the second trigger is used to input the target clock signal; The second trigger is configured to generate the true random number by sampling the target clock signal according to the jittered clock signal.

9. The true random number generating circuit according to any one of claims 1 to 8, characterized in that: The input current or voltage includes multiple values, and each two adjacent switching operations can obtain input currents or voltages with different values.

10. A chip, characterized in that: The method comprises the true random number generating circuit according to any one of claims 1 to 9.

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