Formation method of semiconductor structure

Abstract

The invention relates to a method for forming a semiconductor structure. According to the forming method, after a diffusion barrier layer and a metal adhesion layer are formed in a through hole, reverse sputtering is firstly carried out to transfer part of the metal adhesion layer formed on the bottom wall of the through hole to the side wall of the through hole, the thickness of the metal adhesion layer located on the side wall of the through hole can be increased, flash deposition is then carried out, the thickness of the metal adhesion layer on the inner wall of the through hole is more uniform, and the thickness of the metal adhesion layer is improved. Therefore, the total thickness of the diffusion barrier layer and the metal adhesion layer located on the side wall of the through hole can be increased and is more uniform, the adhesiveness of the metal adhesion layer and the side wall of the through hole is enhanced, when the seed crystal layer grows on the basis of the metal adhesion layer, the crystallization direction of the seed crystal layer on the side wall of the through hole is relatively consistent, and the yield is improved. And then, when a metal material such as copper is grown on the basis of the seed crystal layer, the crystal phase arrangement of the metal material is more uniform, and the filling is more compact, so that the via hole has better supporting performance and reliability, and the test yield is favorably improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] During chip manufacturing, a multi-layer electrical interconnect structure is often formed on a substrate through metal interconnection processes to provide connections between doped regions, devices, circuits, and input / output (I / O). This multi-layer electrical interconnect structure includes multiple layers of metal wiring separated by dielectric materials and vias (vias). The vias are provided between adjacent metal wirings to serve as connection channels.

[0003] Figure 1 This is a cross-sectional diagram of a via formed using an existing process. Figure 1 In the process of forming the via hole, in order to prevent the metal material (such as copper (Cu)) in the via hole from diffusing and to provide adhesion, a diffusion barrier layer and a metal adhesion layer (such as a composite layer 10 of TaN and Ta) are usually formed along the inner wall of the via hole first, and then a seed layer is deposited and the metal material is filled using a process such as electrochemical deposition.

[0004] After forming the via hole using the above process, the copper filled inside has problems of uneven and non-dense crystal phase arrangement, and void defects will also be generated in the via hole. As the stress release of the surrounding metal wiring 20 or dielectric layer 30 increases, the via hole is prone to collapse (crack) (e.g. Figure 2 As shown in FIG, the metal wiring 20 may be broken or the dielectric layer 30 may be delaminated, resulting in new defects in the chip, which in turn may affect the connection function of the via hole and cause a decrease in the test yield (such as CP test). Summary of the Invention

[0005] The study found that when the via hole is formed using the existing process described in the background art, the composite layer 10 (refer to Figure 1 ) has a low and uneven thickness (especially more obvious in the central area of the substrate), and has poor adhesion. When a seed layer is formed on the basis of the composite layer 10, the crystallization direction of the seed layer on the side wall is not consistent. Then, when a metal material such as copper is grown on the basis of the seed layer, the crystal phase arrangement of the copper is also uneven. The copper in the via hole often presents multiple crystal orientation partitions, and void defects are easily formed between the multiple crystal orientation partitions, resulting in a decrease in density. When the stress release of the surrounding material layer increases, the interior of the via hole is prone to collapse (refer to Figure 2 ), which leads to a decrease in test yield.

[0006] In order to improve the reliability of vias and increase the test yield, the present invention provides a method for forming a semiconductor structure.

[0007] The method for forming a semiconductor structure provided by the present invention includes:

[0008] Providing a semiconductor substrate, wherein the semiconductor substrate has a lower metal layer and an interlayer dielectric layer covering the lower metal layer;

[0009] forming a through hole in the interlayer dielectric layer, wherein the through hole exposes the underlying metal layer;

[0010] stacking a diffusion barrier layer and a metal adhesion layer in sequence on the inner wall of the through hole;

[0011] performing reverse sputtering to transfer a portion of the metal adhesion layer formed on the bottom wall of the through hole to the side wall of the through hole; and

[0012] Flash deposition is performed to make the thickness of the metal adhesion layer uniform.

[0013] Optionally, the diffusion barrier layer and the metal adhesion layer are respectively a tantalum nitride layer and a tantalum layer; or the diffusion barrier layer and the metal adhesion layer are respectively a titanium nitride layer and a titanium layer.

[0014] Optionally, before the reverse sputtering is performed, the portion of the metal adhesion layer located in the central area of the bottom of the through hole is the thickest.

[0015] Optionally, the diffusion barrier layer and the metal adhesion layer are both formed by a PVD process.

[0016] Optionally, the process conditions for forming the diffusion barrier layer and the metal adhesion layer include:

[0017] The DC power of the PVD equipment is set to 14,000 W to 16,000 W, the AC bias power is set to 350 W to 450 W, the RF coil power and the DC coil power are set to 0, and the process gases are argon and nitrogen for a first period of time; and

[0018] At the end of the first time period, the DC power is adjusted to 14500W-15500W and the process gas is argon, which lasts for a second time period.

[0019] Optionally, the process conditions for performing the reverse sputtering include:

[0020] The DC power of the PVD equipment is set to 450W-550W, the AC bias power is set to 550W-650W, the RF coil power is set to 900W-1100W, the DC coil power is set to 400W-600W, and the process gas is argon, and the process is continued for a third period of time.

[0021] Optionally, the process conditions for performing the flash deposition include:

[0022] The DC power of the PVD equipment is set to 14000W to 16000W, the AC bias power is set to 350W to 450W, the RF coil power and the DC coil power are set to 0, and the process gas is argon, which is continued for a fourth period of time.

[0023] Optionally, after the flash deposition is completed, the total thickness of the diffusion barrier layer and the metal adhesion layer located on the sidewall of the through hole is greater than or equal to 4 nm and less than or equal to 8 nm.

[0024] Optionally, after completing the flash deposition, the forming method further includes:

[0025] forming a seed layer on the surface of the metal adhesion layer; and

[0026] A metal material is grown on the surface of the seed layer to fill the through hole, and a conductive via is formed corresponding to the through hole.

[0027] Optionally, the seed layer and the metal material include at least one of copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, cobalt and ruthenium.

[0028] In the method for forming a semiconductor structure provided by the present invention, after a diffusion barrier layer and a metal adhesion layer are formed in the through hole in the interlayer dielectric layer, reverse sputtering is first performed to transfer part of the metal adhesion layer formed on the bottom wall of the through hole to the side wall of the through hole, which can increase the thickness of the metal adhesion layer located on the side wall of the through hole. Then, flash deposition is performed to make the thickness of the metal adhesion layer on the inner wall of the through hole more uniform, thereby increasing the total thickness of the diffusion barrier layer and the metal adhesion layer located on the side wall of the through hole and making the thickness more uniform, thereby enhancing the adhesion of the metal adhesion layer to the side wall of the through hole. When a seed layer is grown on the basis of the metal adhesion layer, the crystallization direction of the seed layer on the side wall of the through hole is relatively consistent. Then, when a metal material such as copper is grown on the basis of the seed layer, the crystal phase arrangement of the metal material is more uniform and the filling is denser, so that the obtained conductive hole has better support performance and reliability, which helps to improve the test yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a cross-sectional schematic diagram of a via hole formed using an existing process.

[0030] Figure 2 Schematic diagram of the collapse inside a via formed using an existing process.

[0031] Figure 3 It is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0032] Figures 4A to 4E is a schematic cross-sectional view of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0033] Figure 5 TEM photos of a via hole obtained by using a method for forming a semiconductor structure according to an embodiment of the present invention and a via hole obtained by a conventional process are shown. DETAILED DESCRIPTION

[0034] The following is a further detailed description of the method for forming a semiconductor structure of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the terms "first" and "second" in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate. It should be understood that the drawings in the specification are all in a very simplified form and are not in precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention. In addition, spatially relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the drawing is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0035] Reference Figure 1 and Figure 2 In the vias formed by the existing process, the crystal phase arrangement of the metal material filling the vias is uneven, and is manifested as multiple crystal direction partitions. Such vias are prone to collapse, which in turn leads to a decrease in the test yield. The study found that this is related to the inconsistent crystallization direction of the seed layer on the side wall of the via (such as the inconsistent crystallization direction of the seed layer located at the upper part of the side wall and the seed layer located at the bottom of the side wall), and the crystallization of the seed layer is related to the thickness and uniformity of the composite layer 10. The method for forming a semiconductor structure of an embodiment of the present invention can promote the consistency of the crystallization direction of the seed layer further formed on the side wall of the via by increasing the thickness and thickness uniformity of the metal adhesion layer on the side wall of the via, which helps to make the crystal phase arrangement of the metal material filling the via more uniform and the filling more dense, reduce the risk of collapse of the via, and help to improve the test yield.

[0036] Reference Figure 3 and Figure 4A According to the method for forming a semiconductor structure according to an embodiment of the present invention, first, step S1 is performed to provide a semiconductor substrate, wherein the semiconductor substrate has a lower metal layer 110 and an interlayer dielectric layer 120 covering the lower metal layer 110.

[0037] The semiconductor substrate is a structure based on a substrate (not shown) after some device manufacturing steps (such as deposition, etching, ion implantation, etc.) have been completed. The substrate can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a silicon germanium-on-insulator substrate, or a Group III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate). As an example, the substrate is a silicon wafer. The semiconductor substrate may include one or more electronic components formed based on the substrate. The electronic components may include at least one of MOS devices, sensors, memory devices, and passive devices. The lower metal layer 110 is a wiring layer formed on the substrate using a metal interconnect process. The lower metal layer 110 may be the bottommost wiring layer or the wiring layer above the bottommost wiring layer. The lower metal layer 110 can be connected to the electronic components on the substrate.

[0038] The interlayer dielectric layer 120 is used to isolate the underlying metal layer 110 from the wiring layer to be formed when forming a wiring layer on the underlying metal layer 110. The material of the interlayer dielectric layer 120 can be selected as needed. The interlayer dielectric layer can be a single layer or multiple layers, and specifically can include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and NDC (Nitrogendoped Silicon Carbide). It can also include borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin-on glass (SOG), tetraethyl orthosilicate (TEOS), or high-density plasma CVD (HDP-CVD) oxide, etc.

[0039] Reference Figure 3 and Figure 4A Then, step S2 is performed to form a through hole 101 in the interlayer dielectric layer 120, wherein the through hole 101 exposes the underlying metal layer 110. The through hole 101 can be formed using photolithography and etching processes. In some embodiments, a groove can be formed at the top of the through hole 101, and the groove extends along the length direction in a plane parallel to the surface of the semiconductor substrate to form a wiring pattern. The material subsequently formed in the through hole can also be formed in the groove, so that a wiring layer located above the underlying metal layer 110 can be formed corresponding to the groove.

[0040] Reference Figure 3 and Figure 4B Afterwards, step S3 is performed to sequentially stack a diffusion barrier layer 130 and a metal adhesion layer 140 on the inner wall of the through hole 101 .

[0041] The diffusion barrier layer 130 is used to prevent the metal material subsequently filled in the through-hole 101 from diffusing laterally, thereby preventing electromigration. The metal adhesion layer 140 can enhance the adhesion of the metal material subsequently filled in the through-hole 101. The diffusion barrier layer 130 and the metal adhesion layer 140 can also be formed on the surface outside the through-hole 101. In this embodiment, the diffusion barrier layer 130 is a tantalum nitride layer (TaN), and the metal adhesion layer 140 is tantalum (Ta). However, this is not limiting. For example, in other embodiments, the diffusion barrier layer 130 is titanium nitride (TiN), and the metal adhesion layer 140 is titanium (Ti). The diffusion barrier layer 130 and the metal adhesion layer 140 can be deposited using a suitable process. For example, the tantalum nitride used as the diffusion barrier layer 130 can also be formed using atomic layer deposition or PVD processes, and the tantalum used as the metal adhesion layer 140 can be formed using a PVD process.

[0042] In this embodiment, the diffusion barrier layer 130 and the metal adhesion layer 140 are both formed using a PVD process. The diffusion barrier layer 130 and the metal adhesion layer 140 can be formed by continuous sputtering deposition using the same PVD equipment. The corresponding deposition process can be set by a deposition recipe on the control terminal of the PVD equipment. As an example, when forming the diffusion barrier layer 130 and the metal adhesion layer 140, the PVD equipment is first set to have a DC power of 14,000 W to 16,000 W, an AC bias power of 350 W to 450 W, RF coil power and DC coil power of 0, and argon (Ar) and nitrogen (N2) as process gases (e.g., an Ar flow rate of less than 10 sccm and a N2 flow rate of 10 sccm to 30 sccm) for a first duration. At the end of the first duration, the DC power is adjusted to 14,500 W to 15,500 W, and the process gas is Ar (e.g., an Ar flow rate of less than 10 sccm) (the N2 flow rate is adjusted to 0) for a second duration. The first and second durations can be adjusted according to specific circumstances.

[0043] Testing revealed that after step S3, the metal adhesion layer 140 attached to the sidewalls of via 101 was relatively thin, while the metal adhesion layer 140 attached to the bottom wall of via 101 was relatively thick. Furthermore, the metal adhesion layer 140 attached to the bottom wall of via 101 exhibited a high center and low sides morphology, with the thickest portion located in the center of the bottom of via 101. For subsequent processing, the insufficient thickness of the metal adhesion layer 140 attached to the sidewalls of via 101 results in a relatively low combined thickness of the diffusion barrier layer 130 and the metal adhesion layer 140, increasing the risk of via collapse as described in the background art. If the overall thickness of the metal adhesion layer 140 is increased by extending the deposition time, the metal adhesion layer 140 tends to accumulate at the opening of via 101, which, given the relatively small width of via 101, complicates subsequent filling of via 101. Therefore, simply extending the deposition time to increase the thickness of the metal adhesion layer 140 is not advisable.

[0044] Reference Figure 3 and Figure 4C , performing step S4 to perform reverse sputtering to transfer a portion of the metal adhesion layer 140 formed on the bottom wall of the through hole 101 to the side wall of the through hole 101 . Figure 4C The dashed arrow indicates the direction of transfer of the metal adhesion layer 140 .

[0045] The reverse sputtering refers to setting appropriate PVD process conditions so that ions bombard the bottom wall of the through-hole 101, so that the material originally deposited on the bottom wall of the through-hole 101 is transferred to the side wall. Here, by transferring part of the metal adhesion layer 140 formed on the bottom wall of the through-hole 101 to the side wall of the through-hole 101, the coverage and thickness of the metal adhesion layer 140 on the side wall can be increased. In this embodiment, after performing step S3, the same PVD equipment can still be used to perform steps S4 and S5. In step S4, the reverse sputtering is performed, for example, using the following process conditions: the DC power of the PVD equipment is 450W to 550W, the AC bias power is 550W to 650W, the RF coil power is 900W to 1100W, the DC coil power is 400W to 600W, and the process gas is argon (for example, the flow rate is 5sccm to 15sccm), and it lasts for a third time. The third time can be set according to the specific situation, for example, 6 seconds.

[0046] After step S4, a portion of the metal adhesion layer 140 formed at the bottom of the through-hole 101 is transferred and attached to the sidewall of the through-hole 101, so that the thickness of the metal adhesion layer 140 formed on the sidewall of the through-hole 101 (especially the bottom of the sidewall) increases, thereby increasing the total thickness of the diffusion barrier layer 130 and the metal adhesion layer 140 on the sidewall of the through-hole 101. In addition, the original morphology of the metal adhesion layer 140 on the bottom wall of the through-hole 101, which is higher in the middle and lower on both sides, can be improved, and the thickness of the portion of the metal adhesion layer 140 located on the bottom wall of the through-hole 101 is more uniform.

[0047] Experiments have shown that the thickness uniformity of the metal adhesion layer 140 formed on the sidewall of the through hole 101 also affects the formation of the subsequent seed layer. In order to improve the thickness uniformity of the metal adhesion layer 140, reference is made to FIG. Figure 3 and Figure 4D According to the method for forming a semiconductor structure of this embodiment, after the reverse sputtering is completed, step S5 is performed to perform flash deposition to make the thickness of the metal adhesion layer 140 uniform.

[0048] The flash deposition refers to the use of IMP (ionized metal plasma) technology to ionize and sputter-deposit the corresponding metal target (for example, tantalum in this embodiment). The purpose of performing flash deposition in this embodiment is to repair the surface of the metal adhesion layer 140 after the above-mentioned reverse sputtering, thereby improving the thickness uniformity of the metal adhesion layer 140. As an example, step S5 adopts the following process conditions: the DC power of the PVD equipment is 14000W to 16000W, the AC bias power is 350W to 450W, the RF coil power and the DC coil power are 0, and the process gas is argon (the flow rate is, for example, less than 10sccm), and it lasts for a fourth time. The fourth time can be set according to specific circumstances. Experiments have found that after the flash deposition is completed, the total thickness of the diffusion barrier layer 130 and the metal adhesion layer 140 located on the side wall of the through hole 101 is greater than or equal to 4nm and less than or equal to 8nm.

[0049] Reference Figure 4EThe method for forming a semiconductor structure according to an embodiment of the present invention may further include the steps of forming a seed layer on the inner wall of the through hole 101 and filling it with a metal material. Specifically, after completing the flash deposition, the formation method further includes the following steps: first, forming a seed layer on the surface of the metal adhesion layer 140 by, for example, an atomic layer deposition process; then, growing a metal material on the surface of the seed layer to fill the through hole 101, thereby forming a via corresponding to the through hole 101. The growth of the metal material may be performed by a process such as electrochemical deposition. The seed layer and the metal material may include at least one of copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, cobalt, and ruthenium. As an example, the seed layer is a copper seed layer, and the metal material is copper (Cu).

[0050] Figure 5 The left figure in the middle shows a TEM photo of a via hole obtained by a method for forming a semiconductor structure according to an embodiment of the present invention, and the right figure shows a TEM photo of a via hole obtained by a conventional process as described in the background art. Figure 5 The TEM photo shown on the middle right shows that in the conductive hole formed by the existing process, the total thickness of the tantalum nitride layer and the tantalum layer on the side wall of the through hole is relatively small, and the copper filled in the through hole has a clear black and white boundary, indicating that the copper in the through hole forms multiple crystal orientation partitions, and the crystal phase arrangement is uneven and not dense. Such a conductive hole is prone to void defects, and the interior of the conductive hole is prone to collapse, resulting in low yield. Figure 5 The TEM photo shown on the left shows that the grayscale of the conductive hole obtained by the method for forming a semiconductor structure according to an embodiment of the present invention is uniform, indicating that the crystal phase of the copper filled in the through-hole is consistent and uniform, and the filling is denser. Compared with the existing process, the conductive hole obtained by the embodiment of the present invention has better supporting performance and reliability, which helps to improve the test yield.

[0051] In the method for forming the semiconductor structure described in the above embodiment, after forming the diffusion barrier layer 130 and the metal adhesion layer 140 in the through hole 101 in the interlayer dielectric layer 120, reverse sputtering is first performed to transfer part of the metal adhesion layer 140 formed on the bottom wall of the through hole 101 to the side wall of the through hole 101, thereby increasing the thickness of the metal adhesion layer 140 located on the side wall of the through hole 101. Then, flash deposition is performed to make the thickness of the metal adhesion layer 140 on the inner wall of the through hole 101 more uniform, thereby making the thickness of the metal adhesion layer 140 located on the side wall of the through hole 101 more uniform. The total thickness of the diffusion barrier layer 130 and the metal adhesion layer 140 is increased and the thickness is more uniform, which enhances the adhesion of the metal adhesion layer 140 to the side wall of the through hole 101. When a seed layer is grown on the basis of the metal adhesion layer 140, the crystallization direction of the seed layer on the side wall of the through hole 101 is relatively consistent. Then, when a metal material such as copper is grown on the basis of the seed layer, the crystal phase arrangement of the metal material is more uniform and the filling is denser, so that the obtained conductive hole has better support performance and reliability, which helps to improve the test yield.

[0052] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has a lower metal layer and an interlayer dielectric layer covering the lower metal layer; forming a through hole in the interlayer dielectric layer, wherein the through hole exposes the underlying metal layer; stacking a diffusion barrier layer and a metal adhesion layer in sequence on the inner wall of the through hole; performing reverse sputtering to transfer a portion of the metal adhesion layer formed on the bottom wall of the through hole to the side wall of the through hole; as well as Flash deposition is performed to make the thickness of the metal adhesion layer uniform.

2. The forming method according to claim 1, wherein: The diffusion barrier layer and the metal adhesion layer are respectively a tantalum nitride layer and a tantalum layer; or the diffusion barrier layer and the metal adhesion layer are respectively a titanium nitride layer and a titanium layer.

3. The forming method according to claim 1, wherein: Before the reverse sputtering is performed, the portion of the metal adhesion layer located in the central area of the bottom of the through hole is the thickest.

4. The forming method according to claim 1, wherein: The diffusion barrier layer and the metal adhesion layer are both formed by a PVD process.

5. The forming method according to claim 4, wherein: The process conditions for forming the diffusion barrier layer and the metal adhesion layer include: The DC power of the PVD equipment is set to 14,000 W to 16,000 W, the AC bias power is set to 350 W to 450 W, the RF coil power and the DC coil power are set to 0, and the process gases are argon and nitrogen for a first period of time; and At the end of the first time period, the DC power is adjusted to 14500W-15500W and the process gas is argon, which lasts for a second time period.

6. The forming method according to claim 1, wherein: The process conditions for performing the reverse sputtering include: The DC power of the PVD equipment is set to 450W-550W, the AC bias power is set to 550W-650W, the RF coil power is set to 900W-1100W, the DC coil power is set to 400W-600W, and the process gas is argon, and the process is continued for a third period of time.

7. The forming method according to claim 1, wherein: The process conditions for performing the flash deposition include: The DC power of the PVD equipment is set to 14000W to 16000W, the AC bias power is set to 350W to 450W, the RF coil power and the DC coil power are set to 0, and the process gas is argon, which is continued for a fourth period of time.

8. The forming method according to claim 1, wherein: After the flash deposition is completed, the total thickness of the diffusion barrier layer and the metal adhesion layer located on the sidewall of the through hole is greater than or equal to 4 nm and less than or equal to 8 nm.

9. The forming method according to claim 1, wherein: After completing the flash deposition, the forming method further includes: forming a seed layer on the surface of the metal adhesion layer; and A metal material is grown on the surface of the seed layer to fill the through hole, and a conductive via is formed corresponding to the through hole.

10. The forming method according to claim 9, wherein: The seed layer and the metal material include at least one of copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, cobalt and ruthenium.

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