Integrated GaN power device including PFC and QR flyback controllers

Abstract

The invention relates to an integrated GaN power device including PFC and QR flyback controllers. An electronic component. The electronic component includes: a base; a first semiconductor device attached to the base and having: a first gallium nitride (GaN)-based switch having a first gate, a first source, and a first drain, the first gate being arranged to control a current flow between the first source and the first drain; and a second GaN-based switch having a second source, a second gate, and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic assembly also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect an amplitude of the current flow; and a drive circuit coupled to the first gate and the second gate, the drive circuit arranged to control on and off states of the first GaN-based switch and the second GaN-based switch.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of December 10, 2024, the national application number 202411813056.9, and the invention name “Integrated GaN power device including PFC and QR flyback controller”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 608,792 filed on December 11, 2023, for “POWER FACTOR CORRECTION CONTROLLER CIRCUIT AND AN INTEGRATED GANPOWER DEVICE,” Chinese Provisional Patent Application No. 202311698842.4 filed on December 11, 2023, for “PACKAGE FOR HIGH-VOLTAGE POWER DEVICE AND PACKAGE FOR HIGH-VOLTAGE POWER DEVICE AND CONTROLLER CO-PACKAGE,” and Chinese Provisional Patent Application No. 202311698842.4 filed on November 11, 2024, for “QR FLYBACK CONTROLLERSWITCHER IN A DPAK-4L PACKAGE The contents of all of these patent applications are hereby incorporated by reference in their entirety for all purposes. Technical Field

[0004] The described embodiments relate generally to power converters, and more particularly, embodiments of the invention relate to integrated gallium nitride (GaN) power devices including power factor correction (PFC) controllers and / or quasi-resonant (QR) flyback controllers. Background Art

[0005] Electronic devices such as computers, servers, and televisions employ one or more power conversion circuits to convert one form of electrical energy into another. Some power conversion circuits use a circuit topology called a DC-DC converter to convert a high (or low) DC voltage to a lower (or higher) DC voltage. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, new power converters can provide relatively high efficiency and a smaller size for these new electronic devices. Summary of the Invention

[0006] In some embodiments, an electronic assembly is disclosed. The electronic assembly includes: a base; a first semiconductor device attached to the base and having: a first gallium nitride (GaN)-based switch having a first gate, a first source, and a first drain, wherein the first gate is arranged to control current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate and the second drain is coupled to the first drain; a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect the magnitude of the current flow; and a drive circuit coupled to the first gate and the second gate, the drive circuit being arranged to control the on and off states of the first GaN-based switch and the second GaN-based switch; and an electrically insulating encapsulant at least partially encapsulating the base, the first semiconductor device, and the second semiconductor device.

[0007] In some embodiments, the electronic component further includes a first external terminal coupled to the first drain, a second external terminal coupled to the first source, and a third external terminal coupled to the logic circuit, the third external terminal being arranged to transmit a signal corresponding to the detected amplitude of the current flow.

[0008] In some implementations, the electronic component further includes a resistor coupled to the second source, and wherein the logic circuit detects a voltage drop across the resistor that is proportional to the magnitude of the current flow.

[0009] In some implementations, the resistor is disposed within the second semiconductor device.

[0010] In some embodiments, the driving circuit synchronously controls the on and off states of the first GaN-based switch and the second GaN-based switch.

[0011] In some implementations, the electronic component further includes a fourth external terminal coupled to the logic circuit, wherein the fourth external terminal is arranged to receive a pulse width modulated signal.

[0012] In some embodiments, the electronic component further comprises a fifth external terminal arranged to receive a power supply.

[0013] In some embodiments, an electronic component is disclosed. The electronic component includes: a first semiconductor device including: a first gallium nitride (GaN)-based switch having a first gate, a first source, and a first drain, wherein the first gate is arranged to control current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate, and the second drain is coupled to the first drain; a second semiconductor device including: a drive circuit coupled to the first gate and the second gate, the drive circuit being arranged to control the flow of current between the first GaN-based switch and the second GaN a GaN-based switch configured to switch on and off; a logic circuit configured to: detect the amplitude of the current flow via a first signal received from the second source; and control the drive circuit to turn off the first GaN-based switch and the second GaN-based switch when the detected amplitude of the current flow exceeds a threshold current value; and an electrically insulating encapsulant that at least partially encapsulates the first semiconductor device and the second semiconductor device; a first external terminal that is disposed at an outer surface of the electronic component and is coupled to the first drain; and a second external terminal that is disposed at the outer surface of the electronic component and is coupled to the first source.

[0014] In some embodiments, a method of operating an electronic component is disclosed. The method includes: receiving an input signal at a first external terminal; transmitting the input signal to a driver circuit disposed on a first semiconductor device disposed within the electronic component, wherein the driver circuit transmits a first drive signal and a second drive signal in response to receiving the input signal; causing a first gallium nitride (GaN)-based switch to transition between a first on-state and a first off-state in response to receiving the first drive signal, wherein the first GaN-based switch is disposed on a second semiconductor device disposed within the electronic component and wherein the first GaN-based switch controls the flow of current between a second external terminal of the electronic component and a third external terminal of the electronic component; causing a second gallium nitride (GaN)-based switch to transition between a second on-state and a second off-state in response to receiving the second drive signal, wherein the second GaN-based switch is disposed on the second semiconductor device; detecting the magnitude of the current via a detection circuit disposed on the second semiconductor device, wherein the detection circuit is coupled to the second GaN-based switch; and generating an output signal at a fourth external terminal, wherein the output signal corresponds to the magnitude of the current.

[0015] In some implementations, the detection circuit includes a resistor disposed within the first semiconductor device, the resistor coupled to the fourth external terminal.

[0016] In some implementations, the method further includes detecting a direction of the current via the detection circuit.

[0017] In some embodiments, the generated output signal corresponds to the magnitude and the direction of the current. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A A schematic diagram illustrating a PFC converter using a reduced pin count controller IC according to some embodiments;

[0019] Figure 1B shows a schematic diagram of an integrated GaN power device including a PFC controller IC and a GaN switch according to some embodiments;

[0020] Figure 2A Shown according to some embodiments Figure 1A Schematic diagram of the internal circuit of the PFC controller IC;

[0021] Figure 2B A schematic diagram illustrating internal circuitry of a PFC controller IC according to certain embodiments;

[0022] Figure 3 shows the same diagram with some specific component values according to certain embodiments. Figure 1A The schematic diagram of the PFC converter is similar to the schematic diagram;

[0023] Figure 4 A schematic diagram illustrating a PFC converter employing a capacitive sensing scheme using a reduced pin count controller IC according to some embodiments is shown;

[0024] Figure 5 The equations shown are used to illustrate Figure 4 The simulation results of the PFC working;

[0025] Figure 6 is a diagram illustrating the operation according to some embodiments Figure 1A A simplified flow chart of a method for a PFC converter;

[0026] Figure 7 is a diagram illustrating the operation according to some embodiments Figure 4 A simplified flow chart of a method for a PFC converter;

[0027] Figure 8A An integrated GaN power device 800 according to an embodiment of the present disclosure is shown. Figure 8B An integrated GaN power device in a four-terminal DPAK package is shown according to an embodiment of the present disclosure. Figure 8C An integrated GaN power device 850 is shown according to an embodiment of the present disclosure;

[0028] Figures 9A-9C shows an external view of a surface mount semiconductor package including a controller and a power switch according to some embodiments;

[0029] Figures 9D-9F shows an external view of a surface mount semiconductor package with high voltage pins on the right side, the surface mount semiconductor package including a controller and a power switch according to some embodiments;

[0030] Figures 9G-9I shows an external view of a surface mount semiconductor package with top side cooling that includes a controller and a power switch according to some embodiments;

[0031] Figures 10A-10C shows an external view of a through-hole semiconductor package including a controller and a power switch according to some embodiments;

[0032] Figures 10D-10F shows an external view of a through-hole semiconductor package with an encapsulated backside pad, the package including a controller and a power switch, according to some embodiments;

[0033] Figures 10G-10I shows an external view of a through-hole semiconductor package with high voltage pins on the right side, the package including a controller and a power switch, according to some embodiments;

[0034] Figures 11A-11B shows an external view of a socketed surface-mount semiconductor package including a controller and a power switch according to some embodiments;

[0035] Figures 11C-11D shows an external view of a socketed surface mount semiconductor package with high voltage pins on the right side, the package including a controller and a power switch, according to some embodiments;

[0036] Figures 12A-12B shows an external view of a through-hole semiconductor package with a socket, the package including a controller and a power switch, according to some embodiments;

[0037] Figures 12C-12D shows an external view of a socketed and backside-encapsulated through-hole semiconductor package containing a controller and a power switch according to some embodiments;

[0038] Figures 12E-12F shows an external view of a socketed through-hole semiconductor package with high voltage pins on the right side, the package including a controller and a power switch, according to some embodiments;

[0039] Figure 13AShown is an internal view of a surface mount package containing a controller and a power switch according to some embodiments. Figure 13B A schematic diagram of an integrated GaN power device including a drive circuit and a GaN switch is shown, according to some embodiments. Figure 13C Shown according to some embodiments Figure 13B Schematic diagram of the integrated GaN power device and controller. Figure 13D Shown according to some embodiments Figure 13A A bottom view of the package shown in FIG;

[0040] Figure 14 shows an internal view of a through-hole semiconductor package with a controller and a power switch according to some embodiments;

[0041] Figure 15 shows an internal view of a surface mount semiconductor package having a QR flyback controller and a power switch according to some embodiments;

[0042] Figure 16 shows an internal view of a through-hole semiconductor package with a QR flyback controller and a power switch according to some embodiments;

[0043] Figures 17A-17C shows an external view of a surface mount semiconductor package including a controller and a power switch according to certain embodiments;

[0044] Figures 18A-18B shows an external view of a socketed surface mount semiconductor package including a controller and a power switch according to some embodiments;

[0045] Figure 19 A schematic diagram illustrating a QR flyback converter using a semiconductor package to house a GaN power switch according to some embodiments is shown;

[0046] Figure 20 shows a schematic diagram of a PFC converter using a semiconductor package to house a GaN power switch according to some embodiments;

[0047] Figure 21 A schematic diagram illustrating a PFC converter using a semiconductor package to house a GaN power switch with a PFC controller according to some embodiments is shown;

[0048] Figure 22 A schematic diagram illustrating a QR flyback converter co-packaging a first semiconductor device and a second semiconductor device using an integrated GaN power device in a semiconductor package according to some embodiments;

[0049] Figure 23A schematic diagram and circuit technique illustrating the use of multi-function external terminals to determine current sense resistor values and overvoltage / undervoltage operating conditions according to some embodiments; and

[0050] Figure 24 A schematic diagram of an integrated GaN power device including a flyback controller IC and a GaN-based die is shown, according to some embodiments.

[0051] Figure 25 A schematic diagram is shown of DMAG resistor settings for R1, R2, and R3 according to some embodiments. DETAILED DESCRIPTION

[0052] The circuits, devices, and related techniques disclosed herein generally relate to power converters. More specifically, the circuits, devices, and related techniques disclosed herein relate to integrated gallium nitride (GaN) power devices, including PFC controllers, QR flyback controllers, and / or primary / secondary-side controllers for use in power converters. In some embodiments, a PFC controller circuit with reduced pin count is disclosed. The PFC controller circuits and techniques disclosed herein may include a sensing method in which the sensed voltage at the drain terminal of the PFC switch is multiplexed onto a feedback pin of the PFC controller IC, thereby reducing the pin count of the controller IC. Based on the sensed drain terminal voltage, embodiments of the present disclosure can extract information about the input voltage (Vin) of the PFC converter, the output voltage (Vout) of the PFC converter, and the zero-current instant when the PFC inductor current becomes zero. Furthermore, the disclosed multiplexing scheme can be used to sense valleys during quasi-resonant ringing. Thus, embodiments of the present disclosure can multiplex all of this functionality onto the feedback (FB) pin of the controller IC, reducing pin count and saving space.

[0053] In some embodiments, a capacitive coupling scheme can be used to sense the drain voltage of the PFC switch, where the drain voltage of the PFC switch can be transmitted and multiplexed to the feedback (FB) pin of the controller IC. In various embodiments, an inductive coupling scheme can be used, an auxiliary winding can be coupled to the boost inductor, and the auxiliary winding can be used to inject the AC signal from the boost inductor on top of the feedback (FB) pin voltage. In some embodiments, the controller IC can include various protection detection circuits to keep the power converter in its safe operating area, as summarized here and described in more detail below.

[0054] In some embodiments, a PFC controller IC can be co-packaged with a GaN power switch in a semiconductor package to form an integrated GaN power device, wherein the integrated GaN power device can reduce pin count and can be used in a PFC converter circuit. In various embodiments, the integrated GaN power device can have, for example, 5 terminals. In some embodiments, circuits and methods are disclosed for operating a PFC converter utilizing gallium nitride (GaN) and / or silicon carbide (SiC) power switches, wherein the PFC converter can have a relatively high operating frequency. In various embodiments, the controller IC can be formed from silicon, silicon carbide, GaN, or any other suitable semiconductor material. In various embodiments, the integrated GaN power device can be used in high current and / or high voltage power conversion applications, such as, but not limited to, AC to DC converters, and applications such as solar energy conversion, automotive, and battery charging applications.

[0055] In some embodiments, an integrated GaN power device may include a primary-side controller and a GaN-based main switch, wherein the integrated GaN power device may be used on the primary side of a flyback converter and / or for a quasi-resonant (QR) flyback converter. The circuits and techniques disclosed herein enable the co-packaging of a QR flyback controller IC with a GaN-based switch in a reduced-pin semiconductor package, such as, but not limited to, a DPAK-4L package. In some embodiments, the circuitry on the silicon die may be arranged to detect gate drive signals, current sensing information, temperature, and various other operating parameters, and generate protection signals for the GaN-based power switch. In addition, the silicon die may be electrically coupled to low-voltage signal pins via wire bonds and / or clips to obtain power supply, gate drive signals, current sensing information, overcurrent and overtemperature protection, enable signals, or various other signals.

[0056] In various embodiments, the integrated GaN power device may include a secondary-side controller and a synchronous rectifier GaN-based switch, wherein the integrated GaN power device may be used in the secondary side of a flyback converter and / or a quasi-resonant (QR) flyback converter. The integrated GaN power device may use a semiconductor package to co-package the GaN-based switch with the controller, wherein the package may be relatively simpler, with reduced pins and fewer external components. The thermal performance may be better than a comparable quad flat no-lead (QFN) package. In addition, the disclosed integrated GaN power device may be used in power conversion applications with a relatively wide power range. In addition, the disclosed integrated GaN power device package may be suitable for wave soldering processes.

[0057] In some embodiments, the integrated GaN power device may include current sensing and various protection features within the semiconductor package. The integrated GaN power device may reduce the size of the printed circuit board (PCB) and improve the operating efficiency of the power converter. In the current method using QFN or similar packages, external pins can be used for current sensing, gate drive, and power supply pins. In addition, external pins can be used for internal voltage regulator output and / or switching speed adjustment. Therefore, the packaging cost in the current method may be relatively high. In addition, the current method may use a reflow process, but its cost is relatively high, thereby increasing the system production cost.

[0058] In some embodiments, the semiconductor package can be a surface mount package that can include a high voltage pin, one or more low voltage pins, and a metal die pad exposed on the back of the package. The high voltage pin and the metal die pad on the back of the package can be power pins, and the low voltage pin can be a signal pin. The function of the signal pin can be, but is not limited to, power supply, gate drive, current sensing, overcurrent protection, overtemperature protection, and / or enable. In various embodiments, a minimum gap of 1 mm can be used between the high voltage pin and the adjacent low voltage pin.

[0059] In some embodiments, the disclosed semiconductor package can be a through-hole package, which can include a high-voltage power pin, a low-voltage power pin, and one or more low-voltage signal pins. The metal die pad on the back of the package can be exposed or encapsulated with an encapsulation material. In various embodiments, a gap of a minimum distance of 1 mm can be used between the high-voltage pin and the adjacent low-voltage pin. The functions of the signal pin can be, but are not limited to, power supply, gate drive, current sensing, overcurrent protection, overtemperature protection, and / or enable. In some embodiments, a slot can be added between the high-voltage pin and the low-voltage pin to increase the high-voltage creepage distance.

[0060] In various embodiments, a semiconductor package can be used to integrate one or more dies having a high voltage power switch and one or more silicon dies with control circuitry having protection features. The drain terminal of the high voltage power switch can be electrically coupled to a high voltage pin of the semiconductor package via one or more wire bonds and / or clips, and the source can be electrically coupled to a metal die pad or a low voltage pin via one or more wire bonds or clips. The silicon die can be electrically coupled to the die of the high voltage power device via wire bonds and / or clips. The circuitry on the silicon die can detect gate drive signals, current sensing information, temperature, and various other operating parameters, and generate protection signals for the high voltage power switch. In addition, the silicon die can be electrically coupled to a low voltage signal pin via wire bonds and / or clips to obtain power supply, gate drive signals, current sensing information, overcurrent and overtemperature protection, enable signals, or various other signals.

[0061] Embodiments of the present disclosure may be used for co-packaging of a high voltage power switch with a controller IC. A semiconductor package may integrate one or more dies having a high voltage power device and a silicon controller die, such as a quasi-resonant (QR) flyback converter controller IC. The drain terminal of the high voltage power switch may be electrically coupled to a high voltage pin of the semiconductor package via one or more wire bonds or clips, and the source may be electrically coupled to a metal die pad or a low voltage power pin via one or more wire bonds and / or clips. The silicon controller die may be electrically coupled to the die of the high voltage power switch via multiple wire bonds, thereby enabling sensing / detection of gate drive signals, current sense signals, temperature, and various other operating parameters. In addition, the silicon controller IC die may be electrically coupled to low voltage signal pins via wire bonds to obtain power supply, feedback signals, auxiliary winding signals, current sense, and various other signals.

[0062] In various embodiments, a semiconductor package can be used to provide a package for a GaN-based switch with a reduced number of terminals. In some embodiments, the package can include a high-voltage drain terminal, a low-voltage input signal terminal, a low-voltage current sense terminal, and a low-voltage power supply terminal. The metal die pad can be used as a source terminal.

[0063] In some embodiments, the disclosed semiconductor package can have a relatively small thickness, for example, less than 2 mm. In this way, the semiconductor package may not be the thickest component on the board and may not limit the size of the housing. Various invention embodiments are described herein, including methods, processes, systems, apparatus, and the like.

[0064] Several exemplary embodiments will now be described with respect to the accompanying drawings that form part of the embodiments. The subsequent description provides only embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the subsequent description of the embodiments will provide a description that can be implemented for those skilled in the art for implementing one or more embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the present disclosure. In the following description, for illustrative purposes, specific details are set forth in order to provide a thorough understanding of certain invention embodiments. However, it is apparent that various embodiments can be practiced without these specific details. The drawings and description are not intended to be restrictive. The word "example" or "exemplary" is used herein to mean "used as an example, instance or illustration." Any embodiment or design described herein as "exemplary" or "example" is not necessarily to be interpreted as being preferred or advantageous over other embodiments or designs.

[0065] Figure 1A Schematic diagram of a PFC converter 100 using a reduced pin count controller IC according to some embodiments is shown. Figure 1AIn the PFC converter, various currents and voltages can be sensed using an auxiliary inductor. In some embodiments, the PFC converter can be a PFC boost converter. PFC converter 100 can include a controller IC 102. Controller IC 102 can have six pins, including a Vcc pin 104, a GND pin 106, a COMP pin 108, a DRV pin 114, a CS pin 112, and an FB / ZCD / Vin pin 110. PFC converter 100 can also include a switch 116 having a drain terminal 118, a gate terminal 120, and a source terminal 122. DRV pin 114 can be coupled to gate terminal 120 and configured to provide a drive signal to the gate of switch 116 to control the conduction state of switch 116. CS pin 112 can be coupled to source terminal 122, which can be coupled to a current sense resistor 124. CS pin 112 can be configured to receive a signal corresponding to the current flowing through switch 116. The GND pin may be coupled to the ground node 126 .

[0066] Vcc pin 104 can be coupled to capacitor 128. COMP pin 108 can be coupled to compensation network 158, which can include resistor 162 coupled in series with capacitor 164, where resistor 162 and capacitor 164 are connected in series and the combination is coupled in parallel with capacitor 166. FB / ZCD / Vin pin 110 can be coupled to node 130 and can be arranged to receive a feedback signal indicating the drain voltage at drain terminal 118, a zero current detection signal indicating when the current flowing through boost inductor 142 reaches zero, and a Vin voltage indicating the input voltage at node 148. These signals are multiplexed onto FB / ZCD / Vin pin 110, thereby reducing the pin count of controller IC 102. Output terminal 146 can be connected to feedback circuit 154. In some embodiments, feedback circuit 154 can be a resistor divider including a first feedback resistor Rfb1 connected to a second feedback resistor Rfb2. Feedback circuit 154 may be used to sense voltage Vout at output terminal 146 and generate a corresponding voltage at node 130 , where the corresponding voltage at node 130 may be fed back to controller IC 102 via the FB / ZCD / Vin pin.

[0067] The PFC converter 100 may also include an auxiliary inductor 140 magnetically coupled to the boost inductor 142, wherein the auxiliary inductor 140 may be arranged to sense and generate a signal at a node 130 corresponding to the value of the Vin voltage at a node 148. The auxiliary inductor 140 may also generate a signal corresponding to the direction of current flowing through the boost inductor 142. The auxiliary inductor 140 may also sense the voltage at the drain terminal 118 and provide the sensed drain terminal voltage to the node 130. All of this information may be fed back to the controller IC 102 via the FB / ZCD / Vin pin 110.

[0068] The PFC converter 100 may further include a rectifier circuit 152. The rectifier circuit 152 may be coupled between the input AC line voltage and the node 148. The rectifier circuit 152 may be arranged to provide a filtered full-wave rectified voltage Vin between the power supply mains AC line and the node 148. The rectifier circuit 152 may provide I through the boost inductor 142, the switch 116, and the current sense resistor 124. L During operation, the switch 116 can reduce the drain terminal voltage to ground, and the boost inductor 142 can be adjusted according to I L Builds up its magnetic field and stores energy.

[0069] During operation, the AC current can generate a changing magnetic flux in the boost inductor 142, which can cause the AC voltage across the boost inductor 142 to change. During the on-time, the controller IC 102 can provide a positive drive voltage on the gate terminal 120 of the switch 116. As a result, the switch 116 can be turned on and provide a low impedance current path for the boost inductor 142. The rectifier circuit 152 can provide I through the boost inductor 142, the switch 116, and the current sense resistor 124. L In this way, the switch 116 can reduce the voltage at the drain terminal 118 to ground, and the boost inductor 142 can be switched according to I L Builds up its magnetic field and stores energy.

[0070] During the on-time, current sense resistor 124 can provide a voltage at node 170 that is proportional to the current flowing through switch 116. When controller IC 102 turns on switch 116, the drain-source voltage of switch 116 may be relatively small. The voltage on CS pin 112 may be equal to the voltage across current sense resistor 124. Internal processing circuitry of controller IC 102 may compare the voltage at CS pin 112 to an overcurrent protection threshold. If the voltage at CS pin 112 exceeds the overcurrent protection threshold, controller IC 102 may turn off switch 116.

[0071] During the off-time, the controller IC 102 may turn off the switch 116, which may provide a high impedance current path at the node 149. In response, the boost inductor 142 may resist the I L The diode 144 can be turned on and provide I L The bulk capacitor 174 may store charge to smooth the output voltage across the load and may filter high frequency voltage transitions across the load.

[0072] The FB / ZCD / Vin pin 110 can be arranged to operate as a multi-function input terminal to sense various voltages and currents, including a feedback signal indicating the drain voltage at the drain terminal 118, a zero current detection signal indicating when the current flowing through the boost inductor 142 becomes zero, and the Vin voltage indicating the input voltage at node 148. An auxiliary inductor 140 can be magnetically coupled to the boost inductor 142, wherein the auxiliary inductor 140 can be arranged to inject an AC signal on top of the voltage at FB / ZCD / Vin. The controller IC 102 can use these voltages and currents to detect a variety of conditions, including overcurrent, demagnetization phase, brownout, and overvoltage, and adjust its operation accordingly when the current flowing through the boost inductor 142 becomes zero (ZCD). Details of how the internal circuitry of the controller IC 102 extracts the various voltage and current information from the FB / ZCD / Vin pin will be referred to. Figure 2A As described in more detail, by using the FB / ZCD / Vin pins as multi-function pins (pins may also be referred to as terminals), the controller IC 102 may be implemented with a reduced number of pins. Therefore, the cost of the PFC converter 100 may be reduced.

[0073] Feedback circuit 154 can receive the output voltage Vout and provide a portion of Vout to FB / ZCD / Vin pin 110. The portion can be determined by the ratio of resistors Rfb1 and Rfb2. Controller IC 102 can use the voltage on FB / ZCD / Vin pin 110 to adjust the duty cycle of the gate drive signal at DRV pin 114. In addition, controller IC 102 can compare the voltage on FB / ZCD / Vin pin 110 to a threshold voltage. When the voltage on FB / ZCD / Vin pin 110 exceeds this threshold, controller IC 102 can detect an overvoltage condition and shut down the drive signal to gate terminal 120.

[0074] Controller IC 102 may use the signal at FB / ZCD / Vin pin 110 to regulate the duty cycle of the DRV signal at DRV pin 114. Compensation network 158 may be used to adjust the regulation bandwidth to regulate the DRV signal at DRV pin 114. In some embodiments, vL=Ldi / dt.

[0075] Figure 1B FIG1 shows a schematic diagram of an integrated GaN power device including a PFC controller IC and a GaN switch according to some embodiments. In the embodiment shown, a semiconductor package 180 can be used to integrate a GaN-based switch 184 and a silicon-based PFC controller IC 182. The silicon-based PFC controller IC 182 can be similar to Figure 1A Controller IC 102 in FIG. In some embodiments, GaN-based switch 184 can be a silicon-based switch or a silicon carbide-based switch. Semiconductor package 180 can include a source lead 181 coupled to the source terminal of GaN-based switch 184 and a drain lead 183 coupled to the drain terminal of GaN-based switch 184. PFC IC 182 can have a gate drive terminal 186 (DRV) that can be coupled to the gate terminal of GaN-based switch 184. A ground node 188 of PFC IC 182 can be coupled to the source terminal of GaN-based switch 184. Semiconductor package 180 can also include a power supply lead 190 (Vcc) coupled to a power supply terminal of the PFC controller IC. Additionally, semiconductor package 180 can include a multi-function lead 192 that can be coupled to multi-function terminals (FB / ZCD / Vin) of the PFC IC. Semiconductor package 180 can also include a lead 194 coupled to the COMP terminal of the PFC controller. The PFC controller IC may have an SNSFET terminal 196 coupled to a current sense terminal of the GaN-based switch.

[0076] The SNSFET terminal 196 of the PFC controller IC can be arranged to receive a signal from the GaN-based switch 184 indicating the magnitude and / or direction of the current flowing through the GaN-based switch 184. In some embodiments, the PFC controller IC can include a current sense (CS) pin. In various embodiments, the CS pin can be left floating, while in alternative embodiments, the CS pin can be coupled to the GaN-based switch to detect the current flowing through the GaN-based switch.

[0077] The controller IC 182 can be electrically coupled to the die of the GaN-based switch 184 via wire bonds and / or clips. Circuitry on the silicon die can detect gate drive signals, current sensing information, temperature, and various other operating parameters, and generate protection signals for the high-voltage power switch. Furthermore, the silicon die can be electrically coupled to low-voltage signal pins via wire bonds and / or clips to obtain power supply, gate drive signals, current sensing information, overcurrent and overtemperature protection, enable signals, or various other signals.

[0078] Figure 2A A schematic diagram of the internal circuitry of the controller IC 102 according to some embodiments is shown. In some embodiments, the controller IC 102 can include processing circuitry. Figure 2A Circuits and techniques are shown for extracting various information from the signal multiplexed to the FB / ZCD / Vin pin 110. Figure 2A As shown, the FB / ZCD / Vin pin 110 can be coupled to an averaging circuit 202 and to a sampling circuit 204. In some embodiments, the sampling circuit 204 can include a sample-and-hold circuit. The sampling circuit 204 and the averaging circuit 202 can both be coupled to a summing circuit 210. The output of the summing circuit 210 can be coupled to a node 212. The averaging circuit 202 can provide a voltage corresponding to the average value of the voltage on the FB / ZCD / Vin pin at a node 208. During the on-time (T-on), the sampling circuit 204 can sample the voltage at the FB / ZCD / Vin pin 110 to obtain a voltage corresponding to Vin and provide the sampled voltage value at a node 206. Subsequently, the actual value of the Vin voltage can be obtained by subtracting the sampled value at node 206 from the voltage value at node 208 using the summing circuit 210. The actual value of Vin is provided at a node 212.

[0079] Using the FB / ZCD / Vin pin 110, a zero current detection (ZCD) method can be implemented to detect the current I L When does it become zero? Figure 2AAs shown, the FB / ZCD / Vin pin can also be coupled to a delay circuit 214 and to a first input of a comparator 216. In some embodiments, the delay circuit can include a resistor 232 coupled to a capacitor 234. The output of the delay circuit 214 can be coupled to a second input of the comparator 216. The comparator 216 can have an output terminal coupled to a node 218. To determine when the boost inductor current becomes zero, the comparator 216 can be used to compare the voltage at the FB / ZCD / Vin pin 110 with a delayed version (or slowed down version) of the voltage at the FB / ZCD / Vin pin 110 to determine when the pin voltage deviates from its delayed version. The time when the comparator 216 determines that the voltage has deviated sufficiently can be used as the moment when the inductor current has reached zero or substantially zero.

[0080] The FB / ZCD / Vin pin 110 can also be used to detect overvoltage conditions on the output voltage. Figure 2A As shown, the output of averaging circuit 202 may also be coupled to comparator 240. Comparator 240 may be configured to compare the output of averaging circuit 202 with a first reference voltage and provide a soft overvoltage protection signal. The output of averaging circuit 202 may also be coupled to comparator 242. Comparator 242 may be configured to compare the output of averaging circuit 202 with a second reference voltage and provide a fast overvoltage protection signal. In some embodiments, the first and second reference voltages may have substantially the same value. The output of summing circuit 210 may be coupled to comparator 244. Comparator 244 may be configured to compare the output of the summing circuit with a third reference voltage and provide a power-down signal. In various embodiments, the third reference voltage may have the same value as the first and / or second reference voltages. FB / ZCD / Vin pin 110 may also be coupled to comparator 246. Comparator 246 may be configured to compare the voltage at FB / ZCD / Vin pin 110 with a fourth reference voltage to provide a power-down signal. A power-down condition may occur when the input voltage of the power converter drops below a predetermined threshold voltage.

[0081] The advantages of the disclosed embodiments are the absence of transients associated with RC charging. Furthermore, the disclosed embodiments enable the PFC converter to operate with reduced power losses. The voltage sampled from the auxiliary winding provides real-time information and can significantly reduce calculation errors.

[0082] Figure 2BFIG2 shows a schematic diagram of the internal circuit of the controller IC 102 according to some embodiments. In this embodiment, the controller IC 102 may include a multi-function input terminal FB / ZCD / Vin 250, a COMP input terminal 253, a CS input terminal 255, a SNSFET input terminal 259, a DRV output terminal 261, a GND terminal 265, and a V cc Terminal 267. In some embodiments, the controller IC 102 may only include the multi-function input terminal FB / ZCD / Vin 250, the COMP input terminal 253, the CS input terminal 255, the DRV output terminal 261, the GND terminal 265, and the V cc Terminal 267. In various embodiments, controller IC 102 can be used as a standalone IC with a PFC converter. In some embodiments, controller IC 102 can be formed with all input and output terminals. However, when the controller is used alone in a PFC circuit, some terminals, such as SNSFET input terminal 259, can be left floating. In some embodiments, controller IC 102 can be co-packaged with the power switch in a semiconductor package. In various embodiments, the power switch can be GaN-based, silicon-based, or silicon carbide-based. When the controller and power switch are co-packaged in a semiconductor package, the CS input terminal can be left floating. In some embodiments, whether the input and output terminals are left floating can depend on the specific application and can be changed according to user settings.

[0083] FB / ZCD / Vin input terminal 250 can be coupled to error amplifier 252, feedback (FB) generator circuit 254, Vin generator circuit 256, V out Sampler circuit 258, zero current detection (ZCD) circuit 260 and adaptive valley detection circuit 262. In some embodiments, V out Sampler circuit 258 may include a sample-and-hold circuit. COMP input terminal 253 and the output node of error amplifier 252 may be coupled to summing circuit 270. The output node of summing circuit 270 may be coupled to the input node of comparator 272. In some embodiments, comparator 272 may be an amplifier circuit. COMP input terminal 253 may also be coupled to frequency foldback circuit 274.

[0084] The output node of frequency foldback circuit 274 can be coupled to PWM logic circuit 276. The output node of comparator 272 can be coupled to PWM logic circuit 276. The output node of clock generation circuit 278 can also be coupled to PWM logic circuit 276. CS input terminal 255 and SNSFET input terminal 259 can be coupled to circuit 282 (GaNSense), where circuit 282 can be arranged to generate signals for overcurrent protection (VOCP), overstress protection (OSP), and saturation protection (SAT). These signals can be used to protect the power switch and operate it within its safe operating area (SOA). The output node of circuit 282 can be coupled to protection logic circuit 284, where the output node of protection logic circuit 284 can be coupled to PWM logic circuit 276. The output node of PWM logic circuit 276 can be coupled to driver circuit 286. The output node of driver circuit 286 can be coupled to DRV output terminal 261. DRV output terminal 261 can be coupled to the gate terminal of the power switch.

[0085] The Vin generator circuit 256 may include a delay circuit, a sampling circuit, and a summing circuit. The FB generator circuit 254 may include an averaging circuit. The averaging circuit may be used to extract Vout information. The averaging circuit may provide a signal corresponding to the average value of the voltage on the FB / ZCD / Vin input terminal 250 to the Vin generator circuit 256. During the on-time (T-on), the sampling circuit may sample the voltage at the FB / ZCD / Vin input pin 250 to obtain a voltage corresponding to Vin. Subsequently, the actual value of the Vin voltage may be obtained by subtracting the sampled value from the signal provided by the Vin generator circuit 256. The actual value of Vin is provided at the node VIN_INT.

[0086] Using the FB / ZCD / Vin input terminal 250, a zero current detection (ZCD) method can be used to detect the current I L When becomes zero.FB / ZCD / Vin input terminal 250 can also be coupled to ZCD circuit 260.ZCD circuit can include delay circuit and comparator circuit.ZCD circuit 260 can be arranged to determine when boost inductor current becomes zero.In some embodiments, ZCD circuit can be arranged to compare the voltage at FB / ZCD / Vin input terminal 250 with the delayed version (or slowed down version) of the voltage at FB / ZCD / Vin input terminal 250, to determine when input voltage and its delayed version depart from.ZCD circuit determines that the time when voltage has fully departed can be used as the moment that inductor current has reached zero or is substantially zero.

[0087] The FB / ZCD / Vin input terminal 250 can also be used to detect overvoltage conditions on the output voltage. The FB generator circuit 254 can be arranged to generate an FB_INT signal 259, which can be based on the feedback (FB) signal received at the multi-function terminal 250. The FB_INT signal 259 can be transmitted to the protection logic circuit 284 and used by the protection logic circuit 284 to generate various protections, such as overvoltage protection (soft overvoltage, fast overvoltage), brownout, and boost. The output of the protection logic circuit 284 can be transmitted to the PWM logic circuit 276 for processing and generating drive signals accordingly. The dynamic response enhancement (DRE) circuit 287 can be arranged to receive the FB_INT signal 259 (generated by the FB generator circuit), which can be based on the feedback (FB) signal received at the multi-function terminal 250. The dynamic response enhancement (DRE) circuit 287 can be arranged to generate a signal DRE 289, which can be used by the compensation circuit (COMP) to enhance the charging speed of the compensation network arranged as a compensation loop.

[0088] The PWM logic circuit 276 may be arranged to receive various signals from various circuits within the controller IC 102. The PWM logic circuit 276 may be arranged to provide a drive signal in response to receiving a first voltage representing a voltage proportional to the output voltage of the power converter circuit at the FB / ZCD / Vin input terminal 250 and in response to receiving a second voltage proportional to the current flowing through the auxiliary inductor 140.

[0089] Figure 3 shows the same diagram with some specific component values according to certain embodiments. Figure 1A In the embodiment shown, VFB_ZCD can be derived using the following equation:

[0090]

[0091] During the switching cycle, the average voltage of VFB_ZCD can be VFB, which can be used as feedback for the output voltage Vout. During the PWM on-time, by subtracting the VFB voltage from VFB_ZCD, information about the input voltage VIN can be extracted. Embodiments of the present disclosure can use the VFB voltage level and VFB_ZCD to perform valley switching.

[0092] During the off period, the VFB_ZCD voltage provides an instantaneous snapshot of the VOUT voltage, which can be sampled and extracted in the same manner as Vin. In some cases, this information can be used for another overvoltage protection scheme. This information is not delayed by the average information delay, allowing for a fast response to Vout overvoltage protection scenarios.

[0093] Figure 4 A schematic diagram of a PFC converter 400 employing a capacitive sensing scheme using a reduced pin count controller IC is shown, according to some embodiments. Figure 4 and Figure 1A Similarly, instead of using an auxiliary winding, a sense capacitor 402 may be used to sense the voltage at the drain terminal of the switch 116 and transmit the sensed voltage to the FB / ZCD / Vin pin 110. In the embodiment shown, the value of VFB_ZCD may be determined using the following equation:

[0094]

[0095] vDS AC =vDS-VIN <vDS AC >=0

[0096] vDS AC | PWMON =0-VIN=-VIN

[0097] Figure 5 The simulation results using the above equations are shown. The blue waveform shows the FB_ZCD node waveform, while the red waveform shows the voltage on the drain of switch 116. The blue waveform is marked with an average voltage by a blue dashed line centered at 2.5V. During the on-time, the green double arrow shows the decrease in the blue waveform, and the increase in the average value shows that the amplitude is proportional to Vin.

[0098] Figure 6 is a simplified flow chart illustrating a method 600 of operating a PFC converter 100 having a controller IC 102 according to some embodiments. Figure 6, method 600 includes providing a controller IC (610) having a terminal for multiplexing FB / ZCD / Vin signals. The method also includes providing an auxiliary inductor (620) magnetically coupled to a boost inductor of a PFC converter. The method further includes sensing a voltage at a drain terminal of a switch of the PFC converter using the auxiliary inductor and transmitting the sensed voltage to an FB / CD / Vin terminal (630) of the controller IC. The method also includes sensing an output voltage (Vout) of the PFC converter and transmitting the sensed voltage to an FB / ZCD / Vin terminal (640). The method also includes multiplexing the sensed output voltage and a signal from the auxiliary inductor at the FB / ZCD / Vin terminal of the controller IC (650). Furthermore, the method includes sampling the sensed signal from the auxiliary inductor using a sample-and-hold circuit (660). The method also includes averaging the sensed signal from the auxiliary inductor using an averaging circuit (670). The method further includes determining an actual value of Vin by subtracting the sampled value from the average value (680). The method further includes delaying a signal at the FB / ZCD / Vin terminal using a delay circuit and transmitting the delayed signal to a first comparator (690). The method further includes detecting the occurrence of zero current (ZCD) in the boost inductor using the first comparator and the delayed signal (692). The method further includes detecting an overvoltage condition (694) using a second comparator. The method further includes detecting a brownout condition (696) using a third comparator. The method further includes detecting a boost condition (698) using a fourth comparator.

[0099] It should be understood that Figure 6 The specific steps shown in provide a specific method of operating a PFC converter circuit with a controller IC according to an embodiment of the present disclosure. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the present disclosure may perform the steps outlined above in a different order. In addition, Figure 6 Each step shown in the foregoing may include multiple sub-steps, which may be performed in various orders depending on the needs of the individual steps. In addition, other steps may be added or deleted depending on the specific application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0100] Figure 72 and 4 , method 700 includes providing a controller IC (710) with a terminal for multiplexing FB / ZCD / Vin signals. The method also includes providing a sensing capacitor (720) coupled to a drain terminal of a PFC switch of the PFC converter. The method further includes sensing a voltage at the drain terminal of the switch of the PFC converter using the sensing capacitor and transmitting the sensed voltage to an FB / CD / Vin terminal (730) of the controller IC. The method also includes sensing an output voltage (Vout) of the PFC converter and transmitting the sensed voltage to an FB / ZCD / Vin terminal (740). The method also includes multiplexing the sensed output voltage and a signal from an auxiliary inductor at the FB / ZCD / Vin terminal of the controller IC (750). Furthermore, the method includes sampling the sensed signal from the auxiliary inductor using a sample-and-hold circuit (760). The method further includes averaging the sensed signal from the auxiliary inductor using an averaging circuit (770). The method further includes determining an actual value of Vin by subtracting the sampled value from the average value (780). The method further includes delaying the signal at the FB / ZCD / Vin terminal using a delay circuit and transmitting the delayed signal to a first comparator (790). The method further includes detecting the occurrence of zero current (ZCD) in the boost inductor using the first comparator and the delayed signal (792). The method further includes detecting an overvoltage condition using a second comparator (794). The method further includes detecting a brownout condition using a third comparator (796). The method further includes detecting a boost condition using a fourth comparator (798).

[0101] It should be understood that Figure 7 The specific steps shown in provide a specific method of operating a PFC converter circuit with a controller IC according to an embodiment of the present disclosure. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the present disclosure may perform the steps outlined above in a different order. In addition, Figure 7 Each step shown in the foregoing may include multiple sub-steps, which may be performed in various orders depending on the needs of the individual steps. In addition, other steps may be added or deleted depending on the specific application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0102] PFC controller co-packaged with the power switch

[0103] Figure 8A An integrated GaN power device 800 according to an embodiment of the present disclosure is shown. Figure 8AAs shown, the integrated GaN power device 800 can include a GaN power transistor 814 and a controller IC 812 in a semiconductor package 828. By integrating the GaN power transistor 814 and the controller IC 812 in the semiconductor package 828, the pin count can be reduced and most package parasitic elements can be eliminated, thereby allowing the integrated GaN power device 800 to be used in high current and high power applications. In addition, the integrated GaN power device in the semiconductor package saves PCB area and can save system cost. In some embodiments, the semiconductor package can be, for example, but not limited to, DPACK4.

[0104] Integrated GaN power device 800 may include a drain terminal 802, a source terminal 804, a Vcc terminal 806, a COMP terminal 808, and an FB terminal 810. In some embodiments, the ground node may be the backplate of the semiconductor package. The source terminal of GaN power transistor 814 may be coupled to the source backplate via a plurality of wire bonds 818. The drain terminal of GaN power transistor 814 may be coupled to drain terminal 802 of the semiconductor package via a plurality of wire bonds 816. The gate terminal of GaN power transistor 814 may be coupled to controller IC 812 via wire bonds 820. Wire bonds 820, 840, and intermediate wire bonds may be used to drive the gate terminal of a GaN power switch, or to drive a power-down FET that may hold the gate terminal of the GaN switch low during off-time, or to draw power from its gate terminal during the GaN switch off-time. There may also be a signal from the GaN die that provides a current signal proportional to the current in the main GaN switch to perform a "current limit" function. In various embodiments, the order and / or use of these connections can vary with the various configurations of the GaN die. The ground node of the controller IC 812 can be connected to the same L-shaped pad on the top of the package to which the source bond wire is connected. This connection can be exposed at the top right of the package.

[0105] The Vcc pin of the controller IC 812 can be coupled to the Vcc terminal 806 via wire bond 846. The COMP pin of the controller IC 812 can be coupled to the COMP terminal 808 via wire bond 844. The FB pin of the controller IC 812 can be coupled to the FB terminal 810 via wire bond 842. The ground of the controller IC 812 can be coupled to the package ground via wire bond 848. In the embodiment shown, the current sense (CS) function can be built into the integrated GaN power device 800 (with fine-tuning options), and the current sense threshold is pre-adjusted on the controller. In some embodiments, the wire bond 824 can be another connection from the GaN die to the source / GND node. In various embodiments, the wire bond 824 can be used or not, depending on the configuration of the GaN die used. In some embodiments, the wire bond 824 can be used as a ground connection for any auxiliary circuitry (e.g., the "power down" circuitry in the GaN die). In various embodiments, wire bonds 824 may not be used. In various embodiments, wire bonds may be replaced with alternative attachment techniques.

[0106] In some embodiments, the controller IC 812 can be the same as the controller IC 102 described previously. In various embodiments, the controller IC 812 can control and drive the GaN power transistor 814. In addition, the controller IC 812 can include various features for driving the GaN power transistor 814 and features for keeping the GaN power transistor 814 within its safe operating area. It will be understood by those skilled in the art that the controller IC 812 can be used to drive GaN high electron mobility transistors (HEMTs) as well as other power transistors such as, but not limited to, silicon carbide transistors, isolated gate bipolar transistors (IGBTs), and silicon MOSFETs. Figure 8B An integrated GaN power device in a four-terminal DPAK package is shown according to an embodiment of the present disclosure.

[0107] Figure 8CAn integrated GaN power device 850 according to an embodiment of the present disclosure is shown. The integrated GaN power device 850 may include a drain terminal 852, a source terminal 854, a Vcc terminal 856, a COMP terminal 858, and a FB / ZCD terminal 860. The integrated GaN power device 850 is similar to the integrated GaN power device 800, but the pin functions are different. In the integrated GaN power device 850, the controller IC and the GaN power device can be arranged at a certain angle within the semiconductor package. In this way, the connecting wire bonds can be shorter, thereby reducing parasitic inductance and capacitance that may be associated with the wire bonds. Therefore, the integrated GaN power device 850 can operate at a higher operating frequency and with relatively reduced ringing. In various embodiments, the connecting wire bonds can be replaced by other attachment techniques, such as, but not limited to, copper tape and / or copper clips.

[0108] Integrated GaN power devices

[0109] Figures 9A-9C An external view of a surface mount semiconductor package including a controller and a power switch according to some embodiments is shown. In some embodiments, the package may include one or more power switches. Figures 9A-9C The front view, side view and bottom view of the surface mount package are shown respectively. In this embodiment, pin 1 can be a high voltage pin, pins 2, 3 and 4 can be three low voltage pins, and there can be an exposed metal tube core pad 5 on the back of the package. Pin 1 and the metal pad 5 on the back can be power pins, and the low voltage pins 2, 3 and 4 can be signal pins. In some embodiments, the spacing 902 between the high voltage pin 1 and the low voltage pin 2 can be greater than, for example, 1 mm. In some embodiments, the spacing 902 can be, for example, 1.2 mm, while in other embodiments, the spacing 902 can be between 0.8 mm and 1.1 mm, and in yet other embodiments, the spacing can be between 0.9 mm and 1.05 mm. As will be understood by those of ordinary skill in the art having the benefit of this disclosure, the spacing 902 can be set to any suitable value.

[0110] Figures 9D-9F An external view of a surface mount semiconductor package with high voltage pins on the right side is shown, according to some embodiments, containing a controller and a power switch. In some embodiments, the package may contain one or more power switches.

[0111] Figures 9G-9I An external view of a surface mount semiconductor package with top side cooling that includes a controller and a power switch is shown according to some embodiments. In some embodiments, the package may include one or more power switches.

[0112] Figures 10A-10C An external view of a through-hole semiconductor package including a controller and a power switch according to some embodiments is shown. In some embodiments, the package can include one or more power switches. Figures 10A-10C The front view, side view and bottom view of the package are shown respectively. In this embodiment, pin 1 can be a high-voltage pin, and pins 2, 3 and 4 can be three low-voltage pins. There can be a metal die pad 5 on the back of the package. In some embodiments, the metal pad 5 can be exposed. In various embodiments, the metal pad 5 can be encapsulated with some encapsulation material. The high-voltage pin 1 and the low-voltage pin 2 can be power pins, and the low-voltage pins 3 and 4 can be signal pins. In some embodiments, the spacing 1002 between the high-voltage pin 1 and the low-voltage pin 2 can be greater than, for example, 1 mm. In some embodiments, the spacing 902 can be, for example, 1.2 mm, while in other embodiments, the spacing 902 can be between 0.8 mm and 1.1 mm, and in yet other embodiments, the spacing can be between 0.9 mm and 1.05 mm. As will be understood by those of ordinary skill in the art having the benefit of this disclosure, the spacing 902 can be set to any suitable value.

[0113] Figures 10D-10F An external view of a through-hole semiconductor package with encapsulated backside pads, including a controller and a power switch, is shown according to some embodiments. In some embodiments, the package can include one or more power switches.

[0114] Figures 10G-10I An external view of a through-hole semiconductor package with high voltage pins on the right side is shown, according to some embodiments, the package including a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0115] Figures 11A-11B An external view of a surface mount semiconductor package with a socket, including a controller and a power switch, is shown according to some embodiments. In some embodiments, the package may include one or more power switches. Figures 11A-11B The top and bottom views of the surface mount package with slots are shown. Figures 9A-9C The package is similar to that of , but a slot 1110 with a width a and a depth b is added between the high voltage pin 1 and the low voltage pin 2. This slot (or groove) can increase the high voltage creepage distance between the high voltage pin and the low voltage pin.

[0116] Figures 11C-11DAn external view of a surface mount semiconductor package with a slot and high voltage pins on the right side is shown, according to some embodiments, containing a controller and a power switch. In some embodiments, the package may contain one or more power switches.

[0117] Figures 12A-12B An external view of a through-hole semiconductor package with a socket, including a controller and a power switch, is shown according to some embodiments. In some embodiments, the package can include one or more power switches. Figures 12A-12B The front view and bottom view of the package are shown respectively. Figures 10A-10B The package is similar to that of , but a slot 1210 with a width a and a depth b is added between the high voltage pin 1 and the low voltage pin 2. This slot (or groove) can increase the high voltage creepage distance between the high voltage pin and the low voltage pin.

[0118] Figures 12C-12D An external view of a socketed and backside-encapsulated through-hole semiconductor package including a controller and a power switch is shown according to some embodiments. In some embodiments, the package can include one or more power switches.

[0119] Figures 12E-12F An external view of a through-hole semiconductor package with a slot having high voltage pins on the right side is shown, according to some embodiments, the package including a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0120] Figure 13AAn internal view of a surface mount package including a controller and a power switch according to some embodiments is shown. In some embodiments, the package may include one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first semiconductor device 1302 is co-packaged with a second semiconductor device 1304 having controller circuitry using a semiconductor package. In some embodiments, the first semiconductor device 1302 may include a high-voltage gallium nitride (GaN)-based switch, while the second semiconductor device 1304 may be silicon-based. In some embodiments, the controller circuitry may include a driver circuit. The controller circuitry may integrate sampling / detection and protection functions. The first semiconductor device 1302 having the GaN-based switch may be mounted on a relatively large die pad 5 using, for example, conductive adhesive. The second semiconductor device 1304 may be mounted to the die pad 5 using, for example, non-conductive adhesive or conductive adhesive. The drain terminal of the high-voltage GaN-based switch may be coupled to a high-voltage external pin 1 via one or more wire bonds 1306 or clips. The source terminal of the high voltage GaN-based switch can be coupled to pads 1308 and 1314, which can be plated on the die pad 5, via one or more wire bonds 1310 and 1312 or clips. In some embodiments, pads 1308 and 1314 can be silver plated. Low voltage external terminal 2 can be used for Vcc, low voltage external terminal 3 can be used for PWM, and low voltage external terminal 4 can be used for current sense (CS) connection.

[0121] Figure 13B A schematic diagram of an integrated GaN power device including a driver circuit and a GaN switch, according to some embodiments, is shown. In the illustrated embodiment, a semiconductor package 1380 can be used to integrate a first semiconductor device 1384 and a second semiconductor device 1382. In some embodiments, the first semiconductor device 1384 can be a GaN-based die. In various embodiments, the second semiconductor device 1382 can be a silicon-based die with a driver IC 1398. The first semiconductor device 1384 can include a first GaN-based switch 1372 having a first source, a first gate, and a first drain, and a second GaN-based switch 1374 having a second source, a second gate, and a second drain. In some embodiments, the first gate can be coupled to the second gate, and the first drain can be coupled to the second drain. In various embodiments, the first GaN-based switch can be a first transistor, and the second GaN-based switch can be a second transistor.

[0122] Semiconductor package 1380 may include an external source terminal 1381, an external drain terminal 1383, a current source (CS) terminal 1396, an external PWM terminal 1392, and an external power supply (VDD) terminal 1390. A first source may be coupled to external source terminal 1381. A first drain terminal and a second drain terminal may be coupled to external drain terminal 1383. A driver IC 1398 may have a gate drive terminal 1386 (DRV) coupled to a first gate terminal and a second gate terminal. A ground node 1388 may be coupled to external source terminal 1381. An external power supply terminal 1390 may be coupled to a power supply terminal of driver IC 1398. Driver IC 1398 may have a current sense (CS) terminal 1396 coupled to the second source. Driver IC 1398 may include overtemperature protection circuitry 1369, green mode circuitry 1367, and EMI management control circuitry 1365. In some embodiments, the ground node of the driver IC can be connected to the die pad.

[0123] The CS terminal 1396 can be arranged to receive a signal from the second GaN-based switch 1374 indicating the magnitude and / or direction of the current flowing through the first GaN-based switch 1372. In some embodiments, the driver IC 1398 can include an amplifier 1397 coupled to the CS terminal. In various embodiments, a current sensing resistor 1389 can be coupled between the input of the amplifier 1397 and ground. In some embodiments, the amplifier 1397 can be a comparator. The output of the amplifier 1397 can be coupled to a logic circuit 1399, which is arranged to control the signal entering the driver circuit 1395. The driver circuit can be coupled to the first gate and the second gate. In some embodiments, the CS amplifier 1397 can sense the current from the FET 1374 and, in response, generate a proportional amplified current that can flow out of the CS external terminal 1396.

[0124] The first semiconductor device 1384 can be coupled to the second semiconductor device 1382 via wire bonds and / or clips. In some embodiments, the circuitry on the second semiconductor device can be arranged to detect gate drive signals, current sensing information, temperature, and various other operating parameters, and generate protection signals for the high-voltage power switch. The second semiconductor device can be electrically coupled to the low-voltage signal pin via wire bonds and / or clips.

[0125] The second semiconductor device 1304 can be coupled to the first semiconductor device 1302 via one or more wire bonds 1316, 1318, and 1326 or a clip. The controller circuit on the second semiconductor device 1304 can be configured to detect current flowing through the GaN-based switch. In some embodiments, the controller circuit can be configured to detect the operating temperature or other operating parameters of the GaN-based switch. In various embodiments, the controller circuit can be configured to transmit a power supply voltage, a gate drive signal, an over-temperature protection signal, an over-current protection signal, and / or an enable signal to the GaN-based switch on the first semiconductor device 1302. The second semiconductor device 1304 can be coupled to three low-voltage external pins 2, 3, and 4 via wire bonds 1324, 1322, and 1320, respectively, or via a clip. An external power supply voltage, a gate drive signal, current sensing information, or other signals can be transmitted to the first semiconductor device 1302 via these three pins. Each of the first and second semiconductor devices 1302, 1304, and all wire bonds can be at least partially encapsulated by an electrically insulating encapsulant. In some embodiments, the backside of the die pad 5 may be exposed.

[0126] Figure 13C Shown according to some embodiments Figure 13B In the embodiment shown, the controller circuit 1363 may be arranged to send a PWM signal to the integrated GaN power device 1361.

[0127] Figure 13D Shown according to some embodiments Figure 13A Bottom view of the package shown in .

[0128] Figure 14An internal view of a through-hole semiconductor package with a controller and a power switch according to some embodiments is shown. In some embodiments, the package may include one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first die 1402 is co-packaged with a controller circuit disposed on a second die 1404 using a semiconductor package. In some embodiments, die 1402 may include a high-voltage gallium nitride (GaN)-based switch, while die 1404 may be silicon-based. The controller circuit may integrate sampling / detection and protection functions. The die 1402 with the high-voltage GaN-based switch may be attached to a relatively large die pad 5 using, for example, a conductive adhesive, and the die 1404 may be attached to the die pad 5, for example, using a non-conductive adhesive or a conductive adhesive. The drain terminal of the high-voltage GaN-based switch may be electrically coupled to the high-voltage pin 1 by one or more wire bonds 1406 or clips. The source terminal of the high-voltage GaN-based switch can be electrically coupled to silver pads 1408 and 1414 via one or more wire bonds 1410 and 1412 or a clip, which can be plated on die pad 5. In some embodiments, low-voltage power pin 2 can be directly connected to die pad 5. Die 1404 and the GaN-based switch can be electrically coupled via one or more wire bonds 1416, 1418, and 1426 or via a clip. Controller circuitry on silicon die 1404 can be arranged to sense current, temperature, or other operating parameters of the GaN-based switch via these wire bonds and transmit power supply voltage, gate drive signals, over-temperature protection signals, over-current protection signals, and / or enable signals to the GaN-based switch on die 1402. Die 1404 can be electrically coupled to two low-voltage pins 3 and 4 via wire bonds 1422 and 1420, respectively. External power supply voltage, gate drive signals, current sensing information, or other signals can be transmitted to die 1404 via these three pins. Die 1402 , die 1404 , and all wire bonds may be at least partially encapsulated with an electrically insulating encapsulant.

[0129] Figure 15An internal view of a surface-mount semiconductor package with a QR flyback controller and a power switch according to some embodiments is shown. In some embodiments, the package may include one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first die 1502 is co-packaged with a QR flyback controller circuit disposed on a second die 1504 using a semiconductor package. In some embodiments, die 1502 may include a high-voltage gallium nitride (GaN)-based switch, while die 1504 may be silicon-based. The controller circuit may integrate sampling / detection and protection functions. Die 1502 with the high-voltage GaN-based switch may be attached to a relatively large die pad 5 using, for example, conductive glue, and die 1504 may be attached to the die pad 5 using, for example, non-conductive glue or conductive glue. The drain terminal of the high-voltage GaN-based switch may be electrically coupled to the high-voltage pin 1 via one or more wire bonds 1506 or clips. The source of the GaN-based switch can be electrically coupled to a silver pad 1508, which can be plated onto the die pad 5 via one or more wire bonds 1510 or a clip. In some embodiments, die 1504 and die 1502 can be electrically coupled via several single wire bonds 1512, 1526, 1518, and 1516, or via a clip. Die 1504 can be arranged to sense current, temperature, or other operating parameters of the GaN-based switch via these wire bonds, and to transmit power supply voltage, gate drive signals, protection signals, or enable signals to the GaN-based switch. Die 1504 can be electrically coupled to three low-voltage pins 2, 3, and 4, respectively, via wire bonds 1524, 1522, and 1520, or via a clip. External power supply voltage, current sensing information, feedback signals, auxiliary winding voltage, or other signals can be transmitted to die 1504 via these three pins. Die 1502 , die 1504 , and all wire bonds may be at least partially encapsulated with an electrically insulating encapsulant.

[0130] Figure 16An internal view of a through-hole semiconductor package with a QR flyback controller and a power switch according to some embodiments is shown. In some embodiments, the package may include one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first die 1602 is co-packaged with a QR flyback controller circuit disposed on a second die 1604 using a semiconductor package. In some embodiments, die 1602 may include a high-voltage gallium nitride (GaN)-based switch, while die 1604 may be silicon-based. The controller circuit may integrate sampling / detection and protection functions. Die 1602 with the high-voltage GaN-based switch may be attached to a relatively large die pad 5 using, for example, conductive glue, and die 1604 may be attached to the die pad 5, for example, using non-conductive glue or conductive glue. The drain terminal of the high-voltage GaN-based switch may be electrically coupled to the high-voltage pin 1 via one or more wire bonds 1606 or clips. The source of the GaN-based switch can be electrically coupled to a silver pad 1608, which can be plated onto the die pad 5 via one or more wire bonds 1610 or a clip. In some embodiments, the low-voltage power pin 2 can be directly connected to the die pad 5. The die 1604 and the GaN-based switch can be electrically coupled via one or more wire bonds 1612, 1626, 1618, and 1616, or via a clip. The controller circuit on the silicon die 1604 can be arranged to detect the current, temperature, or other operating parameters of the GaN-based switch via these wire bonds and transmit a power supply voltage, gate drive signal, over-temperature protection signal, over-current protection signal, and / or enable signal to the GaN-based switch on the die 1602. The die 1604 can be electrically coupled to two low-voltage pins 3 and 4 via wire bonds 1622 and 1620, respectively. External power supply voltage, gate drive signal, current sensing information, or other signals can be transmitted to the die 1604 via these three pins. Die 1602 , die 1604 , and all wire bonds may be at least partially encapsulated with an electrically insulating encapsulant.

[0131] Figures 17A-17C An external view of a surface mount semiconductor package including a controller and a power switch according to certain embodiments is shown. In some embodiments, the package may include one or more power switches. Figures 17A-17CThe front view, side view and bottom view of the surface mount package are shown respectively. In this embodiment, pin 1 can be a high voltage pin, pins 2, 3 and 4 can be three low voltage pins, and there can be an exposed metal tube core pad 5 on the back of the package. Pin 1 and the metal pad 5 on the back can be power pins, and the low voltage pins 2, 3 and 4 can be signal pins. In some embodiments, the spacing 1702 between the high voltage pin 1 and the low voltage pin 2 can be greater than, for example, 1 mm. In some embodiments, the spacing 1702 can be, for example, 1.2 mm, while in other embodiments, the spacing 1702 can be between 0.8 mm and 1.1 mm, and in yet other embodiments, the spacing can be between 0.9 mm and 1.05 mm. As will be understood by those of ordinary skill in the art having the benefit of this disclosure, the spacing 1702 can be set to any suitable value.

[0132] Figures 18A-18B An external view of a surface mount semiconductor package with a socket that includes a controller and a power switch is shown according to some embodiments. In some embodiments, the package can include one or more power switches. Figures 18A-18B The front view and bottom view of the surface mount package are shown respectively. In the illustrated embodiment, a slot (or groove) 1810 with a width a and a depth b can be included between the high voltage pin 1 and the low voltage pin 2. In this way, the creepage distance between the high voltage pin and the low voltage pin can be increased.

[0133] Figure 19 A schematic diagram of a QR flyback converter using a semiconductor package to house a GaN power switch, according to some embodiments, is shown. In the illustrated embodiment, semiconductor package 1905 can include a GaN switch, wherein semiconductor package 1905 can have a low-voltage pin current sense (CS), an input pin that can be arranged as a pulse-width modulated (PWM) signal, a low-voltage power supply, a high-voltage drain pin, and a package backside for coupling the source terminal to ground. Furthermore, an integrated GaN device 1915 connected on the secondary side can include a GaN switch and an SR controller. The GaN switch can function as a synchronous rectifier switch on the secondary side.

[0134] Figure 20A schematic diagram of a PFC converter using a semiconductor package to house a GaN power switch, according to some embodiments, is shown. In the illustrated embodiment, semiconductor package 2005 can include a GaN switch used as a PFC switch, wherein semiconductor package 2005 can have a low-voltage pin for current sensing (CS), an input pin that can be arranged for a pulse-width modulated (PWM) signal, a low-voltage power supply, a high-voltage drain pin, and a package backside for coupling the source terminal to ground. A controller 2010, similar to controller 102, can be coupled to semiconductor package 2005, wherein controller 2010 can be arranged to control the on / off state of the GaN switch.

[0135] Figure 21 A schematic diagram of a PFC converter using a semiconductor package to house a GaN power switch with a PFC controller is shown in accordance with some embodiments. In the illustrated embodiment, semiconductor package 2120 can include a GaN switch used as a PFC switch and a PFC controller, wherein semiconductor package 2120 can have low-voltage pins VDD, COMP, and FB / VIN / ZCD (as described in the PFC controller section), a high-voltage drain pin, and a backside of the package for coupling the source terminal to ground.

[0136] QR flyback controller co-packaged with power switch

[0137] Figure 22A schematic diagram illustrates a QR flyback converter using an integrated GaN power device in a semiconductor package to co-package a first semiconductor device and a second semiconductor device, according to some embodiments. According to some embodiments, semiconductor package 2220 may include a first semiconductor device having a first GaN-based switch and a second GaN-based switch, and a second semiconductor device having a silicon-based controller IC. In QR flyback converter circuit 2200, semiconductor package 2220 may include a GaN-based die and controller circuitry. In some embodiments, the controller circuitry may include overtemperature protection circuitry, overcurrent protection circuitry, overvoltage / undervoltage protection circuitry, and GaN main switch current sensing circuitry. Semiconductor package 2220 may include a low-voltage pin 2234 labeled "VDD" for power supply, a low-voltage pin 2232 labeled "DMAG" and serving as a multi-function pin, a low-voltage pin 2240 labeled "FB" for feedback, a high-voltage drain pin 2236, and a package backside 2238 for coupling the source terminal to ground. In some embodiments, the semiconductor package 2220 may include exposed / extended thermal pads for source terminals and / or ground. The VDD pin 2234 may be used for power supply to the controller IC, the FB pin 2240 may be used for CV loop feedback through a shunt regulator, and the DMAG pin 2232 may be used for valley switching detection, indirect Vin (input voltage) and Vo (output voltage) detection and protection, and to determine the internal current sense resistor (R CS In this way, the semiconductor package 2220 can reduce the number of pins used for operation compared to using a separate controller circuit and a separate power switch, thereby achieving system savings, improving reliability, and increasing the power density of the power converter.

[0138] The circuits and techniques disclosed herein are capable of determining the value of a built-in current sensing resistor inside the semiconductor package 2220, where this value can be used to determine the magnitude and / or direction of the current flowing through the first GaN-based switch. The magnitude and / or direction of the current flow can be used to determine the appropriate gate drive for the gate terminal of the first GaN-based switch. The controller IC can have a current sense (CS) terminal that can be coupled to the second GaN-based switch. The magnitude and / or direction of the current flow sensed through the first GaN-based switch can be used to adjust the drive signal entering the gate of the first GaN-based switch and for peak current control. The controller circuit can also include a DRV terminal coupled to the gates of the first GaN-based switch and the second GaN-based switch. The gate drive voltage at the DRV terminal can be adjusted based on the sensed current of the first GaN-based switch and used to optimize the gate drive voltage through the built-in EMI control circuit system (EMI optimizer).

[0139] By co-packaging the GaN power switch with the controller IC, semiconductor package 2220 can reduce pin count and the number of external components used in the system. This reduction in external components can lower system cost and size, increase power density, and improve reliability. In some embodiments, the semiconductor package can be a DPAK 4L, which offers improved thermal performance compared to a QFN package. In various embodiments, the DPAK semiconductor package can reduce operating temperature by 5-10°C.

[0140] The QR flyback converter circuit 2200 may include a resistor 2224 and a resistor 2226 coupled between an auxiliary winding 2230 and ground 2239. The QR flyback converter circuit 2200 may also include a diode 2222 coupled to a first terminal of a resistor 2228, wherein an anode of the diode 2222 may be coupled to the auxiliary winding 2230. A second terminal of the resistor 2228 may be coupled to a node 2241. The node 2241 may be coupled to a multi-function DMAG pin 2232. The anode of the diode 2222 may be coupled to the VDD pin 2234 via a diode 2248. The resistors 2224, 2228, and the diode 2222 may increase the secondary path from the DMAG pin 2232 to the auxiliary winding 2230.

[0141] The QR flyback converter circuit 2200 can be arranged to use the DMAG pin to detect the Vin voltage. For Vin voltage detection, the voltage at the DMAG pin can be clamped to zero by the controller IC. When PWM is on, current can be forced to flow from the DMAG pin 2232 to the resistor 2228 and the resistor 2224 to detect Vin, where the magnitude of Vin can be determined by I DMAG*Z21. Z21 is the impedance of resistors 2228, 2224 and diode 2222 looking from node 2241 toward node 2258. The QR flyback converter circuit 2200 can also be arranged to detect Vout by determining the voltage at the DMAG pin (VDMAG). When the PWM is in the off state and the current discharge cycle, VDMAG can be given by Vaux*Z12 / (Z12+R2)=Vo*Na / Ns*Na / Np. Vaux is the voltage at node 2258, and Z12 is the impedance of diode 2222, resistor 2224 and resistor 2228 looking from node 2258 toward node 2241. Na is the number of turns of the auxiliary winding, and Ns is the number of turns of the secondary winding. The QR flyback converter circuit 2200 can use the detected Vin and Vout to overvoltage or undervoltage protect the power converter and turn off the GaN main switch when an overvoltage / undervoltage condition occurs. In some embodiments, the controller can force current to flow out of the DMAG pin (IDMAG) and can measure the effective impedance at the DMAG pin, Rdmag_EFF. Once Rdmag_EFF is determined, the value of the internal current sense resistor, Rcs, can be determined from a lookup table.

[0142] In some embodiments, the resistor value of the built-in current sensing resistor Rcs can be determined by using a diode 2222 and a resistor 2228 and a DMAG pin. To determine the built-in Rcs value, the value of Z21 can be determined by Z21 = (2224 / / 2226). This can be achieved by forcing the current to flow out of the DMAG pin 2232. Based on the effective resistance detected at the DMAG pin, a lookup table can be used to determine the value of Rcs based on the value of Z21. In some embodiments, the method for determining Vin may include: node 2258 = -|Vaux1|, VDMAG = 0V, and the current forced out of the DMAG pin may flow through resistor 2224. The amplitude of this current can be given by |Vaux1| / resistor 2224. This current can correspond to the Vin voltage. In various embodiments, the method for determining Vout may include: the voltage at node 2258 = +|Vaux2|, VDMAG is the resistor divider between Z12 and resistor 2226, representing the output voltage.

[0143] In some embodiments, the user can select the values of resistors 2224 and 2226 to set the threshold set point for overcurrent protection (OCP). During startup, the current source 2414 can increase the current delivered to the DMAG pin until the voltage at the comparator 2416 reaches the Vref voltage. The comparator 2416 can then transmit a signal to the Rcs determination circuit 2428. The Rcs determination circuit can receive a signal from the current source 2414 (i.e., the Rcs determination circuit can receive a signal that the comparator 2416 has tripped) and receive the voltage at the DMAG pin, and can determine the value of the equivalent parallel resistor (Z21 and / or Z12) accordingly. The Rcs determination circuit can use a lookup table to determine the value of the current sensing Rcs resistor 2424 using the determined equivalent parallel resistor value. The determined Rcs resistor value can be used in the overcurrent protection (OCP) circuit to set the threshold value of the OCP, for example, 8A. The logic circuit can then adjust the value of the Rcs resistor 2424 to an appropriate resistance value so that when the current through the GaN-based switch 2402 reaches a threshold value (e.g., 8 A), the current sense comparator trips and turns off the DRV signal. In this way, the controller 2498 can use the determined effective resistance value at the DMAG pin to fine-tune the OCP threshold.

[0144] Example (reference Figure 25 ):

[0145] DMAG resistor settings for R1, R2, and R3

[0146]

[0147] In the specific R1, N A 、N S and V O 、V DMAG In this case, R2 has a maximum limit.

[0148] V O / V DMAG Set to 6.25.

[0149] Set N S =1, consider N P =5~8,N A =1~3.5

[0150] Worst case N P =8, N A =3.5→R 2-MAX is 4.3kΩ, (R1 / / R2) MAX 4.1kQ

[0151] Therefore, 4kohm is set as the maximum limit of adjustable R1 / / R2

[0152]

[0153] At a specific V O and V DAMG R3 can be obtained under the requirements.

[0154]

[0155] In some embodiments, a method for determining the built-in value of the current sense resistor Rcs may include: 1) For each power cycle, the effective impedance Rdmag_EFF at the DMAG pin is detected once. Rdmag_EFF can be used to determine the value of the current sense resistor Rcs. Current can be forced to flow out of the DMAG pin and the voltage at node 2241 is measured. Next, the cycle-by-cycle operation can include steps 2A and 2B: 2A) When the PWM is on, the voltage at node 2241 is forced to zero, and the current is forced to flow out of the DMAG pin and measured to determine the voltage value (Vaux) at node V2258. 2B) When the PWM is off, the current is forced to flow out of the DMAG pin. The current value can be increased by known values, such as 100μA, 150μA, 200μA, 250μA, etc. When the voltage at the input is greater than the Vref value (e.g., 0.5V), the effective impedance at the DMAG pin is recorded.

[0156] In some embodiments, a secondary-side semiconductor package 2225 may be used, where the semiconductor package 2225 may include a GaN switch that functions as a synchronous rectifier switch, co-packaged with a synchronous rectifier controller circuit.

[0157] Figure 23 An alternative schematic diagram for determining the value of Rdmag_EFF according to some embodiments is shown. Figure 23 In this embodiment, the QR flyback converter may include an auxiliary winding 2330, a resistor 2324 (R1), a resistor 2326 (R2), a resistor 2328 (R3), and a diode 2322. In this embodiment, the method for determining the Rdmag_EFF value includes: 1) When the IC is powered on and before the power converter begins switching, current is forced out of the DMAG pin. Based on the effective impedance at the DMAG pin, the value of the internal Rcs is determined. The value of Rcs is maintained during power-up; 2) when the primary side is off and in reverse mode, VDMAG can sense the secondary voltage information to determine OVP.

[0158] Figure 24A schematic diagram of an integrated GaN power device including a flyback controller IC and a GaN switch, according to some embodiments, is shown. In the illustrated embodiment, a semiconductor package 2480 can be used to integrate a first semiconductor device 2484 and a second semiconductor device 2482. In some embodiments, the first semiconductor device 2484 can be a GaN-based die. In various embodiments, the second semiconductor device 2482 can be a silicon-based die with a flyback controller IC 2498. In some embodiments, the flyback controller IC can be a QR flyback controller IC. The first semiconductor device 2484 can include a first GaN-based switch 2402 having a first source, a first gate, and a first drain, and a second GaN-based switch 2404 having a second source, a second gate, and a second drain. In some embodiments, the first gate can be coupled to the second gate, and the first drain can be coupled to the second drain. In various embodiments, the first GaN-based switch can be a first transistor, and the second GaN-based switch can be a second transistor.

[0159] Semiconductor package 2480 may include an external source terminal 2481, an external drain terminal 2483, an external feedback (FB) terminal 2494, an external multi-function (DMAG) terminal 2492, and an external power supply (VDD) terminal 2490. A first source may be coupled to external source terminal 2481. A first drain and a second drain may be coupled to external drain terminal 2483. A flyback controller IC 2498 may have a gate drive terminal 2486 (DRV) that may be coupled to a first gate and a second gate. In some embodiments, electromagnetic interference (EMI) control management circuitry may be coupled to the DRV terminal. A ground node 2488 of flyback controller IC 2498 may be coupled to external source terminal 2481. An external power supply VDD terminal 2490 may be coupled to a power supply terminal of flyback controller IC 2498. A DMAG terminal 2492 may be coupled to a multi-function terminal of flyback controller IC 2498. The flyback controller IC 2498 may have a current sense (CS) terminal 2496 coupled to the second source.

[0160] The CS terminal 2496 can be arranged to receive a signal from the second GaN-based switch 2404 indicating the magnitude and / or direction of the current flowing through the first GaN-based switch 2402. In some embodiments, the flyback controller IC 2498 can include an amplifier 2422 coupled to the CS terminal 2496 and a resistor 2420 coupled to the CS terminal 2496. In some embodiments, the amplifier 2422 can be a comparator. The amplifier 2422 can generate a current at its output. The output of the amplifier 2422 can be coupled to a current sense resistor 2424 (Rcs).

[0161] The value of the current sense resistor 2424 (Rcs) can be determined by the Rcs determination circuit 2428 based on the effective impedance at the DMAG pin. The determined value of the current sense resistor 2424 (Rcs) can be used to determine the value of the magnitude of the current flowing through the switch 2402. The PWM control circuit 2426 can transmit a PWM signal to the driver circuit 2408 based on the magnitude of the current flowing through the switch 2402. In some embodiments, the direction of the current flowing through the switch 2402 can be determined. The PWM control circuit 2426 can transmit the PWM signal based on at least the magnitude or direction of the current flowing through the switch 2402. The flyback controller 2498 can also include a Vin / Vout detection circuit 2430. The flyback controller 2498 can also include the driver circuit 2408 coupled to the first gate and the second gate. The flyback controller 2498 can include a current source 2414 coupled to the DMAG terminal 2492. In some embodiments, the PWM control circuit 2426 may include an overcurrent protection circuit, an EMI optimizer circuit, and an overvoltage / undervoltage protection circuit.

[0162] The flyback controller 2498 may also include a comparator 2416 having a first terminal coupled to the DMAG terminal 2492 and a second terminal coupled to a reference voltage Vref 2418. In some embodiments, the value of the reference voltage may be, for example, 0.5V. The current flowing through the current source 2414 may be forced to flow out of the DMAG pin, and the voltage at the DMAG pin may be compared to Vref. In some embodiments, the current source 2414 may include multiple individual current sources having values, for example, 100μA, 50μA, 200μA, 250μA. Each current source may be forced to flow out of the DMAG pin until the voltage on the DMAG pin is greater than Vref. When the comparator 2416 trips, a corresponding signal may be transmitted to the Rcs determination circuit 2428. Based on the transmitted signal, a lookup table may be used to select the value of the current sense resistor 2424.

[0163] The first semiconductor device 2484 can be coupled to the second semiconductor device 2482 via wire bonds and / or clips. In some embodiments, the circuitry on the second semiconductor device can be arranged to detect gate drive signals, current sensing information, temperature, and various other operating parameters, and generate protection signals for the high-voltage power switch, such as overcurrent protection, overvoltage / undervoltage protection signals, and overtemperature protection signals. The second semiconductor device can be electrically coupled to the low-voltage signal pin via wire bonds and / or clips.

[0164] In some embodiments, a combination of the circuits, packages, and methods disclosed herein can be utilized to provide a power factor correction controller IC, a QR flyback controller IC, and an integrated GaN power device. Although the circuits and methods are described and illustrated herein with respect to several specific configurations of PFC converter circuits and QR flyback converter circuits, as well as specific semiconductor packages, embodiments of the present disclosure are also applicable to other power converter topologies, such as, but not limited to, power converters, such as, but not limited to, AHB converters utilizing silicon power switches, GaN power switches, or silicon carbide power switches. Furthermore, embodiments of the present disclosure are applicable to other semiconductor packages, such as, but not limited to, flat no-lead packages, and the like.

[0165] In the foregoing description, embodiments of the present disclosure have been described with reference to numerous specific details that may vary in different implementations. Accordingly, the description and drawings should be regarded as illustrative rather than restrictive. The sole and exclusive indication of the scope of the present disclosure, and what the applicants intend as the scope of the present disclosure, is the literal and equivalent scope of the claims published in this application, in the specific form in which such claims are published, including any subsequent amendments. The specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of the present disclosure.

[0166] In addition, spatially relative terms, such as "bottom" or "top", etc., may be used to describe the relationship of one element and / or feature to another element and / or feature, for example, as shown in the figures. It should be understood that spatially relative terms are intended to cover different orientations of the device in use and / or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is turned over, the element described as the "bottom" surface can then be oriented "above" other elements or features. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein can be interpreted accordingly.

[0167] As used herein, the terms "and", "or" and "and / or" may have multiple meanings, which are also expected to depend at least in part on the context in which the terms are used. Generally, "or", if used in an associative list (such as A, B or C), is intended to mean A, B and C (used herein in an inclusive sense) as well as A, B or C (used herein in an exclusive sense). In addition, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular, or may be used to describe some combination of features, structures or characteristics. However, it should be noted that this is merely an illustrative example and the claimed subject matter is not limited to the examples. In addition, the term "at least one of", if used in an associative list (e.g., A, B or C), may be interpreted to mean any combination of A, B and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0168] References throughout this specification to "one example," "an example," "some examples," or "example implementations" mean that a particular feature, structure, or characteristic described in connection with a feature and / or example can be included in at least one feature and / or example of the claimed subject matter. Thus, appearances of the phrases "in one example," "an example," "in some examples," "in some implementations," or other similar phrases throughout this specification are not necessarily all referring to the same feature, example, and / or limitation. Furthermore, particular features, structures, or characteristics may be combined into one or more examples and / or features.

[0169] In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will appreciate that the claimed subject matter may be practiced without these specific details. In other instances, methods and apparatus known to those skilled in the art have not been described in detail in order to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the specific examples disclosed, but that such claimed subject matter may also encompass all aspects falling within the scope of the appended claims and their equivalents.

[0170] In some embodiments, the electronic system may include the following:

[0171] 1. An electronic component comprising:

[0172] base;

[0173] a first semiconductor device attached to the base and comprising:

[0174] a first gallium nitride (GaN) based switch having a first gate, a first source, and a first drain, wherein the first gate is arranged to control current flow between the first source and the first drain;

[0175] a second GaN-based switch having a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate and the second drain is coupled to the first drain;

[0176] a second semiconductor device attached to the base and comprising:

[0177] a driving circuit coupled to the first gate and the second gate, the driving circuit being arranged to control on and off states of the first GaN-based switch and the second GaN-based switch;

[0178] Logic circuits, which are arranged as:

[0179] detecting a magnitude of the current flow via a first signal received from the second source; and

[0180] When the detected magnitude of the current flow exceeds a threshold current value, controlling the driving circuit to turn off the first GaN-based switch and the second GaN-based switch; and

[0181] An electrically insulating encapsulation at least partially encapsulates the base, the first semiconductor device, and the second semiconductor device.

[0182] 2. The electronic component according to technical solution 1, wherein the logic circuit is coupled to an external circuit, and wherein the threshold current value is at least partially determined by the external circuit.

[0183] 3. The electronic component of claim 2 , wherein the external circuit comprises a resistor, and wherein the threshold current value is based at least in part on a resistance of the resistor.

[0184] 4. The electronic component according to technical solution 1, wherein the logic circuit includes an adjustable resistor, and the threshold current value is at least partially based on the resistance of the adjustable resistor.

[0185] 5. The electronic component according to technical solution 1 further includes a sensing resistor coupled to the second source, wherein a voltage at the sensing resistor corresponds to the first signal.

[0186] 6. The electronic component according to technical solution 5, wherein the sensing resistor is provided on the second semiconductor device.

[0187] 7. The electronic component according to technical solution 1, wherein a driver synchronously controls the on and off states of the first GaN-based switch and the second GaN-based switch.

[0188] 8. An electronic component comprising:

[0189] A first semiconductor device comprising:

[0190] a first gallium nitride (GaN) based switch having a first gate, a first source, and a first drain, wherein the first gate is arranged to control current flow between the first source and the first drain;

[0191] a second GaN-based switch having a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate and the second drain is coupled to the first drain;

[0192] A second semiconductor device comprising:

[0193] a driving circuit coupled to the first gate and the second gate, the driving circuit being arranged to control on and off states of the first GaN-based switch and the second GaN-based switch;

[0194] Logic circuits, which are arranged as:

[0195] detecting a magnitude of the current flow via a first signal received from the second source; and

[0196] When the detected magnitude of the current flow exceeds a threshold current value, controlling the driving circuit to turn off the first GaN-based switch and the second GaN-based switch; and

[0197] an electrically insulating encapsulation at least partially encapsulating the first semiconductor device and the second semiconductor device;

[0198] a first external terminal disposed at an outer surface of the electronic component and coupled to the first drain; and

[0199] A second external terminal is disposed at the outer surface of the electronic component and is coupled to the first source.

[0200] 9. The electronic component according to technical solution 8, wherein the logic circuit is coupled to an external circuit via a third external terminal, and wherein the threshold current value is at least partially determined by the external circuit.

[0201] 10. The electronic component of claim 9, wherein the external circuit comprises a resistor, and wherein the threshold current value is based at least in part on a resistance of the resistor.

[0202] 11. The electronic component according to technical solution 9, wherein the first external terminal is coupled to a primary winding of a transformer, and wherein the third external terminal is coupled to a secondary winding of the transformer.

[0203] 12. The electronic component according to technical solution 11, wherein the logic circuit detects the input voltage at the primary winding of the transformer via the third external terminal.

[0204] 13. The electronic component according to technical solution 11, wherein the secondary winding is a first secondary winding, and wherein the logic circuit detects the output voltage at the second secondary winding of the transformer via the third external terminal.

[0205] 14. The electronic component according to technical solution 8, wherein the logic circuit includes an adjustable resistor, and wherein the logic circuit controls the drive circuit to turn off the first GaN-based switch and the second GaN-based switch at least in part based on the resistance of the adjustable resistor.

[0206] 15. The electronic component according to technical solution 8 further includes a sensing resistor coupled to the second source, and wherein the logic circuit detects the magnitude of the current flow via a voltage at the sensing resistor.

[0207] 16. The electronic component according to technical solution 15, wherein the sensing resistor is provided on the second semiconductor device.

[0208] 17. A method of operating an electronic component, the method comprising:

[0209] sensing an external circuit at a first external terminal, wherein the first external terminal is located at an external surface of the electronic component;

[0210] adjusting a value of a variable resistor in response to said sensing said external circuit, wherein said variable resistor is disposed within said electronic component;

[0211] conducting current between a second external terminal and a third external terminal via a first gallium nitride (GaN)-based transistor, wherein the first GaN-based transistor is disposed within the electronic component and the second and third external terminals are located at the outer surface of the electronic component;

[0212] sensing the conduction current via a second GaN-based transistor disposed within the electronic component; and

[0213] The first GaN-based transistor is turned into an off state based on at least the value of the variable resistor and the sensed conduction current.

[0214] 18. The method according to technical solution 17, wherein the external circuit includes a resistor, and wherein the sensing includes sensing the resistance value of the resistor.

[0215] 19. A method according to technical solution 17, wherein the first GaN-based switch includes a first gate, a first source and a first drain, and wherein the second GaN-based switch includes a second source, a second gate and a second drain, and wherein the second gate is coupled to the first gate and the second drain is coupled to the first drain.

[0216] 20. The method according to technical solution 17 also includes sensing the voltage of the transformer winding via the first external terminal.

[0217] 21. A power converter circuit comprising:

[0218] A power factor controller comprising:

[0219] an input terminal arranged to detect a first voltage representative of an output voltage of the power converter circuit and to detect a second voltage proportional to an input voltage of the power converter circuit;

[0220] a drive terminal for transmitting a drive signal to a gate of the switch;

[0221] a logic circuit arranged to add the first voltage and the second voltage to generate a first signal during an on-time of the power converter circuit;

[0222] a delay circuit arranged to generate a zero current detection (ZCD) signal based on the first voltage and the second voltage at the input terminal; and

[0223] A controller circuit is arranged to generate the drive signal in response to the first signal and the ZCD signal.

[0224] 22. A power converter circuit according to technical solution 21, wherein the second voltage is detected by determining a voltage drop across a first transformer winding, wherein the first transformer winding is magnetically coupled to a second transformer winding and the second transformer winding is coupled to an input node of the power converter circuit.

[0225] 23. The power converter circuit according to technical solution 22, wherein the power factor controller further comprises a power-off protection circuit, and the power-off protection circuit is arranged to generate a power-off signal using the first signal.

[0226] 24. The power converter circuit according to technical solution 23, wherein the power factor controller further comprises an overvoltage protection circuit, and the overvoltage protection circuit is arranged to generate an overvoltage signal using an average value of the first voltage.

[0227] 25. A method of operating a power converter circuit, the method comprising:

[0228] providing a power factor controller having an input terminal, a drive terminal, a logic circuit, a delay circuit, and a controller circuit, wherein the drive terminal is arranged to transmit a drive signal to a gate of a switch;

[0229] detecting a first voltage at the input terminal that is representative of an output voltage of the power converter circuit;

[0230] detecting a second voltage at the input terminal that is proportional to an input voltage of the power converter circuit;

[0231] generating a first signal by summing, by the logic circuit, the first voltage and the second voltage during an on-time of the power converter circuit;

[0232] generating, by the delay circuit, a zero current detection (ZCD) signal based on the first voltage and the second voltage at the input terminal; and

[0233] The drive signal is generated by the controller circuit in response to the first signal and the ZCD signal.

Claims

1. An electronic component comprising: base; a ground terminal, a drain terminal, an input terminal, a power supply terminal, and a current sensing terminal at an outer surface of the electronic component; a first semiconductor device attached to the base and comprising a gate, a source, and a drain, the first semiconductor device being arranged to conduct current between the source and the drain, wherein the source is coupled to the ground terminal, and wherein the drain is coupled to the drain terminal; a second semiconductor device attached to the base and arranged to receive power from the power supply terminal, the second semiconductor device comprising: a logic circuit arranged to detect the magnitude of the current and generate a signal at the current sense terminal that is proportional to the current; a drive circuit arranged to control the current in dependence on an input signal at the input terminal; as well as An electrically insulating encapsulation at least partially encapsulates the base, the first semiconductor device, and the second semiconductor device. 2 . The electronic component according to claim 1 , wherein the electronic component comprises only the ground terminal, the drain terminal, the input terminal, the power supply terminal, and the current sensing terminal. 3 . The electronic assembly of claim 1 , wherein the logic circuit is arranged to disable the driver circuit in response to the current exceeding a predetermined threshold. 4 . The electronic component of claim 1 , wherein the logic circuit is arranged to disable the driver circuit in response to a temperature of the first semiconductor device exceeding a predetermined temperature. The electronic component of claim 1 , wherein the input signal is a pulse width modulated (PWM) signal. 6 . The electronic component of claim 1 , wherein a spacing between the drain terminal and the input terminal is greater than a spacing between the input terminal and the current sensing terminal. The electronic component according to claim 1 , wherein the ground terminal is located at an outer surface of the base.

8. The electronic assembly of claim 3, wherein the logic circuit is coupled to external circuitry, and wherein the predetermined threshold is determined at least in part by the external circuitry.

9. The electronic assembly of claim 8, wherein the external circuit includes a resistor, and wherein the threshold current is based at least in part on a resistance of the resistor.

10. The electronic assembly of claim 1, wherein the drain terminal is coupled to a primary winding of a transformer.

11. The electronic component of claim 1, wherein the first semiconductor device is formed on a gallium nitride (GaN) substrate.

12. An electronic assembly comprising: a ground terminal, a drain terminal, an input terminal, and a current sensing terminal at an outer surface of the electronic component; a power circuit arranged to conduct current between the ground terminal and the drain terminal; a logic circuit arranged to detect the magnitude of the current and generate a signal at the current sense terminal that is proportional to the current; as well as A drive circuit is arranged to control the current in dependence on an input signal at the input terminal. 13 . The electronic assembly of claim 12 , further comprising a power supply terminal coupled to the logic circuit and the drive circuit, the power supply terminal being arranged to receive power.

14. The electronic assembly of claim 12, wherein the logic circuit is arranged to disable the driver circuit in response to the current exceeding a predetermined threshold.

15. The electronic assembly of claim 12, wherein the logic circuit is arranged to disable the driver circuit in response to a temperature of the power circuit exceeding a predetermined temperature.

16. The electronic component of claim 12, wherein the input signal is a pulse width modulated (PWM) signal. 17 . The electronic component of claim 12 , wherein a spacing between the drain terminal and the input terminal is greater than a spacing between the input terminal and the current sensing terminal.

18. The electronic component of claim 12, wherein at least a portion of the power circuit is formed on a gallium nitride (GaN) substrate.

19. The electronic assembly of claim 14, wherein the logic circuit is coupled to external circuitry, and wherein the predetermined threshold is determined at least in part by the external circuitry.

20. The electronic assembly of claim 19, wherein the external circuit comprises a resistor, and wherein the threshold current is based at least in part on a resistance of the resistor.

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