A dual-core lockstep processor instruction fetch control system supporting extended instructions

Abstract

The present invention provides an instruction fetch control system for a dual-core lockstep processor supporting extended instructions, comprising an instruction fetch module, an instruction cache, a branch prediction module, a lockstep comparison module, and a dual-core lockstep processor. The present invention implements fine-grained control of the lockstep protection mode of different user codes through lockstep extended instructions. Lockstep extended instructions use a decoding path different from conventional instructions, directly entering the lockstep extended instruction decoding logic after instruction fetching, without relying on resource scheduling of the lockstep processor's subsequent stages or a specific instruction set. Branch prediction faults are treated as a type of branch prediction failure and processed in the instruction fetch module to ensure that branch prediction faults do not contaminate the dual-core lockstep processor's subsequent stages. For subsequent stage faults in the dual-core lockstep processor, the instruction fetch module can widen the pulse width of the subsequent stage fault signal to the difference value of the dual-core instruction cycles, and align the instruction streams in the check core and the execution core by inserting no-operations into the pipeline.

Description

Technical Field

[0001] The present invention relates to the technical field of dual-core lockstep technology, and more particularly to an instruction fetch control system for a dual-core lockstep processor supporting extended instructions. Background Art

[0002] In high-reliability processing systems, dual-core lockstep technology is a widely used hardware redundancy fault-tolerance mechanism. The key to dual-core lockstep technology is that two identical processor cores synchronously execute the same instruction stream, comparing the output results in real time to detect faults. Dual-core lockstep processors adhere to a strict synchronization mechanism: the check core and execution core share the same input data, retrieve instructions from the same instruction cache, and execute identical operations on every clock cycle. The output results of the check core and execution core are checked for consistency cycle by cycle using a comparator. If a discrepancy is detected, the system triggers a lockstep fault and takes appropriate action. Delayed lockstep technology introduces a time offset mechanism that delays the check core and execution core by a fixed period, effectively reducing the probability of common-mode interference affecting both the check core and execution core simultaneously.

[0003] However, traditional dual-core lockstep processors with delayed lockstep capabilities lack instruction stream alignment, making it impossible to enable or disable lockstep in real time during execution, and unable to provide fine-grained control over the protection mode of user code through special extended instructions. Furthermore, traditional lockstep processors do not distinguish between faults in the front-end and back-end stages of the processor, resulting in frequent unnecessary field recovery and reduced real-time performance of the system. Summary of the Invention

[0004] In order to solve the problems that traditional lock-step processors cannot dynamically turn on or off the system's lock-step comparison function with low overhead and cannot perform fine-grained control of the protection mode of user code through extended instructions, the present invention proposes a dual-core lock-step processor instruction fetch control system that supports extended instructions. By introducing a heterogeneous decoding path for lock-step extended instructions, the invention allows user code to dynamically switch lock-step modes during operation and supports the configuration of protection strategies for critical code segments and non-critical code segments respectively.

[0005] The present invention provides a dual-core lockstep processor instruction fetch control system supporting extended instructions, comprising an instruction fetch module, an instruction cache, a branch prediction module, a lockstep comparison module and a dual-core lockstep processor, wherein the dual-core lockstep processor comprises a check core and an execution core;

[0006] The instruction fetch module is configured to generate a read cache control signal based on the instruction fetch address of the check core, read at least one instruction from the instruction cache based on the read cache control signal, determine the type of each instruction, and if it is a lockstep extension instruction, generate a lockstep activation signal and transmit it to the lockstep comparison module to turn the lockstep comparison module on or off; if it is a regular instruction, generate a check core instruction and an execution core instruction based on the regular instruction, and output them to the check core and the execution core respectively; and transmit a branch instruction prediction failure signal and a re-fetch address to the branch prediction module;

[0007] The execution core is configured to process the execution core instruction, obtain an execution core processing result, and transmit the execution core processing result to the verification core;

[0008] The check core is used to process the check core instruction to obtain a check core processing result, compare the check core processing result with the execution core processing result, generate a subsequent fault signal and a pipeline flush signal according to the comparison result, and transmit them to the branch prediction module;

[0009] The branch prediction module is configured to generate a verification core instruction fetch address and an execution core instruction fetch address according to the subsequent fault signal, the pipeline flush signal, the system reset address, the branch instruction prediction failure signal, and the re-fetch address, respectively, input the verification core instruction fetch address to the lockstep comparison module and the instruction fetch module, respectively, and input the execution core instruction fetch address to the lockstep comparison module;

[0010] The lockstep comparison module is used to compare the instruction fetch address of the verification core with the instruction fetch address of the execution core, generate a branch prediction fault signal according to the comparison result, and input the signal to the instruction fetch module.

[0011] The present invention provides an instruction fetch control system for a dual-core lockstep processor supporting extended instructions, which implements fine-grained control of the lockstep protection modes of different user codes through lockstep extended instructions. The lockstep extended instructions adopt a decoding path different from that of conventional instructions, and directly enter the lockstep extended instruction decoding logic after instruction fetching, without relying on resource scheduling of the subsequent stages of the lockstep processor, nor on a specific instruction set. Branch prediction faults are regarded as a type of branch prediction failure and are processed in the instruction fetch module to ensure that the branch prediction faults do not contaminate the subsequent stages of the dual-core lockstep processor. For subsequent stage faults of the dual-core lockstep processor, the instruction fetch module can widen the pulse width of the subsequent stage fault signal to the difference value of the dual-core instruction cycles, and align the instruction streams in the check core and the execution core by inserting no-operations into the pipeline. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A structural block diagram of an instruction fetch control system for a dual-core lockstep processor supporting extended instructions provided by the present invention;

[0013] Figure 2 Schematic diagram of the internal structure of the branch prediction module;

[0014] Figure 3 A schematic diagram of the internal structure of the instruction fetch module. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0016] Figure 1 The present invention provides a dual-core lockstep processor instruction fetch control system supporting extended instructions, such as Figure 1 As shown, the instruction fetch control system includes an instruction fetch module, an instruction cache, a branch prediction module, a lockstep comparison module and a dual-core lockstep processor. The dual-core lockstep processor includes a check core and an execution core, and the check core and the execution core serve as the post-stage modules of the instruction fetch controller module.

[0017] in, Figure 1 The instruction cache, execution core and check core are necessary modules to support the normal operation of the instruction fetch control system proposed in the present invention. The instruction cache stores the instructions to be executed by the dual-core lockstep processor. The input of the instruction cache is the read cache control signal output by the instruction fetch module, and the output of the instruction cache is the cache line storing the instructions. The instructions in the instruction cache are shared by the check core and the execution core of the dual-core lockstep processor. The read cache control signal is generated by the instruction fetch module. The instruction cache temporarily stores the instructions to be executed by the check core and the execution core. The check core and the execution core are respectively the back-end modules of the instruction fetch control system of the dual-core lockstep processor, responsible for receiving the check core instructions and the execution core instructions output by the instruction fetch module, independently completing instruction execution, comparing instruction execution results, and providing back-end fault signals and pipeline flush signals to the branch prediction module.

[0018] The working process of each module in the instruction fetch control system is as follows:

[0019] The instruction fetch module is configured to generate a read cache control signal based on the check core instruction fetch address output by the branch prediction module. Based on the read cache control signal, it reads multiple instructions from the instruction cache and determines the type of each instruction. If the instruction is a lockstep extension instruction, it generates a lockstep activation signal and transmits it to the lockstep comparison module to enable or disable the lockstep comparison module. If the instruction is a regular instruction, it generates a check core instruction and an execution core instruction based on the regular instruction, and outputs them to the check core and execution core of the dual-core lockstep processor, respectively. The instruction fetch module also transmits a branch instruction prediction failure signal and a re-fetch address to the branch prediction module. The branch instruction prediction failure signal is generated by first preliminarily estimating whether the instruction is a branch instruction (branch instructions are a type of regular instruction) based on the check core instruction fetch address. The instruction fetch module then fetches the corresponding instruction from the instruction cache based on the check core instruction fetch address. Based on the fetched instruction, the instruction fetch module accurately determines whether the instruction is a branch instruction. If the preliminarily estimated result is inconsistent with the subsequent determination result, indicating a branch instruction prediction failure, the instruction fetch module outputs a branch instruction prediction failure signal to the branch prediction module. The re-fetch address is calculated based on the checksum core instruction address when the instruction fetch module detects a branch instruction prediction failure signal.

[0020] The execution core is used to process the execution core instruction, obtain the execution core processing result, and send the execution core processing result to the verification core.

[0021] The check core is configured to process the check core instruction to obtain a check core processing result, compare the check core processing result with the execution core processing result, and generate a subsequent stage fault signal and a pipeline flush signal based on the comparison result, and transmit the signals to the branch prediction module. When the check core processing result is inconsistent with the execution core processing result, the check core outputs a subsequent stage fault signal, and when a branch prediction fails, the check core outputs a pipeline flush signal to the branch prediction module.

[0022] The branch prediction module is used to generate a verification core instruction fetch address and an execution core instruction fetch address according to the subsequent fault signal, the pipeline flush signal, the system reset address, the branch instruction prediction failure signal and the re-fetch address, respectively, input the verification core instruction fetch address to the lockstep comparison module and the instruction fetch module respectively, and input the execution core instruction fetch address to the lockstep comparison module.

[0023] The lockstep comparison module is configured to, when enabled (determined by a lockstep activation signal input from the instruction fetch module), compare the instruction fetch address of the verification core with the instruction fetch address of the execution core, and generate a branch prediction failure signal based on the comparison result for input to the instruction fetch module. When the instruction fetch address of the verification core and the instruction fetch address of the execution core are inconsistent, the branch prediction failure signal is output to the instruction fetch module.

[0024] In the present invention, the front stage of the instruction fetch control system only compares the instruction fetch address, and the verification core instructions and execution core instructions read out from the instruction cache are compared in the back stage of the dual-core lockstep processor, thereby distinguishing the front stage faults from the back stage faults, avoiding frequent unnecessary on-site recovery, and thus improving the real-time performance of the system operation.

[0025] See also Figure 2 The instruction fetch module includes an instruction fetch and alignment processing unit, an instruction pre-decoding unit, a first OR gate, a first selector, a first bypass buffer, an instruction queue, a second OR gate, a first NOR gate, a pulse stretching unit, a second selector and a second bypass buffer.

[0026] Among them, the instruction fetch module is responsible for reading the instruction cache, processing cross-cache line instructions and extracting compressed instructions in the cache line, pre-decoding conventional instructions and lockstep extension instructions, and aligning the instruction streams in the check core and the execution core when a post-stage fault or system reset occurs. The instruction fetch module adopts a hybrid storage-heterogeneous decoding architecture, which can reduce the dependence of the lockstep extension instructions on a specific instruction set. During the code compilation stage, the lockstep extension instructions and conventional instructions follow a unified memory mapping mechanism, and are linked by the linker to generate a single executable file, sharing the code storage area and address space. During the code execution stage, the decoding path of the lockstep extension instructions is different from that of the conventional instructions. The lockstep extension instructions directly enter the instruction pre-decoding unit after the instruction alignment processing, and degenerate into a no-operation instruction (NOP, a type of conventional instruction) after the pre-decoding operation is completed and enter the first bypass buffer. The functions of each sub-module in the instruction fetch module are as follows:

[0027] The instruction fetch and alignment processing unit converts the parity core instruction fetch address output by the branch prediction module into a read cache control signal, reads an instruction cache line from the instruction cache according to the read cache control signal, extracts compressed instructions in the instruction cache line according to the instruction opcode, and extracts a corresponding number of instructions from the instruction cache line according to the instruction issue width of the dual-core lockstep processor (in one embodiment of the present invention, the instruction issue width of the lockstep processor is set to 2), aligns all the fetched instructions, and outputs them to the instruction pre-decoding unit; outputs the fetched instructions to the input end of the first selector; and, when the instruction pre-decoding unit detects a branch instruction prediction failure signal, uses the parity core instruction fetch address when no branch instruction prediction failure was detected last time as a re-fetch address, and outputs the re-fetch address to the branch prediction module;

[0028] The instruction pre-decoding unit receives the aligned instruction input by the instruction extraction and alignment processing unit, determines whether the current instruction is a lockstep extension instruction, and if so, generates a lockstep activation signal based on the lockstep extension instruction and outputs it to the lockstep comparison module, and inputs a lockstep extension instruction or branch instruction prediction failure signal into one input end of the first OR gate; if the current instruction is a regular instruction, determines whether the current regular instruction is a branch instruction, and compares the judgment result with the branch instruction result estimated based on the verification and fetch instruction address. If they are inconsistent, outputs a branch instruction prediction failure signal to the branch prediction module. The instruction pre-decoding unit is also used to input the lockstep extension instruction or the branch instruction prediction failure signal into one input end of the first OR gate, and the other input end of the first OR gate is the branch prediction fault signal of the lockstep comparison module.

[0029] Among them, the input signal of the first OR gate is the branch prediction fault signal, the branch instruction prediction failure signal and the lockstep extension instruction identification signal. When any one of the branch prediction fault signal, the branch instruction prediction failure signal or the lockstep extension instruction identification signal is valid, the output of the first OR gate is valid.

[0030] The output signal of the first OR gate serves as the selection end signal of the first selector. The input end of the first selector is a no-operation instruction NOP and an instruction output by the instruction fetch and alignment processing unit. When the selection end signal of the first selector is valid, the output of the first selector is a no-operation instruction; when the selection end signal of the first selector is invalid, the output of the first selector is an instruction output by the instruction fetch and alignment processing unit. The output instructions of the first selector are respectively output to the instruction queue and the first bypass buffer.

[0031] The first bypass buffer is used to buffer the input instructions and then output the verification core instructions to the verification core.

[0032] The two input signals of the second OR gate are the post-stage fault signal output by the check core and the external system reset signal. The output signal of the second OR gate serves as an input terminal signal of the first NOR gate and the input signal of the pulse stretching unit respectively. The other input terminal signal of the first NOR gate is the pipeline flush signal output by the check core. The output signal of the first NOR gate is used to invalidate the instruction entry in the instruction queue.

[0033] The instruction queue temporarily stores instruction entries to be executed by the execution core. An instruction entry consists of an instruction and an instruction valid flag. The instruction valid flag in an instruction entry is set to a valid state when the instruction enters the instruction queue. If a subsequent module of the dual-core lockstep processor fails, a pipeline flush occurs, or the system is reset, the instruction entry in the instruction queue will be set to an invalid state. Instruction entries marked as invalid will not be processed by the subsequent lockstep comparison module of the dual-core lockstep processor (in one embodiment of the present invention, the number of instruction entries in the instruction queue is set to four).

[0034] The pulse stretching unit is used to stretch the pulse width of the output signal of the second OR gate to the number of instruction cycles that differs between the check core and the execution core when the output of the second OR gate is valid (high-level pulse), so as to align the instruction streams of the check core and the execution core. The output signal of the pulse stretching unit serves as the selection end signal of the second selector. The two input end signals of the second selector are the instruction entry in the instruction queue and the no-operation instruction NOP. When the selection end signal of the second selector is valid, the output of the second selector is a no-operation instruction. When the selection end signal of the second selector is invalid, the output of the second selector is the instruction entry. The output signal of the second selector serves as the input of the second bypass buffer.

[0035] When a fault occurs in the back-end module of the dual-core lockstep processor or the system resets, the pulse stretching unit stretches the pulse width of the second OR gate output signal to the number of instruction cycles that differ between the check core and the execution core. This stretched signal serves as the selection signal for the second selector, selecting the no-op instruction and outputting it to the bypass buffer of the execution core. The second selector is a two-to-one selector. The second selector's selection signal is the output of the pulse stretching unit, and its input is the no-op and the instruction entry dequeued from the instruction queue.

[0036] The second bypass buffer is used to buffer the input instructions and then output the execution core instructions to the execution core.

[0037] The input of the first bypass buffer is the output of the first selector, and the output of the first bypass buffer is connected to the check core, which is the instruction to be executed by the check core. The input of the second bypass buffer is the output of the second selector, and the output of the second bypass buffer is connected to the execution core, which is the instruction to be executed by the execution core. Due to the existence of the instruction queue, the instructions dispatched by the second bypass buffer are the instructions dispatched by the first bypass buffer before the fixed instruction cycle. The instruction fetch module dispatches the instructions of the execution core and the check core to the execution core and the check core of the dual-core lockstep processor through the first bypass buffer and the second bypass buffer, thereby coordinating the throughput between the instruction fetch process and the instruction issuance and execution process of the processor's front stage.

[0038] The bypass buffer handshake mechanism followed by the first bypass buffer and the verification core is as follows: when the input signal of the first bypass buffer is not empty, an instruction fetch request is initiated to the verification core, and the instruction that enters the first bypass buffer earliest is dispatched to the verification core; when the input signal of the first bypass buffer is empty, a signal indicating that the first selector fills the first bypass buffer is used as an instruction fetch request initiated by the first bypass buffer to the verification core, and the instruction with which the first selector fills the first bypass buffer is dispatched to the verification core;

[0039] The bypass buffer handshake mechanism followed by the second bypass buffer and the execution core is: when the input signal of the second bypass buffer is not empty, an instruction fetch request will be initiated to the execution core, and the instruction that enters the second bypass buffer earliest will be dispatched to the execution core; when the input signal of the second bypass buffer is empty, the signal of the second selector filling the second bypass buffer will be used as an instruction fetch request initiated by the second bypass buffer to the execution core, and the instruction filled into the second bypass buffer by the second selector will be dispatched to the execution core.

[0040] See also Figure 3 , is the internal structure block diagram of the branch prediction module. The branch prediction module mainly includes the execution core branch prediction unit, the verification core branch prediction unit, the address increment unit, the fixed priority arbiter and the delay logic unit.

[0041] In the branch prediction module, the execution core branch prediction unit and the verification core branch prediction unit have identical structures. Both are capable of updating their branch history information based on the instruction fetch address output by the fixed-priority arbiter and outputting the instruction fetch address processed by the branch prediction unit. The difference between the execution core branch prediction unit and the verification core branch prediction unit proposed in the present invention is that the input of the execution core branch prediction unit is the instruction fetch address output by the fixed-priority arbiter after being delayed by delay logic, while the input of the verification core branch prediction unit is the instruction fetch address output by the fixed-priority arbiter.

[0042] The working principles of each module in the branch prediction module are as follows:

[0043] The fixed priority arbiter is used to arbitrate and output the instruction fetch address based on the post-stage fault signal and pipeline flush signal transmitted by the verification core, the external input system reset signal (used to reset the dual-core lockstep processor, including the instruction fetch control system proposed by the present invention, to the initial state), the branch instruction prediction failure signal and the re-fetch address input by the instruction fetch module, and the incrementing address output by the address incrementing unit. The incrementing address is obtained by the address incrementing unit by incrementing the instruction fetch address according to a fixed increment. The fixed priority arbiter is also used to input the instruction fetch address into the verification core branch prediction unit, and input the instruction fetch address into the execution core branch prediction unit after being delayed by a fixed period through the delay logic unit. In one embodiment of the present invention, the number of delay cycles can be set to 2.

[0044] The check core branch prediction unit is used to generate a check core instruction fetch address according to the instruction fetch address, and input the generated check core instruction fetch address into the lockstep comparison module and the instruction fetch module respectively.

[0045] The execution core branch prediction unit is used to generate an execution core instruction fetch address according to the delayed instruction fetch address, and input the generated execution core instruction fetch address into the lockstep comparison module.

[0046] Among them, it can be seen Figure 3 The branch prediction module further includes a third selector, which is a two-selector selector. The selection end of the third selector is the branch instruction prediction failure signal output by the instruction fetch module, and the two inputs of the selector are the incremented address output by the address increment module and the re-fetch address output by the instruction fetch module. The output signal of the third selector serves as an input signal of the fixed priority arbiter.

[0047] When the branch instruction prediction failure signal is valid, the output of the third selector is the re-fetch address; when the branch instruction prediction failure signal is invalid, the output of the third selector is the increment address.

[0048] The working principle of the fixed priority arbiter is as follows:

[0049] The priorities of the subsequent-stage fault signal, the pipeline flush signal, the system reset signal and the output signal of the third selector are set, wherein the priority of the system reset signal is greater than the priority of the subsequent-stage fault signal, the priority of the pipeline flush signal and the priority of the output signal of the third selector; based on the priorities of the subsequent-stage fault signal, the pipeline flush signal, the system reset signal and the output signal of the third selector, the fixed-priority arbiter outputs the instruction fetch address in order of priority.

[0050] Specifically, the fixed-priority arbiter outputs the instruction fetch address in order of priority based on the priorities of the subsequent-stage fault signal, the pipeline flush signal, the system reset signal, and the output signal of the third selector. The arbitration process is as follows:

[0051] When the system reset signal is valid, the fixed priority arbiter uses the reset address as the output instruction fetch address;

[0052] When the system reset signal is invalid and the subsequent fault signal is valid, the fixed priority arbiter uses the fault recovery address as the output instruction fetch address;

[0053] When the system reset signal is invalid, the subsequent fault signal is invalid and the pipeline flush signal is valid, the fixed priority arbitration module uses the pipeline flush address as the output instruction fetch address;

[0054] When the system reset signal, the subsequent fault signal and the pipeline flush signal are all invalid, and the branch instruction prediction failure signal is invalid, the fixed priority arbiter uses the incremented address output by the third selector as the output instruction fetch address;

[0055] When the system reset signal, the subsequent fault signal and the pipeline flush signal are all invalid and the branch instruction prediction failure signal is valid, the fixed priority arbiter uses the re-fetch address output by the third selector as the output instruction fetch address.

[0056] The invention provides a dual-core lockstep processor instruction fetch control system supporting extended instructions, which has the following advantages:

[0057] (1) Lockstep extension instructions are processed only in the instruction fetch control system and have an independent decoding path, which does not occupy the decoding path of regular instructions. This design can reduce the dependence of lockstep extension instructions on specific instruction sets, avoid the competition between lockstep extension instructions and regular instructions for hardware resources, and improve the execution efficiency of regular instructions.

[0058] (2) The lock-step comparison module can be dynamically turned on or off through the lock-step extension instruction. Compared with the traditional method, it can achieve fine-grained control of the protection mode of the user code, thereby supporting the lock-step mode to be enabled in the critical code segment and disabled in the non-critical code segment.

[0059] (3) Treat branch prediction failures as a special case of branch prediction failure and handle it in the instruction fetch control system to avoid unnecessary on-site recovery when a failure occurs in the early stage of the pipeline.

[0060] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0061] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0062] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0063] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0064] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0065] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0066] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A dual-core lockstep processor instruction fetch control system supporting extended instructions, characterized in that: It includes an instruction fetch module, an instruction cache, a branch prediction module, a lockstep comparison module and a dual-core lockstep processor, wherein the dual-core lockstep processor includes a check core and an execution core; The instruction fetch module is configured to generate a read cache control signal based on the instruction fetch address of the check core, read at least one instruction from the instruction cache based on the read cache control signal, determine the type of each instruction, and if it is a lockstep extension instruction, generate a lockstep activation signal and transmit it to the lockstep comparison module to turn the lockstep comparison module on or off; if it is a regular instruction, generate a check core instruction and an execution core instruction based on the regular instruction, and output them to the check core and the execution core respectively; and transmit a branch instruction prediction failure signal and a re-fetch address to the branch prediction module; The execution core is configured to process the execution core instruction, obtain an execution core processing result, and transmit the execution core processing result to the verification core; The check core is used to process the check core instruction to obtain a check core processing result, compare the check core processing result with the execution core processing result, generate a subsequent fault signal and a pipeline flush signal according to the comparison result, and transmit them to the branch prediction module; The branch prediction module is configured to generate a verification core instruction fetch address and an execution core instruction fetch address according to the subsequent fault signal, the pipeline flush signal, the system reset address, the branch instruction prediction failure signal, and the re-fetch address, respectively, input the verification core instruction fetch address to the lockstep comparison module and the instruction fetch module, respectively, and input the execution core instruction fetch address to the lockstep comparison module; The lockstep comparison module is used to compare the instruction fetch address of the verification core with the instruction fetch address of the execution core, generate a branch prediction fault signal according to the comparison result, and output it to the instruction fetch module.

2. The system according to claim 1, wherein: The instruction fetch module includes an instruction fetch and alignment processing unit, an instruction pre-decoding unit, a first OR gate, a first selector, a first bypass buffer, an instruction queue, a second OR gate, a first NOR gate, a pulse stretching unit, a second selector and a second bypass buffer; The instruction fetching and alignment processing unit is configured to convert the instruction fetch address of the check core into a read cache control signal, read multiple instructions from the instruction cache according to the read cache control signal, and output the multiple instructions to the instruction pre-decoding unit after aligning the multiple instructions; and outputting each instruction to the input end of the first selector, and when a branch instruction prediction failure signal of the lockstep comparison module is detected, outputting the check core fetch instruction address when no branch instruction prediction failure signal was detected last time as a re-fetch address to the branch prediction module; The instruction pre-decoding unit receives the aligned instruction input by the instruction extraction and alignment processing unit, determines whether the current instruction is a lockstep extension instruction, and if so, generates a lockstep activation signal according to the lockstep extension instruction and outputs it to the lockstep comparison module; if the current instruction is a regular instruction, no special processing is required; and is further configured to input the lockstep extension instruction or the branch instruction prediction failure signal into one input terminal of the first OR gate, the other input terminal of the first OR gate being the branch prediction failure signal output by the branch prediction module; The output signal of the first OR gate serves as a selection end signal of the first selector, and the other input end of the first selector is a no-operation instruction NOP. When the selection end signal of the first selector is valid, the output of the first selector is a no-operation instruction; otherwise, the output of the first selector is an instruction input by the instruction fetch and alignment processing unit; wherein the output instructions of the first selector are respectively output to the instruction queue and the first bypass buffer; The first bypass buffer is configured to buffer the output instruction of the first selector, generate a verification core instruction, and output the instruction to the verification core; Two input signals of the second OR gate are a post-stage fault signal output by the check core and an external system reset signal; the output signal of the second OR gate serves as one input terminal signal of the first NOR gate and an input signal of the pulse stretching unit respectively; the other input terminal signal of the first NOR gate is a pipeline flush signal output by the check core; and the output signal of the first NOR gate is used to invalidate instruction entries in the instruction queue; The pulse stretching unit is configured to stretch the pulse width of the output signal of the second OR gate to the number of instruction cycles that differs between the check core and the execution core, and the output signal of the pulse stretching unit serves as the selection end signal of the second selector. The two input end signals of the second selector are the instruction entry in the instruction queue and the no-operation instruction NOP. When the selection end signal of the second selector is valid, the output of the second selector is the no-operation instruction. When the selection end signal of the second selector is invalid, the output of the second selector is the instruction entry. The output signal of the second selector serves as the input of the second bypass buffer. The second bypass buffer is used to buffer the output instructions of the second selector, generate execution core instructions, and output them to the execution core.

3. The system according to claim 2, characterized in that The instruction fetching and alignment processing unit is configured to convert the instruction fetch address of the check core into a read cache control signal, read multiple instructions from the instruction cache according to the read cache control signal, align the multiple instructions, and output the instruction pre-decoding unit, including: The instruction extraction and alignment processing unit converts the check core instruction fetch address output by the branch prediction module into a read cache control signal, reads an instruction cache line from the instruction cache according to the read cache control signal, extracts compressed instructions in the instruction cache line according to the instruction opcode, and extracts a corresponding number of instructions from the instruction cache line according to the instruction issue width of the dual-core lockstep processor. After aligning all instructions, the instructions are output to the instruction pre-decoding unit.

4. The system according to claim 2, wherein: The generation of the branch instruction prediction failure signal includes: The instruction pre-decoding unit estimates whether the corresponding instruction is a branch instruction according to the check core instruction address output by the branch prediction module, wherein the branch instruction is a special instruction of the regular instruction; The instruction fetching and alignment processing unit fetches an instruction address according to the checksum core and reads an instruction from the instruction cache, and the instruction pre-decoding unit determines whether the read instruction is a branch instruction; If the judgment result is inconsistent with the estimated result, the branch instruction prediction fails, and a branch instruction prediction failure signal is output to the branch prediction module.

5. The system according to claim 2, wherein: The bypass buffer handshake mechanism followed by the first bypass buffer and the verification core is as follows: when the input signal of the first bypass buffer is not empty, an instruction fetch request is initiated to the verification core, and the instruction that enters the first bypass buffer earliest is dispatched to the verification core; when the input signal of the first bypass buffer is empty, a signal indicating that the first selector fills the first bypass buffer is used as an instruction fetch request initiated by the first bypass buffer to the verification core, and the instruction with which the first selector fills the first bypass buffer is dispatched to the verification core; The bypass buffer handshake mechanism followed by the second bypass buffer and the execution core is: when the input signal of the second bypass buffer is not empty, an instruction fetch request will be initiated to the execution core, and the instruction that enters the second bypass buffer earliest will be dispatched to the execution core; when the input signal of the second bypass buffer is empty, the signal of the second selector filling the second bypass buffer will be used as an instruction fetch request initiated by the second bypass buffer to the execution core, and the instruction filled into the second bypass buffer by the second selector will be dispatched to the execution core.

6. The system according to claim 1, wherein: The branch prediction module includes an execution core branch prediction unit, a verification core branch prediction unit, an address increment unit, a fixed priority arbiter and a delay logic unit; The fixed-priority arbiter is configured to arbitrate and output an instruction fetch address based on a subsequent fault signal and a pipeline flush signal transmitted by the verification core, an externally inputted system reset signal, a branch instruction prediction failure signal and a re-fetch address inputted by the instruction fetch module, and an incremented address outputted by the address incrementing unit, wherein the incremented address is obtained by incrementing the instruction fetch address by the address incrementing unit; and is further configured to input the instruction fetch address into the verification core branch prediction unit, and input the instruction fetch address into the execution core branch prediction unit after delaying it for a fixed period through the delay logic unit; The check core branch prediction unit is used to generate a check core instruction fetch address according to the instruction fetch address; The execution core branch prediction unit is used to generate an execution core instruction fetch address according to the delayed instruction fetch address.

7. The system according to claim 6, characterized in that The branch prediction module further includes a third selector, which is a two-selector selector, wherein a selection end of the third selector is a branch instruction prediction failure signal output by the instruction fetch module, and two inputs of the selector are an incremented address output by the address increment unit and a re-fetch address output by the instruction fetch module, and an output signal of the third selector serves as an input signal of the fixed priority arbiter; When the branch instruction prediction failure signal is valid, the output of the third selector is the re-fetch address; when the branch instruction prediction failure signal is invalid, the output of the third selector is the increment address.

8. The system according to claim 7, characterized in that The fixed priority arbiter is used to arbitrate and output an instruction fetch address based on a subsequent fault signal and a pipeline flush signal transmitted by the check core, an external system reset signal, a branch instruction prediction failure signal and a re-fetch address input by the instruction fetch module, and an incremented address output by the address increment unit, including: Setting the priorities of the subsequent stage fault signal, the pipeline flush signal, the system reset signal, and the output signal of the third selector, wherein the priority of the system reset signal is greater than the priority of the subsequent stage fault signal, and the priority of the pipeline flush signal is greater than the priority of the output signal of the third selector; Based on the priorities of the subsequent stage fault signal, the pipeline flush signal, the system reset signal, and the output signal of the third selector, the fixed priority arbiter outputs the instruction fetch address in order of priority.

9. The system according to claim 8, characterized in that The fixed priority arbiter outputs the instruction fetch address in order of priority based on the subsequent stage fault signal, the pipeline flush signal, the system reset signal, and the priority of the output signal of the third selector, including: When the system reset signal is valid, the fixed priority arbiter uses the reset address as the output instruction fetch address; When the system reset signal is invalid and the subsequent fault signal is valid, the fixed priority arbiter uses the fault recovery address as the output instruction fetch address; When the system reset signal is invalid, the subsequent fault signal is invalid and the pipeline flush signal is valid, the fixed priority arbiter uses the pipeline flush address as the output instruction fetch address; When the system reset signal, the subsequent fault signal and the pipeline flush signal are all invalid, and the branch instruction prediction failure signal is invalid, the fixed priority arbiter uses the incremented address output by the third selector as the output instruction fetch address; When the system reset signal, the subsequent fault signal and the pipeline flush signal are all invalid and the branch instruction prediction failure signal is valid, the fixed priority arbiter uses the re-fetch address output by the third selector as the output instruction fetch address.

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