Method, apparatus, and storage medium for optimizing digital logic circuit layout

Abstract

The application provides a method, device and storage medium for optimizing a digital logic circuit layout, comprising the following steps: determining a first layout of the digital logic circuit, wherein the first layout comprises a plurality of macro cells and a plurality of standard cells; determining a channel formed between adjacent macro cells; determining a target step parameter of the standard cell according to a position of the standard cell and the channel based on an optimization target of the digital logic circuit, wherein the optimization target comprises at least one of a line length target, a density target and a timing target; and adjusting the standard cell based on the target step parameter to optimize the layout of the digital logic circuit. The method provided by the application can realize automatic layout optimization of the digital logic circuit, reduce the influence of the channel on the layout optimization, and further improve the performance of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a method, device and storage medium for optimizing digital logic circuit layout. BACKGROUND

[0002] Electronic design automation (EDA) software is widely used in chip design. With the aid of various EDA software, engineers can conveniently perform chip design, such as architecture design and register-transfer level (RTL) code design, synthesis, design for test (DFT), physical development, and signoff, etc.

[0003] In the process of chip design by using EDA software, high-quality circuit layout and wiring is a prerequisite for successful chip design, and complex and time-consuming layout planning is the key to achieving high-quality layout and wiring. With the increasing size and complexity of modern digital logic circuits, users have higher and higher requirements for the performance, power consumption or area (PPA) of the circuit. Only by placing each element in the chip at a suitable position, the required target timing, power consumption or area can be achieved. SUMMARY

[0004] Therefore, the present application aims to provide a method, device and storage medium for optimizing digital logic circuit layout to solve or partially solve the above problems.

[0005] To achieve the above object, the present application provides a method for optimizing digital logic circuit layout, which comprises: determining a first layout of the digital logic circuit; wherein the first layout comprises a plurality of macro cells and a plurality of standard cells;

[0006] determining a channel formed between adjacent macro cells;

[0007] determining a target step parameter of the standard cell according to the position of the standard cell and the channel based on an optimization target of the digital logic circuit; wherein the optimization target comprises at least one of a wire length target, a density target and a timing target;

[0008] adjusting the standard cell based on the target step parameter to optimize the layout of the digital logic circuit.

[0009] In a second aspect, the present application provides a computer device, comprising:

[0010] one or more processors, a memory; and

[0011] one or more programs;

[0012] The one or more programs are stored in the memory and executed by the one or more processors, and the programs comprise instructions for performing the method according to the first aspect.

[0013] In a third aspect, the present application provides a non-volatile computer readable storage medium containing a computer program, which, when executed by one or more processors, causes the processors to perform the method according to the first aspect.

[0014] As can be seen from the above, the present application provides a method, device and storage medium for optimizing the layout of a digital logic circuit. The method comprises determining a first layout of the digital logic circuit, the first layout comprising a plurality of macro cells and a plurality of standard cells, determining channels formed between adjacent macro cells, determining a target step parameter of the standard cells based on the positions of the standard cells and the channels, the optimization target comprising at least one of a line length target, a density target and a timing target, and adjusting the standard cells based on the target step parameter to optimize the layout of the digital logic circuit. The method can automatically optimize the layout of the digital logic circuit, reduce the impact of the channels on the layout optimization, and further improve the performance of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present application or related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art descriptions. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0016] Figure 1 A schematic diagram of an exemplary computer device according to an embodiment of the present application is shown.

[0017] Figure 2 A basic structure schematic diagram of a simulation tool according to an embodiment of the present application is shown.

[0018] Figure 3 A flowchart of the design and manufacturing process of an exemplary chip according to an embodiment of the present application is shown.

[0019] Figure 4 A schematic diagram of an exemplary application scenario according to an embodiment of the present application is shown.

[0020] Figure 5 A schematic diagram illustrating an example first layout according to an embodiment of the present application is shown.

[0021] Figure 6A A schematic diagram illustrating an example first region according to an embodiment of the present application is shown.

[0022] Figure 6B A schematic diagram illustrating an example of determining a target region according to an embodiment of the present application is shown.

[0023] Figure 6C A schematic diagram illustrating an example of determining a target region according to an embodiment of the present application is shown.

[0024] Figure 7 A schematic diagram illustrating an example method for optimizing digital logic circuit layout according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0026] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present application should be understood as their common meanings to those skilled in the art to which the present application pertains. The terms “first”, “second” and similar terms used in the embodiments of the present application do not represent any order, number or importance, but are only used to distinguish different components. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms “connect” or “connected” and similar terms do not mean physical or mechanical connection, but can include electrical connection, whether direct or indirect. The terms “upper”, “lower”, “left”, “right” and the like only represent relative positional relationships, which can change when the absolute positions of the described objects change.

[0027] In the related art, in integrated circuit design, macro cells usually occupy a large area, and during the layout process, there is usually a certain gap region between macro cells, referred to as a channel. The existence of these channels has a significant impact on the layout of standard cells. On the one hand, the macro cells around the channel occupy a large area, and on the other hand, the standard cells cannot overlap with the macro cells, so during the layout process, many standard cells will be placed in the channel, resulting in poor layout effect.

[0028] In the related art, the number of standard cells falling into the trench can be controlled by setting an upper limit of the allowed density of the trench. However, when the trench is stacked with many and the standard cell density is high, this method often cannot effectively avoid a large number of standard cells from being placed into the trench. Especially for the cells located in the deep trench area (far from the center of the chip), due to the blockage of the surrounding macro cells, it is difficult for subsequent layout optimization to migrate them to other positions, resulting in the aggravation of the problem of cell aggregation in the trench. In addition, the position of the cell can also be adjusted by using a forced moving strategy, but this strategy also has limitations. The strategy of forced moving standard cells can reduce the number of cells in the trench, but it cannot ensure that the new position meets the optimization target, and this method cannot optimally select which cells to move.

[0029] To at least solve the above problems, the present application provides a method, device and storage medium for optimizing the layout of a digital logic circuit. The method comprises determining a first layout of the digital logic circuit, the first layout comprising a plurality of macro cells and a plurality of standard cells, determining a trench formed between adjacent macro cells, determining a target step parameter of the standard cells according to the positions of the standard cells and the trench based on an optimization target of the digital logic circuit, the optimization target comprising at least one of a line length target, a density target and a timing target, and adjusting the standard cells based on the target step parameter to optimize the layout of the digital logic circuit. Through the method of the present application, automatic layout optimization of the digital logic circuit can be realized, the influence of the trench on the layout optimization is reduced, and the performance of the chip is further improved.

[0030] Figure 1 A schematic diagram of an exemplary computer device 100 according to an embodiment of the present application is shown, which can include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040 and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030 and the communication interface 1040 are connected to each other through the bus 1050 for communication within the device.

[0031] The processor 1010 can be implemented in the form of a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided by the embodiments of the present application.

[0032] The memory 1020 can be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 1020 can store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the related program codes are saved in the memory 1020 and are called and executed by the processor 1010.

[0033] The input / output interface 1030 is configured to connect an input / output module to realize information input and output. The input / output module can be configured in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0034] The communication interface 1040 is configured to connect a communication module (not shown in the figure) to realize the communication interaction between the device and other devices. The communication module can realize communication through a wired manner (such as a USB, a network cable, etc.) or through a wireless manner (such as a mobile network, WIFI, Bluetooth, etc.).

[0035] The bus 1050 includes a channel to transmit information between various components (such as the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040) of the device.

[0036] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only include the components necessary to implement the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0037] Figure 2 A basic structure schematic diagram of the simulation tool 200 according to the embodiments of the present application is shown.

[0038] As shown in Figure 2 the upper part of the dashed line is the user part; the lower part of the dashed line is the simulation tool 200, which can be implemented by a computer system. Figure 1The illustrated computer device 100 implements. The simulation tool 200 can include a Tcl command module 204 (or a graphical / window interface module), various computing modules (e.g., a Place computing module 206 (a layout computing module), a Route computing module 208 (a routing computing module), an Optimization computing module 210 (an optimization computing module), etc.), and a database system 212. A user 202 can operate the simulation tool 200 by inputting relevant commands in the Tcl command module 204 (or the graphical / window interface module). In some embodiments, the simulation tool 200 can be any EDA (Electronic Design Automation) software.

[0039] The Tcl command module 204 mainly functions as a message passing or command passing. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and pass the instructions to the corresponding computing modules to perform specific tasks according to the specific content of the instructions.

[0040] According to different computing tasks, the computing modules can be divided into, for example, the Place computing module 206, the Route computing module 208, the Optimization computing module 210, etc. The Place computing module 206 can be used to calculate a reasonable placement position for all components, the Route computing module 208 can be used to calculate a reasonable wire connection mode between components, and the Optimization computing module 210 can be used to optimize the placement position and the wire connection mode between components. The computing processes of these computing modules can be performed in, for example, the processor 1010. Figure 1

[0041] The database system 212 can be used to record and store all information (such as position, direction, size, structure, wire connection mode, etc.) of the simulated or designed chip completely and comprehensively, for example, stored in the memory 1020. The database system 212 can include database systems of different angles, for example, as illustrated in Figure 1 , a database system (schematic angle) 2122 and a database system (memory angle) 2124. Figure 2

[0042] Figure 3 A flowchart of a design and manufacturing process 300 of an exemplary chip according to embodiments of the present application is illustrated.

[0043] As illustrated in Figure 3 ​​As shown, the design and manufacturing process 300 starts with specification 302. At the specification stage 302, the requirements of the functionality and performance that the integrated circuit (i.e., digital logic circuit) needs to achieve are determined. At the chip design stage, the circuit is designed with the help of EDA software to obtain, for example, a layout file for chip manufacturing. Depending on the type of circuit (e.g., digital circuit or analog circuit), the design 304 can include different design steps. At the manufacturing stage 306, the integrated circuit is formed on a wafer through processes such as photolithography, etching, ion implantation, thin film deposition, polishing, etc. At the packaging stage 308, the wafer is cut to obtain dies, and the dies are packaged to obtain chips through processes such as die bonding, wire bonding, mold encapsulation, etc. The obtained chips are tested at the testing stage 310 to ensure that the performance of the finished chips meets the requirements determined at the specification stage 302. The tested chips 312 that pass the test can be delivered to customers. It can be appreciated that the above process is merely illustrative and does not limit the scope of the present application. In some cases, the design and manufacturing process of a chip can be different. For example, tape-out can be performed before the manufacturing 306. A small number of chips resulting from the tape-out can be used for testing to verify whether the chip design meets the expectation. If not, it indicates that the tape-out fails, and the chip design can need to be adjusted or redesigned.

[0044] In some embodiments, the design 304 of the digital logic circuit can illustratively include architecture design 322, RTL design 324, functional simulation 326, synthesis 328, timing analysis 330, DFT 332, verification check 334, place and route 336, DRC 338 (design rule check), and generate layout 340. The architecture design 322, for example, includes designing the architecture of the chip. For example, the EDA software can be used to determine the types and numbers of components or sub-circuits included in the chip system, as well as the functions, connections, and interactions of the individual components or sub-circuits. At the RTL design 324 stage, the determined chip architecture can be described at the RTL level using a hardware programming language such as Verilog or VHDL. The functional simulation 326 is also known as RTL-level behavioral simulation or front-end simulation. The purpose of the functional simulation is to analyze the correctness of the logical relationship of the designed circuit. The synthesis 328 can convert the RTL into a gate-level netlist. The synthesis 328, for example, can include translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis can first convert the RTL code into a general Boolean equation, and compile it. The netlist can be optimized according to the constraints of delay, area, etc. imposed by the designer, and then the RTL netlist is mapped to a technology library to generate a gate-level netlist.

[0045] The timing analysis 330 is typically static timing analysis, which involves timing computation and prediction for digital circuits. The timing analysis is performed on paths in the digital circuits to determine whether timing closure is achieved, thereby ensuring that the timing of various circuits meets various timing requirements. This verification of digital circuits is typically done statically and does not require simulation of the digital logic. During the DFT 332 phase, various hardware logic for improving chip testability (including controllability and observability) can be embedded in the design. Using this logic, test vectors can be generated for the purpose of testing large scale digital circuits. The DFT can include, for example, scan chain based testing methods or built-in self-test circuits (BIST). During the verification check 334 phase, formal verification and / or equivalence checking can be performed on the circuits. Formal verification can prove correctness or incorrectness of a circuit using mathematical methods according to one or more formal specifications or properties. Formal verification can include, for example, abstract interpretation, formal model checking (also known as property checking), and theorem proving. Equivalence checking can be used to verify consistency between a register transfer level design and a gate level netlist, or between two gate level netlists.

[0046] During the place and route 336 phase, the chip circuits can be placed and routed. The placement can involve arranging the gate level netlist generated by the logic synthesis 328 in a rectangular region corresponding to the chip, taking into account factors such as area, critical path delay length, power consumption, etc. After that, the placed components or sub-circuits can be routed to connect them. The routing is typically desired to be short in total wire length, to meet timing requirements in wire delay, and to comply with process-based routing rules (e.g., routing density). Although placement and routing are described separately, this is merely illustrative and not limiting to the scope of the present application. In some cases, placement and routing can be performed simultaneously or alternately to achieve optimization of placement and routing.

[0047] At the stage of DRC 338, the layout can be checked for violations of design rules that can cause potential open circuits, short circuits, or undesirable effects. After passing the DRC, a file representing the layout, such as a GDSII file, can be generated by the EDA software. It can be appreciated that the above steps are merely exemplary and not intended to limit the scope of the present application. In actual design process, the above steps can be added, deleted, or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software, or can be integrated in one or more EDA software. The present application does not limit this.

[0048] The scheme of the present application for optimizing digital logic circuit layout can be applied to the physical synthesis stage in the stage of synthesis 328. The components of the circuit layout plan include the layout of macro cells and standard cells. Macro cells mainly include memory cells and various custom cells, which are the main functional modules of digital logic circuits. Standard cells are modules of basic electronic logic functions, such as various gate devices, flip-flops, latches, and buffers.

[0049] After the macro cells are placed in the circuit layout, the performance, power consumption, and area required by the circuit are achieved according to the design constraints of the circuit, such as layout rules and routing rules. It can be appreciated that the scheme of the present application can also be applied to other scenarios for optimizing other circuits, which is not limited herein.

[0050] It can be appreciated that although the above describes the operations in a specific order, this should be understood as not being limited to requiring the operations to be performed in the specific order shown or in a sequential order, or requiring all of the illustrated operations to be performed to achieve the desired result. In certain circumstances, multi-tasking and parallel processing can be advantageous. Similarly, although specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments can also be combined in a single implementation. Conversely, various features described in the context of a single implementation can also be separated and implemented in multiple implementations.

[0051] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0052] Figure 4 A schematic diagram of an exemplary application scenario 400 according to an embodiment of the present application is shown.

[0053] As Figure 4As shown, application scenario 400 may include computer device 100. In some embodiments, computer device 100 may be a device with computing capabilities, such as a personal computer, workstation, or server. The process described in this application can be implemented by EDA tool software in electronic devices with computing capabilities, such as personal computers, workstations, or servers. Computer device 100 may be equipped with EDA software. During the EDA design process of a chip, a user (not shown) can input configurations into the EDA software, which then automatically generates digital logic circuits. EDA software includes, but is not limited to, chip design auxiliary software, programmable chip auxiliary design software, and system design auxiliary software. The scope of this application is not limited in this respect.

[0054] Computer device 100 is able to acquire a first layout 402 of digital logic circuits, the first layout 402 of which may include the relative positions of devices in the circuit (e.g., macro cells and standard cells).

[0055] After acquiring the first layout 402, the computer device 100 can determine the target step size parameter of the standard cell based on the position of the standard cell and channel in the first layout 402 and a specific optimization objective. In some embodiments, the computer device 100 can determine the target step size parameter of the standard cell based on at least one of a timing objective, a line length objective, or a density objective.

[0056] After determining the target step size parameter of the standard cell, the computer device 100 can adjust the position of the standard cell according to the target step size parameter to obtain the second layout 404 of the circuit. In some embodiments, the computer device 100 can change the moving step size or moving direction of the standard cell based on the target step size parameter to obtain the second layout 404 of the circuit.

[0057] Figure 5 A schematic diagram of an exemplary first layout 402 according to an embodiment of this application is shown.

[0058] like Figure 5 As shown, in some embodiments, for circuits with a large number of macrocells, a certain gap area, called a channel, is often left between the macrocells in the first layout 402. After the macrocell layout is completed, that is, when the macrocell layout positions are determined, the remaining space can be used to lay out standard cells. In addition to large blank areas, the channels between macrocells can also be used to lay out standard cells.

[0059] As mentioned earlier, when optimizing the layout, related technologies struggle to effectively prevent a large number of standard cells from being placed within the channels. Therefore, after obtaining the first layout 402, it is possible to first determine whether channels are formed between macrocells, and then locate these channels for further processing.

[0060] In some embodiments, the spacing between two adjacent macrocells can be determined first, and the spacing can be determined to be a channel in response to the spacing width being less than a width threshold. Optionally, the width threshold can be calculated based on the size of the macrocell, for example, determined based on the width of the macrocell. Here, the width of the macrocell can be a dimension in the same direction as the spacing width. For example, using... Figure 5 As shown for reference, assuming the spacing between two macrocells is formed between two macrocells arranged in the horizontal direction, the width of a macrocell refers to its size in the horizontal direction. Optionally, the width threshold can be set to a certain proportion of the macrocell width. The channels determined in this way have a greater impact on the optimization effect and require more targeted processing.

[0061] For example, if two adjacent macrocells have the same size, an interval whose width is less than a predetermined proportion (e.g., 1 / 5, 1 / 10, etc.) of the width of either macrocell can be regarded as a channel; if two adjacent macrocells have different sizes, the average width of the two adjacent macrocells is calculated, and an interval whose width is less than a predetermined proportion of the average width is regarded as a channel.

[0062] The channels in the first layout 402, such as channel 500, can be determined using the above method.

[0063] After determining the channel in the first layout 402, in some embodiments, the target step size parameter of the standard cell can be determined based on the optimization objective of the digital logic circuit and the positions of the standard cell and the channel. The target step size parameter can be used to adjust the standard cell to achieve the optimization objective.

[0064] In some embodiments, the computer device 100 may determine the initial step size parameter of the standard cell based on the optimization objective of the digital logic circuit, wherein the initial step size parameter represents the initial magnitude of the standard cell position adjustment at the beginning of the layout optimization phase.

[0065] Specifically, the optimization objective is represented as a target function, and the goal of the optimization algorithm is to find the solution that optimizes the target function. For example, the target function satisfies the following expression:

[0066]

[0067] in: This represents the objective function for a single wire length, used to measure wiring length. represents a single density objective function, which can reflect the density of the standard cells in the region, represents a single timing objective function, which is related to the timing performance of the circuit and ensures that the signals are transmitted within a specified time. Then, according to the first layout 402, the position information of all the standard cells is substituted into the objective function, and the function value of the objective function is calculated. In response to the function value not satisfying the optimization target, that is, the calculated function value does not satisfy the preset optimization target, such as the upper limit of the expected timing delay, the upper limit of the density, the lower limit of the total line length, and the like, the initial step parameter is calculated according to the objective function. It should be understood that if the function value satisfies the optimization target, it means that the standard cells do not need to be optimized again. The introduction of the objective function to evaluate whether the current layout satisfies the optimization target and to calculate the function value for judgment provides a quantitative and objective evaluation method, which can clearly reflect the gap between the layout and the optimization target, and provides a strong basis for subsequent step parameter adjustment. When the function value does not satisfy the optimization target, the initial step parameter is calculated according to the objective function, so that a more optimal initial step parameter can be determined according to the different states of the circuit layout and the optimization requirements, laying a foundation for subsequent accurate adjustment and improving the efficiency of the entire optimization process.

[0068] In some embodiments, the initial step parameter is obtained by deriving the objective function based on the Conjugate Gradient algorithm. The Conjugate Gradient algorithm is an efficient iterative optimization algorithm that obtains the fastest descent direction of the objective function under the current layout state by derivation, quickly approaches the optimal solution, and obtains the initial step parameter. The Conjugate Gradient algorithm has a faster convergence speed and higher calculation efficiency, can quickly and accurately obtain the initial step parameter, saves calculation time and resources, and improves the overall efficiency of the layout optimization.

[0069] Then, the step coefficient is determined according to the positions of the standard cells and the channel 500 and the initial step parameter. The step coefficient is a factor for adjusting the initial step parameter, which reflects the influence of the specific position characteristics of the standard cells in the channel 500 on the layout adjustment. When the step coefficient is less than 1, the initial step will be reduced, and when the step coefficient is greater than 1, the adjustment range can be enlarged. By determining the step coefficient, the initial step parameter can be finely adjusted according to the local position, improving the accuracy of the layout optimization.

[0070] Figure 6A A schematic diagram of an exemplary first region 600 according to embodiments of the present application is shown.

[0071] As Figure 6AAs shown, in some embodiments, the first layout 402 is scanned to determine the target region in the first layout 402 by using a sliding window. The sliding window is a dynamic scanning technology that can analyze the distribution of elements and the channel 500 by sliding a fixed-size window on the layout of the digital logic circuit. Specifically, the region covered by the sliding window at the current position is defined as the first region 600. For example, the window size of the sliding window is set to 1 / 10 of the chip area, and the sliding step size is 1 / 4 of the sliding window size. Then, the area ratio of the channel 500 in the first region 600 in the first region 600 and / or the number of channels 500 in the first region 600 is determined. In response to determining that the area ratio is greater than a proportion threshold and / or the number of channels 500 is greater than a number threshold, the first region 600 is determined as the target region. For example, when the area ratio is greater than 0.5 or the number of channels 500 is greater than 5, the first region 600 is considered as the target region, that is, the first region 600 is the region in which the standard cells are affected by the channel 500.

[0072] Figure 6B As shown in the schematic diagram of determining the target region 602 according to the area ratio of the channel 500 according to an embodiment of the present application.

[0073] As shown in the schematic diagram of determining the target region 602 according to the number of channels 500 according to an embodiment of the present application. Figure 6B As shown, when the target region 602 is determined according to the area ratio of the channel 500, in some embodiments, in each first region 600, the computer device 100 can calculate the area ratio of the channel 500 by measuring the actual area of the channel 500 and dividing the total area of the first region 600. The area ratio of the channel 500 refers to the proportion of the area occupied by the channel 500 in the region covered by the sliding window. If the area ratio of the channel 500 exceeds the preset proportion threshold (for example, 0.5), the first region 600 is determined as the target region 602, indicating that the standard cells in the region will be affected by the channel 500 in the layout optimization process and need to be further optimized.

[0074] Figure 6C As shown in the schematic diagram of determining the target region 602 according to the number of channels 500 according to an embodiment of the present application.

[0075] As shown in the schematic diagram of determining the target region 602 according to the number of channels 500 according to an embodiment of the present application. Figure 6C As shown, when the target region 602 is determined according to the number of channels 500, in some embodiments, the computer device 100 can identify the number of channels 500 in the first region 600. If the number of channels 500 exceeds the preset number threshold (for example, 5), the first region 600 is determined as the target region 602. As shown in the schematic diagram of determining the target region 602 according to the number of channels 500 according to an embodiment of the present application. Figure 6CIn the embodiment, if the number of the channels 500 in the first region 600 is 6, the first region 600 is determined as the target region 602, and the standard cells in the target region 602 are also affected by the channels 500 and need to be further optimized in the layout optimization process.

[0076] In some embodiments, in the determined target region 602, the number of the target channels 604 in the target region 602 is counted, and the standard cells in the target region 602, i.e. the standard cells affected by the channels 500, are recorded with the information of the position, the moving step and the moving direction of the standard cells according to the initial step parameter. Then, the relative position between the target channels 604 and the center of the first layout 402 is determined. For example, a coordinate system is established with the center of the first layout 402 as the origin, and the relative position relationship between the target channels 604 and the center of the first layout 402 is obtained according to the coordinate difference, the distance, the angle and other parameters calculated based on the coordinates of the target channels 604 and the coordinates of the center of the first layout 402.

[0077] It should be noted that the center of the first layout 402 can be regarded as the geometric center of the chip. With the center of the first layout 402 as the origin, the channel 500 far from the origin is defined as a deep channel. For the standard cells close to the deep channel and surrounded by the dense macro cells, the degree of influence is higher, which indicates that the wiring pressure of the region is large, and the step needs to be reduced to avoid the congestion of the wiring caused by the movement of the standard cells, and vice versa. Through the differentiated step adjustment, the movement speed of the standard cells in the deep channel region is slowed down, and the standard cells are preferentially optimized to other low-density regions.

[0078] In some embodiments, based on the moving step and the moving direction of the standard cells, the relative position and / or the number of the target channels 604, the step coefficient of the standard cells in the target region 602 is determined.

[0079] For each standard cell in the target region 602, according to its moving direction, it is determined whether it is away from or close to the center of the first layout 402. If the moving direction of the standard cell is away from the center of the first layout 402, a step length coefficient is determined according to the relative position of the target channel 604 to the center and the number of target channels 604. The step length coefficient is set to be less than 1 and negatively correlated with the relative position and the number of target channels 604. For example, if the target channel 604 is farther away from the layout center or the number of target channels 604 is greater, the step length coefficient is smaller, so as to reduce the amplitude of the outward movement of the standard cell and prevent the layout from over-expanding. If the moving direction of the standard cell is close to the center of the first layout 402, the step length coefficient is set to be greater than or equal to 1, and the standard cell is aggregated to the center, which helps to reduce the wiring pressure. In determining the step length coefficient, multiple factors are considered, such as the moving step length, moving direction, relative position of the target channel 604, and number of target channels 604. The determination of the step length coefficient is to make the standard cell adjust the position according to the optimization direction in the moving process, and also make appropriate step length adjustment according to the layout environment (such as the distance from the center and the number of channels 500), so as to realize more reasonable layout optimization. At the same time, the step length adjustment does not change the original objective function, ensuring the synchronous optimization of line length, density and timing results.

[0080] Further, the target step length parameter is determined according to the initial step length parameter and the step length coefficient.

[0081] The initial step length parameter includes a moving step length and a moving direction.

[0082] In some embodiments, the step length coefficient is multiplied by the moving step length to obtain the target step length. The target step length of a single element is represented by the following formula:

[0083]

[0084] The target step length parameter is determined according to the target step length and the moving direction. The step length coefficient is within the range of the channel 500, , in other regions, ; The moving step length is also the global initial step length value.

[0085] In some embodiments, the target step length parameter is determined according to the target step length and the moving direction. The target step length parameter can combine the target step length (step length) and the moving direction to obtain a complete moving description. For example, the target step length parameter can be expressed as a vector, target step length parameter = (target step length_x, target step length_y), which represents the displacement vector of the standard cell in the two-dimensional plane and contains the size and direction of the movement.

[0086] Specifically, after the gradient derivation of the above objective function, the moving direction of each element can be obtained . Combined with , and the step coefficient , the target step parameter can be obtained through multiple iterations by the conjugate gradient algorithm.

[0087] The calculation formula of the target step parameter is:

[0088] .

[0089] Finally, the calculated target step is combined with the moving direction to form a complete target step parameter. And according to the moving direction in the target step parameter, the standard cell is moved by the moving distance corresponding to the target step to adjust the standard cell, so as to realize the optimization of the layout.

[0090] Wherein, the new layout after adjusting the standard cell is the second layout 404.

[0091] In some embodiments, the parameters of the second layout 404 are input into the objective function, and the function value of the objective function is calculated. The specific expression of the objective function is as described above, and the optimization target includes line length, density, timing, etc., and then the overall advantages and disadvantages of the layout are reflected through specific weight combination.

[0092] In response to the function value of the objective function reaching the target value, the layout optimization of the digital logic circuit is ended, and the current layout is output as the optimal solution. In response to the function value of the objective function not reaching the target value, the above steps of optimizing the digital logic circuit based on the optimization target are repeatedly executed, the target step parameter of the standard cell is determined according to the positions of the standard cell and the channel 500, and the standard cell is adjusted based on the target step parameter to generate a new layout (i.e. enter the next iteration), so as to optimize the layout of the digital logic circuit, until the optimization target is met or the number of iterations reaches a predetermined number.

[0093] It should be understood that the above method of iteratively optimizing the layout of the digital logic circuit is to optimize and adjust the step length of the standard cell affected by the channel 500, so as to adjust the number of elements falling into the channel 500. In addition, this method can also optimize the step length of all cells on the circuit, and by optimizing the step length of the cells with different position constraints, the step length optimization is used to meet the position constraint requirements of the elements.

[0094] Figure 7 A flowchart of an exemplary method 700 for optimizing the layout of a digital logic circuit according to an embodiment of the present application is shown. The method 700 can be performed by a computer device 100 as shown in Figure 1 , and can include the following steps.

[0095] At step 702, a first layout of the digital logic circuit (e.g., the first layout 402 in FIG. 4) is determined; wherein the first layout includes a plurality of macro cells and a plurality of standard cells. Figure 4

[0096] At step 704, a channel (e.g., the channel 500 in FIG. 5) formed between adjacent macro cells is determined. Figure 5

[0097] In some embodiments, the method further includes: determining a spacing between two adjacent macro cells; in response to a width of the spacing being less than a width threshold, determining the spacing as a channel; wherein the width threshold is calculated according to a size of the macro cells. The width threshold is calculated according to the size of the macro cells, which can dynamically adjust the judgment standard according to the size characteristics of different macro cells, adapt to the combination of different types and sizes of macro cells, enhance the universality and flexibility of the method, and improve the accuracy of channel identification.

[0098] At step 706, a target step parameter of the standard cell is determined according to positions of the standard cell and the channel based on an optimization target of the digital logic circuit; wherein the optimization target includes at least one of a wire length target, a density target, and a timing target.

[0099] In some embodiments, the method further includes: determining an initial step parameter of the standard cell based on the optimization target of the digital logic circuit; determining a step coefficient according to the positions of the standard cell and the channel and the initial step parameter; and determining the target step parameter according to the initial step parameter and the step coefficient. According to the specific position of the standard cell and the channel, the initial step parameter is dynamically adjusted, so that different standard cells can be allocated with independent step coefficients according to their positions, avoiding unreasonable layout adjustment or slow optimization caused by excessively large or small step length, and better meeting the optimization target requirements.

[0100] In some embodiments, determining the initial step parameter of the standard cell based on the optimization target of the digital logic circuit further includes: determining an objective function; calculating a function value of the objective function according to the first layout; and in response to the function value not satisfying the optimization target, calculating the initial step parameter according to the objective function. When the function value does not satisfy the optimization target, the initial step parameter is calculated according to the objective function, which can obtain the initial step according to different states of the circuit layout and optimization requirements, lay a foundation for further optimization, and improve the efficiency and pertinence of the entire optimization process.

[0101] ​​In some embodiments, calculating the initial step size parameter based on the objective function further includes: differentiating the objective function using a conjugate gradient algorithm to obtain the initial step size parameter. The conjugate gradient algorithm has a fast convergence speed and high computational efficiency, enabling the rapid and accurate acquisition of the initial step size parameter, saving computation time and resources, and improving the overall efficiency of layout optimization.

[0102] In some embodiments, the initial step size parameter includes a movement step size and a movement direction; determining a step size coefficient based on the positions of the standard cell and the channel, and the initial step size parameter, further includes: scanning the first layout using a sliding window to determine a target region in the first layout (e.g., Figure 6B Target area 602); determine the target channel in the target area (e.g., Figure 6C The method involves determining the number of target channels (604) and the standard cells located in the target area; determining the relative position of the target channels with respect to the center of the first layout; and determining the step size coefficient of the standard cells located in the target area based on the movement step size and movement direction of the standard cells, the relative position, and / or the number of target channels. Using a sliding window to scan the first layout to determine the target area allows for detailed local analysis of the layout, accurately identifying areas requiring focused attention and adjustment, i.e., the target area, avoiding blindly adjusting the entire layout and improving the targeting and efficiency of optimization. Furthermore, considering multiple factors such as the number of target channels in the target area, the relative position of the standard cells with respect to the layout center, and the initial step size parameters (movement step size and movement direction) to determine the step size coefficient ensures that the step size coefficient comprehensively reflects the position of the standard cells and the adjustment requirements, further improving the accuracy and rationality of the adjustment.

[0103] In some embodiments, a sliding window is used to scan the first layout to determine a target region in the first layout, further including: determining a first region delineated by the sliding window at the current position (e.g., Figure 6A The first region (600) is defined as follows: The area ratio of channels in the first region and / or the number of channels in the first region are determined. In response to determining that the area ratio is greater than a ratio threshold and / or the number of channels is greater than a number threshold, the first region is defined as the target region. Optimization resources (such as computation time and step size adjustment) are concentrated on high-density channel regions, reducing ineffective optimization of non-critical regions and significantly shortening the overall convergence time. Furthermore, high channel area ratio regions and densely channeled regions typically correspond to cabling congestion risks; prioritizing optimization of such regions can effectively reduce the global cabling length.

[0104] In some embodiments, determining the step length coefficient of the standard cell located in the target region based on the moving step length and the moving direction of the standard cell and the relative position and / or the number of target channels further comprises: determining whether the moving direction is away from the center of the first layout; in response to the moving direction being away from the center of the first layout, setting the step length coefficient to be less than 1; wherein the step length coefficient is negatively correlated with the distance of the relative position and / or the number of target channels; in response to the moving direction being close to the center of the first layout, setting the step length coefficient to be greater than or equal to 1. According to the relative position and the number of channels, the step length coefficient is dynamically adjusted to meet the actual needs of layout optimization, which helps to adjust the standard cell to a position more conducive to achieving the optimization goal.

[0105] In some embodiments, determining the target step length parameter according to the initial step length parameter and the step length coefficient further comprises: multiplying the step length coefficient by the moving step length to obtain a target step length; and determining the target step length parameter according to the target step length and the moving direction. The step length coefficient is determined to enable the standard cell to adjust its position in the optimization direction and to adjust the step length according to the layout environment during the movement, so as to achieve more reasonable layout optimization. At the same time, the step length adjustment does not change the original target function, ensuring the simultaneous optimization of line length, density and timing results.

[0106] In step 708, the standard cell is adjusted based on the target step length parameter to optimize the layout of the digital logic circuit.

[0107] In some embodiments, the method further comprises: moving the standard cell according to the moving direction by a moving distance corresponding to the target step length to adjust the standard cell. In combination with the moving direction (such as the gradient descent direction), the standard cell can be adjusted to a low-density region, avoiding movement in the direction of deep channels, and improving the effect of layout optimization.

[0108] In some embodiments, after adjusting the standard cell based on the target step length parameter, the method further comprises: determining a second layout (for example, a layout after the standard cell is adjusted) of the digital logic circuit after the standard cell is adjusted; and determining whether the second layout meets the optimization target. Figure 4reaches the target value, ending the layout optimization of the digital logic circuit; in response to the function value of the target function not reaching the target value, repeatedly performing the steps of determining a target step length parameter of the standard cell according to the positions of the standard cell and the channel based on the optimization target of the digital logic circuit, and adjusting the standard cell based on the target step length parameter to optimize the layout of the digital logic circuit until the optimization target is met or the number of iterations reaches a predetermined number of times. When the function value does not reach the target value, the related optimization steps are repeatedly performed until the optimization target is met or the predetermined number of iterations is reached, and this mechanism of cyclic iteration ensures that the optimization process can continue until the optimization target is as close as possible, avoiding the problem of insufficient optimization due to insufficient adjustment times or premature termination, and improving the integrity and effectiveness of the layout optimization.

[0109] The method, device and storage medium for optimizing the layout of a digital logic circuit provided by the present application can determine a first layout of the digital logic circuit, the first layout including a plurality of macro cells and a plurality of standard cells, determine a channel formed between adjacent macro cells, determine a target step length parameter of the standard cell according to the positions of the standard cell and the channel based on an optimization target of the digital logic circuit, the optimization target including at least one of a line length target, a density target and a timing target, and adjust the standard cell based on the target step length parameter to optimize the layout of the digital logic circuit. Through the method of the present application, automatic layout optimization of the digital logic circuit can be realized, the influence of the channel on the layout optimization is reduced, and the performance of the chip is further improved. At the same time, different layout features can be extracted for different optimization targets to obtain a more targeted density function value for optimizing the layout of the element.

[0110] It should be noted that the method of the embodiments of the present application can be executed by a single device, such as a computer or a server, etc. The method of the embodiments of the present application can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In this distributed scenario, one of the multiple devices can only execute one or more steps in the method of the embodiments of the present application, and the multiple devices can interact with each other to complete the method.

[0111] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than the order described above and still achieve the desired result. In addition, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0112] Based on the same technical concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method 700 according to any of the above embodiments.

[0113] The computer readable medium of the embodiments can include permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape disk storage or other magnetic storage device, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0114] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the method 700 according to any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which are not described here.

[0115] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope (including claims) of the present application is limited to these examples; the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of the different aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in detail.

[0116] Additionally, to simplify the description and discussion, and so as not to obscure the embodiments of the application being presented, the well-known functions or constructions of integrated circuit (IC) chips and other components can or can not be shown in the figures and will be omitted as not to unnecessarily obscure the embodiments of the application being presented. Moreover, the devices can be shown in block diagram form in order to avoid obscuring the embodiments of the application, and this also acknowledges the fact that the details in regard to the implementation of the block diagram devices are highly dependent on the platform within which the embodiments of the application are to be implemented (i.e., these details should be well within the purview of one of ordinary skill in the art). Where specific details are set forth in order to describe an illustrative embodiment of the application, it will be apparent to one of ordinary skill in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Thus, the description is to be considered as illustrative and not restrictive, and the scope of the application should be determined not with reference to the above description, but should be given to the appended claims.

[0117] While the application has been described in connection with specific embodiments thereof, many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0118] Embodiments of the application are intended to cover all such alternatives, modifications and variations as falling within the scope of the appended claims. Accordingly, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the application should be included in the scope of protection of the application.

Claims

1. A method for optimizing a digital logic circuit layout, characterized by, The method comprises: determining a first layout of the digital logic circuit; wherein the first layout comprises a plurality of macro cells and a plurality of standard cells; determining a channel formed between adjacent macro cells, comprising: determining a spacing between two adjacent macro cells; in response to a width of the spacing being less than a width threshold, determining that the spacing is a channel; wherein the width threshold is calculated according to a size of the macro cells; determining a target step parameter of the standard cells according to positions of the standard cells and the channels based on an optimization target of the digital logic circuit; wherein the optimization target comprises at least one of a wire length target, a density target, and a timing target; adjusting the standard cells based on the target step parameter to optimize the layout of the digital logic circuit; wherein determining a target step parameter of the standard cells according to positions of the standard cells and the channels based on an optimization target of the digital logic circuit comprises: determining an initial step parameter of the standard cells based on the optimization target of the digital logic circuit; determining a step coefficient according to positions of the standard cells and the channels and the initial step parameter; determining the target step parameter according to the initial step parameter and the step coefficient; wherein the initial step parameter comprises a moving step and a moving direction, and if the standard cell is located in a target region and the moving direction is away from a center of the first layout, the step coefficient of the standard cell is set to be less than 1, and if the standard cell is located in the target region and the moving direction is close to the center of the first layout, the step coefficient of the standard cell is set to be greater than or equal to 1; the target region is determined according to an area proportion of channels in the target region and / or a number of channels in the target region.

2. The method of claim 1, wherein, determining an initial step parameter of the standard cells based on an optimization target of the digital logic circuit comprises: determining an objective function; calculating a function value of the objective function according to the first layout; in response to the function value not satisfying the optimization target, calculating the initial step parameter according to the objective function.

3. The method of claim 2, wherein, calculating the initial step parameter according to the objective function comprises: deriving the initial step parameter by differentiating the objective function based on a conjugate gradient algorithm.

4. The method of claim 1, wherein: determining a step coefficient according to positions of the standard cells and the channels and the initial step parameter comprises: scanning the first layout using a sliding window to determine a target region in the first layout; determining a number of target channels in the target region and the standard cells located in the target region; determining a relative position of the target channels to a center of the first layout; determining the step coefficient of the standard cells located in the target region based on the moving step and the moving direction of the standard cells and the relative position and / or the number of the target channels.

5. The method of claim 4, wherein, scanning the first layout using a sliding window to determine a target region in the first layout comprises: determining a first region defined by the sliding window at the current position; determining an area proportion of the channel in the first region and / or a number of channels in the first region; in response to determining that the area proportion is greater than a proportion threshold and / or the number of channels is greater than a number threshold, determining that the first region is the target region.

6. The method of claim 4, wherein, determining the step length coefficient of the standard cell located in the target region based on the moving step length and the moving direction of the standard cell and the relative position and / or the number of target channels, comprising: determining whether the moving direction is away from the center of the first layout; in response to the moving direction being away from the center of the first layout, setting the step length coefficient to be less than 1; wherein the step length coefficient is negatively correlated with the distance of the relative position and / or the number of target channels; in response to the moving direction being close to the center of the first layout, setting the step length coefficient to be greater than or equal to 1.

7. The method of claim 4, wherein, determining the target step length parameter according to the initial step length parameter and the step length coefficient, comprising: multiplying the step length coefficient by the moving step length to obtain a target step length; determining the target step length parameter according to the target step length and the moving direction.

8. The method of claim 7, wherein, adjusting the standard cell based on the target step length parameter, comprising: moving the standard cell according to the moving distance corresponding to the target step length according to the moving direction to adjust the standard cell.

9. The method of claim 1, wherein, after adjusting the standard cell based on the target step length parameter, the method further comprises: determining a second layout after adjusting the standard cell; calculating a function value of a target function according to the second layout; in response to the function value of the target function reaching a target value, ending the layout optimization of the digital logic circuit; in response to the function value of the target function not reaching the target value, repeating the steps of determining the target step length parameter of the standard cell based on the optimization target of the digital logic circuit, and adjusting the standard cell based on the target step length parameter to optimize the layout of the digital logic circuit according to the positions of the standard cell and the channel until the optimization target is met or the number of iterations reaches a predetermined number.

10. A computer device, characterized by comprising: one or more processors, memory; and one or more programs; the one or more programs are stored in the memory and executed by the one or more processors, and the programs comprise instructions for executing the method according to any one of claims 1-9.

11. A non-transitory computer readable storage medium containing a computer program, characterized in that, when the computer program is executed by one or more processors, the processor executes the method according to any one of claims 1-9.

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