3D chip module layout method and system supporting autonomous clustering of macro-cells and multi-level modules as seeds

Abstract

The invention provides a 3D chip module layout method and system supporting autonomous clustering of macro-cells and multi-level modules as seeds. The 3D chip module layout method comprises the following steps: step 1, designating a level instance Hinst in design as a seed; 3, creating a clustering module for each seed in the seed division process; 3, inheriting network connection information of the original design, and constructing a seed-level network based on a pin connection relationship; 4, iteratively generating a 3D initial layout solution; and step 5, based on a simulated annealing algorithm, finally outputting a historical optimal 3D seed layout result, and distributing chip layer information die id in the layout result to each leaf instance in the seed. In the invention, the seed is a basic execution unit of subsequent three-dimensional layout, has the characteristics of compact structure and controllable scale, can effectively reduce the layout problem scale, keeps the local structure consistency, and remarkably improves the efficiency and quality of cross-layer division and space optimization.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design automation technology, and in particular to a 3D chip module layout method and system that supports autonomous clustering of macrocells and multi-level modules as seeds. Background Technology

[0002] With the continuous development of 3D IC technology, both academia and industry have begun to explore the use of modular clustering to reduce the scale of 3D placement, thereby improving the overall efficiency of tier partitioning and layout optimization. Existing research, such as gate-level clustering-based 3D partitioning methods, hierarchical clustering-based layered placement methods based on logical and physical relationships, and hybrid-size 3D placement methods based on electric field forces, typically group several strongly related circuit units into a logical group, allowing subsequent partitioning and placement to be performed at a higher level, thus effectively reducing the problem size. However, these clustering methods primarily serve gate-level or cell-level design flows, clustering nodes (gates or cells) in the circuit diagram, and have not been extended to a modular clustering framework that can be directly used at the hierarchy level. Furthermore, existing methods lack designer-controllable clustering strategies, failing to flexibly adapt to the planning needs of different design structures, team strategies, or multi-version projects.

[0003] In terms of commercial tools, tools like Cadence Integrity3D-IC provide a mechanism that uses hierarchical instances (hInst) as "seeds" for pre-layout, and uses these seeds as the basic optimization unit for 3D layout planning. For example, in... Figure 1 In the described hierarchical structure, hInstA and B can be set as seeds respectively; or hInstA, B / B1, B / B2, and B / B3 can each be set as independent seeds. This seeding mechanism has clear constraints: First, the tool does not support nested seed assignment; that is, if a seed is set for a node at a certain level, its sub-levels will no longer be individually configured as seeds (for example, setting both B and B / B1 as seeds is an illegal configuration); second, seed assignment must cover the entire hierarchical tree, ensuring that all modules are assigned to a seed (for example, if B / B1 and B / B2 are specified as seeds, then B / B3 must also be specified as a seed). These rules ensure the determinism and completeness of the hierarchical division, maintaining structural consistency in industrial processes.

[0004] However, its seed mechanism has obvious limitations: using a single hInst as a seed cannot merge multiple logically related but hierarchically independent modules into the same seed. These limitations lead to two extreme cases under certain hierarchical structures (e.g., a hierarchy containing numerous sub-modules): (1) The seed granularity is too large: if "parent" is used as the seed, a single large seed with a huge volume and complex internal relationships is generated, which loses the flexibility to control its internal structure and reduces the controllability when partitioning across layers. For example, as... Figure 2 As shown, the seed area in the topdie is too large, causing it to occupy a separate die, while other seeds can only adjust their positions in the bottomdie and are difficult to be assigned to the topdie. (2) Too many seeds: If "leaf" is used as the seed, too many fine-grained seeds will be generated, which will significantly increase the search scale for 3D partitioning and layout optimization. For example, as Figure 3 As shown, if we choose to split the single large seed mentioned above, many new small seeds will be formed, which will greatly increase the search scale and reduce the running speed of the method.

[0005] Therefore, while existing commercial tools provide basic seed setting capabilities, they still lack a refined, controllable, and mergeable seed partitioning mechanism in 3D module layout scenarios with complex hierarchical structures, strong module interdependencies, or the need for cross-layer structure control. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a 3D chip module layout method and system that supports autonomous clustering of macrocells and multi-level modules as seeds. In this invention, the seed is the basic execution unit for subsequent 3D layout. It has the characteristics of compact structure and controllable scale, which can effectively reduce the scale of layout problems, maintain local structural consistency, and significantly improve the efficiency and quality of cross-layer partitioning and spatial optimization.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a 3D chip module layout method that supports autonomous clustering of macrocells and multi-level modules as seeds, comprising the following steps:

[0008] Step 1: Based on the hierarchical structure of the integrated circuit design, designate the hierarchical instance Hinst in the design as a seed; wherein, the seed includes single-module seed and multi-module seed, the multi-module seed is formed by clustering and packaging multiple Hinsts; for macro units that are designated as independent seeds by the user, they are set as separate seeds, so that they are removed from the original hierarchical structure;

[0009] Step 2: During the seed partitioning process, for each seed Create a clustering module It recursively traverses all leaf instances `leaf inst` under `Hinst` contained in the seed, and adds leaf instances that are not specified as independent macrounit seeds to the clustering module. ; Calculate the clustering module The clustering module calculates the sum of the areas of all leaf instances (leaf inst) and combines this with the user-defined utilization rate. The effective area is used to set the initial geometry of the seed to a square with an effective area equal to its size.

[0010] Step 3: Inherit the net connection information of the original design, map the pin positions of the sub-modules to the geometric center of their respective clustering modules, and construct seed-level nets based on the pin connection relationships;

[0011] Step 4: Based on the seed-level net, the attractive force generated by the net connection and the repulsive force generated by the module overlap are used to generate a 2D layout solution through iterative optimization; then, the 2D layout area is divided into panes, and cross-layer partitioning is performed according to the position of the seed in the pane and the area utilization rate of the top and bottom chips, the seed is assigned to different chip layers, and a 3D initial layout solution is generated iteratively.

[0012] Step 5: Based on the simulated annealing algorithm, apply various types of perturbations to the initial 3D layout solution, including position movement, shape transformation, position exchange, and inter-layer migration; evaluate the layout state after perturbation through a multi-objective cost function, and accept or reject the perturbation according to the Metropolis criterion; the multi-objective cost function includes at least line length cost, density cost, area equalization cost, and cross-layer interconnection cost; iteratively optimize through a temperature control mechanism, and finally output the historically optimal 3D seed layout result, and assign the die id information of the chip layer in the layout result to each leaf instance inside the seed.

[0013] In a preferred embodiment, step 3 involves traversing the pins of the submodules and uniformly setting their positions to the clustering module. The geometric center of the pin is determined; simultaneously, the net corresponding to the pin is obtained, and the other modules connected to the pin in the net are traversed to obtain the clustering module to which it belongs. Then add a clustering module to the netlist. With clustering module The connection relationship is established; the original network information is inherited and converted into a seed-level network.

[0014] In a preferred embodiment, during the 3D layout process in step 4, a single-module seed or a multi-module seed is considered as a soft module with a variable aspect ratio, while a macro module seed has a fixed aspect ratio.

[0015] In a preferred embodiment, step 4, generating the 2D optimal layout, includes: first, performing mesh modeling based on the connection relationships between seeds, attracting seed modules closer together according to the mesh connections; then, using a B2B model to perform mesh modeling, constructing the matrix and force vector of the secondary layout; subsequently, applying the conjugate gradient method to solve for the coordinates of the converged seed modules; the position of each seed module will serve as the initial input for the next iteration; simultaneously, applying a layout optimization algorithm considering overlap relationships to the seed modules; using the layout result after reducing overlap in this iteration as an anchor point in the next modeling, simulating the repulsive force in the secondary layout, thereby constraining the attractive force; repeating the iteration process until the line length converges, generating the 2D optimal layout.

[0016] In a preferred embodiment, step 4, generating the 3D initial solution, includes: dividing the 2D layout area into 4×4 panes for dividing upper and lower layer modules; considering the position of the pane where the center point of the module is located, dividing the modules within the pane into the top-level chip and the bottom-level chip; during the division, if the area utilization rate of the top-level chip or the bottom-level chip exceeds a threshold, the modules are preferentially assigned to the chip with the smaller area utilization rate; after the division is completed, the chip layout area is reduced, and the 3D initial solution is iteratively generated in the top-level chip and the bottom-level chip based on the net attraction and repulsion generated by the overlap between the modules.

[0017] In a preferred embodiment, the disturbance in step 5 specifically refers to:

[0018] Position movement: Adjust the coordinates of the seed module within the temperature-adaptive movement window;

[0019] Shape transformation: Change the geometric dimensions of the seed module within a preset aspect ratio range, while the aspect ratio of the macro module seed is fixed;

[0020] Position swap: Swap the spatial positions of two seeds;

[0021] Interlayer migration: Transferring seeds to other chip layers.

[0022] In a preferred embodiment, the multi-objective combination function in step 5 is:

[0023]

[0024] in, It's the cost of a longer line. It is the area overflow rate. It is the cost of area equilibrium. It is the cost of cross-layer network interconnection. , , , These are the weighting coefficients for each cost, which are adjusted according to design requirements.

[0025] In a preferred embodiment, the cost in step 5 is calculated as follows:

[0026] (1) Cost of line length

[0027]

[0028] E is the set of nets between seeds, w e Let x be the weight of the wire mesh e. i ,y i The coordinates of the seed module i connected to net e; x j ,y j The coordinates of the seed module j connected to the net e; The half-perimeter line length of the 3D initial solution for the normalized baseline;

[0029] (2) Density cost

[0030] The layout area is divided into two-dimensional grid bins, and each two-dimensional grid bin records the soft block area density. When it is necessary to perform incremental calculations on the perturbation action to evaluate the density cost, it is necessary to determine the two-dimensional grid bin area covered by the perturbation seed before and after the perturbation. Only the density value of the affected two-dimensional grid bin is updated. The density cost change is calculated through the density difference.

[0031] (3) Cost of area balance

[0032]

[0033] Where A0 is the total area of ​​the seed contained in the lower layer chip, and A1 is the total area of ​​the seed contained in the upper layer chip;

[0034] (4) Cost of cross-layer network interconnection

[0035]

[0036] Where m is a seed module, M is the set of all seeds, |M| is the total number of seeds, and E m Let |E be the set of nets e contained in the current seed. m | indicates the number of network types contained in the current seed; when e is a cross-layer network, 1[e iscut] is 1, otherwise it is 0.

[0037] In a preferred embodiment, step 5 further includes setting initial and termination temperature thresholds for the simulated annealing algorithm, and implementing the optimization process through a two-layer loop structure. The outer loop control module runs continuously until the termination temperature or the maximum number of iterations is reached. After each outer loop iteration, the cooling rate is dynamically adjusted according to the current temperature state, and the historical optimal layout scheme is finally output. The number of iterations of the inner loop execution module is determined by the number of seeds and the inner loop coefficient. Each inner loop randomly selects and executes from four perturbation strategies. Each perturbation operation must undergo legality verification, including boundary constraint checks. The Metropolis criterion is used for perturbation acceptance decisions: when the cost change Δcost ≤ 0, the new state is automatically accepted; when Δcost > 0, it is selectively accepted with probability exp(-Δcost / T); the accepted perturbation will trigger a layout state update, and if the current cost is better than the historical record, the optimal state is updated synchronously; finally, the optimal state is used as the 3D seed layout result, and the sub-modules contained within the seed will directly inherit the die id information of their corresponding seed.

[0038] The present invention also includes a 3D chip module layout system that supports autonomous clustering of macrocells and multi-level modules as seeds, including a processor, a memory, and a bus. The memory stores machine-readable instructions executed by the processor. When the system is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, they are as described in the 3D chip module layout method that supports autonomous clustering of macrocells and multi-level modules as seeds.

[0039] Compared with existing technologies, this invention has the following advantages: By introducing a hierarchical seed partitioning mechanism, this invention enables layout planning to be performed at a higher level of abstraction, thereby significantly reducing the scale of the 3D layout problem. By supporting the clustering of independent but logically closely related modules at multiple levels into a multi-module seed, and allowing key macrounits to be independently set as individual seeds, this method can reasonably control the granularity of the seeds, ensuring that the layout avoids both excessively large single seeds and search space expansion caused by too many seeds. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the seed hierarchy structure in the prior art;

[0041] Figure 2 This is a schematic diagram of existing technology using "parent" as the seed.

[0042] Figure 3 This is a schematic diagram of existing technology using "leaf" as the seed.

[0043] Figure 4 This is an example diagram of the hierarchical modules of a preferred embodiment of the present invention;

[0044] Figure 5 This is an overall flowchart of the method according to a preferred embodiment of the present invention;

[0045] Figure 6 This is an example diagram illustrating the seed setting method of a preferred embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of window division according to a preferred embodiment of the present invention. Detailed Implementation

[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0048] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0049] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0050] This invention proposes a 3D chip module layout method that supports autonomous clustering of macrocells and multi-level modules as seeds. The aim is to construct high-quality, structurally stable, and scalable 3D module layout execution units, enabling subsequent 3D partitioning and optimization processes to operate efficiently within a reasonable problem scale. By introducing a hierarchical, controllable seed partitioning strategy, this method allows designers to flexibly set the seed granularity according to the design structure and planning requirements, thereby avoiding the problems of excessively large layout algorithm scale or excessive expansion of individual seeds, and further improving the efficiency of subsequent 3D partitioning and layout optimization. The specific algorithm flow is as follows:

[0051] 1. Hierarchical Seed Partitioning: Based on a hierarchical structure, this invention supports not only designating a single Hint as a seed, but also clustering multiple Hints into a single "multi-module seed." During seed partitioning, each seed inherits information such as the area and net connections of its contained instances, enabling subsequent layout stages to be optimized at a higher level of abstraction, ensuring structural stability and significantly reducing layout size.

[0052] In addition, this invention also supports setting key macro units as separate seeds, so that a single macro can be separated from the original hierarchical structure and participate in subsequent 3D layout as a separate seed.

[0053] Specifically, users can enter one or more hInst names to designate a seed. For each seed... This will create a clustering module. And perform the following processing on its contained hierarchical modules: For all hInst contained in the seed, recursively traverse all its submodules until the leaf instance (leafinstance, leafinst), and add all these leafinst to the seed. If a `leafinst` is a macro module specified by the user as an independent seed, then that `inst` is skipped during cluster traversal and not added to the cluster. Meanwhile, a mapping table is established between the seed and the hInst, which facilitates the subsequent allocation of die to each leaf instance based on the 3D seed layout result.

[0054] Subsequently, calculation The sum of all Leafins areas included, calculated based on the user-defined utilization rate. The effective area. The area is used as the seed The area of ​​the seed is set, and the initial geometry of the seed is set to a square with an equal area, providing a regular initial shape for subsequent 2D / 3D layout.

[0055] Next, iterate through the pins of the submodules and uniformly set their positions to the clustering module. The geometric center of the pin is determined. Simultaneously, the corresponding net is obtained, and the other modules connected to the pin within that net are traversed to obtain the clustering module to which it belongs. Then add to the netlist and The connection relationships are defined. Repeated network connections strengthen the connection weights between each other, which affects the attraction and repulsion forces between modules in subsequent layouts. This achieves the inheritance of the original net information and converts it into a seed-level net.

[0056] In the subsequent 3D layout process, a single-module seed or a multi-module seed can be regarded as a soft module with a variable aspect ratio, while a macro module seed has a fixed aspect ratio.

[0057] 2. Constructing the 3D initial solution

[0058] The floorplan size is increased, and a 2D layout solution is generated based on the attractive forces generated by the nets between seeds and the repulsive forces generated by the overlapping of modules. Then, the obtained 2D layout solution is divided into 4×4 panes using a window partitioning method. Cross-layer partitioning is performed based on the position of the seeds in the panes and the area occupancy of the two chips (top die / bottom die).

[0059] Specifically, the process begins with mesh modeling based on the connections between seeds, attracting seed modules closer together. The B2B (bound-to-bound) model effectively represents the interconnections between pins, and this invention utilizes it for mesh modeling to construct the matrix and force vectors of the secondary layout. Subsequently, the conjugate gradient method is applied to solve for the coordinates of the converged seed modules. The position of each seed module serves as the initial input for the next iteration. Simultaneously, a layout optimization algorithm considering overlap is applied to the seed modules to reduce the overlap area. The layout result after reducing overlap in this iteration is used as an anchor point in the next modeling iteration to simulate the repulsive force in the secondary layout, thereby constraining the attractive force. This iterative process is repeated until the line length converges, resulting in the optimal 2D layout.

[0060] Next, a 4×4 pane is created within the 2D layout area to divide the modules into upper and lower layers. Considering the position of the pane where the module's center point is located, the modules within the pane are assigned to the top and bottom layers of the chip. During this division, the area utilization of the two layers of chips should be kept as consistent as possible. If one layer exceeds a threshold (defaulting to the chip density before division), the module is preferentially assigned to the chip with the lower area utilization to balance the area utilization of the two chips. After the division is complete, the chip layout area is reduced (defaulting to twice the size), and the optimal 3D initial solution is iteratively generated in both layers of chips based on the attraction between the wire meshes and the repulsion caused by overlap.

[0061] 3. Simulated Annealing Optimization

[0062] After obtaining the initial 3D seed layout, this invention further optimizes the seed layout globally based on the Simulated Annealing (SA) algorithm. This invention applies multiple types of perturbations to the seeds, including: swapping the spatial positions of two seeds, moving a seed to another die, adjusting the width and height of the seeds, and translating the overall position of the seeds. Specifically:

[0063] Position movement: Adjust the coordinates of the seed module within the temperature-adaptive movement window;

[0064] Shape transformation: Change the geometric size of the seed module within the preset aspect ratio range (the aspect ratio of the macro module seed is fixed and will not be affected by this perturbation).

[0065] Position swap: Swap the spatial positions of two seeds;

[0066] Interlayer migration: Transferring seeds to other chip layers.

[0067] By simulating the temperature control mechanism of annealing, the size, coordinates, and dieid of the seed are repeatedly updated to achieve layout convergence. The main optimization objectives in this stage include: minimizing line length, reducing overlap between seeds, reducing the number of cross-layer meshes, and balancing the area of ​​the upper and lower dies.

[0068]

[0069] in, It's the cost of a longer line. It is the area overflow rate. It is the cost of area equilibrium. It is the cost of cross-layer network interconnection. , , , : These are the weighting coefficients for each cost, which can be adjusted according to design requirements.

[0070] The four costs are calculated as follows:

[0071] (1) Cost of line length

[0072]

[0073] E is the set of nets between seeds, w e Let x be the weight of the wire mesh e. i ,y i The coordinates of the seed module i connected to the net e; The semi-circumference line length of the 3D initial solution for the normalized baseline.

[0074] (2) Density cost

[0075] The layout area is divided into two-dimensional grid bins (each bin records the soft block area density); when incremental calculations are needed to evaluate the density cost of perturbation actions, it is necessary to determine the bin area covered by the perturbation seed before and after the perturbation; only the density value is updated for the affected bins; the density cost change is calculated through density differences.

[0076] (3) Cost of area balance

[0077]

[0078] Where A0 represents the total area of ​​the seed module contained in the lower-layer chip, and A1 represents the total area of ​​the seed module contained in the upper-layer chip. The goal of this module design is to maintain a balanced area distribution of the seed module across different chips in a 3D chip.

[0079] (4) Cost of cross-layer network interconnection

[0080]

[0081] Where m is a seed module, M is the set of all seeds, |M| is the total number of seeds, and E m Let |E| be the set of networks e contained in the current seed. m |: The number of network types contained in the current seed. When 'e' is a cross-layer network, 1[eiscut] is 1; otherwise, it is 0. The goal of this module design is to minimize cross-layer network connections, reducing wiring complexity and manufacturing costs.

[0082] An initial and final temperature thresholds are set for the simulated annealing algorithm, and the optimization process is implemented through a two-layer loop structure. The outer loop control module runs continuously until the final temperature or the maximum number of iterations is reached. After each outer loop iteration, the cooling rate is dynamically adjusted according to the current temperature state, and the historical optimal layout scheme is finally output. The number of iterations of the inner loop execution module is determined by the seed number and the inner loop coefficient. Each inner loop randomly selects and executes one of four perturbation strategies. Each perturbation operation must undergo legality verification, including boundary constraint checks and overlap assessment. The Metropolis criterion is used for perturbation acceptance decisions: when the cost change Δcost ≤ 0, the new state is automatically accepted; when Δcost > 0, it is selectively accepted with probability exp(-Δcost / T). The accepted perturbation will trigger a layout state update, and if the current cost is better than the historical record, the optimal state is updated synchronously.

[0083] Ultimately, the optimal state is used as the 3D seed layout result, and the sub-modules contained within the seed will directly inherit the dieid information of their corresponding seed.

[0084] In this invention, when specifying a seed, users can not only directly set a single-level module as an independent seed, just like in traditional tools, but also cluster multiple level modules into a multi-module seed. Furthermore, this invention further supports macro modules being detached from their original hierarchical structure and set as independent seeds. For example, a schematic diagram of the hierarchical modules for a user-specified seed is shown below. Figure 4 As shown in the diagram. In the diagram, top, A, B, B / B1, B / B2, and B / B3 are all hierarchical modules. The top module contains two sub-modules, A and B; sub-modules under A are omitted in the diagram; B contains three lower-level modules: B / B1, B / B2, and B / B3. Assuming there is a macro module macro1 under B / B1, other instances are also omitted in the diagram. User-configurable settings:

[0085] (1) Single module seed: A and B can be designated as two seeds respectively; or A, B / B1, B / B2, and B / B3 can be designated as four seeds respectively;

[0086] (2) Multi-module seed: B / B1 and B / B2 can be clustered into one seed, while B / B3 and A can be used as independent seeds respectively; or A, B / B1, and B / B2 can be clustered into a larger multi-module seed, with B / B3 used as another independent seed.

[0087] (3) Macro module seed: B / B1 / macro1 can be designated as a separate seed, which will no longer contain other instances as an independent layout unit; at the same time, macro1 will no longer be clustered into the seed to which B / B1 belongs.

[0088] The overall flowchart of this algorithm is as follows: Figure 5 As shown, after the user specifies the seed, the subsequent 3D layout will be performed using the seed as the basic execution unit, and finally the seed will be placed on the topdie and bottomdie.

[0089] Assuming in Figure 4 In the hierarchical structure shown, the user selects to package A, B / B1, and B / B2 into a multi-module seed, and B / B3 as an independent seed. The macro module is also set as an independent seed. The seed setting method is as follows: Figure 6 As shown. For each seed This will create a clustering module. And perform the following processing on the hierarchical modules contained in the seed: For all hierarchical modules contained in the seed (such as A, B / B1, B / B2 in seed 1), recursively traverse all its sub-modules until the leaf instance (leafinstance, leafinst), and add all these leafinst to the seed. In the middle, if a certain leafinst is a macromodule specified by the user as an independent seed (such as B / B1 / macro1), then this inst is skipped during cluster traversal and not added to the cluster. middle.

[0090] Subsequently, calculation The sum of all Leafins areas included, calculated based on the user-defined utilization rate. The effective area. The area is used as the seed The area of ​​the seed is determined, and the initial geometry is set to a square with an equal area, providing a regular initial shape for subsequent 2D / 3D layout. Figure 6In the seed settings shown, seed 1 includes all instances under A, B / B1, and B / B2 except for B / B1 / macro1. Therefore, the area of ​​B / B1 / macro1 will not be included in the area calculation. Seed 2, on the other hand, only includes B / B1 / macro1, so only the area of ​​macro1 needs to be calculated.

[0091]

[0092] Simultaneously, iterate through the pins of the submodules and uniformly set their positions to the clustering module. The geometric center of the pin is determined. Simultaneously, the corresponding net is obtained, and the other modules connected to the pin within that net are traversed to obtain the clustering module to which it belongs. Then add to the netlist and The connection relationships are defined. Repeated network connections strengthen the connection weights between each other, which affects the attraction and repulsion forces between modules in subsequent layouts. This achieves the inheritance of the original net information and converts it into a seed-level net.

[0093] After obtaining the seeds according to the above process, we perform wire mesh modeling based on the connection relationships between the seeds, constructing the matrices and vectors required for the secondary layout. At this stage, we only consider the attractive forces between the seed connections and the repulsive forces generated by module overlap, obtaining the optimal layout result in the 2D plane through iterative solution. Subsequently, as... Figure 7 As shown, the 2D plane is divided into 4×4 pane areas and used for the division of upper and lower modules; according to the position of the pane where the center point of each seed is located, the seeds in the pane are assigned to the top or bottom layer chips, thereby generating the initial solution of the 3D seed layout.

[0094] Finally, simulated annealing is used to globally optimize the initial 3D seed layout. During the annealing process, various perturbation operations are applied to the seeds, including: swapping the spatial positions of two seeds, moving a seed to another die, adjusting the width and height of the seeds, and translating the overall position of the seeds, thereby continuously updating the spatial coordinates, size parameters, and dieid of the seeds. The main optimization objectives in this stage include: minimizing line length, reducing overlap between seeds, reducing the number of cross-layer meshes, and balancing the area of ​​the upper and lower dies. Ultimately, after obtaining the 3D seed layout, the sub-modules contained within a seed will directly inherit the dieid information of their corresponding seed.

Claims

1. A 3D chip module layout method that supports autonomous clustering of macrocells and multi-level modules as seeds, characterized in that, Includes the following steps: Step 1: Based on the hierarchical structure of the integrated circuit design, designate the hierarchical instance Hinst in the design as a seed; wherein, the seed includes single-module seed and multi-module seed, the multi-module seed is formed by clustering and packaging multiple Hinsts; for macro units that are designated as independent seeds by the user, they are set as separate seeds, so that they are removed from the original hierarchical structure; Step 2: During the seed partitioning process, for each seed Create a clustering module It recursively traverses all leaf instances `leaf inst` under `Hinst` contained in the seed, and adds leaf instances that are not specified as independent macrounit seeds to the clustering module. ; Calculate the clustering module The clustering module calculates the sum of the areas of all leaf instances (leaf inst) and combines this with the user-defined utilization rate. The effective area is used to set the initial geometry of the seed to a square with an effective area equal to its size. Step 3: Inherit the net connection information of the original design, map the pin positions of the sub-modules to the geometric center of their respective clustering modules, and construct seed-level nets based on the pin connection relationships; Step 4: Based on the seed-level net, the attractive force generated by the net connection and the repulsive force generated by the module overlap are used to generate a 2D layout solution through iterative optimization; then, the 2D layout area is divided into panes, and cross-layer partitioning is performed according to the position of the seed in the pane and the area utilization rate of the top and bottom chips, the seed is assigned to different chip layers, and a 3D initial layout solution is generated iteratively. Step 5: Based on the simulated annealing algorithm, apply various types of perturbations to the initial 3D layout solution, including position movement, shape transformation, position exchange, and inter-layer migration; evaluate the layout state after perturbation through a multi-objective cost function, and accept or reject the perturbation according to the Metropolis criterion; the multi-objective cost function includes at least line length cost, density cost, area equalization cost, and cross-layer interconnection cost; iteratively optimize through a temperature control mechanism, and finally output the historically optimal 3D seed layout result, and assign the die id information of the chip layer in the layout result to each leaf instance inside the seed.

2. The 3D chip module layout method according to claim 1, which supports autonomous clustering of macrocells and multi-level modules as seeds, is characterized in that, In step 3, the pins of the submodules are traversed, and their positions are uniformly set to the clustering module. The geometric center of the pin is determined; simultaneously, the net corresponding to the pin is obtained, and the other modules connected to the pin in the net are traversed to obtain the clustering module to which it belongs. Then add a clustering module to the netlist. With clustering module The connection relationship is established; the original network information is inherited and converted into a seed-level network.

3. The 3D chip module layout method according to claim 1, which supports autonomous clustering of macrocells and multi-level modules as seeds, is characterized in that... In the 3D layout process of step 4, a single-module seed or a multi-module seed is regarded as a soft module with a variable aspect ratio, while the macro module seed has a fixed aspect ratio.

4. The 3D chip module layout method according to claim 1, which supports autonomous clustering of macrocells and multi-level modules as seeds, is characterized in that... Step 4, generating the 2D optimal layout, includes: first, performing mesh modeling based on the connection relationships between seeds, attracting seed modules closer together according to the mesh connections; next, using a B2B model to perform mesh modeling, constructing the matrix and force vector of the secondary layout; then, applying the conjugate gradient method to solve for the coordinates of the converged seed modules; the position of each seed module will serve as the initial input for the next iteration; simultaneously, applying a layout optimization algorithm considering overlap relationships to the seed modules; using the layout result after reducing overlap in this iteration as an anchor point in the next modeling, simulating the repulsive force in the secondary layout, thereby constraining the attractive force; repeating the iteration process until the line length converges, generating the 2D optimal layout.

5. A 3D chip module layout method supporting autonomous clustering of macrocells and multi-level modules as seeds, as described in claim 1, characterized in that, Step 4, generating the 3D initial solution, includes: dividing the 2D layout area into 4×4 panes to divide the upper and lower layer modules; considering the position of the pane where the center point of the module is located, dividing the modules within the pane into the top layer chip and the bottom layer chip; during the division, if the area utilization rate of the top layer chip or the bottom layer chip exceeds a threshold, the modules are preferentially assigned to the chip with the smaller area utilization rate; after the division is completed, the chip layout area is reduced, and the 3D initial solution is iteratively generated in the top layer chip and the bottom layer chip according to the net attraction and repulsion generated by the overlap between the modules.

6. A 3D chip module layout method supporting autonomous clustering of macrocells and multi-level modules as seeds, as described in claim 1, is characterized in that... The disturbance in step 5 is specifically as follows: Position movement: Adjust the coordinates of the seed module within the temperature-adaptive movement window; Shape transformation: Change the geometric dimensions of the seed module within a preset aspect ratio range, while the aspect ratio of the macro module seed is fixed; Position swap: Swap the spatial positions of two seeds; Interlayer migration: Transferring seeds to other chip layers.

7. A 3D chip module layout method supporting autonomous clustering of macrocells and multi-level modules as seeds, as described in claim 1, characterized in that, The multi-objective combination function in step 5: in, It's the cost of a longer line. It is the area overflow rate. It is the cost of area equilibrium. It is the cost of cross-layer network interconnection. , , , These are the weighting coefficients for each cost, which are adjusted according to design requirements.

8. A 3D chip module layout method supporting autonomous clustering of macrocells and multi-level modules as seeds, as described in claim 1, characterized in that, The cost in step 5 is calculated as follows: (1) Cost of line length E is the set of nets between seeds, w e Let x be the weight of the wire mesh e. i ,y i The coordinates of the seed module i connected to net e; x j ,y j The coordinates of the seed module j connected to the net e; The half-perimeter line length of the 3D initial solution for the normalized baseline; (2) Density cost The layout area is divided into two-dimensional grid bins, and each two-dimensional grid bin records the soft block area density. When it is necessary to perform incremental calculations on the perturbation action to evaluate the density cost, it is necessary to determine the two-dimensional grid bin area covered by the perturbation seed before and after the perturbation. Only the density value of the affected two-dimensional grid bin is updated. The density cost change is calculated through the density difference. (3) Cost of area balance Where A0 is the total area of ​​the seed contained in the lower layer chip, and A1 is the total area of ​​the seed contained in the upper layer chip; (4) Cost of cross-layer network interconnection Where m is a seed module, M is the set of all seeds, |M| is the total number of seeds, and E m Let |E be the set of nets e contained in the current seed. m | indicates the number of network types contained in the current seed; when e is a cross-layer network, 1[e is cut] is 1, otherwise it is 0.

9. A 3D chip module layout method supporting autonomous clustering of macrocells and multi-level modules as seeds, as described in claim 1, characterized in that, Step 5 further includes setting initial and termination temperature thresholds for the simulated annealing algorithm, and implementing the optimization process through a two-layer loop structure; the outer loop control module runs continuously until the termination temperature or the maximum number of iterations is reached; after each outer loop iteration, the cooling rate is dynamically adjusted according to the current temperature state, and finally the historical optimal layout scheme is output; the number of iterations of the inner loop execution module is determined by the number of seeds and the internal loop coefficient, and each inner loop randomly selects and executes from four perturbation strategies; each perturbation operation must undergo legality verification, including boundary constraint checks; the Metropolis criterion is used for perturbation acceptance decisions: when the cost change Δcost≤0, the new state is automatically accepted; when Δcost>0, it is selectively accepted with probability exp(-Δcost / T); the accepted perturbation will trigger a layout state update, and if the current cost is better than the historical record, the optimal state is updated synchronously; finally, the optimal state is used as the 3D seed layout result, and the sub-modules contained within the seed will directly inherit the die id information of their corresponding seed.

10. A 3D chip module layout system supporting autonomous clustering of macrocells and multi-level modules as seeds, comprising a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executed by the processor; characterized in that, When the system is running, the processor communicates with the memory via a bus, and the machine-readable instructions are executed by the processor as described in any one of claims 1 to 9, which is a 3D chip module layout method that supports autonomous clustering of macrocells and multi-level modules as seeds.

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