Collaborative storage system and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of collaborative design of field programmable gate arrays and high-speed memories, in particular to a collaborative storage system and method based on an FPGA. The system comprises an input interface module used for receiving access instructions and data of the FPGA; the dynamic storage decision module is used for dynamically adjusting a data partitioning strategy according to the real-time data characteristics and the system resource state; the address mapping unit is used for maintaining a mapping table of logic addresses and physical storage addresses; the SRAM controller and the DDR controller are used for realizing sequential control and access operation of the SRAM and the DDR; the parallel access pipeline module is used for dividing a data storage and reading process into a plurality of parallel stages through hardware parallelism and a pipeline architecture; and the CRC verification module is used for verifying the access data and comparing the access data with the verification value in the mapping table. The storage speed and the system throughput are remarkably improved.

Description

Technical Field

[0001] The present application relates to the technical field of collaborative design of field programmable gate arrays and high-speed memories, and to a collaborative storage system and method based on FPGA. Background Art

[0002] In modern electronic system design, FPGAs (field-programmable gate arrays) have been widely used in fields such as communications, image processing, and industrial control due to their high flexibility, reconfigurability, and powerful parallel processing capabilities. To meet the growing data storage needs of FPGAs, external memory has become a common solution, with DDR (double data rate memory) and SRAM (random access memory) being two widely used storage media. However, in practical applications, external DDR and SRAM memories for FPGAs face numerous challenges, especially when processing fragmented data (such as network packets and small data blocks collected by sensors).

[0003] Fragmented data is discontinuous and small in size, requiring frequent address switching when processing FPGAs. When using DDR as the storage medium, each address switch requires time to complete operations such as address decoding, row activation, and column access. Frequent address switching not only increases system complexity but also significantly impacts DDR memory throughput, limiting overall system performance. Furthermore, DDR read and write operations typically adhere to specific timing specifications, making FPGA read and write control of DDR difficult.

[0004] While SRAM offers fast read and write speeds, enabling quick data access, its limited capacity makes it difficult to directly store large amounts of data. When processing large amounts of data, SRAM often falls short. Furthermore, SRAM is relatively expensive, significantly increasing system costs if solely reliant on SRAM for data storage.

[0005] To address these issues, existing solutions typically rely on a single memory controller or simple caching strategies to manage memory usage. However, these solutions often fail to effectively leverage the complementary strengths of DDR and SRAM, failing to balance fast data access with improved storage efficiency. For example, some solutions may overly rely on the large storage capacity of DDR, storing all data in DDR and ignoring the impact of fragmented data on storage efficiency, resulting in poor system performance when processing fragmented data. Other solutions may overemphasize the fast access characteristics of SRAM, storing large amounts of data in SRAM, but are limited by its limited storage capacity and cannot meet the needs of large-scale data storage.

[0006] In summary, existing technologies for handling FPGA-attached external DDR and SRAM memories have numerous shortcomings, particularly in optimizing the storage and access efficiency of fragmented data. Therefore, there is an urgent need for a solution that can fully leverage the respective advantages of DDR and SRAM to achieve collaborative storage, thereby improving the overall access efficiency of FPGAs to external storage areas and meeting the demands of modern electronic systems for high-performance, high-efficiency data storage. It should be noted that the information disclosed in the above background section is intended only to enhance understanding of the background of this application and, therefore, may include information that does not constitute prior art known to persons of ordinary skill in the art. Summary of the Invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide an FPGA-based collaborative storage system and method to optimize the storage and access efficiency of fragmented data and improve the overall access efficiency of the FPGA to the external storage area.

[0009] In some embodiments, the system comprises: Input interface module, used to receive access instructions and data from FPGA; Dynamic storage decision module, used to dynamically adjust the data block strategy according to real-time data characteristics and system resource status, storing data packets with lengths less than or equal to a preset threshold into SRAM, and storing data packets with lengths greater than the threshold in batches into DDR; An address mapping unit, configured to maintain a mapping table between a logical address and a physical storage address, wherein the mapping table includes a logical address, a storage medium type, a physical address, and additional information; The SRAM controller and DDR controller are used to implement the timing control and access operations of SRAM and DDR respectively; The parallel access pipeline module divides the data storage and reading process into multiple parallel stages through hardware parallelism and pipeline architecture, including data reception and classification, block division and address allocation, SRAM reading and writing, DDR batch reading and writing, and data verification. The CRC check module is used to check the access data and compare it with the check value in the mapping table.

[0010] Preferably, the dynamic storage decision module is further configured to: When the remaining space in the SRAM is less than a set threshold, the preset threshold is dynamically adjusted to reduce the probability of storing the data packet in the SRAM.

[0011] Preferably, the additional information in the address mapping table includes data length and CRC check value, the logical address is an application layer visible address, and the physical address is an actual storage address of SRAM or DDR.

[0012] Preferably, the multiple parallel stages of the parallel access pipeline module include: Complete data reception and classification through the input interface module; Data segmentation and address allocation are completed through dynamic storage decision module and address mapping unit; The SRAM controller is used to write or read the SRAM. Complete DDR batch writing or reading through the DDR controller; Data verification is completed through the CRC verification module.

[0013] Preferably, the dynamic storage decision module optimizes the triggering conditions for batch writing according to the DDR bandwidth load status when dividing data into blocks.

[0014] Preferably, the system is suitable for storing and accessing fragmented data in 5G communication or high-speed image processing scenarios.

[0015] In some embodiments, a collaborative storage method based on FPGA includes the following steps: Receive access instructions and data from FPGA; Dynamically adjust the block strategy based on the packet size and the remaining SRAM space, storing packets with lengths less than or equal to the threshold into SRAM and packets with lengths greater than the threshold into DDR in batches; Maintain a mapping table between logical addresses and physical storage addresses and record additional information; Complete SRAM and DDR reading and writing, as well as data verification through parallel pipeline operations; When reading data, the storage medium and physical address are located according to the mapping table, and the data integrity is verified through CRC check.

[0016] Preferably, the parallel pipeline operation includes multiple stages with overlapping timing, each stage being executed by an independent hardware module to maximize system throughput.

[0017] In some embodiments, the device includes: a processor and a memory storing program instructions, and the processor is configured to execute the FPGA-based collaborative storage method when running the program instructions.

[0018] In some embodiments, the storage medium stores a computer program thereon, and when the program is executed by a processor, the FPGA-based collaborative storage method is implemented.

[0019] The embodiments of the present disclosure provide an FPGA-based collaborative storage system and method, which can achieve the following technical effects: This invention addresses the efficiency bottleneck of fragmented data storage through dynamic storage allocation and address mapping mechanisms. The system caches fragmented data in SRAM and stores large data blocks in DDR. Combining parallel read and write with dynamic scheduling strategies significantly improves storage speed and system throughput. It is suitable for scenarios requiring high real-time performance, such as 5G communications and high-speed image processing.

[0020] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition, Figure 1 It is a schematic diagram of the overall system architecture; Figure 2 Flowchart for data segmentation and storage; Figure 3 This is an example diagram of an address mapping table.

[0022] Figure 4 is a schematic diagram of the method flow chart; Figure 5 It is a schematic diagram of the device structure of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0024] In the description and claims of the embodiments of the present disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to describe the embodiments of the present disclosure herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0025] Unless otherwise stated, the term "plurality" means two or more.

[0026] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0027] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0028] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0029] Example 1 A collaborative storage system based on FPGA, Figure 1 This is the main module of this system and the connection relationship between each module. The module consists of input interface module, dynamic storage decision module, address mapping unit, CRC check module, parallel access pipeline module, SRAM controller and DDR controller.

[0030] Optimize the storage and access efficiency of fragmented data and improve the overall access efficiency of FPGA to external storage areas.

[0031] In some embodiments, the system comprises: The input interface module is used to receive access instructions and data from the FPGA.

[0032] The dynamic storage decision module is used to dynamically adjust the data block strategy according to the real-time data characteristics and system resource status, store data packets with lengths less than or equal to the preset threshold into SRAM, and store data packets with lengths greater than the threshold in batches into DDR.

[0033] The address mapping unit is used to maintain a mapping table between logical addresses and physical storage addresses, wherein the mapping table includes logical addresses, storage medium types, physical addresses and additional information.

[0034] The SRAM controller and DDR controller are used to implement timing control and access operations of SRAM and DDR respectively.

[0035] The parallel access pipeline module divides the data storage and reading process into multiple parallel stages through hardware parallelism and pipeline architecture, including data reception and classification, block division and address allocation, SRAM reading and writing, DDR batch reading and writing, and data verification stages.

[0036] The CRC check module is used to check the access data and compare it with the check value in the mapping table.

[0037] The CRC check module verifies accessed data and compares it with the checksum in the mapping table. This allows for timely detection of data errors during storage and transmission, ensuring data integrity and accuracy. Once a data error is detected, the system can promptly take appropriate measures to correct or re-store the data, avoiding system failures or service interruptions caused by data errors.

[0038] As a refinement of the above embodiment, the dynamic storage decision unit is responsible for dynamically adjusting the data block strategy according to real-time data characteristics (packet size) and system resource status (such as SRAM remaining space) to decide whether the data block is stored in DDR or SRAM.

[0039] Data blocking strategy: Data packets with a length less than or equal to a preset threshold (Lt) are stored in SRAM and the SRAM physical address is recorded. If the packet length is greater than the threshold (Lt), the packet is stored in DDR through batch write mode and the DDR physical address is recorded.

[0040] The dynamic storage decision module dynamically adjusts the data segmentation strategy based on real-time data characteristics and system resource status, rationally allocating data packets of varying lengths to SRAM and DDR for storage. Packets with lengths less than or equal to a preset threshold are stored in SRAM, while packets longer than the threshold are stored in batches in DDR. This avoids the efficiency bottleneck of a single storage medium when processing diverse data, fully leveraging the high-speed read and write capabilities of SRAM and the large storage capacity of DDR, effectively improving the storage efficiency of fragmented data.

[0041] The dynamic storage decision module is further configured to: When the remaining space in the SRAM is less than a set threshold, the preset threshold is dynamically adjusted to reduce the probability of storing the data packet in the SRAM, thereby achieving dynamic allocation of data storage.

[0042] The dynamic storage decision module dynamically adjusts the data segmentation strategy based on real-time data characteristics and system resource status, rationally allocating data packets of varying lengths to SRAM and DDR for storage. Packets with lengths less than or equal to a preset threshold are stored in SRAM, while packets longer than the threshold are stored in batches in DDR. This avoids the efficiency bottleneck of a single storage medium when processing diverse data, fully leveraging the high-speed read and write capabilities of SRAM and the large storage capacity of DDR, effectively improving the storage efficiency of fragmented data.

[0043] When the remaining SRAM space is less than the set threshold, the dynamic storage decision module can dynamically adjust the preset threshold to reduce the probability of data packets being stored in the SRAM, thereby ensuring that the SRAM has enough space to process subsequent urgent or important data, avoiding system performance degradation or data loss due to insufficient SRAM space, and improving system stability and reliability.

[0044] As a refinement of the above embodiment, the address mapping unit is used to form a management address mapping table, which is maintained by the FPGA master control module and is used to record the mapping relationship between the logical address (application layer visible address) and the physical storage address (SRAM / DDR actual address) to support rapid positioning and jumping of data blocks.

[0045] The address mapping table includes a logical address, a storage medium type, a physical address corresponding to the storage medium, and additional information.

[0046] The additional information includes data length and data CRC checksum. The additional information in the address mapping table, including data length and CRC checksum, provides a more comprehensive reference for data storage and access, helping the system better manage and maintain data. It also provides an important basis for data troubleshooting and recovery.

[0047] The address mapping unit maintains a mapping table between logical addresses and physical storage addresses, enabling the FPGA to quickly locate the actual storage location when accessing data, reducing the time overhead of address translation. The parallel access pipeline module leverages hardware parallelism and a pipeline architecture to divide the data storage and reading process into multiple parallel stages. This enables parallel processing of data reception and classification, block segmentation and address allocation, SRAM read and write, DDR batch read and write, and data verification. This significantly reduces data access latency and improves the overall efficiency of the FPGA's access to external storage areas.

[0048] Specifically, such as Figure 3 As shown, the address mapping table contains the logical address of the stored data, the storage medium type, the SRAM or DDR physical address corresponding to the logical address, and additional information. The additional information includes the length of the stored data block and the CRC checksum of the data block. When writing data, the mapping table corresponding to the logical address needs to be updated. When reading data, the address mapping table must be read first to obtain the memory type and physical address corresponding to the logical address. After reading the data, a CRC check is performed and compared with the CRC checksum value in the mapping table to determine the correctness of the read data.

[0049] As a refinement of the above embodiment, the parallel access pipeline achieves timing overlap of read and write operations and data verification between DDR and SRAM through the hardware parallelism and pipeline architecture of FPGA, thereby maximizing the storage system throughput.

[0050] The parallel access pipeline divides the storage and reading process of fragmented data into five parallel stages, each of which is executed by an independent hardware module, forming a pipeline operation: Stage 1: Data reception and classification, completed by the input interface module; Stage 2: Data segmentation and address allocation, completed by the storage decision module and address mapping unit; Stage 3: SRAM write / read, completed by the SRAM controller; Stage 4: DDR batch write / read, completed by the DDR controller; Stage 5: Data verification, completed by the CRC verification unit.

[0051] As a refinement of the above embodiment, the dynamic storage decision module optimizes the triggering conditions for batch writing according to the DDR bandwidth load status when partitioning data.

[0052] The system is suitable for storing and accessing fragmented data in 5G communication or high-speed image processing scenarios.

[0053] It should be noted that this system is suitable for storing and accessing fragmented data in 5G communications or high-speed image processing scenarios. 5G communications feature high data rates, high volumes of data traffic, and fragmented data. This system can efficiently store and access this fragmented data, meeting the real-time and reliability requirements of 5G communications. In high-speed image processing scenarios, image data is often highly fragmented. This system can rapidly store and process image data, providing efficient data support for image processing algorithms and improving both efficiency and quality.

[0054] Example 2 like Figure 4 As shown, a collaborative storage method based on FPGA includes the following steps: S1: Receives access instructions and data from FPGA.

[0055] S2: Dynamically adjust the blocking strategy based on the packet size and the remaining SRAM space, storing packets with lengths less than or equal to the threshold into SRAM and packets with lengths greater than the threshold into DDR in batches.

[0056] S3: Maintains a mapping table between logical addresses and physical storage addresses, and records additional information.

[0057] S4: Completes SRAM and DDR reading and writing, as well as data verification through parallel pipeline operations.

[0058] S5: When reading data, the storage medium and physical address are located according to the mapping table, and the data integrity is verified through CRC check.

[0059] As a refinement of the above embodiment, the input interface module receives a data storage instruction and data to be stored.

[0060] The dynamic storage decision module obtains the data size and makes a judgment. The decision strategy is: packets with a length less than or equal to a preset threshold (Lt) are stored in SRAM. Packets longer than the threshold (Lt) are stored in DDR. When the remaining SRAM space is less than a set threshold, the preset threshold Lt is adjusted to reduce the SRAM storage probability.

[0061] As a refinement of the above embodiment, the parallel pipeline operation includes multiple stages with overlapping timing, and each stage is executed by an independent hardware module to maximize system throughput.

[0062] Combine Figure 5 As shown, an embodiment of the present disclosure provides an FPGA-based collaborative storage device 300, including a processor 304 and a memory 301. Optionally, the device may also include a communication interface 302 and a bus 303. The processor 304, communication interface 302, and memory 301 may communicate with each other via bus 303. The communication interface 302 may be used for information transmission. The processor 304 may invoke logic instructions in the memory 301 to execute the FPGA-based collaborative storage method of the above embodiment.

[0063] In addition, the logic instructions in the memory 301 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0064] Memory 301, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 304 executes the program instructions / modules stored in memory 301 to execute functional applications and data processing, thereby implementing the FPGA-based collaborative storage method in the above-mentioned embodiments.

[0065] The memory 301 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory 301 may include high-speed random access memory and non-volatile memory.

[0066] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned FPGA-based collaborative storage method.

[0067] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0068] The technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, and other media that can store program code, or a transient storage medium.

[0069] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. Moreover, the terms used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, the singular forms "a", "an" and "the" are intended to also include the plural forms unless the context clearly indicates otherwise. Similarly, the term "and / or" as used in this application means any and all possible combinations of one or more of the associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, an element defined by the sentence "comprising a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be referred to the description of the method part.

[0070] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0071] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices and equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units may be merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or omitting or disabling some features. In addition, the coupling or direct coupling or communication connection shown or discussed between each other may be through some interface, or the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to implement the present embodiments according to actual needs. In addition, the functional units in the embodiments of the present disclosure may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0072] The flowcharts and block diagrams in the accompanying drawings show the possible implementation architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A collaborative storage system based on FPGA, characterized in that: include: Input interface module, used to receive access instructions and data from FPGA; Dynamic storage decision module, used to dynamically adjust the data block strategy according to real-time data characteristics and system resource status, storing data packets with lengths less than or equal to a preset threshold into SRAM, and storing data packets with lengths greater than the threshold in batches into DDR; An address mapping unit, configured to maintain a mapping table between a logical address and a physical storage address, wherein the mapping table includes a logical address, a storage medium type, a physical address, and additional information; The SRAM controller and DDR controller are used to implement the timing control and access operations of SRAM and DDR respectively; The parallel access pipeline module divides the data storage and reading process into multiple parallel stages through hardware parallelism and pipeline architecture, including data reception and classification, block division and address allocation, SRAM reading and writing, DDR batch reading and writing, and data verification. The CRC check module is used to check the access data and compare it with the check value in the mapping table.

2. The FPGA-based collaborative storage system according to claim 1, characterized in that: The dynamic storage decision module is further configured to: When the remaining space in the SRAM is less than a set threshold, the preset threshold is dynamically adjusted to reduce the probability of storing the data packet in the SRAM.

3. The FPGA-based collaborative storage system according to claim 1, wherein: The additional information in the address mapping table includes data length and CRC check value. The logical address is an application layer visible address, and the physical address is an actual storage address of SRAM or DDR.

4. The FPGA-based collaborative storage system according to claim 1, wherein: The multiple parallel stages of the parallel access pipeline module include: Complete data reception and classification through the input interface module; Data segmentation and address allocation are completed through dynamic storage decision module and address mapping unit; The SRAM controller is used to write or read the SRAM. Complete DDR batch writing or reading through the DDR controller; Data verification is completed through the CRC verification module.

5. The FPGA-based collaborative storage system according to claim 1, wherein: The dynamic storage decision module optimizes the triggering conditions for batch writing according to the DDR bandwidth load status when dividing data into blocks.

6. The FPGA-based collaborative storage system according to claim 1, wherein: The system is suitable for storing and accessing fragmented data in 5G communication or high-speed image processing scenarios.

7. A collaborative storage method based on FPGA, characterized in that: The following steps are involved: Receive access instructions and data from FPGA; Dynamically adjust the block strategy based on the packet size and the remaining SRAM space, storing packets with lengths less than or equal to the threshold into SRAM and packets with lengths greater than the threshold into DDR in batches; Maintain a mapping table between logical addresses and physical storage addresses and record additional information; Complete SRAM and DDR reading and writing, as well as data verification through parallel pipeline operations; When reading data, the storage medium and physical address are located according to the mapping table, and the data integrity is verified through CRC check.

8. The FPGA-based collaborative storage method according to claim 7, characterized in that: The parallel pipeline operation includes multiple stages with overlapping timing, and each stage is executed by an independent hardware module to maximize system throughput.

9. A collaborative storage device based on FPGA, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the FPGA-based collaborative storage method according to claim 7 or 8 when running the program instructions.

10. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the program is executed by a processor, the FPGA-based collaborative storage method as described in claim 7 or 8 is implemented.

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