Hybrid system calculation method and system for dynamic configuration, chip and storage medium

Abstract

The invention provides a dynamically-configured mixed system calculation method and system, a chip and a storage medium. The method comprises the steps that metadata and data labels of two operands participating in a target calculation instruction are read; respectively writing the two operands into two target registers according to a calculation mode; and distributing a corresponding calculation unit for the target calculation instruction for calculation according to tag bits of the two target registers. According to the hybrid system calculation method and system, the chip and the storage medium provided by the embodiment of the invention, native instruction support is provided for hybrid system calculation, a dynamic register combination mechanism allows flexible adjustment of an arithmetic unit according to task requirements, and power consumption is remarkably reduced through strategies such as idle state closing, dynamic voltage adjustment and frequency scaling; multiple ternary modes and operation units with different lengths are supported, larger numerical values and complex tasks can be easily expanded, and different application requirements are met.

Description

Technical Field

[0001] The present application relates to the field of computer systems, and in particular to a dynamically configured mixed-base calculation method, system, chip, and storage medium. Background Art

[0002] In traditional computer architecture, binary computing systems dominate. However, with the rapid development of fields such as the Internet of Things and artificial intelligence, the demand for diversified data types and high-efficiency computing is increasing. Ternary computing, with its unique advantages, exhibits higher efficiency and accuracy in certain application scenarios. However, existing computer architectures find it difficult to effectively support ternary computing. The main reasons include: hardware limitations: traditional instruction set architectures lack native support for multi-base computing; energy consumption issues: existing technologies often require additional energy consumption when implementing multi-base computing; lack of flexibility: traditional instruction set architectures are difficult to dynamically adjust to adapt to different computing needs.

[0003] Prior art techniques exist that utilize existing binary hardware to simulate ternary calculations through software algorithms, thereby enabling mixed binary and ternary calculations. However, these techniques suffer from low computational performance, low energy efficiency, and difficulty handling large-scale calculations. Other techniques utilize field-programmable gate arrays (FPGAs) for hardware acceleration and design of dedicated ternary calculation circuits, but these methods consume significant resources and place high demands on developers. Furthermore, techniques exist that specifically design application-specific integrated circuits (ASICs) for efficient ternary calculations, but these methods suffer from long development cycles, high costs, and poor flexibility. Furthermore, these solutions lack native instruction sets and hardware circuit support, making efficient mixed binary and ternary calculations difficult to achieve. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a dynamically configured mixed-base calculation method, system, chip and storage medium.

[0005] In a first aspect, an embodiment of the present invention provides a dynamically configured mixed-base calculation method, the method comprising:

[0006] Reading metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tags are used to indicate whether the metadata of the corresponding operands is binary or ternary;

[0007] Determining a calculation mode corresponding to the target calculation instruction, and writing the two operands into two target registers respectively according to the calculation mode, and writing data tags of the two operands into tag bits of the two target registers;

[0008] According to the tag bits of the two target registers, a corresponding computing unit is allocated to the target computing instruction for calculation; wherein, when the tag bits of the two target registers do not match, a hardware base converter is called to convert the data in the register whose tag bit is binary into ternary and a ternary calculation unit is called for calculation.

[0009] Optionally, writing the two operands into two target registers respectively specifically includes:

[0010] When the operand to be written into the target register is ternary, the high-order and low-order bits of the operand are written into the high-order unit and the low-order unit of the target register respectively.

[0011] Optionally, the method further includes:

[0012] When the tag bits of the two target registers match, a corresponding binary or ternary calculation unit is called to perform calculation according to the tag bits of the target registers.

[0013] Optionally, the method further includes:

[0014] Wherein, during the process of writing the two operands into the two target registers respectively and performing the calculation, the power supply module of the corresponding target register is dynamically turned on or off according to the change of the value in each target register.

[0015] Optionally, the method further includes:

[0016] According to the complexity of the computing task where the target computing instruction is located, the power supply voltage of the power module and the clock frequency of the system are dynamically adjusted.

[0017] Optionally, the calculation mode includes a triple-increment mode and a symmetric mode.

[0018] Optionally, the calculation unit includes a binary calculation unit, a ternary calculation unit and a mixed-base calculation unit.

[0019] In a second aspect, an embodiment of the present invention provides a dynamically configured mixed-base computing system, characterized in that the system includes:

[0020] A data and tag reading module is used to read metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tag is used to indicate whether the metadata of the corresponding operand is binary or ternary;

[0021] A register dynamic configuration module is used to determine a calculation mode corresponding to the target calculation instruction, and write the two operands into two target registers respectively according to the calculation mode, and write the data tags of the two operands into the tag bits of the two target registers:

[0022] A computing unit dynamic configuration module is used to allocate corresponding computing units for the target computing instruction for calculation according to the tag bits of the two target registers; wherein, when the tag bits of the two target registers do not match, a hardware base converter is called before calculation to convert the data in the register with the tag bit as binary into ternary.

[0023] In a third aspect, an embodiment of the present invention provides a chip, characterized in that the chip includes:

[0024] one or more processors;

[0025] a memory for storing one or more programs;

[0026] When the one or more programs are executed by the one or more processors, the one or more processors execute the method as described in the first aspect.

[0027] In a fourth aspect, an embodiment of the present invention provides a storage medium having computer program instructions stored thereon, characterized in that when the computer program instructions are executed, the instruction processing method described in the first aspect is implemented.

[0028] The dynamically configurable mixed-base computation method, system, chip, and storage medium provided by the embodiments of the present invention provide native instruction support for mixed-base computation through the HEX4 instruction architecture. The extended instruction set ensures the efficiency and accuracy of ternary computation. A dynamic register combination mechanism allows flexible adjustment of arithmetic units based on task requirements. Strategies such as idle state shutdown, dynamic voltage regulation, and frequency scaling significantly reduce power consumption, making it particularly suitable for resource-constrained environments such as edge computing and IoT devices. Supporting multiple ternary modes and arithmetic units of varying lengths, it is easily scalable to larger values and complex tasks, adapting to diverse application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application.

[0030] Figure 1 A schematic diagram of a flow chart of a dynamically configured mixed-base calculation method provided in an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the structure of a dynamically configured mixed-base computing system provided by an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0034] Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0035] In traditional computer architecture, binary computing systems dominate. However, with the rapid development of fields such as the Internet of Things and artificial intelligence, the demand for diversified data types and high-efficiency computing is increasing. Ternary computing, with its unique advantages, exhibits higher efficiency and accuracy in certain application scenarios. However, existing computer architectures find it difficult to effectively support ternary computing. The main reasons include: hardware limitations: traditional instruction set architectures lack native support for multi-base computing; energy consumption issues: existing technologies often require additional energy consumption when implementing multi-base computing; lack of flexibility: traditional instruction set architectures are difficult to dynamically adjust to adapt to different computing needs.

[0036] Prior art techniques exist that utilize existing binary hardware to simulate ternary calculations through software algorithms, thereby enabling mixed binary and ternary calculations. However, these techniques suffer from low computational performance, low energy efficiency, and difficulty handling large-scale calculations. Other techniques utilize field-programmable gate arrays (FPGAs) for hardware acceleration and design of dedicated ternary calculation circuits, but these methods consume significant resources and place high demands on developers. Furthermore, techniques exist that specifically design application-specific integrated circuits (ASICs) for efficient ternary calculations, but these methods suffer from long development cycles, high costs, and poor flexibility. Furthermore, these solutions lack native instruction sets and hardware circuit support, making efficient mixed binary and ternary calculations difficult to achieve.

[0037] Based on this, the embodiment of the present invention proposes a dynamically configured ternary calculation method, as shown in the attached Figure 1 As shown, the method specifically includes the following steps.

[0038] Step S110, reading metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tag is used to represent that the metadata of the corresponding operand is binary or ternary.

[0039] In the embodiment of the present invention, a unified memory space design is adopted to store all data in the original encoding without the need for format conversion, and transparent access is achieved through metadata and tags. This can reduce data conversion overhead, support mixed storage of heterogeneous data types such as binary or ternary, and improve memory utilization. The cache line stores binary and ternary data at the same time, and the data type is identified by an extended tag bit (Tag). When multiple data types share the same cache line, the target data can be quickly located through the tag bit. In addition, based on the historical instruction stream and data access pattern, the prefetch strategy can be dynamically adjusted. Specifically, data types that are accessed frequently can be prefetched first to reduce the cache miss rate.

[0040] In this step, metadata and data tags need to be read first. Specifically, it is necessary to parse the target calculation instruction, extract the operand address, read the metadata and data tag from the memory according to the address, and then determine the encoding format (binary or ternary) of the operand through the data tag. According to the data tag, the original encoded data in the memory can be directly accessed, and the processor parses the data according to the tag without additional conversion. By adding a data type identification bit to the cache line tag (Tag), when the cache line hits, the target data type can be quickly located through the tag bit.

[0041] Furthermore, this step can also incorporate an intelligent prefetch strategy. By collecting historical instruction stream access data, we can calculate the access frequency of different data types. Based on these statistics, we then build a prediction model to predict the types of data likely to be accessed later. Finally, based on these predictions, we dynamically adjust the prefetch strategy to prioritize the loading of frequently accessed data types.

[0042] For example, take the execution of the addition operation A+B as an example, where A is binary and B is ternary. First, the instruction is parsed: HEMIXJIAFA R1, R2, R3 (add the values of R1 and R2, and store the result in R3). HEMIXJIAFA is a customized addition instruction in the instruction set system HEX4 in the embodiment of the present invention, which is used for mixed addition operations of binary and ternary. After parsing the instruction, the metadata and tags of R1 and R2 are read from the memory through memory access operations. The tag judgment result is that the R1 tag is 0 (binary) and the R2 tag is 1 (ternary). At this time, the original encoded data of R1 and R2 can be read directly without format conversion. Then, cache lines can be allocated to R1 and R2. Specifically, R1 and R2 are allocated to the same cache line, and the tag bit extension can be 3 bits (such as 001 for binary and 010 for ternary).

[0043] For the intelligent prefetch strategy, the historical access frequencies of R1 and R2 can be recorded. When it is found that the access pattern of R2 (ternary) is more complex and needs to be prefetched first, the prefetch priority of R2 can be dynamically adjusted according to the real-time data stream.

[0044] Step S120, determining the calculation mode corresponding to the target calculation instruction, and writing the two operands into two target registers respectively according to the calculation mode, and writing the data tags of the two operands into the tag bits of the two target registers.

[0045] This step is the register dynamic configuration step in the embodiment of the present invention, which aims to achieve flexible combination of multiple registers through flexible dynamic combination logic design and developable hardware programmable interconnection network to simultaneously support binary operands and ternary operands of different lengths in operation instructions.

[0046] In this step, it is first necessary to determine the computation mode (Computation Mode), which is used to describe the operation rules of the target computation instruction. In the embodiment of the present invention, two modes are provided: a carry-on-three mode and a symmetric mode. Taking the register as a 2-bit register as an example, the carry-on-three mode refers to the basic carry rule of the ternary system. In the ternary system, when the value of a certain bit reaches 3, 1 is added to the higher bit and the current bit is reset to zero. In the embodiment of the present invention, each 2-bit register can represent three states (00, 01, 10), which correspond to the ternary values 0, 1, and 2, respectively, and are used for the carry-on-three rule. The symmetric system (also known as the balanced ternary system or the negative ternary system) is another computation mode of the ternary system. It uses the three numbers -1, 0, and 1 to represent the value, instead of the usual 0, 1, and 2. The rule in the symmetric system is to carry-on-three every + / -2, that is, when the value of a certain bit reaches 2, 1 is added to the higher bit and the current bit becomes -1; when the value of a certain bit reaches -2, 1 is borrowed from the higher bit and the current bit becomes 1. Therefore, in the embodiment of the present invention, the operands can be written into the target register in a corresponding form only after the calculation mode is determined.

[0047] The "carry-three" mode uses 0, 1, and 2 to represent values, while the "symmetric" mode uses -1, 0, and 1. Symmetric mode eliminates the need for an additional sign bit when representing negative numbers. The "carry-three" mode follows the same rules as standard ternary arithmetic, but the "carry-three" mode is based on carrying 1 every -2 (equivalent to a borrow of -1). Addition and subtraction are simpler because the values are symmetrically distributed. In practical applications, the "symmetric" mode leverages HEX4's hardware acceleration to speed up basic operations like addition and subtraction. However, the "carry-three" mode, which handles three possible states for each operation, may incur higher latency. The "symmetric" mode reduces the possibility of overflow and errors through explicit sign representation. In contrast, the "carry-three" mode may require more checks to prevent calculation errors when handling edge cases. The "symmetric" mode is particularly suitable for applications that require handling positive and negative values, such as certain scientific simulations and data compression. The "carry-three" mode offers superior performance in traditional ternary arithmetic and is well-suited for specific mathematical tasks. In this embodiment of the present invention, the system determines the calculation mode information based on the type of calculation task before issuing it, and the target calculation instruction carries this information. For example, for tasks that require processing positive and negative values, such as scientific simulations and data compression applications, the system will determine the calculation mode to be symmetric. For traditional ternary mathematical calculations, the system will determine the calculation mode to be incremented every three.

[0048] A register is a hardware unit that stores operands in embodiments of the present invention and supports dynamic switching of encoding rules. The target register can be used to store binary or ternary data, and the register header contains a 1-bit tag bit to identify the data type. Therefore, the data tag of the metadata read from the memory is also written to the header of the target register, i.e., a 1-bit identifier attached to the register header to distinguish the data type stored in the register. For example, 0 represents binary data, and 1 represents ternary data. Specifically, when storing ternary data, since each 2-bit register in embodiments of the present invention can represent three states (00, 01, 10), the remaining state 11 can be used to mark as a carry flag, an idle state, etc., supporting operations such as carry propagation and power off. For example, during the process of writing the two operands into the two target registers and performing the calculation, the power module of the corresponding target register is dynamically turned on or off according to the changes in the value in each target register. This process can be determined by monitoring whether the value in each target register is in state 11. When the value in the target register remains unused for a defined period and the state is 11, the power module for the corresponding target register can be turned off. When the value in the target register is not 11, the power module for the corresponding target register can be turned on. This dynamic management of control states can significantly reduce system energy consumption. Furthermore, when the value in the target register is in use and the state is 11, it generally indicates a carry state, requiring a carry signal to be transmitted to the higher register group.

[0049] Furthermore, embodiments of the present invention not only support turning the power module of the target register on and off, but also provide more precise control over the supply voltage and clock frequency when the power module is turned on, thereby further reducing system energy consumption. Chip power consumption is proportional to the square of the voltage. Reducing the voltage can significantly reduce power consumption, but this requires simultaneous frequency adjustment to maintain stability. By varying the clock signal period, computing speed is controlled. Higher frequencies result in higher performance, but power consumption increases linearly with frequency. Dynamic voltage and frequency adjustment can minimize power consumption while meeting performance requirements. Specifically, load can be assessed using hardware performance counters (such as instruction retirement count and cache hit rate) or software sampling (such as task queue length). If the load is less than threshold 1, the system enters low-power mode (low voltage and low frequency). If the load is greater than threshold 2, the system switches to high-performance mode (high voltage and high frequency). The specific values of threshold 1, threshold 2, low voltage, low frequency, high voltage, and high frequency can be set based on user requirements and are not specifically limited in this embodiment. The adjusted performance and power consumption data are monitored, and if anomalies (such as insufficient performance or overheating) are detected, the system falls back to safe parameters.

[0050] The dynamic encoding rule in this step implements hardware-supported mixed binary and ternary computations. The register encoding method is dynamically adjusted according to the computation mode as follows: for binary data, the target register can be encoded using traditional binary encoding (e.g., a 32-bit register stores a 32-bit binary integer); for ternary data, the target register is divided into multiple two-bit cells, each storing a ternary value. For example, when the operand written to the target register is ternary, the high and low bits of the operand can be written to the high and low cells of the target register, respectively. Taking a 32-bit register as an example, it can be configured so that when storing binary data, a 32-bit binary integer is actually stored; when storing ternary data, the register is divided into 16 two-bit cells, storing a 16-trit ternary number. Specifically, in the HEX4 instruction set system, the register mode can be dynamically switched by calling a mode switch instruction (e.g., HEMODE_SWITCH), enabling fast switching between different base support. In terms of hardware, a programmable interconnect network (Crossbar Switch) is used to connect multiple registers through a crossbar switch matrix, supporting dynamic reorganization during runtime. The following is a possible implementation example: combine four two-bit registers into a 4-trit ternary number (retaining 11 bits of parity). Register group [R3 R2 R1 R0] represents the ternary value V = R0 × 3 0 +R1×3 1 +R2×3 2 +R3×3 3 By dynamically specifying the register group start address and length through configuration instructions (such as the ternary addition instruction HETRITJIAFA), the hardware controller will automatically allocate physical registers and establish connection paths.

[0051] Step S130, according to the tag bits of the two target registers, assign a corresponding computing unit to the target computing instruction for calculation; wherein, when the tag bits of the two target registers do not match, call the hardware base converter to convert the data in the register with the tag bit as binary into ternary and call the ternary calculation unit for calculation.

[0052] In the previous steps, the tag bit in the target register has been written with the operand's data tag, which is used to identify its data base type (binary or ternary). Therefore, the tag bit is the identification information associated with the target register, which is used to indicate the base format of the data in the register, facilitating the allocation of subsequent calculation units and data processing. At this time, when performing an instruction operation (taking the addition instruction as an example), three situations may occur:

[0053] When the tag bits of the two target registers match and are both 0, it indicates that both target registers store binary data. In this case, the binary addition unit should be assigned to the addition instruction. In the HEX4 instruction set system, the binary addition instruction HEJIAFA Nb = xXxXXxxx, Rd, Rs1, Rs2 can actually be executed, that is, the adder or shifter in the binary ALU is used for calculation.

[0054] When the tag bits of the two target registers match and are both 1, indicating that both target registers store ternary data, the addition instruction should be assigned to a ternary addition unit. In the HEX4 instruction set system, the binary addition instruction HETRIJIAFA Nb=xXxxxxXx11, Rd, Rs1, Rs2 can actually be executed, using logic gates such as the ternary full adder in the ternary ALU.

[0055] When the tag bits of the two target registers are 0 and 1, respectively, indicating that the two target registers store binary and ternary data, respectively, the HEX4 instruction set system also provides the corresponding instruction HEMIXJIAFARd, Rs1, Rs2 for mixed computations. The underlying logic of this instruction automatically detects the data type and performs mixed operations. If Rs1 is binary and Rs2 is ternary, the hardware base converter is automatically called to convert Rs1 to ternary, and then the ternary full adder and other logic gates in the ternary ALU are called to perform the computation.

[0056] The above design leverages the advantages of binary and ternary computation, improving the flexibility and efficiency of computing systems. Binary is the foundation of modern computers because electronic circuits only have two states (on / off, high / low voltage), making binary representation a natural fit. However, with the rapid development of fields such as the Internet of Things and artificial intelligence, the demand for diversified data types and high-performance computing is increasing. Ternary has unique advantages, as it can carry more information, improve computing efficiency and energy efficiency. In IoT terminal devices that utilize multiple sensor signals, or other heterogeneous systems, support for hybrid computing is necessary. The HEX4 instruction architecture in this embodiment of the present invention provides native instruction support for mixed-base computation. The extended instruction set ensures the efficiency and accuracy of ternary computation. A dynamic register combination mechanism allows flexible adjustment of arithmetic units based on task requirements. Strategies such as idle state shutdown, dynamic voltage regulation, and frequency scaling significantly reduce power consumption, making it particularly suitable for resource-constrained environments such as edge computing and IoT devices. Support for multiple ternary modes (increment every third, symmetric) and arithmetic units of varying lengths facilitates scalability to larger values and complex tasks, adapting to diverse application requirements.

[0057] Based on any of the above embodiments, Figure 2As shown, an embodiment of the present invention provides a dynamically configured ternary calculation system, specifically including:

[0058] The data and tag reading module 210 is used to read metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tag is used to indicate whether the metadata of the corresponding operand is binary or ternary;

[0059] a register dynamic configuration module 220, configured to determine a computation mode corresponding to the target computation instruction, and write the two operands into two target registers respectively according to the computation mode, and write the data tags of the two operands into tag bits of the two target registers;

[0060] The computing unit dynamic configuration module 230 is used to allocate the corresponding computing unit for the target computing instruction to perform calculation according to the tag bits of the two target registers; wherein, when the tag bits of the two target registers do not match, the hardware base converter is called before the calculation to convert the data in the register with the tag bit as binary into ternary.

[0061] Based on any of the above embodiments, Figure 3 The schematic diagram of the physical structure of the chip provided by an embodiment of the present invention is shown. The electronic device may include: a processor (processor) 310, a communication interface (Communications Interface) 320, a memory (memory) 330 and a communication bus 340. The processor 310, the communication interface 320, and the memory 330 communicate with each other via the communication bus 340. The processor 310 can call the logic instructions in the memory 330 to execute the following method:

[0062] Reading metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tags are used to indicate whether the metadata of the corresponding operands is binary or ternary;

[0063] Determining a calculation mode corresponding to the target calculation instruction, and writing the two operands into two target registers respectively according to the calculation mode, and writing data tags of the two operands into tag bits of the two target registers;

[0064] According to the tag bits of the two target registers, a corresponding computing unit is allocated to the target computing instruction for calculation; wherein, when the tag bits of the two target registers do not match, a hardware base converter is called to convert the data in the register whose tag bit is binary into ternary and a ternary calculation unit is called for calculation.

[0065] In addition, the logic instructions in the above-mentioned memory 330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the embodiment of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0066] On the other hand, an embodiment of the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method provided in each of the above embodiments is implemented, for example, including:

[0067] Reading metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tags are used to indicate whether the metadata of the corresponding operands is binary or ternary;

[0068] Determining a calculation mode corresponding to the target calculation instruction, and writing the two operands into two target registers respectively according to the calculation mode, and writing data tags of the two operands into tag bits of the two target registers;

[0069] According to the tag bits of the two target registers, a corresponding computing unit is allocated to the target computing instruction for calculation; wherein, when the tag bits of the two target registers do not match, a hardware base converter is called to convert the data in the register whose tag bit is binary into ternary and a ternary calculation unit is called for calculation.

[0070] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0071] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A dynamically configured mixed-base calculation method, characterized in that: The method comprises: Reading metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tags are used to indicate whether the metadata of the corresponding operands is binary or ternary; Determining a calculation mode corresponding to the target calculation instruction, and writing the two operands into two target registers respectively according to the calculation mode, and writing data tags of the two operands into tag bits of the two target registers; According to the tag bits of the two target registers, a corresponding computing unit is allocated to the target computing instruction for calculation; wherein, when the tag bits of the two target registers do not match, a hardware base converter is called to convert the data in the register whose tag bit is binary into ternary and a ternary calculation unit is called for calculation.

2. The mixed-base calculation method according to claim 1, wherein: Writing the two operands into two target registers respectively specifically includes: When the operand to be written into the target register is ternary, the high-order and low-order bits of the operand are written into the high-order unit and the low-order unit of the target register respectively.

3. The mixed-base calculation method according to claim 1, wherein: The method further comprises: When the tag bits of the two target registers match, a corresponding binary or ternary calculation unit is called to perform calculation according to the tag bits of the target registers.

4. The mixed-base calculation method according to claim 1, wherein: The method further comprises: Wherein, during the process of writing the two operands into the two target registers respectively and performing the calculation, the power supply module of the corresponding target register is dynamically turned on or off according to the change of the value in each target register.

5. The mixed-base calculation method according to claim 1, wherein: The method further comprises: According to the complexity of the computing task where the target computing instruction is located, the power supply voltage of the power module and the clock frequency of the system are dynamically adjusted.

6. The mixed-base calculation method according to claim 1, wherein: The calculation modes include a triple-increment mode and a symmetric mode.

7. The mixed-base calculation method according to claim 1, wherein: The calculation unit includes a binary calculation unit, a ternary calculation unit and a mixed-base calculation unit.

8. A dynamically configured mixed-base computing system, characterized in that: The system comprises: A data and tag reading module is used to read metadata and data tags of two operands involved in the target computing instruction from the memory according to the target computing instruction; wherein the data tag is used to indicate whether the metadata of the corresponding operand is binary or ternary; a register dynamic configuration module, configured to determine a calculation mode corresponding to the target calculation instruction, and write the two operands into two target registers respectively according to the calculation mode, and write the data tags of the two operands into the tag bits of the two target registers; A computing unit dynamic configuration module is used to allocate corresponding computing units for the target computing instruction for calculation according to the tag bits of the two target registers; wherein, when the tag bits of the two target registers do not match, a hardware base converter is called before calculation to convert the data in the register with the tag bit as binary into ternary.

9. A chip, characterized in that: The chip includes: one or more processors; a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors are enabled to perform the method according to any one of claims 1 to 7.

10. A storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed, the ternary calculation method according to any one of claims 1 to 7 is implemented.

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