Repair circuit, display panel and display device

Abstract

The invention provides a repair circuit, a display panel and a display device. The repairing circuit comprises an input module, a first input end of which is connected with a to-be-repaired signal, a first output end of which is electrically connected with a first node, and which is used for carrying out voltage reduction processing on the to-be-repaired signal and then outputting a first input signal; and the processing module comprises a dedelay unit, a shaping unit and a level conversion unit. The control end of the de-delay unit is electrically connected to the first node, the input end is coupled with the corresponding clock signal, the output end is electrically connected to the second node, the de-delay unit is used for performing de-delay processing on the first input signal according to the corresponding clock signal and then outputting a de-delay signal, and the falling edge of the de-delay signal is consistent with the falling edge of the corresponding clock signal; the shaping unit is electrically connected to the second node and is used for shaping the waveform of the dedelayed signal and then outputting a square wave signal; and the level conversion unit is electrically connected to the output end of the shaping unit and is used for performing level adjustment on the square wave signal and then outputting a scanning repair signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a repair circuit, a display panel, and a display device. Background Art

[0002] During the display panel manufacturing process, various display defects can occur due to process defects. Among these defects, gate drive-related defects account for up to 30%. Poor gate drive results in abnormal scan signal output for the corresponding row, which manifests as dark horizontal lines on the display. Typically, these products are downgraded or scrapped on the production line, increasing production costs. Summary of the Invention

[0003] The present application provides a repair circuit, a display panel, and a display device, which aim to solve the problem of dark lines appearing on the display screen due to poor gate drive in the prior art.

[0004] In order to solve the above technical problems, the first technical solution provided by this application is to provide a repair circuit. The repair circuit is used to repair abnormal scanning signals in the display panel, and the repair circuit includes:

[0005] An input module, wherein a first input terminal receives a signal to be repaired, a first output terminal is electrically connected to a first node, and is configured to perform voltage reduction processing on the signal to be repaired and output the first input signal at the first output terminal;

[0006] The processing module includes a delay removal unit, a shaping unit and a level conversion unit; wherein,

[0007] The control end of the de-delay unit is electrically connected to the first node, the input end is coupled to the corresponding clock signal, and the output end is electrically connected to the second node, and is used to de-delay the falling edge of the first input signal according to the corresponding clock signal and output the de-delay signal at the output end, wherein the falling edge of the de-delay signal is consistent with the falling edge of the corresponding clock signal;

[0008] The input end of the shaping unit is electrically connected to the second node, and is used to shape the waveform of the de-delayed signal and output a square wave signal at the output end;

[0009] The level conversion unit has an input end electrically connected to the output end of the shaping unit, is used to adjust the level of the square wave signal, and output a scanning repair signal at the output end.

[0010] In some embodiments, the de-delay unit includes a switch transistor, a control terminal of the switch transistor is electrically connected to the first node, a first terminal is coupled to the corresponding clock signal, and a second terminal is electrically connected to the second node;

[0011] The shaping unit includes an operational amplifier chip, a first input terminal of the operational amplifier chip is electrically connected to the second node, a second input terminal is connected to the reference voltage signal, and an output terminal is electrically connected to the input terminal of the level conversion unit; the operational amplifier chip is used to compare the de-delayed signal with the reference voltage signal to output a square wave signal at the output terminal of the operational amplifier chip;

[0012] The level conversion unit includes a level conversion chip, the input end of the level conversion chip is electrically connected to the output end of the shaping unit, the first power input end is connected to the gate high level signal, and the second power input end is connected to the gate low level signal, so as to convert the high level of the square wave signal into the gate high level and the low level of the square wave signal into the gate low level.

[0013] In some embodiments, the shaping unit further includes a first voltage dividing unit, the first voltage dividing unit including a first voltage dividing resistor, a second voltage dividing resistor, and a third voltage dividing resistor connected in series; one end of the first voltage dividing resistor is connected to the initial power supply signal, the connection node between the first voltage dividing resistor and the second voltage dividing resistor is a first voltage dividing node, and the connection node between the second voltage dividing resistor and the third voltage dividing resistor is a second voltage dividing node;

[0014] The first voltage dividing node is electrically connected to the positive power input terminal of the operational amplifier chip, and is used to provide a positive power supply voltage signal to the operational amplifier chip; the second voltage dividing node is electrically connected to the second input terminal of the operational amplifier chip, and is used to provide a reference voltage signal to the operational amplifier chip.

[0015] In some embodiments, the delay removal unit further includes an adjustment unit, one end of the adjustment unit is electrically connected to the second node, and the other end is connected to the pull-down power signal;

[0016] The adjustment unit includes a pull-up resistor, one end of the pull-up resistor is electrically connected to the second node, and the other end is connected to the pull-down power supply signal; the pull-up resistor is an adjustable resistor.

[0017] In some embodiments, the input module includes a second voltage divider unit and a third voltage divider unit; the second voltage divider unit is used to reduce the voltage of the signal to be repaired and output the first input signal, and the third voltage divider unit is used to reduce the voltage of the corresponding clock signal and output the second input signal;

[0018] The second voltage dividing unit includes a fourth voltage dividing resistor and a fifth voltage dividing resistor, wherein one end of the fourth voltage dividing resistor is connected to the signal to be repaired and the other end is electrically connected to the first node; one end of the fifth voltage dividing resistor is electrically connected to the first node and the other end is grounded;

[0019] The third voltage-dividing unit includes a sixth voltage-dividing resistor and a seventh voltage-dividing resistor, one end of the sixth voltage-dividing resistor is connected to the corresponding clock signal, and the other end is electrically connected to the third voltage-dividing node, one end of the seventh voltage-dividing resistor is electrically connected to the third voltage-dividing node, and the other end is grounded; the input end of the de-delay unit is electrically connected to the third voltage-dividing node.

[0020] In some embodiments, the repair circuit further includes an output module, the output module being electrically connected to the output end of the level conversion unit and configured to match the corresponding impedance for the scan repair signal; the output module including a first adjustment unit and a second adjustment unit;

[0021] The first regulating unit includes a first regulating resistor, one end of the first regulating resistor is electrically connected to the output end of the level conversion unit, and the other end is electrically connected to the regulating node; the first regulating resistor is a variable resistor;

[0022] The second adjustment unit includes a second adjustment resistor and a third adjustment resistor; one end of the second adjustment resistor is electrically connected to the adjustment node, and the other end serves as an output end for outputting the adjusted first scanning repair signal; one end of the third adjustment resistor is electrically connected to the adjustment node, and the other end serves as an output end for outputting the adjusted second scanning repair signal.

[0023] In order to solve the above technical problems, the second technical solution provided by this application is to provide a display panel. The display panel includes:

[0024] A driving substrate comprising a pixel array region, a first gate driving module and a second gate driving module located on opposite sides of the pixel array region, and a plurality of scanning lines;

[0025] A drive control board is provided on one side of the drive substrate and is coupled to the drive substrate;

[0026] The drive control board includes the repair circuit provided in the above embodiment, which is used to repair abnormal scanning signals; the display panel also includes:

[0027] The first repair input line and the first repair output line are arranged between the pixel array area and the first gate driving module, and are arranged in different layers and cross-connected with the plurality of scanning lines;

[0028] The second repair input line and the second repair output line are arranged between the pixel array area and the second gate driving module at intervals and are arranged in a different layer and cross-arranged with the plurality of scanning lines;

[0029] When the output of the n-th level driving unit in the first gate driving module or the second gate driving module is abnormal, the two ends of the n-th row scanning line are respectively disconnected from the corresponding n-th level driving unit, and the normal n-th level driving unit in the first gate driving module or the second gate driving module is electrically connected to the first input end of the repair circuit through the first repair input line or the second repair input line, so as to provide the repair circuit with a signal to be repaired, and the two ends of the n-th row scanning line are respectively electrically connected to the output end of the repair circuit through the first repair output line and the second repair output line, so as to receive the scanning repair signal after repair by the repair circuit.

[0030] In some embodiments, the drive control board includes a first drive control unit and a second drive control unit; the first drive control unit and the second drive control unit are arranged in a direction parallel to a side of the drive substrate; and the repair circuit is disposed in the first drive control unit;

[0031] The drive control board is coupled to the drive substrate via a plurality of chip-on-films (CFOs); wherein, among the plurality of CFOs electrically connected to the first drive control unit, the outermost CFO is a first outer CFO, and the CFO closest to the second drive control unit is a first inner CFO; and among the plurality of CFOs electrically connected to the second drive control unit, the outermost CFO is a second outer CFO, and the CFO closest to the first drive control unit is a second inner CFO.

[0032] The first repair input line and the first repair output line extend to the repair circuit through the first outer chip-on-film and are electrically connected to the repair circuit;

[0033] The second repair input line and the second repair output line extend to the second drive control unit through the second outer chip-on-chip film, and extend along the second drive control unit to a position close to the first drive control unit, and then extend along the second inner chip-on-chip film to the drive substrate, and extend on the drive substrate in a direction close to the first drive control unit to a position of the first inner chip-on-chip film, and extend along the first inner chip-on-chip film to the first drive control unit, and are electrically connected to the repair circuit.

[0034] In some embodiments, the flip chip film is divided into a data area and a gate area, and the gate area is located on opposite sides of the data area along an extension direction parallel to the drive control board; the data area is provided with a driver chip, and the gate area is used for wiring; wherein, the first repair input line, the first repair output line, the second repair input line and the second repair output line are arranged in the gate area and extend along the gate area.

[0035] In order to solve the above technical problems, the third technical solution provided by this application is to provide a display device. The display device includes:

[0036] The display panel is the display panel provided in the above embodiment;

[0037] The central control board is used to provide a driving control signal to the display panel so that the display panel displays a corresponding image.

[0038] Beneficial effects of the present application: Different from the prior art, the present application provides a repair circuit, a display panel and a display device. The repair circuit is used to repair abnormal scanning signals in the display panel, and the repair circuit includes an input module and a processing module. By connecting the first input end of the input module to the repair signal, the signal to be repaired is subjected to voltage reduction processing and then outputted as the first input signal, so as to meet the voltage specification requirements of the processing module for the signal and avoid damage to the components in the processing module. The processing module includes a de-delay unit, a shaping unit and a level conversion unit. By electrically connecting the control end of the level conversion unit to the first node and coupling the input end to the corresponding clock signal, the de-delay unit de-delays the falling edge of the first input signal according to the corresponding clock signal and then inputs the de-delay signal, so that the falling edge of the de-delay signal is consistent with the falling edge of the corresponding clock signal, thereby avoiding the problem that the driving transistor of the corresponding row is delayed and turned off, resulting in the data of the next row being incorrectly charged into the row, resulting in abnormal images. By electrically connecting the input of the shaping unit to the second node, the shaping unit receives the de-delay signal and shapes the de-delay signal before outputting a square wave signal. This improves the slow ramp-up of the de-delay signal's rising edge, making the signal waveform a more regular square wave, and thus making the signal output by the level conversion unit more accurate. By electrically connecting the input of the level conversion unit to the output of the shaping unit, the shaping unit receives the square wave signal and adjusts the level of the square wave signal before outputting a scan repair signal. This ensures that the high and low levels of the scan repair signal meet the requirements of the scan signal. The coordinated operation of the input module, de-delay unit, shaping unit, and level conversion unit generates a scan repair signal, effectively repairing the output signal of the gate drive in the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 1 is a schematic diagram of a circuit structure of a gate driving unit provided by an embodiment of the related art;

[0041] Figure 2 It corresponds to Figure 1 A driving timing diagram provided by an embodiment of the present invention;

[0042] Figure 3 is a structural diagram of a display panel provided in one embodiment of the present application;

[0043] Figure 41 is a schematic structural diagram of a chip-on-film provided in one embodiment of the present application;

[0044] Figure 5 is a structural diagram of a repair circuit provided in one embodiment of the present application;

[0045] Figure 6 This is a schematic diagram of the structure of an input module provided in one embodiment of the present application;

[0046] Figure 7 is a structural diagram of an input module provided in another embodiment of the present application;

[0047] Figure 8 This is a schematic diagram of the driving timing of a normal scanning signal and a signal to be repaired provided in one embodiment of the present application;

[0048] Figure 9 1 is a schematic structural diagram of a delay removal unit provided in one embodiment of the present application;

[0049] Figure 10 1 is a driving timing diagram of a delay removal unit provided in one embodiment of the present application;

[0050] Figure 11 1 is a driving timing diagram of a delay removal unit provided in another embodiment of the present application;

[0051] Figure 12 This is a schematic structural diagram of a shaping unit provided in one embodiment of the present application;

[0052] Figure 13 This is a schematic diagram of the driving timing of the shaping unit provided in one embodiment of the present application;

[0053] Figure 14 1 is a schematic structural diagram of a level conversion unit provided in one embodiment of the present application;

[0054] Figure 15 1 is a driving timing diagram of a level conversion unit provided in one embodiment of the present application;

[0055] Figure 16 This is a schematic diagram of the structure of the output single module provided in the first embodiment of the present application;

[0056] Figure 17 is a schematic structural diagram of an output module provided in the second embodiment of the present application;

[0057] Figure 18 is a schematic structural diagram of an output module provided in the third embodiment of the present application;

[0058] Figure 19 It corresponds to Figure 18 A schematic diagram of status output provided by an embodiment of the output module;

[0059] Figure 20 2 is a schematic structural diagram of a display device provided in one embodiment of the present application.

[0060] Reference numerals:

[0061] 100 - display panel; 10 - drive substrate; 11 - pixel array area; 121 - first gate drive module; 122 - second gate drive module; 123 - drive unit; 123n - nth stage drive unit; 131 - first repair input line; 132 - first repair output line; 141 - second repair input line; 142 - second repair output line; 20 - drive control board; 21 - first drive control unit; 211 - first connector 211; 22 - second drive control unit; 221 - second connector 221; 30 - repair circuit; 31 - input module; 311 - second voltage divider unit; 312 - third voltage divider unit; 313 - dial switch Switch; 32-processing module; 33-de-delay unit; 331-adjustment unit; 34-shaping unit; 341-op amp chip; 342-first voltage divider unit; 35-level conversion unit; 351-level conversion chip; 36-output module; 361-first adjustment unit; 362-second adjustment unit; 363-resistance-capacitance unit; 364-target transistor; 365-transmission channel; 40-chip on film; 401-data area; 402-gate area; 41-first outer chip on film; 42-first inner chip on film; 43-second outer chip on film; 44-second inner chip on film; 45-driver chip; 200-central control board;

[0062] M1 - first transistor; M2 - second transistor; M3 - third transistor; M4 - fourth transistor; Cst - storage capacitor Cst; Cgd - parasitic capacitor; A1 - pull-up node; A2 - output node; A3 - reset node; CLK - clock signal; P(n-1) - stage transmission signal; Out(n-1) - previous stage scan signal; Out(n) - current stage scan signal; Out(n+1) - next stage scan signal; Rst - reset signal; Vss - pull-down power supply signal; t1 - first stage; t2 - second stage; t3 - third stage; t4 - fourth stage; V1 - first potential; V2 - second potential;

[0063] G1~Gw-scan lines; Gn-nth row scan line; N1-first node; N2-second node; N3-third node; N4-first voltage-dividing node; N5-second voltage-dividing node; N6-regulation node; Q1-switching transistor; CLKi-corresponding clock signal; fn-signal to be repaired; f1-first input signal; f2-de-delay signal; f3-square wave signal; f4-scan repair signal; f51-first scan repair signal; f52-second scan repair signal; R1-first voltage-dividing resistor; R2-second voltage-dividing resistor; R3-third voltage-dividing resistor; R 4-fourth voltage-dividing resistor; R5-fifth voltage-dividing resistor; R6-sixth voltage-dividing resistor; R7-seventh voltage-dividing resistor; R8-pull-up resistor; R9-first adjustment resistor; R10-second adjustment resistor; R11-third adjustment resistor; C1-first filter capacitor; C2-second filter capacitor; C3-third filter capacitor; C4-fourth filter capacitor; C5-fifth filter capacitor; Vref-reference voltage signal; VCC-positive power supply voltage signal; HVAA-initial power supply signal; VGH-gate high level signal; VGL-gate low level signal; GND-ground. DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0065] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0066] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0067] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0068] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0069] In related art, a display panel (not shown) includes a display area and a gate driver module disposed on one side of the display area. The gate driver module generates scan signals, thereby turning on the drive transistors in the display area row by row, thereby driving the sub-pixels to emit light. Specifically, the gate driver module includes multiple cascaded gate driver units to output scan signals for multiple rows.

[0070] See also Figure 1 and Figure 2 , Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a gate driving unit provided by an embodiment of the related art. Figure 2 It corresponds to Figure 1 Taking the n-th level gate driving unit as an example, the gate driving unit includes a charging unit, an output unit, an energy storage unit and a reset unit.

[0071] The charging unit includes a first transistor M1. The control terminal (gate) and input terminal (drain) of the first transistor M1 are electrically connected to the output terminal of the previous-stage gate driving unit, and are used to receive the level transmission signal P(n-1) (i.e., the previous-stage scanning signal Out(n-1)) output by the previous-stage gate driving unit. The output terminal (source) of the first transistor M1 is electrically connected to the pull-up node A1. When the level transmission signal P(n-1) is at a high level, the first transistor M1 is turned on, causing the potential of the pull-up node A1 to rise.

[0072] The output unit includes a second transistor M2. The control terminal (gate) of the second transistor M2 is electrically connected to the pull-up node A1, the input terminal (drain) is connected to the corresponding clock signal CLK (i.e., the clock signal CLK corresponding to the gate drive unit of this stage), and the output terminal (source) is electrically connected to the output node A2. When the potential of the pull-up node A1 reaches the threshold voltage of the second transistor M2, the second transistor M2 is turned on. At the same time, when the corresponding clock signal CLK is at a high level, the output node A2 outputs a high level.

[0073] The energy storage unit includes a storage capacitor Cst, one end of which is electrically connected to the pull-up node A1 and the other end is electrically connected to the output node A2. When the level transfer signal P(n-1) output by the previous-stage gate driver unit 123 is at a high level, the first transistor M1 is turned on to pre-charge the storage capacitor Cst.

[0074] The reset unit includes a third transistor M3 and a fourth transistor M4. The control terminals (gates) of the third and fourth transistors M3 and M4 are electrically connected to a reset node A3, which is electrically connected to the output terminal of the next-stage gate driver unit. This allows the next-stage scan signal Out(n+1) output by the next-stage gate driver unit to also serve as the reset signal Rst for the current-stage gate driver unit. The input terminal (drain) of the third transistor M3 is electrically connected to the pull-up node A1, and the input terminal (drain) of the fourth transistor M4 is electrically connected to the output node A2. The output terminal (source) of the third transistor M3 and the output terminal (source) of the fourth transistor M4 are connected to the pull-down power supply signal Vss. When the reset signal Rst is at a valid level, the third transistor M3 and the fourth transistor M4 are turned on, so that the pull-up node A1 and the output node A2 are both turned on to the pull-down power signal Vss, so as to discharge both ends of the storage capacitor Cst, so that the level of the pull-up node A1 is the level of the pull-down power signal Vss, so that the second transistor M2 is turned off, and the level of the output node A2 is the level of the pull-down power signal Vss.

[0075] like Figure 2As shown, in the first stage t1, the stage transfer signal P(n-1) output by the previous stage gate driving unit 123 is at a low level. Although the corresponding clock signal CLK has a high potential input to the input end of the second transistor M2, the pull-up node A1 is at a low potential, the second transistor M2 is in a closed state, and the output node A2 does not output a high potential.

[0076] In the second stage t2, the level transfer signal P(n-1) output by the previous-stage gate driving unit 123 is at a high potential, the first transistor M1 is turned on, the potential of the pull-up node A1 is increased to the first potential V1, and the second transistor M2 is also in the on state. However, since the clock signal CLK connected to the input end of the second transistor M2 is still at a low potential, the output node A2 of the current-stage gate driving unit is still at a low potential.

[0077] In the third phase t3, the corresponding clock signal CLK is at a high potential. Due to the capacitive coupling between the parasitic capacitance Cgd between the gate (control terminal) and the drain (input terminal) of the second transistor M2, the potential of the pull-up node A1 is also synchronously pulled up. The potential of the pull-up node A1 is increased from the first potential V1 to the second potential V2, which greatly increases the conductivity of the second transistor M2, outputs current, and causes the output node A2 to output a high potential.

[0078] In the fourth phase t4, since the current-stage scanning signal Out(n) output by the current-stage gate driver unit is the stage transmission signal P(n) of the next-stage gate unit, the next-stage gate driver unit is also precharging while the current-stage scanning signal Out(n) is at a high level. As the potential of the clock signal CLK changes from a high level to a low level, the high-level output signal of the next stage (i.e., the next-stage scanning signal Out(n+1)) is input to the current stage as the reset signal Rst, causing the reset node A3 to be at a high level. The third transistor M3 and the fourth transistor M4 are then turned on, connecting the two ends of the storage capacitor Cst to the low-level pull-down power signal Vss for discharge. The output node A2 is also connected to the low-level pull-down power signal Vss, causing the output signal to change to a low level, thereby turning off the corresponding row of sub-pixels.

[0079] This embodiment provides a gate driver unit with a 4T1C structure. In specific embodiments, the gate driver unit may include more transistors, resulting in a more complex circuit structure. Transistor yield is the most critical aspect of the entire gate driver module design, requiring the highest manufacturing process. Therefore, if a single transistor exhibits manufacturing defects, the output of the gate driver unit at that level will be abnormal, leading to display anomalies in the corresponding row of sub-pixels.

[0080] In order to solve the above technical problems, the present application provides a display panel 100 (see below) Figure 3 ), the display panel 100 includes:

[0081] The driving substrate 10 includes a pixel array area 11, a first gate driving module 121 and a second gate driving module 122 located on opposite sides of the pixel array area 11, and a plurality of scanning lines G1 to Gw;

[0082] The driving control board 20 is disposed on one side of the driving substrate 10 and coupled to the driving substrate 10;

[0083] The first repair input line 131 and the first repair output line 132 are spaced apart and arranged between the pixel array area 11 and the first gate driving module 121 , and are arranged in different layers and cross-connected with the plurality of scanning lines G1 to Gw;

[0084] The second repair input line 141 and the second repair output line 142 are spaced apart and arranged between the pixel array area 11 and the second gate driving module 122 , and are arranged in different layers and cross-connected with the plurality of scanning lines G1 -Gw;

[0085] In which, the driving substrate 10 includes a repair circuit 30 for repairing abnormal scanning signals; when the n-th level driving unit 123n in the first driving module or the second driving module is abnormal, the two ends of the n-th row scanning line Gn are respectively disconnected from the corresponding n-th level driving unit 123n, and the normal n-th level driving unit 123n in the first gate driving module or the second gate driving module 122 is electrically connected to the first input end of the repair circuit 30 through the first repair input line 131 or the second repair input line 141, for providing the repair circuit 30 with a signal fn to be repaired, and the two ends of the n-th row scanning line Gn are respectively electrically connected to the output end of the repair circuit 30 through the first repair output line 132 and the second repair output line 142, for receiving the scanning repair signal f4 after repair by the repair circuit 30.

[0086] In the embodiment of the present application, through the above configuration, when the n-th gate driver unit 123 in the first driver module or the second driver module is abnormal, both ends of the n-th scan line Gn are disconnected from the corresponding n-th stage driver unit 123n, thereby preventing the abnormal n-th scan signal from entering the n-th scan line Gn. A normal n-th stage driver unit 123n in the first gate driver module 121 or the second gate driver module 122 is electrically connected to the first input terminal of the repair circuit 30 in the driver control board 20 via the first repair input line 131 or the second repair input line 141, thereby providing the repair circuit 30 with a signal to be repaired fn. Due to the influence of the in-plane wiring RC, there is a delay problem in the signal to be repaired fn sent to the repair circuit 30. The repair circuit 30 repairs the signal to be repaired fn and generates a scanning repair signal f4 as a new n-th row scanning signal; the output end of the repair circuit 30 is electrically connected to the two ends of the n-th row scanning line Gn through the first repair output line 132 and the second repair output line 142 respectively, so that the new n-th row scanning signal generated after the repair by the repair circuit 30 is transmitted to the two ends of the n-th row scanning line Gn through the first repair output line 132 and the second repair output line 142 respectively, so as to drive the n-th row scanning line Gn from both ends at the same time, thereby completing the effective repair of the abnormal scanning signal of the n-th row.

[0087] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0088] See also Figure 3 , Figure 3 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. In this embodiment, a display panel 100 is provided, and the display panel 100 includes:

[0089] The driving substrate 10 includes a pixel array area 11, a first gate driving module 121 and a second gate driving module 122 located on opposite sides of the pixel array area 11, and a plurality of scanning lines G1 to Gw;

[0090] The driving control board 20 is disposed on one side of the driving substrate 10 and coupled to the driving substrate 10;

[0091] The first repair input line 131 and the first repair output line 132 are spaced apart and arranged between the pixel array area 11 and the first gate driving module 121 , and are arranged in different layers and cross-connected with the plurality of scanning lines G1 to Gw;

[0092] The second repair input line 141 and the second repair output line 142 are spaced apart and arranged between the pixel array area 11 and the second gate driving module 122 , and are arranged in different layers and cross-connected with the plurality of scanning lines G1 -Gw;

[0093] In which, the drive control board 20 includes a repair circuit 30 for repairing abnormal scanning signals; when the output of the n-th level driving unit 123n in the first gate driving module 121 or the second gate driving module 122 is abnormal, the two ends of the n-th row scanning line Gn are respectively disconnected from the corresponding n-th level driving unit 123n, and the normal n-th level driving unit 123n in the first gate driving module or the second gate driving module 122 is electrically connected to the first input end of the repair circuit 30 through the first repair input line 131 or the second repair input line 141, for providing the repair circuit 30 with a signal fn to be repaired, and the two ends of the n-th row scanning line Gn are respectively electrically connected to the output end of the repair circuit 30 through the first repair output line 132 and the second repair output line 142, for receiving the scan repair signal f4 repaired by the repair circuit 30.

[0094] in:

[0095] The pixel array region 11 includes a plurality of sub-pixels (not shown) arranged in an array. A plurality of scan lines G1-Gw are arranged in an array along the columns of sub-pixels and disposed between adjacent rows of sub-pixels. Each scan line G1-Gw extends along the rows of sub-pixels, and its ends are electrically connected to a corresponding stage driver unit 123 in the first gate driver module 121 and a corresponding stage driver unit 123 in the second gate driver module 122, respectively, to receive a scan signal for the corresponding stage.

[0096] The first gate driver module 121 and the second gate driver module 122 are respectively arranged on either side of the pixel array area 11 along the row direction of the sub-pixels. The first gate driver module 121 and the second gate driver module each include multiple cascaded driver units 123. The first ends of the scan lines G1-Gw are electrically connected to the corresponding stage driver unit 123 in the first gate driver module 121 near that end, and the second ends of the scan lines G1-Gw are electrically connected to the corresponding stage driver unit 123 in the second gate driver module 122 near that end. It can be understood that the display panel 100 uses double-sided gate drive, and the first gate driver modules 121 and the second gate driver modules 122 on both sides simultaneously drive both ends of the same scan line G1-Gw.

[0097] The drive control board 20 is disposed on one side of the drive substrate 10 along the pixel columns and is coupled to the drive substrate 10 via a chip-on-film (COF) 40. It is used to provide the required drive signals and power signals to the pixel array area 11, the first gate driver module 121, and the second gate driver module 122. The drive control board 20 also includes a repair circuit 30 for repairing abnormal scan signals output by the first gate driver module 121 and / or the second gate driver module 122.

[0098] First repair input lines 131 and first repair output lines 132 are disposed between the first gate driver module 121 and the pixel array area 11, and are spaced apart. These lines extend along the columns of sub-pixels and extend through the chip-on-film 40 to the driver control board 20, where they are electrically connected to the repair circuit 30. These lines are intersecting the scan lines G1-Gw on different layers.

[0099] Second repair input lines 141 and second repair output lines 142 are disposed between the second gate driver module 122 and the pixel array area 11, and are spaced apart. These lines extend along the columns of sub-pixels and extend through the chip-on-film 40 to the driver control board 20, where they are electrically connected to the repair circuit 30. These lines 141 and 142 are intersecting and arranged on different layers from the scan lines G1-Gw.

[0100] When the output of the nth-stage driver unit 123n in the first gate driver module 121 or the second gate driver module 122 is abnormal, the first end of the nth-row scan line Gn is disconnected from the nth-stage driver unit 123n in the first gate driver unit 123, and the second end of the nth-row scan line Gn is disconnected from the nth-stage driver unit 123n in the second gate driver unit 123, so that the abnormal nth-row scan signal no longer enters the nth-row scan line Gn. The output end of the normal nth-stage driver unit 123n in the first gate driver unit 123 or the second gate driver unit 123 is electrically connected to the first repair input line 131 or the second repair input line 141, so that the normal nth-row scan signal is transmitted to the repair circuit 30 via the first repair input line 131 or the second repair input line 141. Due to the influence of the in-plane wiring RC, the to-be-repaired signal fn sent to the repair circuit 30 is delayed, which can easily cause the next row of data to be incorrectly charged into the sub-pixels in that row. To address this technical issue, the repair circuit 30 repairs the signal to be repaired fn to generate a scan repair signal f4 as a new scan signal for the nth row. Furthermore, the first repair output line 132 and the second repair output are electrically connected to the nth scan line Gn, so that the new scan signal for the nth row is transmitted to the nth scan line Gn via the first repair output line 132 and the second repair output line 142. This drives the sub-pixels in that row simultaneously from both ends, thereby resolving the issue of dark or weak lines appearing on the display screen due to abnormal output of the nth-level scan signal from the first gate driver module 121 or the second gate driver module 122.

[0101] Furthermore, the line widths of the first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 are greater than the line widths of the routing lines in the gate drive module. In specific applications, the line widths of the first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 are set as large as possible to reduce the impedance on the repair lines, thereby reducing signal delay. It should be noted that the repair lines described in the embodiments of the present application include the first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 described above.

[0102] In a specific application, the first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 are arranged on a different layer from the output wiring of the gate drive module, that is, on a different metal wiring layer. The first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 located on the drive substrate 10 are reserved wiring formed during the manufacturing stage of the drive substrate 10, and the first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 are all in a floating state on the drive substrate 10, that is, they are not electrically connected to other wiring and components on the drive substrate 10.

[0103] During the test phase of the display panel 100, when an abnormal output of the n-th driving unit 123n in the first gate driving module 121 or the n-th driving unit 123n in the second gate driving module 122 is detected, a laser method can be used to disconnect the first end of the n-th scan line Gn from the output end of the n-th driving unit 123n in the first gate driving module 121, and disconnect the second end of the n-th scan line Gn from the output end of the n-th driving unit 123n in the second gate driving module 122. Then, at the intersection of the first repair input line 131 or the second repair input line 141 and the normal output end wiring of the n-th stage driver unit 123n, a laser method is used to destroy the insulation layer between the first repair input line 131 or the second repair input line 141 and the normal output end wiring of the n-th stage driver unit 123n, thereby achieving electrical connection between the first repair input line 131 or the second repair input line 141 and the output end wiring of the n-th stage driver unit 123n, so that the output signal of the normal n-th stage driver unit 123n can be transmitted to the modification circuit through the first repair input line 131 or the second repair input line 141 as the signal to be repaired fn.

[0104] At the same time, at the intersection of the first repair output line 132 and the first end of the n-th row scan line Gn, and at the intersection of the second repair output line 142 and the second end of the n-th row scan line Gn, a laser method is also used to achieve the electrical connection between the first repair output line 132 and the first end of the n-th row scan line Gn, and the electrical connection between the second repair output line 142 and the second end of the n-th row scan line Gn, so that the scanning repair signal f4 generated by the repair circuit 30 is transmitted as a new n-th level scanning signal to the two ends of the n-th row scan line Gn through the first repair output line 132 and the second repair output line 142, respectively, to normally drive the n-th row sub-pixel.

[0105] It should be noted that the locations of the electrical connections of the traces cut off by laser or the electrical connections of the traces must be outside the pixel array area 11, that is, the breakpoints and connection points between the scan lines G1~Gw, the repair lines and the output end traces of the gate drive module must be located outside the pixel array area 11, so as to avoid the breakpoints and connection points affecting the normal display of the display area.

[0106] For example, Figure 3 As shown, the example of an n-th driver unit 123n in the second gate driver module 122 experiencing an abnormal output while the first gate driver module 121 experiences a normal output is described. As described above, the first end of the n-th scan line Gn is disconnected from the n-th driver unit 123n in the first gate driver module 121, and the second end of the n-th scan line Gn is disconnected from the n-th driver unit 123n in the second gate driver module 122. The output end of the n-th driver unit 123n in the first gate driver module 121 is electrically connected to the first repair input line 131, transmitting the output signal of the n-th driver unit 123n to the repair circuit 30 as a signal to be repaired fn. The repair circuit 30 then performs repair processing on the signal to be repaired fn and generates a scan repair signal f4, which serves as a new n-th scan signal. One end of the first repair output line 132 and the second repair output line 142 are electrically connected to the output end of the repair circuit 30, and the other end are electrically connected to the first end and the second end of the nth scan line G1~Gw respectively, so as to transmit the new nth level scan signal to the nth row scan line Gn, thereby normally driving the nth row sub-pixel.

[0107] In some embodiments, the drive control board 20 includes a first drive control unit 21 and a second drive control unit 22 ; the first drive control unit 21 and the second drive control unit 22 are arranged in a direction parallel to the side of the drive substrate 10 ; the repair circuit 30 is disposed in the first drive control unit 21 ;

[0108] The drive control board 20 is coupled to the drive substrate 10 via a plurality of chip-on-films (COFs) 40 . Among the COFs 40 electrically connected to the first drive control unit 21 , the outermost COF 40 is a first outer COF 41 , and the COF 40 closest to the second drive control unit 22 is a first inner COF 42 . Among the COFs 40 electrically connected to the second drive control unit 22 , the outermost COF 40 is a second outer COF 43 , and the COF 40 closest to the first drive control unit 21 is a second inner COF 44 .

[0109] The first repair input line 131 and the first repair output line 132 extend to the repair circuit 30 through the first outer chip-on-film 41 and are electrically connected to the repair circuit 30 ;

[0110] The second repair input line 141 and the second repair output line 142 extend to the second drive control unit 22 through the second outer chip-on-film 43, and extend along the second drive control unit 22 to a position close to the first drive control unit 21, and then extend along the second inner chip-on-film 44 to the drive substrate 10, and extend on the drive substrate 10 in a direction close to the first drive control unit 21 to a position of the first inner chip-on-film 42, and extend along the first inner chip-on-film 42 to the first drive control unit 21, and are electrically connected to the repair circuit 30.

[0111] Specifically, the driver control board 20 includes a first driver control unit 21 and a second driver control unit 22 arranged along the sub-pixel rows. Considering that the second driver unit 123 often has insufficient flash memory space, the repair circuit 30 is disposed within the first driver control unit 21 to overcome this issue and prevent insufficient flash memory space within the driver unit 123 from affecting signal processing within the repair circuit 30 and resulting in poor repair performance.

[0112] Due to the narrow frame design, the space available for wiring on the drive substrate 10 is relatively tight, and there is insufficient space for wiring design of the repair line and the repair circuit 30. To solve this technical problem, the embodiment of the present application sets the repair circuit 30 on the first drive control unit 21 outside the drive substrate 10 through the above-mentioned setting method, and extends the first repair input line 131, the first repair output line 132, the second repair input line 141 and the second repair output line 142 to the first drive control unit 21 through the cover film 40, and realizes electrical connection with the repair circuit 30, effectively reducing the space occupied by the repair circuit 30 and the repair line on the drive substrate 10, thereby solving the problem of tight wiring space and difficult wiring on the drive substrate 10.

[0113] In this embodiment, taking the side where the first gate driving module 121 and the first driving control unit 21 are located as the left side and the side where the second gate driving module 122 and the second driving control unit 22 are located as the right side as an example, the first repair input line 131 and the first repair output line 132 are located on the left side, and the second repair input line 141 and the second repair output line 142 are located on the right side.

[0114] The first repair input line 131 and the first repair output line 132 extend into the first driving control unit 21 through the first outer flip chip film 41 closest to the left, and are electrically connected to the first input end and the first output end of the driving circuit respectively to reduce the path length of the first repair input line 131 and the first repair output line 132.

[0115] In one embodiment, the first drive control unit 21 is provided with a first connector 211, and the second drive control unit 22 is provided with a second connector 221. The first connector 211 and the second connector 221 are used to electrically connect to the central control board 200 (CB) or the client system on a chip (SOC) to receive relevant control signals provided by the central control board 200 or the client system on a chip. The second repair input line 141 and the second repair output line 142 extend through the second outermost chip-on-film 43 closest to the right to the second drive control unit 22. Then, the second connector 221 passes through the central control board 200 or the client system on a chip, connecting the corresponding signals of the second connector 221 to the first connector 211. Finally, the second connector 211 enters the first drive control unit 21 and is electrically connected to the first input terminal and the second output terminal of the repair circuit 30, respectively, thereby realizing signal transmission between the repair circuit 30 and the corresponding abnormal scan line Gn for the signal to be repaired fn and the scan repair signal f4.

[0116] In specific applications, the data transmission protocol used by the first connector 211 and the second connector 221 typically requires a common pin on each connector. While this method of connecting repair line signals through connectors is relatively easy to implement, it presents challenges with compatibility. Specifically, the second repair input line 141 and the second repair output line 142 need to be connected via common pins on the first connector 211 and the second connector 221. This requires adding two new signals (input and output) to the pin definitions of each connector, depending on the data transmission protocol used by the connectors. First, due to the limited number of pins on the connectors, there may not be enough space for these new signals. Second, the change in pin definition requires separate design changes to the client's system-on-chip (SOC) or central control board 200 (CB), making the existing SOC or CB incompatible. Furthermore, developing a dedicated SOC or CB significantly increases costs.

[0117] To solve the above technical problems, in an embodiment of the present application, the second repair input line 141 and the second repair output line 142 extend to the second drive control unit 22 through the second outer chip-on-chip film 43 on the far right, and extend along the second drive control unit 22 to a position close to the first drive control unit 21, and then extend along the second inner chip-on-chip film 44 back to the edge position of the drive substrate 10, and extend on the drive substrate 10 in a direction close to the first drive control unit 21 to the position of the first inner chip-on-chip film 42, and extend to the first drive control unit 21 through the first inner chip-on-chip film 42, and are electrically connected to the first input end and the second output end of the repair circuit 30, thereby realizing signal transmission of the signal to be repaired fn and the scanning repair signal f4.

[0118] By routing the second repair input line 141 and the second repair output line 142 on the right side in this manner, the second repair input line 141 and the second repair output line 142 can be electrically connected to the repair circuit 30 simply by routing them across the driver substrate 10, the COF 40, the second driver control unit 22, and the first driver control unit 21, thereby repairing the abnormal output of the abnormal driver unit 123. Signal connections are no longer made through the first connector 211 and the second connector 221. This solves the problem of simultaneously introducing the second repair output line 142 and the second repair output line 142 due to the limited number of common pins on the first connector 211 and the second connector 221. Furthermore, because this embodiment can repair abnormal scan signals within the display panel 100 without requiring the involvement of the client SoC or the central control board 200, no modifications are required to the client, and no dedicated client SoC is required. This not only solves the problem of the client SoC or the central control board 200 being non-universal, but also significantly reduces repair costs, thereby effectively reducing product production costs. In addition, this repair method does not require defining the universal pins of the connector, that is, it does not require changing the pin definitions of the connector, nor does it require any changes to the client system-on-chip or the central control board 200. It can effectively simplify the repair operation, greatly reduce the difficulty of repair, and thus improve the quality of repair.

[0119] In this embodiment, the first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 are arranged in the aforementioned manner to cut off abnormal scanning signals appearing on the display panel 100, preventing the abnormal scanning signals from entering the pixel array area 11 and causing display abnormalities. The output signals of normal drive units 123 at the same level as the abnormal drive unit 123 are transmitted to the repair circuit 30 via the first repair input line 131 or the second repair input line 141, completing signal acquisition. The repair circuit 30 then performs repair processing based on the acquired signals. The repaired scan repair signal f4 is then transmitted back to the corresponding scan line Gn via the first repair output line 132 and the second repair output line 142. The coordinated operation of the repair lines and the repair circuit 30 effectively repairs the abnormal scanning signals. Furthermore, by integrating the repair lines into the repair circuit 30 of the first drive control unit 21, signal repair can be performed outside the drive substrate 10 and then sent back inside the panel. This simplifies the repair structure on the drive substrate 10, improves versatility, and facilitates a narrow-frame design for the display panel 100.

[0120] Furthermore, the first repair input line 131, the first repair output line 132, the second repair input line 141 and the second repair output line 142 extend through the gate area 402 of the COF to the drive control board 20 to realize electrical connection with the repair circuit 30, and the wiring method is simple and easy to implement. Among them, the second repair input line 141 and the second repair output line 142 are wired through the second outer chip-on-film 43—second drive control unit 22—second inner chip-on-film 44—drive substrate 10—first inner chip-on-film 42—first drive control unit 21—repair circuit 30. The wiring only passes through the chip-on-film 40 to enter the drive control board 20 and realize electrical connection with the repair circuit 30. Compared with wiring through the connector in the second drive control unit 22 and the connector in the second drive control unit to realize signal connection, this wiring method does not require any changes to the client SOC. The repair can be completed only on the display panel. The structure is simpler, the introduction difficulty is lower, the repair difficulty is greatly reduced, and the repair effect is better. In addition, there is no need to consider the problem of insufficient number of universal pins of the connector and the need to redesign the client SOC to match the connector after the pin definition (pin define) is changed. That is, the wiring method of this embodiment does not require changing the pins of the connector on the drive control unit, which greatly reduces the difficulty and is easy to implement. It can be used with the existing client SOC, effectively reducing product costs.

[0121] See also Figure 4 , Figure 4 The structure of a COF (Chip-on-Foil) according to one embodiment of the present application is schematically shown. Specifically, COF 40 is divided into a data region 401 and a gate region 402. The gate regions 402 are located on opposite sides of the data region 401, parallel to the extension direction of the driver control board 20. The data region 401 houses the driver chip 45, while the gate region 402 is used for wiring. Specifically, the first repair input line 131, the first repair output line 132, the second repair input line 141, and the second repair output line 142 are routed within and extend along the gate region 402.

[0122] Specifically, along the extension direction of the drive control board 20, the areas on both sides of the chip-on-chip film 40 are gate areas 402, and the middle area is the data area 401. The data area 401 in the middle is used to set the drive chip 45 and the wiring connected to the drive chip 45 (not shown); the gate areas 402 on both sides are usually vacant. In the embodiment of the present application, the repair line only needs to be wired on the chip-on-chip film 40. Therefore, laying the repair line in the gate area 402 can rationally utilize the structural characteristics of the chip-on-chip film 40, and the part of the repair line located on the chip-on-chip film 40 can be manufactured in the same process as the wiring of the data area 401. There is no need to make an additional metal layer specifically for forming this part of the repair line. It can simplify the process and the structure of the chip-on-chip film 40, so that it can be bound to the drive substrate 10 and the drive control board 20, thereby reducing the difficulty of wiring.

[0123] Please refer to Figure 3 Specifically, part of the routing of the second repair input line 141 and the second repair output line 142 on the second outer chip-on-film 43 can be set at the gate area 402 on the side of the second outer chip-on-film 43 away from the second inner chip-on-film 44, that is, set at the right gate area 402 of the second outer chip-on-film 43; part of the routing of the second repair input line 141 and the second repair output line 142 on the second inner chip-on-film 44 can be set at the gate area 402 on the side of the second inner chip-on-film 44 away from the second outer chip-on-film 43, that is, set at the left gate area 402 of the second inner chip-on-film 44; part of the routing of the second repair input line 141 and the second repair output line 142 on the first inner chip-on-film 42 can be set at the gate area 402 on the side of the first inner chip-on-film 42 close to the second inner chip-on-film 44, that is, set at the right gate area 402 of the first inner chip-on-film 42. The first repair input line 131 and the first repair output line 132 on the first outer COF 41 can be partially routed in the gate region 402 on the side of the first outer COF 41 away from the first inner COF 42, i.e., the left gate region 402 of the first outer COF 41. In specific applications, depending on the specific wiring situation, the partial routing of the repair line on the COF 40 can be routed in one or both of the two gate regions 402 to reduce routing length and mitigate the impact of routing RC.

[0124] The specific structure of the repair circuit 30 and the signal repair process are as shown in the previous embodiment, and please refer to the following detailed description.

[0125] See also Figure 5 , Figure 5 : is a schematic diagram of the structure of a repair circuit provided in an embodiment of the present application. In this embodiment, a repair circuit 30 is provided, which is used to repair abnormal scanning signals in the display panel 100. The repair circuit 30 includes:

[0126] An input module 31, having a first input terminal receiving a signal to be repaired fn and a first output terminal electrically connected to a first node N1, for performing voltage reduction processing on the signal to be repaired fn and outputting a first input signal f1 at the first output terminal;

[0127] The processing module 32 includes a delay removal unit 33, a shaping unit 34, and a level conversion unit 35; wherein:

[0128] The control terminal of the de-delay unit 33 is electrically connected to the first node N1, the input terminal is coupled to the corresponding clock signal CLKi, and the output terminal is electrically connected to the second node N2. The de-delay unit 33 is configured to de-delay the falling edge of the first input signal f1 according to the corresponding clock signal CLKi and output a de-delayed signal f2 at the output terminal. The falling edge of the de-delayed signal f2 is consistent with the falling edge of the corresponding clock signal CLKi.

[0129] The input end of the shaping unit 34 is electrically connected to the second node N2, and is used to shape the waveform of the delay-removed signal f2 and output a square wave signal f3 at the output end;

[0130] The level conversion unit 35 has an input end electrically connected to the output end of the shaping unit 34 , is used to adjust the level of the square wave signal f3 , and output the scan repair signal f4 at the output end.

[0131] As described above, in the display panel 100, when the output of the n-th driver unit 123n in the first gate driver module 121 or the second gate driver module 122 is abnormal, the scan signal on the corresponding n-th scan line Gn becomes abnormal. The normal n-th scan signal output by the n-th driver unit 123n is transmitted to the repair circuit 30 via the first repair input line 131 or the second repair input line 141 as the signal to be repaired fn for the repair circuit 30. Due to the influence of the wiring RC within the display panel 100, the signal to be repaired fn sent to the repair circuit 30 is delayed. If it is directly sent back to the n-th scan signal, the signal delay will cause the sub-pixels in that row to be turned off later. This will cause the data of the next row to be incorrectly charged into the sub-pixels in that row, resulting in image distortion. The repair circuit 30 provided in this embodiment repairs the delayed signal to be repaired fn, generates a de-delayed scan repair signal f4 as a new n-th level scan signal, and sends it to the n-th row scan line Gn through the above-mentioned first repair output line 132 and second repair output line 142, thereby normally driving the n-th row of sub-pixels.

[0132] The first input terminal of the input module 31 in the repair circuit 30 is electrically connected to the first repair input line 131 or the second repair input line 141 to receive the signal to be repaired fn. The input module 31 is configured to reduce the voltage of the signal to be repaired fn to generate the first input signal f1. The output terminal of the input module 31 is electrically connected to the first node N1 of the repair circuit 30 to output the generated first input signal f1 after the voltage reduction process to the first node N1.

[0133] It should be noted that the voltage difference between the high and low levels of a normal scanning signal is a first voltage difference, and the maximum threshold voltage that the de-delay unit 33 can withstand is less than the first voltage difference. The voltage difference between the high and low levels of the signal to be repaired fn is also the first voltage difference. Therefore, if the signal to be repaired fn is directly connected to the control terminal of the de-delay unit 33, it will damage the de-delay unit 33, resulting in the repair circuit 30 being unable to properly repair the signal to be repaired fn. For example, the first voltage difference between the high and low levels of a normal scanning signal typically reaches 37V, meaning that the high and low voltage difference of the signal to be repaired fn can reach 37V, while the maximum threshold voltage of the de-delay unit 33 is 30V.

[0134] In this embodiment, the input module 31 is configured to first reduce the voltage of the signal to be repaired fn to generate the first input signal f1, so that the high and low voltage difference of the first input signal f1 can meet the threshold voltage specification of the de-delay unit 33, thereby preventing the voltage difference of the input signal from being too large and damaging the de-delay unit 33.

[0135] The control terminal of the de-delay unit 33 is electrically connected to a first node N1 to receive the first input signal f1 after voltage reduction. The input terminal of the de-delay unit 33 is coupled to the corresponding clock signal CLKi, and the output terminal is electrically connected to a second node N2. The corresponding clock signal CLKi is the clock signal CLK corresponding to the n-th stage driver unit 123n. The de-delay unit 33 is configured to de-delay the first input signal f1 based on the corresponding clock signal CLKi, so that the falling edge of the output de-delayed signal f2 is aligned with the falling edge of the corresponding clock signal CLKi, thereby eliminating the delay in the falling edge of the first input signal f1. This prevents the driver transistor of the corresponding row from being delayed in turning off, which could cause the data of the next row to be incorrectly fed into the row and cause image distortion.

[0136] Among them, the input end of the shaping unit 34 is electrically connected to the second node N2 to receive the de-delayed signal f2 at the second node N2, and performs shaping processing on the de-delayed signal f2 to convert the de-delayed signal f2 into a square wave signal f3, and output it to the output end of the shaping unit 34, thereby improving the problem of the slow rising edge of the de-delayed signal f2, making the signal waveform a more regular square wave, and further making the signal output by the level conversion unit 35 more accurate.

[0137] Among them, the input end of the level conversion unit 35 is electrically connected to the output end of the shaping unit 34 to receive the square wave signal f3, and level-adjust the square wave signal f3 to generate a scanning repair signal f4, so that the high and low levels of the scanning repair signal f4 generated after the level adjustment are consistent with the high and low levels of the scanning signal to meet the requirements of sub-pixel scanning drive.

[0138] The embodiment of the present application generates a scanning repair signal f4 through the coordinated work of the above-mentioned input module 31, de-delay unit 33, shaping unit 34 and level conversion unit 35, thereby achieving effective repair of the output signal of the gate drive in the display panel 100, thereby avoiding the problem of dark lines appearing on the display screen due to poor gate drive in the display panel 100, and effectively improving product yield.

[0139] See also Figure 6 , Figure 6 3 is a schematic diagram of the structure of an input module provided in an embodiment of the present application. In this embodiment, the input module 31 includes a second voltage dividing unit 311, which is used to reduce the voltage of the signal to be repaired fn and output the first input signal f1.

[0140] Among them, the second voltage dividing unit 311 includes a fourth voltage dividing resistor R4 and a fifth voltage dividing resistor R5, one end of the fourth voltage dividing resistor R4 is connected to the signal to be repaired fn, and the other end is electrically connected to the first node N1, and one end of the fifth voltage dividing resistor R5 is electrically connected to the first node N1, and the other end is grounded GND.

[0141] Specifically, the resistance values of the fourth voltage-dividing resistor R4 and the fifth voltage-dividing resistor R5 can be set according to the voltage-dividing requirement, and there is no specific limitation on this. The potential at the first node N1 is Gin·R5 / (R4+R5). It can be seen that the voltage-dividing ratio of the second voltage-dividing unit 311 is R5 / (R4+R5). Specifically, the voltage-dividing ratio of the second voltage-dividing unit 311 can be controlled by adjusting the ratio between the fourth voltage-dividing resistor R4 and the fifth voltage-dividing resistor R5, thereby adjusting the voltage of the first input signal f1 output by the second voltage-dividing unit 311. Furthermore, in this embodiment, by grounding the other end of the fifth voltage-dividing resistor R5 to GND, the ground GND voltage is used as a reference during voltage division, so that the first input signal f1 can reach the threshold voltage of the de-delay unit 33 more quickly, causing the de-delay unit 33 to turn on quickly, thereby reducing the delay time of the rising edge of the first input signal f1.

[0142] Furthermore, the input module 31 also includes at least one dip switch 313, the dip switch 313 includes multiple switch channels, the input end of the switch channel is connected to each clock signal CLK, and the output end is electrically connected to the input end of the de-delay unit 33. The dip switch 313 is used to turn on the switch channel where the corresponding clock signal CLKi is located to send the corresponding clock signal CLKi to the input end of the de-delay unit 33.

[0143] For example, in one specific application, the display panel 100 uses 12 clock signals CLK with different timing sequences. The input module 31 includes two dip switches 313, each of which includes six switching channels. Thus, the two dip switches 313 have a total of 12 switching channels, each of which corresponds to a clock signal CLK. When the output of the n-th stage driver unit 123n in the first gate driver module 121 or the second gate driver module 122 is abnormal, the repair circuit 30 repairs the n-th stage scan signal. The corresponding clock signal CLKi connected to the input of the de-delay unit 33 is the clock signal CLK corresponding to the n-th stage driver unit 123n. The dip switch 313 then turns on the switching channel corresponding to the clock signal CLKi, thereby transmitting the corresponding clock signal CLKi to the input of the de-delay unit 33.

[0144] Furthermore, the input module 31 also includes a first filter capacitor C1, the first end of the first filter capacitor C1 is electrically connected to the first node N1, and the second end is grounded GND, so as to offset the parasitic capacitance in the de-delay unit 33, thereby filtering out the noise in the first input signal f1 after voltage division that is at the same frequency as the clock signal CLK, effectively suppressing signal noise and improving the signal repair effect.

[0145] See also Figure 7 , Figure 7 Schematic diagram of the structure of the input module provided by another embodiment of the present application. Figure 6 The difference from the embodiment is that, in this embodiment, the input module 31 further includes a third voltage dividing unit 312, and the third voltage dividing unit 312 is used to perform voltage reduction processing on the corresponding clock signal CLKi and output a second input signal.

[0146] Among them, the third voltage-dividing unit 312 includes a sixth voltage-dividing resistor R6 and a seventh voltage-dividing resistor R7, one end of the sixth voltage-dividing resistor R6 is connected to the corresponding clock signal CLKi, and the other end is electrically connected to the third voltage-dividing node, one end of the seventh voltage-dividing resistor R7 is electrically connected to the third voltage-dividing node, and the other end is grounded GND; the input end of the de-delay unit 33 is electrically connected to the third voltage-dividing node.

[0147] Specifically, the resistance values of the sixth voltage-dividing resistor R6 and the seventh voltage-dividing resistor R7 can be set according to the voltage-dividing requirement, and no specific limitation is imposed on this. The potential at the third node N3 is CLKi·R7 / (R7+R8). It can be seen that the voltage-dividing ratio of the third voltage-dividing unit 312 is R7 / (R7+R8). Specifically, the voltage-dividing ratio of the third voltage-dividing unit 312 can be controlled by adjusting the ratio between the seventh voltage-dividing resistor R7 and the eighth voltage-dividing resistor, thereby adjusting the voltage of the second input signal output by the third voltage-dividing unit 312.

[0148] Specifically, due to the presence of parasitic capacitance in the de-delay unit 33, the signals at the control end and the output end of the de-delay unit 33 are prone to spike waveforms (noise) with the same frequency as the corresponding clock signal CLKi. By setting the above-mentioned third voltage divider unit 312 between the corresponding clock signal CLKi and the input end of the de-delay unit 33, the voltage of the corresponding clock signal CLKi is reduced before being sent to the input end of the de-delay unit 33, thereby reducing the impact of the parasitic capacitance and weakening the spike waveforms (noise) in the signals at the control end and the output end of the de-delay unit 33.

[0149] In some embodiments, the input module 31 also includes at least one dip switch 313, the dip switch 313 includes multiple switch channels, the input end of the switch channel is connected to each clock signal CLK, and the output end is electrically connected to one end of the sixth voltage-dividing resistor R6, so as to send the corresponding clock signal CLKi into the third voltage-dividing unit 312 through the dip switch 313, and the corresponding clock signal CLKi is subjected to the above-mentioned voltage-dividing processing through the third voltage-dividing unit 312.

[0150] See also Figure 8 , Figure 8 This is a driving timing diagram of a normal scanning signal and a signal to be repaired provided by an embodiment of the present application. As shown in the figure, the green waveform is the clock signal CLK corresponding to the n-th level driving unit 123n, that is, the corresponding clock signal CLKi, the blue waveform is the signal to be repaired fn after the voltage reduction process, that is, the first input signal f1, and the orange signal is the data signal. Among them, T1 is the charging time of the n-th row sub-pixel, but because the signal to be repaired fn collected back through the first repair input line 131 or the second repair input line 141 will be delayed after passing through the wiring RC in the display panel 100, the falling edge of the signal to be repaired fn will be delayed. Correspondingly, the driving transistor in the corresponding n-th row sub-pixel is delayed in closing, resulting in that when the next row of sub-pixels is turned on, the sub-pixels in the changed row are still not closed, so that the next row of data signals are mistakenly charged into the sub-pixels in this row, resulting in abnormal screen display.

[0151] See also Figure 9 and Figure 10 , Figure 9 is a schematic structural diagram of a delay removal unit provided in one embodiment of the present application. Figure 10 Figure 3 is a schematic diagram of the driving timing of a de-delay unit provided in one embodiment of the present application. In this embodiment, the de-delay unit is provided within processing module 32 to address the aforementioned data signal mismatching issue. Specifically, de-delay unit 33 includes a switching transistor Q1, whose control terminal is electrically connected to a first node N1, a first terminal coupled to a corresponding clock signal CLKi, and a second terminal electrically connected to a second node N2.

[0152] Specifically, the switch transistor Q1 may be an NMOS transistor, the control end of the switch transistor Q1 is a gate, the first end is a drain, and the second end is a source.

[0153] like Figure 10 As shown, when the first input signal f1 is at a high level, the switching transistor Q1 is turned on. After being turned on, since the corresponding clock signal CLKi at the first end of the switching transistor Q1 is at a high level, the second end also inputs a high level. When the corresponding clock signal CLKi switches to a low level, the second end also switches to a low level, thereby achieving the effect of turning off the first input signal f1 in advance, so that the falling edge of the de-delayed signal f2 outputted from the second end is completely aligned with the falling edge of the corresponding clock signal CLKi.

[0154] In this embodiment, since the maximum specification of the threshold voltage of the NMOS tube is less than the first voltage difference between the high and low levels of the signal to be repaired fn, the above-mentioned second voltage divider module is set in the input module 31 to perform voltage division processing on the signal to be repaired fn to generate a maximum specification that meets the threshold voltage of the switching transistor Q1.

[0155] See also Figure 11 , Figure 11 FIG2 is a driving timing diagram of a de-delay unit according to another embodiment of the present application. In this embodiment, the de-delay unit 33 further includes an adjustment unit 331, one end of which is electrically connected to the second node N2 and the other end of which is connected to the pull-down power signal Vss. The adjustment unit 331 also includes a pull-up resistor R8, one end of which is electrically connected to the second node N2 and the other end of which is connected to the pull-down power signal Vss. The pull-down resistor is an adjustable resistor.

[0156] Specifically, one end of the pull-up resistor R8 is electrically connected to the source of the switching transistor Q1, and the other end is connected to the pull-down power signal Vss. When the switching transistor Q1 is turned on, the pull-down power signal Vss discharges the second end (second node N2) of the switching transistor Q1, thereby pulling down the potential of the second node N2 and reducing the high potential at the second node N2. The pull-up resistor R8 is used to pull up the potential of the second end (second node N2) of the switching transistor Q1 so that the low level at the second node N2 does not fall below a preset value.

[0157] In one embodiment, the pull-up resistor R8 is an adjustable resistor. The resistance of the pull-up resistor R8 can be adjusted to keep the voltage of the signal at the second node N2 within the normal operating range of the shaping unit 34. For example, the pull-down power supply signal Vss can be 1.8V. Thus, after the adjustment unit 331 adjusts the signal voltage at the second node N2, the voltage fluctuation range can be within a voltage range of (-0.3)V to VCC, where VCC represents the positive power supply voltage signal VCC required by the shaping unit 34.

[0158] Furthermore, the delay removal unit 33 may also include a second filter capacitor C2 and a third filter capacitor C3. The second filter capacitor C2 has one end electrically connected between the pull-up resistor R8 and the pull-down power supply signal Vss, and the other end is grounded to GND. The third filter capacitor C3 has one end electrically connected to the second node N2 and the other end is grounded to GND. The second and third filter capacitors C2 and C3 are used to remove signal noise and stabilize voltage.

[0159] See also Figure 12 and Figure 13 , Figure 12 is a structural diagram of a shaping unit provided in one embodiment of the present application. Figure 13 Figure 3 is a schematic diagram of the driving timing of a shaping unit according to an embodiment of the present application. In this embodiment, shaping unit 34 includes an op amp chip 341. Op amp chip 341 has a first input electrically connected to second node N2, a second input connected to reference voltage signal Vref, and an output electrically connected to the input of level shifter 35. Op amp chip 341 is configured to compare the de-delayed signal f2 with reference voltage signal Vref to output a square wave signal f3 at its output.

[0160] The operational amplifier chip 341 can function as a comparator. A first input terminal of the operational amplifier chip 341 is electrically connected to the second node N2 and is configured to receive the second input signal generated after the delay removal process. A second input terminal of the operational amplifier chip 341 is connected to the reference voltage signal Vref, enabling the operational amplifier chip 341 to perform a comparison operation and output a high or low level based on the comparison result, thereby forming a square wave signal f3. Specifically, when the potential of the second input signal is greater than the potential of the reference voltage signal Vref, the operational amplifier chip 341 outputs a high level; when the potential of the second input signal is less than the potential of the reference voltage signal Vref, the operational amplifier chip 341 outputs a low level.

[0161] The first power input terminal of the operational amplifier chip 341 is connected to the positive power voltage signal VCC, and the second power input terminal is connected to the ground GND. It should be noted that the voltage of the positive power voltage signal VCC is greater than the ground GND voltage. Specifically, Figure 13As shown, when the potential of the second input signal is greater than the reference voltage signal Vref, the op amp chip 341 outputs a high level, the value of which is the same as the voltage of the positive power supply voltage signal VCC. When the potential of the second input signal is less than the reference voltage signal Vref, the op amp chip 341 outputs a low level, the value of which is the same as the ground voltage GND. Thus, after the op amp chip 341 performs the above-mentioned processing on the second input signal, a square wave signal f3 is generated and outputted through the output terminal. By performing the comparative processing on the second input signal by the op amp chip 341 to generate a square wave signal f3 with a more regular waveform, the signal output by the level conversion unit 35 can be further made more accurate, thereby improving the accuracy of signal repair.

[0162] In one embodiment, the power supply voltage input range of the operational amplifier chip 341 is 4.5V to 19V, while the voltage input range of the input of the level shifter 35 electrically connected to the output of the operational amplifier chip 341 is (-0.3)V to 5.5V. Therefore, the voltage range of the square wave signal f3 output by the operational amplifier chip 341 must meet the voltage input range of the input of the level shifter 35. Therefore, the voltage value of the positive power supply voltage signal VCC can range from 2V to 5V. For example, in one specific embodiment, the voltage value of the positive power supply voltage signal VCC can be set to 5V, and the voltage value of the reference voltage signal Vref can be set to 2.5V, so that the operational amplifier chip 341 generates a square wave signal f3 of 0 to 5V, which meets the voltage input range requirement of the input of the level shifter 35.

[0163] In one embodiment, the shaping unit 34 further includes a first voltage divider unit 342, which includes a first voltage divider resistor R1, a second voltage divider resistor R2, and a third voltage divider resistor R3 connected in series. One end of the first voltage divider resistor R1 is connected to the initial power signal HVAA. The connection node between the first voltage divider resistor R1 and the second voltage divider resistor R2 is a first voltage divider node N4, and the connection node between the second voltage divider resistor R2 and the third voltage divider resistor R3 is a second voltage divider node N5. The first voltage divider node N4 is electrically connected to the positive power input terminal of the operational amplifier chip 341 for providing a positive power supply voltage signal VCC to the operational amplifier chip 341. The second voltage divider node N5 is electrically connected to the second input terminal of the operational amplifier chip 341 for providing a reference voltage signal Vref to the operational amplifier chip 341.

[0164] In this embodiment, a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, and a third voltage-dividing resistor R3 are connected in series. A first voltage-dividing node N4 is provided between the first and second voltage-dividing resistors R1 and R2, and a second voltage-dividing node N5 is provided between the second and third voltage-dividing resistors R2 and R3. The end of the first voltage-dividing resistor R1, away from the first voltage-dividing node N4, is connected to the initial power signal HVAA, and the other end of the third voltage-dividing resistor R3, away from the second voltage-dividing node N5, is connected to ground GND. It can be seen that the voltage at the first voltage-dividing node N4 is HVAA·(R2+R3) / (R1+R2+R3), and the voltage at the second voltage-dividing node N5 is HVAA·R3 / (R1+R2+R3). Specifically, the voltage at the first voltage dividing node N4 and the voltage at the second voltage dividing node N5 can be adjusted by adjusting the resistance values of the first voltage dividing resistor R1, the second voltage dividing resistor R2 and the third voltage dividing resistor R3 to meet the requirements of the operational amplifier chip 341 for the positive power supply voltage signal VCC and the reference voltage signal Vref.

[0165] It should be noted that the initial power signal HVAA is provided by the driver control board 20 of the display panel 100 and is the most stable voltage source on the driver control board 20. In this embodiment, by providing a first voltage divider resistor R1, the positive power supply voltage signal VCC and the reference voltage signal Vref required by the operational amplifier chip 341 are both divided by the initial power supply signal HVAA. This makes the positive power supply voltage signal VCC and the reference voltage signal Vref more stable, thereby making the square wave signal f3 generated by the operational amplifier chip 341 more regular and stable.

[0166] Furthermore, the first voltage divider unit 342 also includes a fourth filter capacitor C4 and a fifth filter capacitor C5. One end of the fourth filter capacitor C4 is electrically connected to the first voltage divider node N4, and the other end is grounded to GND. One end of the fifth filter capacitor C5 is electrically connected to the second voltage divider node N5, and the other end is grounded to GND. The fourth filter capacitor C4 and the fifth filter capacitor C5 are respectively used to filter out signal noise at the first voltage divider node N4 and the second voltage divider node N5, thereby further stabilizing the positive power supply voltage signal VCC and the reference voltage signal Vref.

[0167] See also Figure 14 and Figure 15 , Figure 14 is a schematic structural diagram of a level conversion unit provided in an embodiment of the present application. Figure 15FIG2 is a schematic diagram of the driving timing of a level conversion unit provided in one embodiment of the present application. In this embodiment, the level conversion unit 35 includes a level conversion chip 351. The input end of the level conversion chip 351 is electrically connected to the output end of the shaping unit 34. The first power input end is connected to the gate high level signal VGH, and the second power input end is connected to the gate low level signal VGL. The level conversion unit 351 is used to convert the high level of the square wave signal f3 into the gate high level and the low level of the square wave signal f3 into the gate low level.

[0168] The input terminal of the level conversion chip 351 is electrically connected to the output terminal of the shaping unit 34 to receive the square wave signal f3; the first power input terminal is connected to the gate high level signal VGH, and the second power input terminal is connected to the gate low level signal VGL. Figure 15 As shown, when the square wave signal f3 is at a high level, the level conversion chip 351 pulls the high level up to the gate high level; when the square wave signal f3 is at a low level, the level conversion chip 351 pulls the low level down to the gate low level to generate a scan repair signal f4, and makes the high level and low level of the scan repair signal f4 the same as the high level and low level of the required scan signal, and the falling edge is also aligned with the falling edge of the corresponding constant signal, thereby achieving effective repair of the signal to be repaired fn.

[0169] See also Figure 16 , Figure 16 FIG2 is a schematic diagram of the structure of the output module provided in the first embodiment of the present application. In this embodiment, the repair circuit 30 further includes an output module 36, which is electrically connected to the output terminal of the level conversion unit 35 and is used to match the corresponding impedance of the scan repair signal f4. The output module 36 includes a first adjustment unit 361, which includes a first adjustment resistor R9. One end of the first adjustment resistor R9 is electrically connected to the output terminal of the level conversion unit 35, and the other end is electrically connected to the adjustment node N6. The first adjustment resistor R9 is a variable resistor.

[0170] Specifically, the scan repair signal f4 is transmitted to the corresponding scan lines G1-Gw in the pixel array area 11 via the first repair output line 132 and the second repair output line 142. Scan lines G1-Gw at different locations require different matching impedances. In this embodiment, a first adjustment resistor R9 is provided at the output end of the level converter to match the corresponding impedance of the scan repair signal f4. This ensures that the impedance-matched scan repair signal f4, after being transmitted to the nth row scan line Gn, has a smaller display effect than the scan signals of adjacent rows.

[0171] Specifically, the first adjustment resistor R9 can be a variable resistor, such as a knob resistor, so that it can be adjusted to match the scan repair signal f4 at different locations, thereby further improving the repair effect of the scan signal. Specifically, the longer the routing path of the repair output line, the smaller the resistance of the knob resistor.

[0172] See also Figure 17 , Figure 17 FIG2 is a schematic diagram of the structure of an output module provided in a second embodiment of the present application. In this embodiment, the output module 36 further includes a second adjustment unit 362, which includes a second adjustment resistor R10 and a third adjustment resistor R11. One end of the second adjustment resistor R10 is electrically connected to the adjustment node N6, and the other end serves as an output end for outputting the adjusted first scanning repair signal f51. One end of the third adjustment resistor R11 is electrically connected to the adjustment node N6, and the other end serves as an output end for outputting the adjusted second scanning repair signal f52.

[0173] Please refer to Figure 3 Since the first repair output line 132 and the second repair output line 142 have different routing path lengths and different routing impedances, it is necessary to match the scanning repair signal f4 on the first repair output line 132 and the scanning signal on the second repair output line 142 with different impedances, respectively. This ensures that the scanning repair signal f4 transmitted to the first end of the n-th row scanning line Gn through the first repair output line 132 is the same as the scanning repair signal f4 transmitted to the second end of the n-th row scanning line Gn through the second repair output line 142, thereby avoiding signal differences at the two ends that may cause display image errors.

[0174] Specifically, after impedance matching is performed through the second adjustment resistor R10, a first scanning repair signal f51 is output. The first scanning repair signal f51 can be transmitted to the first end of the n-th row of scan lines Gn via the first repair output line 132. After impedance matching is performed through the third adjustment resistor R11, a second scanning repair signal f52 is output. The second scanning repair signal f52 can be transmitted to the second end of the n-th row of scan lines Gn via the second repair output line 142.

[0175] In this embodiment, the output impedance of the scanning repair signal f4 is preliminarily matched by the first adjustment unit 361 to correspond to the output impedance of the n-th row scanning line Gn; then the output impedance of the first scanning repair signal f51 on the first repair output line 132 and the second scanning repair signal f52 on the second repair output line 142 are finely matched by the second adjustment unit 362 to correspond to the output impedance of the first end and the second end of the n-th row scanning line Gn, thereby achieving fine adjustment of the output impedance of the output signals on both sides, so that the display effect after repair is more uniform.

[0176] Furthermore, in some high-precision application scenarios, on the one hand, the output impedance matching of the scan repair signal f4 is performed by the output module 36 in the above embodiment. Since the output module 36 uses a variable resistor (such as a knob resistor) for manual adjustment, the adjustment accuracy cannot meet the high-precision requirements; on the other hand, during the manual adjustment operation, frequent contact with the panel will inevitably cause friction, and it is also very likely to cause static damage to the display panel. To solve this technical problem, in some embodiments, another output module 36 is provided at the output end of the level conversion unit 35 (see Figure 18 ), the output module 36 can perform impedance matching on abnormal scanning lines Gn at different positions through a digitally adjustable impedance matching method. The adjustment accuracy is adjustable to meet high-precision requirements, and the digital adjustment method does not require manual adjustment, which can improve the anti-static ability. Please refer to the detailed introduction below for details.

[0177] See also Figure 18 , Figure 18 3 is a schematic diagram of the structure of the output module provided in the third embodiment of the present application. In this embodiment, the output module 36 includes a plurality of RC units 363 connected in series with the output end of the level conversion unit 35 and a plurality of transmission channels 365 connected in parallel.

[0178] A transmission channel 365 is connected between every two adjacent RC units 363 , and each transmission channel 365 is electrically connected to the repair output terminal of the output module 36 . At least one target transistor 364 is connected in series to each transmission channel 365 .

[0179] The gate of the target transistor 364 is used to input a target control signal, and the target control signal is used to control one target transmission channel 365 among the multiple transmission channels 365 to be turned on, so as to transmit the scan repair signal f4 to the repair output end through the target transmission channel 365 after passing through at least one resistor-capacitor unit 363 between the target transmission channel 365 and the output end of the level conversion unit 35.

[0180] The position of the target transmission channel 365 in the plurality of transmission channels 365 matches the position of the scanning lines G1 to Gw where the abnormality occurs.

[0181] Here, the multiple transmission channels 365 can be arranged in multiple rows along the horizontal direction, and the multiple resistor-capacitor units 363 (i.e., RC units) can be arranged in a column along the vertical direction with the output end of the level conversion unit 35, and a transmission channel 365 is connected between every two adjacent resistor-capacitor units 363.

[0182] In one embodiment, the RC unit 363 includes a resistor and a capacitor, the resistor and the capacitor are connected in parallel, and one end of the capacitor is grounded GND.

[0183] In one embodiment, the number of the RC units 363 is the same as the number of the transmission channels 365 , for example, both are 8.

[0184] In one embodiment, each transmission channel 365 may include one or more target transistors 364 . For example, the number of target transistors 364 included in multiple transmission channels 365 may be the same, and the target transistors 364 included in different transmission channels 365 may be controlled by different target control signals.

[0185] In one embodiment, the target transistor 364 may be an N-type metal-oxide-semiconductor field-effect transistor (NMOS) or a P-type metal-oxide-semiconductor field-effect transistor (PMOS). For example, the target transistor 364 is a PMOS transistor. When the target control signal is at a low level, the target transistor 364 is turned on. When the target control signal is at a high level, the target transistor 364 is turned off.

[0186] In one embodiment, when an abnormality occurs at a target position (such as the position of the nth row scan line Gn), that is, during the impedance matching process of a normal signal, only one target transmission channel 365 is turned on, that is, the scan repair signal f4 at the output end of the level conversion unit 35 is only transmitted to the repair output end through one target transmission channel 365.

[0187] In one embodiment, different transmission channels 365 have different numbers of RC units 363 connected in series with the output end of the level conversion unit 35 . The lower the transmission channel 365 is, the more RC units 363 are connected in series with the output end of the level conversion unit 35 .

[0188] For example, one RC unit 363R31C31 is connected in series between the first row of transmission channels 365 and the output end of the level shifter 35. Two RC units 363R31C31 and R32C32 are connected in series between the second row of transmission channels 365 and the output end of the level shifter 35. ... and eight RC units 363R31C31, R32C32 through R38C38 are connected in series between the eighth row of transmission channels 365 and the output end of the level shifter 35. The greater the number of RC units 363 connected in series between a transmission channel 365 and the output end of the level shifter 35, the greater the impedance corresponding to that transmission channel 365.

[0189] In one embodiment, the position of the target transmission channel 365 in the multi-row transmission channel 365 matches the target position where the abnormal scanning signal occurs, which may refer to the position of the target transmission channel 365 in the multi-row transmission channel 365 corresponding to the position of the target row where the abnormal scanning signal occurs in the pixel array area 11.

[0190] For example, the position of the target row in the pixel array area 11 is at the upper part, and the position of the selected target transmission channel 365 in the multi-row transmission channels 365 is also at the upper part, for example, the 1st row or the 2nd row is selected, etc.; the position of the target row in the pixel array area 11 is in the middle part, and the position of the selected target transmission channel 365 in the multi-row transmission channels 365 is also in the middle part, for example, the 4th row is selected, etc.; the position of the target row in the pixel array area 11 is at the lower part, and the position of the selected target transmission channel 365 in the multi-row transmission channels 365 is also at the lower part, for example, the 7th row or the 8th row is selected, etc.

[0191] In this way, based on the relative position of the abnormal scanning signal in the pixel array area 11, a target transmission channel 365 with a matching position is selected. When the impedance matching requirements required for different abnormal positions are different, the impedances provided by the resistor-capacitor units 363 corresponding to different target transmission channels 365 are different, thereby achieving accurate and flexible impedance matching, improving accuracy, and avoiding low accuracy and electrostatic damage caused by manual adjustment of the variable resistor.

[0192] In some embodiments, the target control signal includes: a plurality of first control signals and a plurality of second control signals, the number of the first control signals is the same as the number of the second control signals, and each second control signal is an inverted signal of a first control signal.

[0193] The gate of each target transistor 364 is used to input a first control signal or a second control signal; based on different combinations of multiple first control signals and multiple second control signals, a target transmission channel 365 is controlled to be turned on.

[0194] Here, controlling a target transmission channel 365 to be turned on may refer to controlling all target transistors 364 in the target transmission channel 365 to be turned on. A first control signal or a second control signal may be input to multiple target transistors 364 located in the same column. The multiple target transistors 364 located in the same column may be located in different transmission channels 365.

[0195] For example, Figure 18 As shown, there are three first control signals and three second control signals. The first control signal includes D2, D1 and D0, and the second control signal includes the inverted signal of D2. The inverted signal of D1 and the inverted signal of D0 R31C31, R32C32 . . . R38C38 are the first to eighth resistor-capacitor units 363 respectively.

[0196] In one embodiment, different combinations may refer to different phase combinations. By controlling the phase combinations of multiple first control signals, multiple second control signals can be controlled simultaneously. Each combination of multiple first control signals only corresponds to one transmission channel 365 being turned on.

[0197] Please refer to Figure 19 , Figure 19 It corresponds to Figure 18 For example, when the target position or target row where the abnormal scanning signal is located corresponds to the middle of the pixel array area 11, the phases of D2, D1 and D0 are controlled to be 1, 0 and 0 respectively, and the second control signals are 0, 1 and 1 respectively. Figure 19 As shown, when the target transistors 364 are PMOS transistors, only all target transistors 364 in the fourth transmission channel 365 of the multiple rows of transmission channels 365 are turned on. That is, the fourth transmission channel 365 serves as the target transmission channel 365. At least one target transistor 364 in the remaining transmission channels 365 is turned off. That is, the remaining transmission channels 365 remain closed. At this time, the scan repair signal f4 at the output end of the level conversion unit 35 is transmitted to the repair output end through the first four RC units 363 and the fourth transmission channel 365.

[0198] In this way, by controlling the phase of the first control signal, the switching control of all target transistors 364 can be achieved, and then by combining different combinations of the first control signal, the switching control of different row transmission channels 365 can be accurately achieved, thereby further improving the accuracy and convenience of channel selection control.

[0199] At the same time, considering that the display panel 100 has multiple refresh rates, the signal attenuation of the repair scan signal after it is sent to the target row is different between different refresh rates of the same display panel 100. In some embodiments, the method still adopts Figure 18 The output module 36 in or 19 can be connected to the timing controller (TCON) through the integrated circuit interconnect bus (Inter-Integrated Circuit) protocol.

[0200] In a specific repair process, the attenuation coefficient of the scanning repair signal f4 at different refresh rates can be obtained through testing, and a corresponding relationship table between the refresh rate and the attenuation signal can be stored in a memory.

[0201] When performing impedance matching, the TCON detects the refresh rate of the frame start signal (Shift Register Timing Vertical, STV), reads the corresponding attenuation coefficient based on the refresh rate, and selects the corresponding resistance and capacitance values based on the attenuation coefficient. For example, when selecting the matching impedance corresponding to the fourth row transmission channel 365 based on the refresh rate, the TCON transmits the first control signal D2D1D0 through the IIC. At this time, the output first control signal D2D1D0 is 100, and the scan repair signal f4 passes through the resistor-capacitor units 363R31C31, R32C32, R33C34, and R34C34, and then outputs to the repair output terminal through the fourth row transmission channel 365 to match the corresponding impedance to the corresponding refresh rate.

[0202] When the refresh rate of the display panel 100 changes, TCON can control the corresponding transmission channel 365 to be turned on through the IIC conversion instruction, so as to realize the repair of the abnormal scanning signal of the panel under different refresh rates.

[0203] Furthermore, in some embodiments, the output module 36 includes: Figure 18 The plurality of resistor-capacitor units 363 connected in series with the output end of the level conversion unit 35 and the plurality of transmission channels 365 connected in parallel, as well as Figure 17 The second regulating unit 362 in the embodiment is electrically connected to the repair output terminal.

[0204] In this way, by combining different combinations of the first control signal, the switching control of different row transmission channels 365 can be accurately achieved, and the impedances provided by the resistor-capacitor units 363 corresponding to different target transmission channels 365 are different, so as to achieve accurate and flexible impedance matching to correspond to the target rows where different abnormal scanning signals are located; further, different impedances are provided to the first and second ends relative to the target row through the second adjustment unit 362, so as to further perform refined impedance matching on the two relative ends of the target row, so that the first scanning repair signal f51 and the second scanning repair signal f52 are more accurate, and the display effect of the display panel 100 is more uniform.

[0205] See also Figure 20 , Figure 20 FIG2 is a schematic diagram of the structure of a display device provided in one embodiment of the present application. In this embodiment, a display device is provided, comprising a display panel 100 and a central control board 200. The central control board 200 is coupled to the display panel 100 and is configured to provide a drive control signal to the display panel 100 so that the display panel 100 displays a corresponding image.

[0206] Among them, the specific structure and function of the display panel 100 are the same or similar to the structure and function of the display panel 100 provided in the above embodiment, and can achieve the same technical effects. For details, please refer to the detailed introduction above and will not be repeated here.

[0207] In some embodiments, the display device may further include peripheral components, which are electrically connected to the display panel to implement corresponding functions to expand the usage scenarios of the display device.

[0208] The above is only an implementation method of the present application and does not limit the scope of patent protection of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present application.

Claims

1. A repair circuit for repairing abnormal scanning signals in a display panel, characterized in that: include: An input module, wherein a first input terminal receives a signal to be repaired, a first output terminal is electrically connected to a first node, and is configured to perform voltage reduction processing on the signal to be repaired and output the first input signal at the first output terminal; The processing module includes a delay removal unit, a shaping unit and a level conversion unit; wherein, The control end of the de-delay unit is electrically connected to the first node, the input end is coupled to the corresponding clock signal, and the output end is electrically connected to the second node, and is configured to perform de-delay processing on the falling edge of the first input signal according to the corresponding clock signal, and output a de-delay signal at the output end, wherein the falling edge of the de-delay signal is consistent with the falling edge of the corresponding clock signal; The input end of the shaping unit is electrically connected to the second node, and is used to shape the waveform of the de-delayed signal and output a square wave signal at the output end; The level conversion unit has an input end electrically connected to the output end of the shaping unit, is used to adjust the level of the square wave signal, and output a scan repair signal at an output end.

2. The repair circuit according to claim 1, characterized in that: The de-delay unit includes a switch transistor, wherein a control terminal of the switch transistor is electrically connected to the first node, a first terminal is coupled to the corresponding clock signal, and a second terminal is electrically connected to the second node; The shaping unit includes an operational amplifier chip, a first input terminal of the operational amplifier chip is electrically connected to the second node, a second input terminal is connected to the reference voltage signal, and an output terminal is electrically connected to the input terminal of the level conversion unit; the operational amplifier chip is used to compare the de-delayed signal with the reference voltage signal to output the square wave signal at the output terminal of the operational amplifier chip; The level conversion unit includes a level conversion chip, the input end of the level conversion chip is electrically connected to the output end of the shaping unit, the first power input end is connected to the gate high level signal, and the second power input end is connected to the gate low level signal, so as to convert the high level of the square wave signal into the gate high level and convert the low level of the square wave signal into the gate low level.

3. The repair circuit according to claim 2, characterized in that: The shaping unit further includes a first voltage dividing unit, the first voltage dividing unit including a first voltage dividing resistor, a second voltage dividing resistor, and a third voltage dividing resistor connected in series; one end of the first voltage dividing resistor is connected to the initial power supply signal, the connection node between the first voltage dividing resistor and the second voltage dividing resistor is a first voltage dividing node, and the connection node between the second voltage dividing resistor and the third voltage dividing resistor is a second voltage dividing node; The first voltage dividing node is electrically connected to the positive power input terminal of the operational amplifier chip, and is used to provide a positive power supply voltage signal to the operational amplifier chip; the second voltage dividing node is electrically connected to the second input terminal of the operational amplifier chip, and is used to provide the reference voltage signal to the operational amplifier chip.

4. The repair circuit according to claim 2, characterized in that: The delay removal unit further includes an adjustment unit, one end of the adjustment unit is electrically connected to the second node, and the other end is connected to the pull-down power signal; The adjustment unit includes a pull-up resistor, one end of which is electrically connected to the second node, and the other end of which is connected to the pull-down power supply signal; the pull-up resistor is an adjustable resistor.

5. The repair circuit according to claim 1, wherein: The input module includes a second voltage dividing unit and a third voltage dividing unit; the second voltage dividing unit is used to reduce the voltage of the signal to be repaired and output the first input signal, and the third voltage dividing unit is used to reduce the voltage of the corresponding clock signal and output the second input signal; The second voltage-dividing unit includes a fourth voltage-dividing resistor and a fifth voltage-dividing resistor, one end of the fourth voltage-dividing resistor is connected to the signal to be repaired, and the other end is electrically connected to the first node; one end of the fifth voltage-dividing resistor is electrically connected to the first node, and the other end is grounded; The third voltage-dividing unit includes a sixth voltage-dividing resistor and a seventh voltage-dividing resistor, one end of the sixth voltage-dividing resistor is connected to the corresponding clock signal, and the other end is electrically connected to the third voltage-dividing node, one end of the seventh voltage-dividing resistor is electrically connected to the third voltage-dividing node, and the other end is grounded; the input end of the de-delay unit is electrically connected to the third voltage-dividing node.

6. The repair circuit according to claim 1, characterized in that: The repair circuit further includes an output module, the output module being electrically connected to the output end of the level conversion unit and configured to match the corresponding impedance for the scan repair signal; the output module including a first adjustment unit and a second adjustment unit; The first regulating unit includes a first regulating resistor, one end of the first regulating resistor is electrically connected to the output end of the level conversion unit, and the other end is electrically connected to the regulating node; The first regulating resistor is a variable resistor; The second regulating unit includes a second regulating resistor and a third regulating resistor; one end of the second regulating resistor is electrically connected to the regulating node, and the other end serves as an output end for outputting the regulated first scanning repair signal; One end of the third regulating resistor is electrically connected to the regulating node, and the other end serves as an output end for outputting the regulated second scanning and repairing signal.

7. A display panel comprising: A driving substrate comprising a pixel array area, a first gate driving module and a second gate driving module respectively located on two opposite sides of the pixel array area, and a plurality of scanning lines; a driving control board, disposed on one side of the driving substrate and coupled to the driving substrate; It is characterized in that the driving control board includes a repair circuit according to any one of claims 1 to 6, which is used to repair abnormal scanning signals; the display panel also includes: A first repair input line and a first repair output line are arranged between the pixel array area and the first gate driving module, and are arranged in a different layer and cross-arranged with the plurality of scanning lines; A second repair input line and a second repair output line are arranged between the pixel array area and the second gate driving module at intervals, and are arranged in a different layer and cross-arranged with the plurality of scanning lines; When the output of the n-th level driving unit in the first gate driving module or the second gate driving module is abnormal, the two ends of the scan line in the n-th row are respectively disconnected from the corresponding n-th level driving unit, and the normal n-th level driving unit in the first gate driving module or the second gate driving module is electrically connected to the first input end of the repair circuit through the first repair input line or the second repair input line, so as to provide the repair circuit with a signal to be repaired, and the two ends of the scan line in the n-th row are respectively electrically connected to the output end of the repair circuit through the first repair output line and the second repair output line, so as to receive the scan repair signal after repair by the repair circuit.

8. The display panel according to claim 7, wherein: The drive control board includes a first drive control unit and a second drive control unit; the first drive control unit and the second drive control unit are arranged in a direction parallel to the side of the drive substrate; the repair circuit is provided in the first drive control unit; The drive control board is coupled to the drive substrate via a plurality of chip-on-films (CFOs); wherein, among the plurality of CFOs electrically connected to the first drive control unit, the outermost CFO is a first outer CFO, and the CFO closest to the second drive control unit is a first inner CFO; and among the plurality of CFOs electrically connected to the second drive control unit, the outermost CFO is a second outer CFO, and the CFO closest to the first drive control unit is a second inner CFO. The first repair input line and the first repair output line extend to the repair circuit through the first outer chip-on-film and are electrically connected to the repair circuit; The second repair input line and the second repair output line extend to the second drive control unit through the second outer chip-on-film, and extend along the second drive control unit to a position close to the first drive control unit, and then extend along the second inner chip-on-film to the drive substrate, and extend on the drive substrate in a direction close to the first drive control unit to a position of the first inner chip-on-film, and extend along the first inner chip-on-film to the first drive control unit, and are electrically connected to the repair circuit.

9. The display panel according to claim 8, wherein: The flip chip film is divided into a data area and a gate area, and the gate area is located on opposite sides of the data area along an extension direction parallel to the drive control board; the data area is provided with a driver chip, and the gate area is used for wiring; wherein, the first repair input line, the first repair output line, the second repair input line and the second repair output line are arranged in the gate area and extend along the gate area.

10. A display device, characterized in that: include: The display panel is a display panel according to any one of claims 7 to 9; The central control board is used to provide a driving control signal to the display panel so that the display panel displays a corresponding image.

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