Process integration method of high-voltage CMOS (complementary metal oxide semiconductor) device in flash memory device

Abstract

The invention provides a process integration method of a high-voltage CMOS (Complementary Metal Oxide Semiconductor) device in a flash memory device, which comprises the following steps of: before a grid electrode of a high-voltage MOS (Metal Oxide Semiconductor) device region is prepared, by virtue of a mask plate of threshold voltage ion implantation of a flash memory device region, adopting a non-self-alignment mode and taking a patterned sacrificial layer as a mask, forming a high-voltage MOS device region; and performing threshold voltage ion implantation (CVT ion implantation) on the substrate in the flash memory device region and the high-voltage MOS device region to form a first threshold voltage ion implantation region in the first well region and form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer, and replacing traditional LDD implantation in the MOS device region with the threshold voltage ion implantation to form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer. Therefore, a low-doped expansion region can be formed between the lower part of the grid boundary of the high-voltage MOS device region and the source / drain, and an independent high-voltage LDD ion implantation process of the traditional high-voltage CMOS device region can be omitted, so that the process manufacturing cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a process integration method for high-voltage CMOS devices in flash memory devices. Background Art

[0002] CMOS devices, with their low power consumption and high integration density, hold a significant position in the integrated circuit field. MOS devices are the core components of various devices, including NOR Flash, NAND Flash, Trench MOS, and IGBTs. Since their introduction, their structural principles have remained essentially unchanged, leading to research focused on reducing costs and enhancing product competitiveness.

[0003] During the fabrication of flash memory devices, high-voltage CMOS device regions (e.g., 5V CMOS device regions) are typically implanted using a traditional self-aligned LDD (Lightly Doped Drain) ion implantation process to improve the breakdown voltage (BV) of the CMOS device. This requires a high-voltage LDD implantation mask, increasing process costs. Summary of the Invention

[0004] The present application provides a process integration method for high-voltage CMOS devices in flash memory devices, which can solve the problem that in the traditional flash memory device preparation process, high-voltage LDD injection in the high-voltage CMOS device area requires a separate ion injection process, which increases the process cost.

[0005] An embodiment of the present application provides a process integration method for a high-voltage CMOS device in a flash memory device, comprising:

[0006] A substrate is provided, wherein the substrate includes a flash memory device region and a high-voltage MOS device region, and a plurality of shallow trench isolation structures are formed in the substrate, wherein the shallow trench isolation structures are used to isolate different device regions;

[0007] forming a first well region in the substrate of the flash memory device region and a second well region in the substrate of the high-voltage MOS device region respectively through an ion implantation process;

[0008] forming a sacrificial layer, wherein the sacrificial layer covers the substrate surface of the flash memory device area and the high-voltage MOS device area;

[0009] Removing the sacrificial layer in the flash memory device area and removing part of the sacrificial layer in the high-voltage MOS device area to define a threshold voltage ion implantation window in the flash memory device area and a threshold voltage ion implantation window in the high-voltage MOS device area, respectively;

[0010] Using the remaining sacrificial layer as a mask, performing threshold voltage ion implantation on the substrate of the flash memory device region and the high-voltage MOS device region to form a first threshold voltage ion implantation region in the first well region, and forming a second threshold voltage ion implantation region in the second well region on both sides of the remaining sacrificial layer, wherein the second threshold voltage ion implantation region serves as a first lightly doped drain region of the high-voltage MOS device region;

[0011] removing the remaining sacrificial layer;

[0012] Forming a stacked first gate dielectric layer, a floating gate layer, an ONO film layer, and a control gate layer on the substrate of the flash memory device region, and forming a stacked second gate dielectric layer and a gate on the substrate of the high-voltage MOS device region;

[0013] Two second lightly doped drain regions are formed in the first threshold voltage ion implantation region of the flash memory device region through a selective ion implantation process.

[0014] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, the threshold voltage ion implantation for forming the second threshold voltage ion implantation region is a non-self-aligned ion implantation.

[0015] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, the lateral overlap size between each of the second threshold voltage ion implantation regions and the gate is 30 nm to 90 nm.

[0016] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, the depth of the first threshold voltage ion implantation region in the substrate is the same as the depth of the second threshold voltage ion implantation region in the substrate.

[0017] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, in the process of forming the first threshold voltage ion implantation region and the second threshold voltage ion implantation region, the ion implantation energy is 20KeV to 60KeV, and the ion implantation dose is 2E13 / cm 2 ~6E13 / cm 2 .

[0018] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, after forming the two second lightly doped drain regions, the process integration method of the high-voltage CMOS device in the flash memory device further includes:

[0019] A first side wall and a second side wall are formed, wherein the first side wall is respectively located on both sides of the first gate dielectric layer, floating gate layer, ONO film layer and control gate layer stacked in the flash memory device area, and on both sides of the second gate dielectric layer and gate stacked in the high-voltage MOS device area, and the second side wall is located on the outside of the first side wall.

[0020] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, after forming the first spacer and the second spacer, the process integration method of the high-voltage CMOS device in the flash memory device further includes:

[0021] Through an ion implantation process, a first heavily doped region is formed in the second lightly doped drain region of the flash memory device region, and a second heavily doped region is formed in the second threshold voltage ion implantation region of the high-voltage MOS device region.

[0022] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, the height of the shallow trench isolation structure is 2500 angstroms to 3000 angstroms.

[0023] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, the depth of the second threshold voltage ion implantation region in the substrate is less than the height of the shallow trench isolation structure.

[0024] Optionally, in the process integration method of the high-voltage CMOS device in the flash memory device, the conductivity type of the doped ions in the first well region is P-type; the conductivity type of the doped ions in the second well region is N-type; the conductivity type of the doped ions in the first threshold voltage ion injection region and the second threshold voltage ion injection region is P-type; and the conductivity type of the doped ions in the second lightly doped drain region is N-type.

[0025] The technical solution of this application has at least the following advantages:

[0026] The present application provides a process integration method for a high-voltage CMOS device in a flash memory device. Before preparing the gate of the high-voltage MOS device region, a threshold voltage ion implantation mask for the flash memory device region is used to perform threshold voltage ion implantation (CVT ion implantation) on the substrate of the flash memory device region and the high-voltage MOS device region in a non-self-aligned manner with a patterned sacrificial layer as a mask. This forms a first threshold voltage ion implantation region in a first well region and a second threshold voltage ion implantation region in second well regions on both sides of the patterned sacrificial layer. The threshold voltage ion implantation replaces the traditional LDD implantation in the MOS device region. This not only forms a low-doping extension region below the gate boundary and between the source / drain of the high-voltage MOS device region, but also eliminates the need for a separate high-voltage LDD ion implantation process in the traditional high-voltage CMOS device region, thereby reducing process manufacturing costs.

[0027] Furthermore, before preparing the gate of the high-voltage MOS device area, the present application uses CVT ion implantation to replace the high-voltage LDD ion implantation in traditional high-voltage CMOS devices to form a second threshold voltage ion implantation area in the substrate of the high-voltage MOS device area, and improves the breakdown voltage (BV) of the high-voltage MOS device area by optimizing the size of the overlapping area between the second threshold voltage ion implantation area and the gate, without affecting the performance of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 is a flow chart of a process integration method of a high-voltage CMOS device in a flash memory device according to an embodiment of the present invention;

[0030] Figure 2-Figure 8 Schematic diagram of the semiconductor structure in each step of the integrated manufacturing process of the flash memory device and the high-voltage CMOS device according to an embodiment of the present invention;

[0031] 10-substrate, 101-shallow trench isolation structure, 102-first well region, 202-second well region, 1031-first threshold voltage ion implantation region, 1032-second threshold voltage ion implantation region, 11-sacrificial layer, 104-first gate dielectric layer, 154-floating gate layer, 153-ONO film layer, 105-gate material layer, 204-second gate dielectric layer, 106-second lightly doped drain region, 107-first sidewall, 108-second sidewall, 109-first heavily doped region, 110-second heavily doped region. DETAILED DESCRIPTION

[0032] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0033] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0035] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0036] The present invention provides a method for integrating a high-voltage CMOS device in a flash memory device. Figure 1 , Figure 1 1 is a flow chart of a process integration method for a high-voltage CMOS device in a flash memory device according to an embodiment of the present invention. The process integration method for a high-voltage CMOS device in a flash memory device includes:

[0037] First, perform step S1: refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after a shallow trench isolation structure is formed in an embodiment of the present application. A substrate 10 is provided, wherein the substrate 10 includes a flash memory device area and a high-voltage MOS device area. A plurality of shallow trench isolation structures 101 are formed in the substrate 10, and the shallow trench isolation structures 101 are used to isolate different device areas.

[0038] The embodiment of the present application takes the flash memory device area as an N-type channel and the high-voltage MOS device area as a PMOS device as an example to specifically introduce the process integration method of the high-voltage CMOS device in the flash memory device.

[0039] In this embodiment, the shallow trench isolation structure 101 is at least used to isolate the high-voltage PMOS device region and the flash memory device region.

[0040] Preferably, the height of the shallow trench isolation structure 101 is 2500 angstroms to 3000 angstroms.

[0041] Then, execute step S2: refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the first well region and the second well region are formed in an embodiment of the present application. Through the ion implantation process, a first well region 102 is formed in the substrate 10 of the flash memory device region, and a second well region 202 is formed in the substrate 10 of the high-voltage MOS device region.

[0042] In this embodiment, the conductivity type of the doped ions in the first well region 102 is P-type; the conductivity type of the doped ions in the second well region 202 is N-type.

[0043] Next, execute step S3: refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after forming the first threshold voltage ion implantation region and the second threshold voltage ion implantation region in an embodiment of the present application, forming a sacrificial layer 11, which covers the surface of the substrate 10 of the flash memory device region and the high-voltage MOS device region.

[0044] The sacrificial layer 11 may be a hard mask material layer or a photoresist material layer.

[0045] In this embodiment, the sacrificial layer 11 is a photoresist material layer.

[0046] In other embodiments, the sacrificial layer 11 is a hard mask material layer. Specifically, the sacrificial layer 11 is a silicon nitride layer, or a silicon oxide layer, or a stack of a silicon nitride layer and a silicon oxide layer.

[0047] Further, execute step S4: continue to refer to Figure 4 Through photolithography and etching processes, the sacrificial layer 11 in the flash memory device area and part of the sacrificial layer 11 in the high-voltage MOS device area are removed to obtain a patterned sacrificial layer 11, which respectively defines the threshold voltage ion implantation window of the flash memory device area and the threshold voltage ion implantation window of the high-voltage MOS device area.

[0048] Then, execute step S5: continue to refer to Figure 4Using the remaining sacrificial layer (patterned sacrificial layer) 11 as a mask, threshold voltage ion implantation is performed on the substrate of the flash memory device region and the high-voltage MOS device region to form a first threshold voltage ion implantation region 1031 in the first well region 102, and a second threshold voltage ion implantation region 1032 in the second well region 202 on both sides of the remaining sacrificial layer 11. The second threshold voltage ion implantation region 1032 serves as a first lightly doped drain region of the high-voltage MOS device region.

[0049] It should be noted that the threshold voltage ion implantation for forming the second threshold voltage ion implantation region 1032 is a non-self-aligned ion implantation.

[0050] Preferably, the depth of the first threshold voltage ion implantation region 1031 in the substrate 10 is the same as the depth of the second threshold voltage ion implantation region (first lightly doped drain region) 1032 in the substrate 10 .

[0051] In this embodiment, the depth of the second threshold voltage ion implantation region (first lightly doped drain region) 1032 in the substrate 10 is less than the height of the shallow trench isolation structure 101 .

[0052] Preferably, in the process of forming the first threshold voltage ion implantation region 1031 and the second threshold voltage ion implantation region (first lightly doped drain region) 1032, the ion implantation energy is 20KeV to 60KeV, and the ion implantation dose is 2E13 / cm 2 ~6E13 / cm 2 .

[0053] In this embodiment, the conductivity type of the doped ions in the first threshold voltage ion implantation region 1031 and the second threshold voltage ion implantation region (first lightly doped drain region) 1032 is P-type.

[0054] Furthermore, step S6 is performed: removing the remaining sacrificial layer (patterned sacrificial layer) 11 .

[0055] In the present application, before preparing the gate of the high-voltage MOS device area, a mask for the threshold voltage ion implantation in the flash memory device area is used, and a non-self-aligned ion implantation method is adopted, which is a carpet ion implantation method. With a patterned sacrificial layer as a mask, threshold voltage ion implantation (CVT ion implantation) is performed on the substrate of the flash memory device area and the high-voltage MOS device area, so as to form a first threshold voltage ion implantation area in the first well area while forming a second threshold voltage ion implantation area in the second well area on both sides of the patterned sacrificial layer. The present application uses threshold voltage ion implantation to replace the traditional LDD implantation in the high-voltage PMOS device area, so that a low-doped extension area (the low-doped extension area is named the second threshold voltage ion implantation area 1032 in the present application) can be formed below the gate boundary of the high-voltage PMOS device area and between the source / drain, and the separate high-voltage LDD ion implantation process of the traditional high-voltage CMOS device area can be omitted, thereby reducing process manufacturing costs and improving product competitiveness.

[0056] Then, execute step S7: refer to Figure 5 and Figure 6 , Figure 5 Schematic diagram of the semiconductor structure after forming the first gate dielectric layer, the floating gate layer, the ONO film layer and the second gate dielectric layer in an embodiment of the present application. Figure 6 It is a schematic diagram of the semiconductor structure after the control gate layer, the gate and the second lightly doped drain region are formed in an embodiment of the present application, wherein a stacked first gate dielectric layer 104, a floating gate layer 154, an ONO film layer 153 and a control gate layer (gate material layer 105) are formed on the substrate 10 of the flash memory device area, and a stacked second gate dielectric layer 204 and a gate (gate material layer 105) are formed on the substrate 10 of the high-voltage MOS device area.

[0057] Preferably, the lateral overlapping dimension of each second threshold voltage ion implantation region (first lightly doped drain region) 1032 and the gate (gate material layer 105) is 30nm to 90nm, that is, the lateral overlapping area of each second threshold voltage ion implantation region 1032 and the gate (gate material layer 105) is 30nm to 90nm.

[0058] The step S7 may specifically include:

[0059] Step S7.1: First, a first gate dielectric layer 104 of the flash memory device region and a second gate dielectric layer 204 of the high-voltage PMOS device region are sequentially formed by a chemical vapor deposition process;

[0060] Step S7.2: Then, a floating gate layer 154 is formed by a chemical vapor deposition process, and the floating gate layer 154 covers the first gate dielectric layer 104 and the second gate dielectric layer 204;

[0061] Step S7.3: Then, the floating gate layer 154 of the high-voltage PMOS region is removed by etching through a selective etching process;

[0062] Step S7.4: Further, forming an ONO film layer 153, the ONO film layer 153 covers the floating gate layer 154 and the second gate dielectric layer 204;

[0063] Step S7.5: Next, the ONO film layer 153 in the high-voltage PMOS region is removed by a selective etching process, while the ONO film layer 153 in the flash memory device region is retained;

[0064] Step S7.6: Further, forming a gate material layer 105 by a chemical vapor deposition process;

[0065] Step S7.7: Finally, the gate material layer 105 is etched by photolithography, etching and other processes to form the control gate structure of the flash memory device area and the gate structure of the high-voltage PMOS device area.

[0066] In the present application, before preparing the gate of the high-voltage MOS device area, CVT ion implantation is used instead of the high-voltage LDD ion implantation in the traditional high-voltage CMOS device to form a second threshold voltage ion implantation area in the substrate of the high-voltage MOS device area, and the size of the overlapping area between the second threshold voltage ion implantation area and the gate is optimized to improve the breakdown voltage (BV) of the high-voltage MOS device area without affecting the performance of the flash memory device.

[0067] Finally, execute step S8: continue to refer to Figure 6 , two second lightly doped drain regions 106 are formed in the first threshold voltage ion implantation region 1031 of the flash memory device region through a selective ion implantation process.

[0068] In this embodiment, the conductivity type of the doped ions in the second lightly doped drain region 106 is N-type.

[0069] In summary, the process integration method of high-voltage CMOS devices in flash memory devices provided in this application not only eliminates the traditional PLDD mask and its PLDD ion implantation and other related processes in high-voltage PMOS devices, but also further improves the BV of the high-voltage PMOS device area without affecting the performance of the flash memory device, reducing process costs and improving product competitiveness.

[0070] Furthermore, after forming the two second lightly doped drain regions, the process integration method of the high-voltage CMOS device in the flash memory device further includes step S9: referring to Figure 7 and Figure 8 , Figure 7 is a schematic diagram of the semiconductor structure after the first sidewall spacer is formed in an embodiment of the present application. Figure 8This is a schematic diagram of the semiconductor structure after the second side wall and the first heavily doped region and the second heavily doped region are formed in an embodiment of the present application, forming a first side wall 107 and a second side wall 108. The first side wall 107 is respectively located on both sides of the first gate dielectric layer 104, the floating gate layer 154, the ONO film layer 153 and the control gate layer (gate material layer 105) stacked in the flash memory device area, and on both sides of the second gate dielectric layer 204 and the gate (gate material layer 105) stacked in the high-voltage MOS device area. The second side wall 108 is located on the outside of the first side wall 107.

[0071] Preferably, after forming the first sidewall spacer 107 and the second sidewall spacer 108, the process integration method of the high-voltage CMOS device in the flash memory device further includes step S10: continue to refer to Figure 8 Through the ion implantation process, a first heavily doped region 109 is formed in the second lightly doped drain region 106 of the flash memory device region, and a second heavily doped region 110 is formed in the second threshold voltage ion implantation region 1032 of the high-voltage MOS device region.

[0072] In this embodiment, the conductivity type of the doped ions in the first heavily doped region 109 is N-type; the conductivity type of the doped ions in the second heavily doped region 110 is P-type.

[0073] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A process integration method for a high-voltage CMOS device in a flash memory device, characterized in that: include: A substrate is provided, wherein the substrate includes a flash memory device region and a high-voltage MOS device region, and a plurality of shallow trench isolation structures are formed in the substrate, wherein the shallow trench isolation structures are used to isolate different device regions; forming a first well region in the substrate of the flash memory device region and a second well region in the substrate of the high-voltage MOS device region respectively through an ion implantation process; forming a sacrificial layer, wherein the sacrificial layer covers the substrate surface of the flash memory device area and the high-voltage MOS device area; Removing the sacrificial layer in the flash memory device area and removing part of the sacrificial layer in the high-voltage MOS device area to define a threshold voltage ion implantation window in the flash memory device area and a threshold voltage ion implantation window in the high-voltage MOS device area, respectively; Using the remaining sacrificial layer as a mask, performing threshold voltage ion implantation on the substrate of the flash memory device region and the high-voltage MOS device region to form a first threshold voltage ion implantation region in the first well region, and forming a second threshold voltage ion implantation region in the second well region on both sides of the remaining sacrificial layer, wherein the second threshold voltage ion implantation region serves as a first lightly doped drain region of the high-voltage MOS device region; removing the remaining sacrificial layer; Forming a stacked first gate dielectric layer, a floating gate layer, an ONO film layer, and a control gate layer on the substrate of the flash memory device region, and forming a stacked second gate dielectric layer and a gate on the substrate of the high-voltage MOS device region; Two second lightly doped drain regions are formed in the first threshold voltage ion implantation region of the flash memory device region through a selective ion implantation process.

2. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1, characterized in that: The threshold voltage ion implantation for forming the second threshold voltage ion implantation region is a non-self-aligned ion implantation.

3. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1, characterized in that: The overlap size between each of the second threshold voltage ion implantation regions and the gate in the lateral direction is 30 nm to 90 nm.

4. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1, wherein: The depth of the first threshold voltage ion implantation region in the substrate is the same as the depth of the second threshold voltage ion implantation region in the substrate.

5. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1, wherein: In the process of forming the first threshold voltage ion implantation region and the second threshold voltage ion implantation region, the ion implantation energy is 20KeV to 60KeV, and the ion implantation dose is 2E13 / cm 2 ~6E13 / cm 2 .

6. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1, wherein: After forming the two second lightly doped drain regions, the process integration method of the high-voltage CMOS device in the flash memory device further includes: A first side wall and a second side wall are formed, wherein the first side wall is respectively located on both sides of the first gate dielectric layer, floating gate layer, ONO film layer and control gate layer stacked in the flash memory device area, and on both sides of the second gate dielectric layer and gate stacked in the high-voltage MOS device area, and the second side wall is located on the outside of the first side wall.

7. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 6, characterized in that: After forming the first spacer and the second spacer, the process integration method of the high-voltage CMOS device in the flash memory device further includes: Through an ion implantation process, a first heavily doped region is formed in the second lightly doped drain region of the flash memory device region, and a second heavily doped region is formed in the second threshold voltage ion implantation region of the high-voltage MOS device region.

8. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1, characterized in that: The height of the shallow trench isolation structure is 2500 angstroms to 3000 angstroms.

9. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1 or 8, characterized in that: The depth of the second threshold voltage ion implantation region in the substrate is less than the height of the shallow trench isolation structure.

10. The process integration method of a high-voltage CMOS device in a flash memory device according to claim 1, wherein: The conductivity type of the doped ions in the first well region is P type; the conductivity type of the doped ions in the second well region is N type; the conductivity type of the doped ions in the first threshold voltage ion injection region and the second threshold voltage ion injection region is P type; the conductivity type of the doped ions in the second lightly doped drain region is N type.

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