Super junction metal oxide semiconductor field effect transistor and manufacturing method thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a super junction metal oxide semiconductor field effect transistor, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, and is characterized in that the semiconductor epitaxial layer specifically comprises two P well layers, two P + layers, two N well layers, an N substrate layer and an N drift layer; a beam waist N-layer is formed in the N drift layer through ion implantation; the girdling N-layer is composed of an upper half area and a lower half area, and the profile of the section of the girdling N-layer is in the shape that the upper end and the lower end are thick and the middle is thin. The gradient doped N-layer with the waist-shaped cross section is formed in the N drift layer, electric field distribution is optimized, the longitudinal electric field supporting capacity is enhanced in the middle thin and narrow area, and the breakdown voltage is improved; a transverse conduction path is expanded in thick areas at the two ends, so that the specific on-resistance is remarkably reduced, and high-voltage tolerance and low conduction loss are synchronously realized.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a super junction metal oxide semiconductor field effect transistor and a manufacturing method thereof. Background Art

[0002] In existing super-junction MOSFETs, traditional planar or columnar doping structures have limited breakdown voltage due to uneven electric field distribution, and there is an inherent contradiction between on-resistance and voltage resistance. At the same time, the concentrated electric field at the top of the drift region can easily cause local breakdown, the resistance of the longitudinal conduction path at the bottom is high, and charge imbalance can also lead to switching oscillation and reduced dynamic stability, restricting the reliability of the device in high-voltage application scenarios.

[0003] The existing patent discloses a superjunction metal-oxide-semiconductor field-effect transistor structure (CN202434527U), comprising: a semiconductor base layer; a plurality of source semiconductor trenches embedded in the semiconductor base layer, each forming a base layer and a trench at the upper and lower ends of each source semiconductor trench, respectively; a first connection layer and a second connection layer formed on the top surface of the base layer; at least one additional doped layer bonded around each source semiconductor trench to form a superjunction; and at least one gate connected between the top of the semiconductor base layer and the base layer and the first connection layer of each source semiconductor trench. This invention addresses three core issues of the superjunction MOSFET described in the referenced document (CN202434527U): the discrepancy between breakdown voltage and on-resistance caused by uneven electric field distribution in conventional planar / columnar doping structures; the risk of local breakdown caused by electric field concentration at the top of the drift region; and dynamic oscillation and excessively high longitudinal on-path resistance caused by charge imbalance during switching. Summary of the Invention

[0004] The present invention provides a super junction metal oxide semiconductor field effect transistor and a manufacturing method thereof to solve the existing technical problems, which solve the problems of dynamic oscillation caused by charge imbalance during switching and excessively high longitudinal conduction path resistance.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a super junction metal oxide semiconductor field effect transistor is provided, comprising a drain, a semiconductor epitaxial layer, a source, and a gate, wherein the semiconductor epitaxial layer specifically includes two P well layers, two P+ layers, two N well layers, an N substrate layer, and an N drift layer, wherein a beam waist N- layer is formed inside the N drift layer by ion implantation; The beam waist N-layer consists of an upper half region and a lower half region, wherein the cross-sectional profile of the beam waist N-layer is thick at the upper and lower ends and thin in the middle.

[0006] Furthermore, a constrained P-layer is formed on the top of the upper half of the beam waist N-layer by ion implantation, and the constrained P-layer is located between the two P-well layers.

[0007] Furthermore, a high-resistance dielectric is provided on the top of the upper half of the waist N-layer. The high-resistance dielectric is located between the two P-well layers, and the high-resistance dielectric is in ohmic contact with the gate.

[0008] Furthermore, two groups of highly doped N+ layers are provided in the lower half of the beam waist N- layer, and each group of highly doped N+ layers is in contact with the N substrate layer.

[0009] Furthermore, side P-block layers are provided on the left and right sides of each group of the highly doped N+ layers, and the side P-block layers are in contact with the highly doped N+ layers.

[0010] Furthermore, the upper half of the beam waist N-layer is also a heavily doped upper region.

[0011] Furthermore, a constrained N-layer is formed in the upper half of the beam waist N-layer by ion implantation, and the doping concentration of the constrained N-layer is 0.4-0.7 times the doping concentration of the beam waist N-layer.

[0012] Furthermore, a suppression P-layer is formed in the lower half of the beam waist N-layer by ion implantation. The suppression P-layer is aligned with the constrained N-layer in the horizontal direction and contacts the N substrate layer.

[0013] A method for manufacturing a super junction metal oxide semiconductor field effect transistor, comprising: S1. Growing a low-doped N drift layer on the surface of the N substrate layer by epitaxial process; S2. A multi-step mask etching process is used inside the N drift layer to etch a waist-shaped groove in the middle region of the N drift layer, which is narrow in the middle and wide at the top and bottom. S3. Forming a beam waist N-layer with a gradient doping concentration in the groove by epitaxial filling or tilted ion implantation process, ensuring that its cross section is thick at both ends and thin in the middle; S4, implanting into the upper half of the beam waist N-layer to form a confined N-layer, controlling its doping concentration to be 0.4–0.7 times the background concentration of the beam waist N-layer; S5, implanting an inhibited P-layer into the corresponding position of the lower half of the beam waist N-layer so that it is horizontally aligned with the constrained N-layer and contacts the N substrate; S6. Forming a symmetrical P-well layer, N-well layer, and P+ layer by photolithography and ion implantation; S7. Deposit a gate dielectric layer and form a gate structure to form a source on the front side of the device and a drain on the back side.

[0014] The present invention provides a super junction metal oxide semiconductor field effect transistor and a method for manufacturing the same. Compared with the prior art, the present method achieves the following effects: 1. The present invention optimizes the electric field distribution by forming a gradient-doped N-layer with a waisted cross-section inside the N-drift layer. The narrow region in the middle enhances the longitudinal electric field support capability and improves the breakdown voltage. The thick regions at both ends expand the lateral conduction path and significantly reduce the specific on-resistance, thereby simultaneously achieving high-voltage tolerance and low conduction loss.

[0015] 2. This invention forms a vertical charge compensation structure by implanting a lightly doped constrained N-layer in the upper half of the beam waist N-layer and a horizontally aligned suppressed P-layer in the lower half. This design effectively suppresses electric field oscillations and charge imbalance during switching, improving dynamic stability, while also reducing leakage current and enhancing gate control response speed.

[0016] 3. This invention addresses the risk of electric field concentration at the top of the beam waist structure by adding a constrained P-layer or a high-resistance dielectric. The former forms a P-type region through ion implantation, directly suppressing the electric field peak between the P-well layers; the latter uses a dielectric material to achieve electric field equalization and forms an ohmic contact with the gate, preventing carrier recombination losses. Both significantly reduce the probability of local breakdown and extend device life.

[0017] 4. The present invention sets a highly doped N+ layer and a lateral P-block layer at the bottom of the waist N-layer. The N+ layer is directly connected to the N substrate, shortening the longitudinal current path and reducing the on-resistance. The side P-block wraps the N+ layer to form a local charge balance, enhance the bottom voltage resistance, suppress longitudinal penetration breakdown, and improve the current expansion uniformity.

[0018] 5. This manufacturing method uses multi-step mask etching to form a beam waist groove, combined with epitaxial fill or tilted ion implantation to achieve gradient doping, precisely controlling the geometry and concentration distribution of the beam waist N-layer. This process is compatible with existing semiconductor processes, and through self-aligned implantation of the confinement and suppression layers, the positional accuracy of the vertical charge compensation structure is ensured, improving mass production feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of Example 1 of the present invention; Figure 2 This is a schematic diagram of Example 2 of the present invention; Figure 3 This is a schematic diagram of Example 3 of the present invention; Figure 4 This is a schematic diagram of Example 4 of the present invention; Figure 5 This is a schematic diagram of Example 5 of the present invention; Figure 6 This is a schematic diagram of Example 6 of the present invention.

[0020] In the figure: 1. Drain; 2. Source; 3. Gate; 4. P-well layer; 5. P+ layer; 6. N-well layer; 7. N substrate layer; 8. N drift layer; 9. Waist N-layer; 10. Constrained P-layer; 11. High-resistance dielectric; 12. Side P-block layer; 13. Highly doped N+ layer; 14. Heavily doped upper region; 15. Suppressed P-layer; 16. Constrained N-layer. DETAILED DESCRIPTION

[0021] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1-6 As shown, a method for manufacturing a super junction metal oxide semiconductor field effect transistor includes: Step 1: Growing a low-doped N drift layer 8 on the surface of the N substrate layer 7 through an epitaxial process; Epitaxially growing a low-doped N drift layer 8 on the N substrate layer 7 ensures that the drift region has a uniform thickness and controllable doping concentration, laying the foundation for the subsequent formation of a super junction structure. At the same time, the low-doping characteristics are conducive to improving the breakdown voltage of the device.

[0023] Step 2: A multi-step mask etching process is used inside the N-drift layer 8 to etch a waist-shaped groove in the central area of the N-drift layer 8. The waist-shaped groove is narrow in the middle and wide at the top and bottom. By using multi-step mask etching to form a waist-shaped groove in the middle of the N-drift layer 8, the unique "narrow in the middle and wide at the top and bottom" three-dimensional structure is achieved by precisely controlling the etching depth and sidewall angle, providing a geometric basis for optimizing the electric field distribution.

[0024] Step 3: Form a doping waist N-layer 9 with a gradient doping concentration in the groove through epitaxial filling or tilted ion implantation, ensuring that its cross-section is thick at both ends and thin in the middle. The gradient-doped waist N-layer 9 is formed through epitaxial filling or tilted ion implantation. Its thick-end-thick-in-the-middle cross-section design can simultaneously reduce on-resistance and enhance withstand voltage capability, and the tilted implantation process can precisely control the concentration gradient.

[0025] Step 4: Implant a constrained N-layer 16 into the upper half of the beam waist N-layer 9, and control its doping concentration to be 0.4–0.7 times the background concentration of the beam waist N-layer; inject a constrained N-layer 16 (concentration 0.4–0.7 times the background concentration) into the upper half of the beam waist N-layer 9. This lightly doped layer can suppress the electric field peak and optimize the charge balance, thereby improving the dynamic stability of the device and avoiding switching oscillations.

[0026] Step 5: Inject an inhibited P-layer 15 into the corresponding position of the lower half of the beam waist N-layer 9 so that it is horizontally aligned with the constrained N-layer 16 and contacts the N substrate 7; align the injected inhibited P-layer 15 into the lower half of the beam waist N-layer 9 so that it is horizontally aligned with the constrained N-layer 16 and contacts the substrate, forming a vertical charge compensation structure, significantly enhancing the longitudinal withstand voltage capability and reducing leakage current.

[0027] Step 6: Symmetrical P-well layer 4, N-well layer 6, and P+ layer 5 are formed through photolithography and ion implantation. Symmetrical P-well layer 4, N-well layer 6, and P+ layer 5 are formed through photolithography and ion implantation. The strict symmetry design ensures uniform current distribution, avoids local overheating, and improves device reliability.

[0028] Step 7: Deposit a gate dielectric layer and form the gate 3 structure. The source 2 is formed on the front of the device, and the drain 1 is formed on the back. Depositing the gate dielectric and forming the gate 3 structure, combined with the ohmic contact process between the front source 2 and the back drain 1, ensures low contact resistance and high gate control efficiency, ultimately achieving high-performance device integration.

[0029] Example 1 like Figure 1 As shown, a superjunction metal-oxide-semiconductor field-effect transistor (SMOSFET) consists of a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer specifically includes two P-well layers 4, two P+ layers 5, two N-well layers 6, an N substrate layer 7, and an N-drift layer 8. A waisted N-layer 9 is formed within the N-drift layer 8 through ion implantation. The waisted N-layer 9 consists of an upper and lower region, and its cross-section is thicker at the top and bottom and thinner in the middle. The N-layer 9 is designed within the N-drift layer 8 to have a waisted cross-section (thicker at the ends and thinner in the middle). Conventional superjunction MOSFETs suffer from uneven electric field distribution under high voltage, resulting in limited breakdown voltage and high on-resistance. The waisted structure optimizes the electric field distribution in the N-drift layer 8, increasing the breakdown voltage while reducing on-resistance and enhancing the device's withstand voltage capability.

[0030] Example 2 like Figure 2 As shown, a constrained P-layer 10 is formed on top of the upper half of the beam-waist N-layer 9 through ion implantation. This constrained P-layer 10 is located between the two P-well layers 4. The constrained P-layer 10 is implanted on top of the beam-waist N-layer 9, between the two P-well layers 4. The structure of the beam-waist N-layer 9 tends to concentrate the electric field at the top, potentially causing localized breakdown. The constrained P-layer 10 suppresses the peak electric field at the top, improving device reliability and simplifying the process (implemented through ion implantation).

[0031] Example 3 like Figure 3As shown, a high-resistance dielectric 11 is provided on top of the upper half of the waist N-layer 9. This high-resistance dielectric 11 is located between the two P-well layers 4 and forms an ohmic contact with the gate 3. High-resistance dielectric 11 replaces the constrained P-layer and forms an ohmic contact with the gate 3. The P-type injection layer may introduce carrier recombination, affecting switching speed. High-resistance dielectric 11 both averages the electric field and prevents carrier loss, improving switching efficiency and the controllability of the gate 3.

[0032] Example 4 like Figure 4 As shown, the lower half of the waist N-layer 9 is provided with two sets of highly doped N+ layers 13, each set of highly doped N+ layers 13 in contact with the N substrate layer 7. Each set of highly doped N+ layers 13 is provided with side P-block layers 12 on both sides, which are in contact with the highly doped N+ layers 13. The highly doped N+ layer 13 and the side P-block layers 12 on both sides are provided at the bottom of the waist N-layer 9. The conduction path resistance at the bottom of the device is high and is prone to longitudinal breakdown under high voltage. The N+ layer 13 reduces the on-resistance, while the side P-blocks 12 enhance the longitudinal withstand voltage and optimize the current spreading capability.

[0033] Example 5 like Figure 5 As shown, the upper half of the beam waist N-layer 9 also forms a heavily doped upper region 14. The upper half of the beam waist N-layer 9 is designed as the heavily doped upper region 14. The narrow region in the middle of the beam waist structure can easily become a conduction bottleneck, limiting current capability. The heavily doped upper region 14 reduces channel resistance, increases saturation current, and enhances device conduction performance.

[0034] Example 6 like Figure 6 As shown, the upper half of the waist N-layer 9 is formed with a constrained N-layer 16 via ion implantation. The doping concentration of this constrained N-layer 16 is 0.4–0.7 times that of the waist N-layer 9. The lower half of the waist N-layer 9 is formed with a suppressed P-layer 15 via ion implantation. This suppressed P-layer 15 is horizontally aligned with the constrained N-layer 16 and contacts the N substrate layer 7. The constrained N-layer 16 (with a concentration of 0.4–0.7 times that of the waist N-layer 9) is implanted in the upper half of the waist N-layer 9, while the suppressed P-layer 15 is implanted in the lower half. Charge imbalance in the drift region reduces the withstand voltage and can lead to oscillation during switching. The constrained N-layer 16 and suppressed P-layer 15 achieve vertical charge balance, significantly improving breakdown voltage stability and suppressing dynamic oscillations.

[0035] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A superjunction metal oxide semiconductor field effect transistor, comprising a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3), wherein the semiconductor epitaxial layer specifically comprises two P well layers (4), two P+ layers (5), two N well layers (6), an N substrate layer (7) and an N drift layer (8), characterized in that: A beam waist N-layer (9) is formed inside the N drift layer (8) by ion implantation; The beam waist N-layer (9) consists of an upper half region and a lower half region, wherein the cross-sectional profile of the beam waist N-layer (9) is thick at the upper and lower ends and thin in the middle.

2. The superjunction metal oxide semiconductor field effect transistor according to claim 1, wherein: A constrained P-layer (10) is formed on the top of the upper half of the waist N-layer (9) by ion implantation, and the constrained P-layer (10) is located between two P-well layers (4).

3. The superjunction metal oxide semiconductor field effect transistor according to claim 1, wherein: A high-resistance dielectric (11) is provided on the top of the upper half of the waist N-layer (9), the high-resistance dielectric (11) is located between the two P-well layers (4), and the high-resistance dielectric (11) is in ohmic contact with the gate (3).

4. The superjunction metal oxide semiconductor field effect transistor according to claim 1, wherein: Two groups of highly doped N+ layers (13) are provided in the lower half of the waist N-layer (9), and each group of highly doped N+ layers (13) is in contact with the N substrate layer (7).

5. The superjunction metal oxide semiconductor field effect transistor according to claim 4, wherein: Side P-block layers (12) are provided on both the left and right sides of each group of the highly doped N+ layers (13), and the side P-block layers (12) are in contact with the highly doped N+ layers (13).

6. The super junction metal oxide semiconductor field effect transistor according to claim 1, wherein: The upper half of the beam waist N-layer (9) is also a heavily doped upper region (14).

7. The super junction metal oxide semiconductor field effect transistor according to claim 1, wherein: The upper half of the waist N-layer (9) is formed with a constrained N-layer (16) by ion implantation, and the doping concentration of the constrained N-layer (16) is 0.4 to 0.7 times the doping concentration of the waist N-layer (9).

8. The super junction metal oxide semiconductor field effect transistor according to claim 7, wherein: A suppression P-layer (15) is formed in the lower half of the beam waist N-layer (9) by ion implantation. The suppression P-layer (15) and the constraint N-layer (16) are aligned with each other in the horizontal direction, and the suppression P-layer (15) is in contact with the N substrate layer (7).

9. A method for manufacturing a super junction metal oxide semiconductor field effect transistor, characterized in that: The super junction metal oxide semiconductor field effect transistor according to any one of claims 1, 7 or 8, wherein the method for manufacturing the super junction metal oxide semiconductor field effect transistor comprises: S1, growing a low-doped N drift layer (8) on the surface of the N substrate layer (7) by an epitaxial process; S2, using a multi-step mask etching process inside the N drift layer (8) to etch a waist-shaped groove in the middle region of the N drift layer (8) that is narrow in the middle and wide at the top and bottom; S3, forming a beam waist N-layer (9) with a doping concentration gradient in the groove by epitaxial filling or tilted ion implantation process, ensuring that its cross section is thick at both ends and thin in the middle; S4, implanting into the upper half of the beam waist N-layer (9) to form a constrained N-layer (16), controlling its doping concentration to be 0.4–0.7 times the background concentration of the beam waist N-layer; S5. Implant the suppressed P-layer (15) at the corresponding position in the lower half of the beam waist N-layer (9) so that it is horizontally aligned with the constrained N-layer (16) and contacts the N substrate (7); S6, forming a symmetrical P-well layer (4), an N-well layer (6) and a P+ layer (5) by photolithography and ion implantation; S7, depositing a gate dielectric layer and forming a gate (3) structure to form a source (2) on the front side of the device and a drain (1) on the back side.

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