Power optimization through DRAM bank management in solid state drives
By dynamically switching the usage strategies of DRAM and HMB in storage devices, the problems of power consumption exceeding the limit and data access delay are solved, and performance optimization and efficiency improvement under predefined power upper limit are achieved.
Patent Information
- Application Number
- CN202480005459.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2024-05-29
- Publication Date
- 2025-08-12
AI Technical Summary
The power consumption of existing storage devices may exceed the power limit when using DRAM, resulting in limited performance and the use of HMB increases data access latency.
Dynamically switch RAM usage strategies through the power optimization module, use internal DRAM and external HMB to adjust the usage ratio of RAM according to power usage and performance requirements, and optimize power consumption and performance.
Optimize the performance of storage devices under predefined power upper limits, reduce power consumption and reduce data access latency, and improve the overall efficiency of storage devices.
Smart Images
Figure CN120476379A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims the benefit of the entire contents of U.S. non-provisional application No. 18 / 373,403, filed with the U.S. Patent and Trademark Office on September 27, 2023, entitled “ENABLING POWEROPTIMIZATION THROUGH DRAM BANK MANAGEMENT IN SOLID STATE DRIVES,” and is incorporated herein by reference for all purposes. Background Art
[0003] The storage device is communicatively coupled to a host and can receive data from the host to store on a non-volatile memory. The memory can be, for example, a flash memory device that is also communicatively coupled to the storage device. When processing data on the storage device, a controller on the storage device can access volatile memory located on the storage device. For example, the controller can access static random access memory (SRAM) located on the same chip as the controller, or the controller can access DRAM located on another chip in the storage device via a dynamic random access memory (DRAM) interface. SRAM and DRAM can be used as cache to store data structures and / or as buffers in a read / write path, or when manipulating data such as flash translation tables.
[0004] The controller can also access a host memory buffer (HMB) (i.e., a cache provided by the host) to improve the performance of the storage device. The size of the HMB can be limited to, for example, 64 megabytes (MB), while the size of the DRAM can be many times larger than the size of the HMB. Therefore, unlike the DRAM that the controller can use to temporarily store large amounts of data (such as flash translation tables), the controller can use the HMB as a cache to store a relatively limited amount of data. When the controller uses the HMB instead of DRAM to store information in the flash translation table, the controller may have to swap the information in the flash translation table into and out of the HMB, which may result in cache misses and processing overhead on the storage device.
[0005] A storage device may have an upper limit on the amount of power it can consume. For example, in some storage devices, the power cap may be 5 watts (W) or 8 W. Although the use of DRAM may be necessary for the storage device to meet performance targets, when the DRAM is located in the storage device, the power consumed by the DRAM may be attributed to the storage device. Therefore, the power cap under which the storage device can operate may hinder the storage device when using the full functionality of the DRAM. Unlike DRAM, the power consumed by the HMB is attributed to the host and does not increase the power consumption attributed to the storage device. In order to stay below the power cap, the controller may only be able to use portions of the DRAM and / or the HMB. However, as noted, the HMB is typically smaller than the DRAM, and swapping data in and out of the HMB during its use may increase data access latency on the storage device. Therefore, a system flow is needed so that the storage device can optimize power consumption and performance. Summary of the Invention
[0006] In some embodiments, a storage device optimizes performance and operates under a predefined power cap. The storage device includes a controller configured to receive an indication from a host device of a power mode in which the storage device is to operate. The storage device also includes a power optimization module configured to determine power usage of the storage device. When the power usage is below a power cap threshold, the power optimization module issues a first random access memory (RAM) usage policy for the controller to use internal RAM when processing host data. When the power usage is above the power cap threshold, the power optimization module issues a second RAM usage policy for the controller to use external RAM or portions of the external RAM and the internal RAM when processing the host data.
[0007] In some implementations, one or more methods are provided for optimizing performance on a storage device while operating under a predefined power cap. The method includes receiving an indication from a host device of a power mode in which the storage device is to operate and determining the power usage of the storage device. The method also includes issuing a first random access memory (RAM) usage policy to use internal RAM when processing host data when the power usage is below a power cap threshold; and issuing a second RAM usage policy to use external RAM or portions of the external RAM and the internal RAM when processing the host data when the power usage is above the power cap threshold. The method also includes receiving a high-performance mode command from the host device, determining that the host device is operating in the high-performance mode, determining that there is a decrease in cache hits on the external RAM, or determining that a congestion level on a link between the host device and the storage device is above a congestion threshold while operating under the second RAM usage policy; and issuing the first RAM usage policy to use the internal RAM when processing the host data. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a schematic block diagram of an example system according to some specific implementations.
[0009] Figure 2 is a flow chart of an example process for a storage device to optimize performance and operate within a predefined power cap, according to some implementations.
[0010] Figure 3 is a flow chart of an example process for a storage device to improve performance by switching from an external cache to an internal cache, according to some implementations.
[0011] Figure 4 is an illustration of an example environment in which systems and / or methods described herein may be implemented.
[0012] Figure 5 yes Figure 1 An illustration of example components of a host.
[0013] Those skilled in the art will appreciate that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the sizes of some elements in the drawings may be magnified relative to other elements to help improve understanding of the specific implementation of the present disclosure.
[0014] Where appropriate, apparatus and method components have been represented by conventional symbols in the drawings, showing those specific details relevant to understanding the specific implementations of the disclosure so as not to obscure the disclosure with details that would be readily apparent to those skilled in the art.
[0015] Detailed description of the invention
[0016] The following detailed description of example implementations refers to the accompanying drawings, in which the same reference numbers in different drawings may identify the same or similar elements.
[0017] Figure 1 is a schematic block diagram of an example system according to some specific implementations. System 100 includes a host 102 and a storage device 104. The host 102 can send commands to read data from or write data to the storage device 104. The host 102 may include a host memory buffer (HMB) 106, which is used to cache mapping information used by, for example, the storage device 104. The host 102 and the storage device 104 can be in the same physical location as components on a single computing device or on different computing devices that are communicatively coupled. In various specific implementations, the storage device 104 can be set at one or more different locations relative to the host 102, and the storage device 104 can communicate with the host 102 via a peripheral component interconnect express (PCIe) protocol, etc. The host 102 may include additional components (not shown in this figure for simplicity).
[0018] The storage device 104 may include a controller 108, one or more memory devices 110a to 110n (referred to herein as memory devices 110), a host interface 112, a PCIe traffic monitor 114, a cache hit monitor 116, a power optimization module 118, a flash translation layer (FTL) module 120, a DRAM 122, and an SRAM 124. The controller 108 may process foreground operations to read data from or write data to the memory device 110 based on instructions received from the host 102. The controller may also perform background operations to manage resources on the memory device 110. For example, the controller 108 may monitor the memory device 110 and may perform garbage collection and other relocation functions according to an internal relocation algorithm to refresh and / or relocate data on the memory device 110.
[0019] The controller 108 may cache information needed to process foreground and / or background operations on the DRAM 122 and / or SRAM 124. The memory device 110 may be flash-based, including, for example, NAND flash memory. The memory device 110 may be included in the storage device 104 or may be otherwise communicatively coupled to the storage device 104.
[0020] The host 102 may provide power to the storage device 104, and the host 102 may indicate to the storage device 104 which power mode or power state (PS) to operate in. For example, if the power cap of the storage device 104 is 5 watts (W) and if 5W is associated with PS2, the host 102 may indicate to the storage device 104 that it is to operate in PS2; or if the power cap of the storage device 104 is 8W and if 8W is associated with PS1, the host 102 may indicate to the storage device 104 that it is to operate in PS1. The host 102 may also indicate that the storage device 104 can operate in a high-performance mode, which may be associated with, for example, PS 0. The high-performance mode may be set using a vendor-unique host command, a non-volatile memory express (NVMe) workload hint, and / or a maximum power state (PS 0). When the storage device is operating in high-performance mode, the storage device 104 may ignore the power cap under which the storage device 104 is to operate.
[0021] When the host 102 sends a command to the storage device 104, the host interface 112 may receive the command and provide an indication of the host command to the power optimization module 118. The command may be, for example, a read command, a write command, or a power mode command. When the host 102 issues a read command, the host 102 may send a logical block address associated with the data to be read from the memory device 110. The controller 108 may access the data stored on the memory device 110 by accessing a logical-to-physical (L2P) table, which includes a mapping of the logical address associated with the data to the physical address on the memory device 110. The FTL module 120 may map the logical block address generated by the host to the physical address of the memory device 110 and store the FTL mapping in a volatile random access memory (RAM) (e.g., DRAM 122) using a first RAM usage policy as defined by the power optimization module 118. The first RAM usage policy may be issued when the storage device 104 is operating below its power cap or power cap threshold. The power cap threshold may be a predefined threshold that may be lower than the power cap at which the storage device 104 is to operate. As the FTL module 120 is processing back-end storage operations while operating under the first RAM usage policy, the FTL module 120 may access the L2P table and other information cached in the DRAM 122.
[0022] Since the power used by DRAM 122 is attributed to storage device 104, in order to remain below the power cap under which storage device 104 is to operate, power optimization module 118 can track the power usage of storage device 104. When power optimization module 118 determines that the power usage of storage device 104 is equal to or above the power cap threshold, power optimization module 118 can issue a second RAM usage policy to FTL module 120. The second RAM usage policy can be set to conserve power attributed to storage device 104 and / or meet power targets. The second RAM usage policy can also be set to enable storage device 104 to use external cache (e.g., HMB 106) even if internal cache (e.g., DRAM 122) is available for use.
[0023] As part of the second RAM usage policy, the power optimization module 118 can notify the FTL module 120 to minimize or stop using the DRAM 122 and increase the use of the HMB 106. For example, as part of the second RAM usage policy, the power optimization module 118 can notify the FTL module 120 to stop using the DRAM 122 for a predefined period of time or until the power consumption on the memory device 104 reaches a certain point. In another example, as part of the second RAM usage policy, the power optimization module 118 can notify the FTL module 120 to use the HMB 106 and a portion of the DRAM 122. Thus, based on the second RAM usage policy, the memory device 104 can shut down some memory banks in the DRAM 122 and proportionally use the HMB 106 to meet the power target specification.
[0024] Based on the instruction from power optimization module 118, FTL module 120 can load L2P mapping information into HMB 106 instead of DRAM 122, or can load L2P mapping information into HMB 106 and each part of DRAM 122. The use of HMB 106 may result in a longer delay than that which may be experienced when using DRAM 122. Therefore, when FTL module 120 switches to HMB 106, there may be a performance impact (especially at very low queue depth). In some specific implementations, the partial use of DRAM 122 can continue to be used for commands with higher hit counts, wherein HMB 106 serves as a secondary cache. Under thermal throttling conditions where performance is intended to be limited, DRAM 122 can be completely shut down, and storage device 104 can switch to HMB 106.
[0025] Because the size of HMB 106 can be relatively smaller than the size of DRAM 122. FTL module 120 can load relatively few L2P table pages in HMB 106, and FTL module 120 may have to swap L2P table pages in and out of HMB 106 to process back-end storage operations. Therefore, when HMB 106 is being used, the input / output traffic between host 102 and storage device 104 may increase. PCIe traffic monitor 114 can monitor the traffic between host 102 and storage device 104 and provide updates to traffic flow to power optimization module 118. Power optimization module 118 can use the information provided by PCIe traffic monitor 114 to monitor the congestion level on the PCIe link between host 102 and storage device 104.
[0026] In one embodiment, the FTL module 120 may cache the information in the HMB 106. If the FTL module 120 is processing a large number of requests, the information cached in the HMB 106 may not be the information required by the FTL module 120, and the FTL module 120 may have to swap out the information stored in the HMB 106 and replace the information with the information required by the FTL module 120. This swapping in and out of the cached information may cause a decrease in the cache hits of the FTL module 120. Since the FTL module 120 swaps the mapping information cached in the HMB 106, the use of the HMB 106 may increase the overhead on the storage device 104. The cache hit monitor 116 can track how many pages are swapped in and out of the HMB 106 and provides an indication of the swap-in / swap-out rate to the power optimization module 118. The power optimization module 118 can use the information provided by the cache hit monitor 116 to monitor the swap-in / swap-out rate on the HMB 106.
[0027] When the storage device 104 uses the HMB 106, the power optimization module 118 may also determine whether the host 102 is operating in high-performance mode. The power optimization module 118 may determine that the host 102 is operating in high-performance mode based on a host command received by the host interface 112 or based on an internal mechanism on the storage device 104. For example, the internal mechanism may determine that the command being issued by the host 102 is associated with high-performance mode and may provide an indication to the power optimization module 118 that the host 102 is operating in high-performance mode. When the power optimization module 118 determines that the host 102 is operating in high-performance mode, the power optimization module 118 may ignore the power cap and issue the first RAM usage policy. Therefore, in high-performance mode, the storage device 104 may operate according to the first RAM usage policy.
[0028] If the storage device 104 receives a high-performance mode command from the host 102 or otherwise determines that the host 102 is operating in high-performance mode, determines that there is a drop in cache hits based on information received from the cache hit monitor 116, or determines that congestion on the PCIe link is above a congestion threshold, the power optimization module 118 may issue a first RAM usage policy to direct the FTL module 120 to use DRAM 122. This may enable the storage device 104 to selectively enable or disable the internal DRAM interface. For example, the storage device 104 may selectively enable the internal DRAM interface when in high-performance mode and may selectively disable the internal DRAM interface when the host 102 is not operating in high-performance mode. In another example, the storage device 104 may selectively enable or disable the use of DRAM 122 based on cache hits and / or PCIe traffic congestion. Thus, storage device 104 may use HMB 106, such as during off-peak loads, when it determines that FTL module 120 is accessing a narrow range of data requests or when PCIe traffic is such that HMB 106 accesses will not congest the PCIe traffic lanes.
[0029] The storage device 104 can perform these processes based on, for example, the execution of software instructions stored by a non-transitory computer-readable medium such as the storage component 110 by a processor of the controller 108. As used herein, the term "computer-readable medium" refers to a non-transitory memory device. The software instructions can be read into the storage component 110 from another computer-readable medium or from another device. When executed, the software instructions stored in the storage component 110 can cause the controller 108 to perform one or more processes described herein. Additionally or alternatively, hardware circuitry can be used instead of or in combination with software instructions to perform one or more processes described herein. Therefore, the specific implementations described herein are not limited to any particular combination of hardware circuitry and software. The system 100 may include additional components (not shown in this figure for simplicity). Figure 1 are provided as examples. Other examples may vary. Figure 1 The example described.
[0030] Figure 22 is a flow chart of an example process for optimizing performance of a storage device and operating under a predefined power cap, according to some implementations. At 210, the host 102 may provide power to the storage device 104, and the host 102 may indicate to the storage device 104 which power mode to operate in. At 220, the host interface 112 may receive a command sent from the host 102 and provide an indication to the power optimization module 118. At 230, based on the host command, the FTL module 120 may map the host-generated logical block address to a physical address of the memory device 110 and store the FTL map in the DRAM 122 using the first RAM usage policy defined by the power optimization module 118.
[0031] At 240, the power optimization module 118 can track the power usage of the storage device 104 and can issue a second RAM usage policy to the FTL module 120 when the power usage of the storage device 104 exceeds the power capping threshold. At 250, as part of the second RAM usage policy, the power optimization module 118 can notify the FTL module 120 to minimize or stop using DRAM 122 and increase using HMB 106. At 260, based on the second RAM usage policy, the storage device 104 can shut down some banks in DRAM 122 and use HMB 106 proportionally to meet the power target specification. At 270, based on the second RAM usage policy, the FTL module 120 can load L2P mapping information into HMB 106 instead of DRAM 122, or can load L2P mapping information into HMB 106 and portions of DRAM 122. Figure 2 are provided as examples. Other examples may vary. Figure 2 The example described.
[0032] Figure 3 FIG3 is a flow chart of an example process for improving performance of a storage device by switching from an external cache to an internal cache, according to some implementations. At 310, the power optimization module 118 can track the power usage of the storage device 104 and can issue a second RAM usage policy to the FTL module 120 when the power usage of the storage device 104 exceeds a power capping threshold. At 320, based on the second RAM usage policy, the FTL module 120 can load the L2P mapping information into the HMB 106 instead of the DRAM 122, or can load the L2P mapping information into the HMB 106 and portions of the DRAM 122.
[0033] At 330, the PCIe traffic monitor 114 may monitor traffic between the host 102 and the storage device 104 and provide updates on the traffic flow to the power optimization module 118 for use in monitoring the congestion level on the PCIe link between the host 102 and the storage device 104. At 340, the cache hit monitor 116 may track how many pages are swapped in and out of the HMB 106 and provide an indication of the swap-in / swap-out rate to the power optimization module 118 for use in monitoring the swap-in / swap-out rate on the HMB 106. At 350, the power optimization module 118 may also determine whether the host 102 is operating in a high-performance mode command. At 360, if the power optimization module 118 determines that the host 102 is operating in a high performance mode command, determines that there is a drop in cache hits based on information received from the cache hit monitor 116, or determines that congestion on the PCIe link is above a congestion threshold, the power optimization module 118 may issue a RAM policy to direct the FTL module 120 to use DRAM 122 instead of HMB 106. As shown above, Figure 3 are provided as examples. Other examples may vary. Figure 3 The example described.
[0034] Figure 4 is a diagram of an example environment in which the systems and / or methods described herein are implemented. Figure 4 As shown, environment 400 may include hosts 102 through 102n (referred to herein as hosts 102) and storage devices 104a through 104n (referred to herein as storage devices 104).
[0035] The storage device 104 may include a controller 108 for managing resources on the storage device 104. The controller 108 may execute a power optimization module to manage power consumption on the storage device 104 and issue a RAM usage policy based on the power consumption on the storage device 104. The host 102 and the storage device 104 may communicate via a Non-Volatile Memory Express (NVMe) interface.
[0036] Figure 4 The number and arrangement of components shown are provided as examples. In practice, there may be additional components, fewer components, different components, or components that are different from the components shown. Figure 4 Components arranged differently than those shown. Figure 4 Two or more of the devices shown may be implemented in a single device, or Figure 4 The single device shown may be implemented as multiple distributed devices. Additionally or alternatively, one set of devices (eg, one or more devices) of environment 400 may perform one or more functions described as being performed by another set of devices of environment 400.
[0037] Figure 5 yes Figure 1 5. In some implementations, host 102 can include one or more devices 500 and / or one or more components of device 500. Device 500 can include, for example, a communication component 505, an input component 510, an output component 515, a processor 520, a storage component 525, and a bus 530. Bus 530 can include components that enable communication between multiple components of device 500, where components of device 500 can be coupled to communicate with other components of device 500 via bus 530.
[0038] Input components 510 may include components that permit device 500 to receive information via user input (e.g., a keypad, keyboard, mouse, pointing device, microphone, and / or display), and / or components that permit device 500 to determine location or other sensor information (e.g., an accelerometer, gyroscope, actuator, another type of location or environmental sensor). Output components 515 may include components that provide output information from device 500 (e.g., a speaker and / or display, etc.). Input components 510 and output components 515 may also be coupled to communicate with processor 520.
[0039] The processor 520 may be a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or another type of processing component. In some implementations, the processor 520 may include one or more processors that can be programmed to perform functions. The processor 520 may be implemented in hardware, firmware, and / or a combination of hardware and software.
[0040] The storage component 525 may include, for example, the storage device 104, which may include one or more memory devices such as random access memory (RAM), read-only memory (ROM), and / or another type of dynamic or static storage device (e.g., flash memory, magnetic storage, and / or optical storage) that stores information and / or instructions for use by the processor 520. An example of RAM in the storage component 525 may include DRAM 122. A memory device may include memory space within a single physical storage device or memory space distributed across multiple physical storage devices. The storage component 525 may also store information and / or software related to the operation and use of the device 500. For example, the storage component 525 may include a hard disk (e.g., a magnetic disk, an optical disk, and / or a magneto-optical disk), a solid-state drive (SSD), a compact disk (CD), a digital versatile disk (DVD), a floppy disk, a cassette, a magnetic tape, and / or another type of non-transitory computer-readable medium, and a corresponding drive.
[0041] The communication component 505 may include a component similar to a transceiver that enables the device 500 to communicate with other devices, such as via a wired connection, a wireless connection, or a combination of a wired connection and a wireless connection. The communication component 505 may allow the device 500 to receive information from another device and / or provide information to another device. For example, the communication component 505 may include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, a radio frequency (RF) interface, a universal serial bus (USB) interface, a Wi-Fi interface, and / or a cellular network interface that can be configured to communicate with the network component and other user equipment within its communication range. The communication component 505 may also include one or more broadband and / or narrowband transceivers and / or other similar types of wireless transceivers that can be configured to communicate via a wireless network for infrastructure communications. The communication component 505 may also include one or more local area network or personal area network transceivers, such as a Wi-Fi transceiver or a Bluetooth transceiver.
[0042] The device 500 may perform one or more processes described herein. For example, the device 500 may perform these processes based on the processor 520 executing software instructions stored by a non-transitory computer-readable medium such as the storage component 525. As used herein, the term "computer-readable medium" refers to a non-transitory memory device. The software instructions may be read into the storage component 525 from another computer-readable medium or from another device via the communication component 505. When executed, the software instructions stored in the storage component 525 may cause the processor 520 to perform one or more processes described herein. Additionally or alternatively, hardware circuitry may be used instead of or in combination with software instructions to perform one or more processes described herein. Therefore, the specific implementations described herein are not limited to any particular combination of hardware circuitry and software.
[0043] Figure 5 The number and arrangement of components shown are provided as examples. In practice, device 500 may include additional components, fewer components, different components, or components that are different from those shown in FIG. Figure 5 Additionally or alternatively, one set of components (eg, one or more components) of device 500 may perform one or more functions described as being performed by another set of components of device 500.
[0044] The foregoing disclosure provides illustrative and descriptive implementations, but is not intended to be exhaustive or to limit implementations to the precise forms disclosed herein. Those skilled in the art will appreciate that various modifications and variations may be made without departing from the scope of the present disclosure as set forth in the following claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present teachings.
[0045] As used herein, the term "component" is intended to be broadly understood as hardware, firmware, and / or a combination of hardware and software. It will be apparent that the systems and / or methods described herein can be implemented by different forms of hardware, firmware, and / or a combination of hardware and software.
[0046] Although particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of each implementation. In fact, many of these features can be combined in ways not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of each implementation includes each dependent claim in combination with all other claims in the claim set.
[0047] Unless expressly stated otherwise, any element, action or instruction used herein should not be considered critical or essential. In addition, as used herein, the articles "a" and "an" are intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the term "group" is intended to include one or more items (e.g., related items, unrelated items, a combination of related items and unrelated items, etc.) and can be used interchangeably with "one or more". The term "only one" or similar wording is used to refer to that only one item is expected. In addition, unless expressly stated otherwise, the phrase "based on" is intended to mean "based at least in part on".
[0048] Furthermore, in this document, relational terms such as first and second, top and bottom may be used solely to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprises," "having," "includes," "contains," or any other variations thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises, has, contains, or includes a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by "comprises...a," "has...a," "includes...a," or "contains...a" does not, without more constraints, preclude the presence of additional identical elements in the process, method, article, or apparatus that comprises, has, contains, or includes such element. The terms "substantially," "essentially," "approximately," "about," or any other versions thereof, are defined as being approximately as understood by one of ordinary skill in the art, and in one non-limiting embodiment, the terms are defined as within 10%, within 5% in another embodiment, within 1% in another embodiment, and within 0.5% in another embodiment. The term "coupled," as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. A device or structure that is "configured" in a certain manner is configured in at least that manner, but may also be configured in ways not listed.
Claims
1. A storage device for optimizing performance and operating under a predefined power cap, the storage device comprising: a controller for receiving, from a host device, an indication of a power mode in which the storage device is to operate; and and a power optimization module for determining power usage of the storage device, wherein when the power usage is below a power capping threshold, the power optimization module is for issuing a first random access memory (RAM) usage policy for the controller to use internal RAM when processing host data, and when the power usage is above the power capping threshold, the power optimization module is for issuing a second RAM usage policy for the controller to use external RAM and one of portions of the external RAM and the internal RAM when processing the host data.
2. The storage device of claim 1 , further comprising a host interface for receiving commands from the host device and providing an indication of the host commands to the power optimization module for determining the power mode in which the storage device is to operate.
3. The storage device according to claim 1 further comprises a flash translation layer (FTL) module, wherein the flash translation layer (FTL) module is used to process backend operations and store FTL mapping according to the RAM usage policy issued by the power optimization module.
4. The storage device according to claim 1 further comprises a traffic monitor for monitoring the traffic between the host device and the storage device, and providing updates on the traffic flow to the power optimization module for monitoring the congestion level on the link between the host device and the storage device.
5. The storage device of claim 1 , further comprising a cache hit monitor for tracking how many pages are swapped in and out of the external RAM and providing an indication of the swap in / out rate to the power optimization module for monitoring the swap in / out rate on the external RAM. The memory device of claim 1 , wherein the power mode is associated with a power cap at which the memory device is to operate. 7 . The memory device of claim 1 , wherein the power mode is associated with a high-performance mode, wherein when the memory device is operating in the high-performance mode, the memory device ignores the power cap and operates according to the first RAM usage policy.
8. The storage device of claim 7, wherein the power optimization module determines that the storage device is operating in the high-performance mode based on one of a host command and an indication from an internal mechanism on the storage device. 9 . The memory device of claim 1 , wherein based on the second RAM usage policy, the controller shuts down memory banks in the internal RAM and proportionally uses the external RAM to meet a power target specification.
10. The storage device according to claim 1, wherein the power optimization module issues the first RAM usage policy when one of the following is performed: the storage device receives a high-performance mode command from the host device, determines that the host device is operating in the high-performance mode, determines that there is a decrease in cache hits on the external RAM, and determines that the congestion on the link between the host device and the storage device is higher than a congestion threshold.
11. A method for optimizing performance on a storage device and operating under a predefined power cap, wherein one or more processors on the storage device are configured to perform the method, the method comprising: receiving, from a host device, an indication of a power mode in which the storage device is to operate; determining power usage of the storage device; as well as When the power usage is below a power capping threshold, issuing a first random access memory (RAM) usage policy to use internal RAM when processing host data, and When the power usage is above the power capping threshold, a second RAM usage policy is issued to use external RAM and one of portions of the external RAM and the internal RAM when processing the host data.
12. The method according to claim 11, further comprising: Memory banks in the internal RAM are shut down, and the external RAM is used proportionally to meet a power target specification based on the second RAM usage policy.
13. A method for optimizing performance on a storage device and operating under a predefined power cap, one or more processors on the storage device being configured to perform the method, the method comprising: receiving, from a host device, an indication of a power mode in which the storage device is to operate; as well as determining power usage of the storage device; issuing a first random access memory (RAM) usage policy to use internal RAM when processing host data when the power usage is below a power capping threshold, issuing a second RAM usage policy to use external RAM and one of portions of the external RAM and the internal RAM when processing the host data when the power usage is above the power capping threshold; as well as When operating under the second RAM usage policy, one of the following is performed: receiving a high performance mode command from the host device, determining that the host device is operating in the high performance mode, determining that there is a decrease in cache hits on the external RAM, and determining that the congestion level on the link between the host device and the storage device is above a congestion threshold; and issuing the first RAM usage policy to use the internal RAM when processing the host data.
14. The method according to claim 13, further comprising: A command is received from the host device and an indication of the host command is used to determine the power mode in which the storage device is to operate.
15. The method according to claim 13, further comprising: Handles backend operations and stores mappings according to RAM usage policy.
16. The method according to claim 13, further comprising: Traffic between the host device and the storage device is monitored, and updates to the traffic flow are used to monitor the congestion level on the link between the host device and the storage device.
17. The method according to claim 13, further comprising: How many pages are swapped in and out of the external RAM is tracked, and the indication of the swap in / out rate is used to monitor the swap in / out rate on the external RAM.
18. The method according to claim 13, wherein when the storage device is operating in the high performance mode, the method further comprises: The power cap is ignored and operation is performed according to the first RAM usage policy.