A method for manufacturing a high-temperature high-power-density SiC power semiconductor device

Abstract

This invention belongs to the field of semiconductor device fabrication technology and discloses a method for fabricating high-temperature, high-power-density SiC power semiconductor devices. The invention has low equipment requirements: due to the short sintering time, few sintering cycles, and all planar sintering, a common hot press and heating table can be used for sintering in air, eliminating the need for expensive nitrogen-filled pressurized silver sintering furnaces. The process is simple and fast: only two sintering cycles, two welding cycles, one bonding cycle, and one potting cycle are needed to complete the fabrication of a double-sided cooled 250°C high-temperature SiC power semiconductor device, including a heat dissipation base plate and insulating potting. A low-cost solution for 250°C high-temperature applications: expensive materials such as nano-silver are used only in some key locations. Utilizing thermal diffusion characteristics, high-temperature solder is used instead of nano-silver at the heat dissipation base plate-substrate welding interface where heat flow is fully diffused. This avoids the problems of high difficulty and high material cost associated with large-area silver sintering without significantly reducing heat dissipation performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, and particularly relates to a method for fabricating a high-temperature, high-power-density SiC power semiconductor device. Background Technology

[0002] Wide bandgap power devices, due to their advantages such as high critical electric field, high thermal conductivity, low on-resistance, high switching speed, and low switching loss, have broad application prospects in many harsh working environments, including aerospace, electric vehicles, and energy exploration. To fully utilize the ability of wide bandgap devices to operate under high temperature and high pressure, wide bandgap power module packaging technology is developing towards higher temperature resistance, higher pressure resistance, and higher reliability.

[0003] High-temperature SiC power semiconductor devices with double-sided cooling and ceramic hermetically sealed composite conformal coating encapsulation combine the advantages of high-temperature packaging and double-sided cooling packaging, which can significantly improve the output power level and switching frequency, thereby significantly improving the power density of power electronic converters.

[0004] However, due to the introduction of specially designed ceramic hermetically sealed structures and the requirement for high-temperature applications at 250 degrees Celsius, the fabrication schemes suitable for traditional double-sided cooled SiC power semiconductor devices are no longer directly applicable to the fabrication of ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor devices.

[0005] Existing technology discloses a method for fabricating a double-sided cooled SiC power module. This method uses a high thermal conductivity metal plate as an interlayer and employs a vacuum brazing process to integrate the upper and lower heat sinks with the SiC chip to form an integral structure, thereby achieving efficient double-sided heat dissipation performance. This solution is mainly applied in fields such as electric vehicle inverters and aerospace power converters, and can operate stably in medium-high temperature environments (approximately 175°C).

[0006] However, the aforementioned existing technologies have significant limitations when dealing with higher temperature requirements (such as 250°C). On the one hand, this method requires solder with multiple temperature gradients, and the highest process temperature exceeds 400°C when used to fabricate a 250°C high-temperature power module, which can damage the chip. On the other hand, this method does not involve hermetic design, and cannot effectively protect the SiC chip from the erosion of moisture and corrosive gases in harsh external environments at extreme temperatures, limiting its application under extreme high-temperature and high-pressure conditions. Furthermore, it does not address the specific processes and steps involved in the fabrication of hermetic components within the module.

[0007] To address the aforementioned shortcomings of existing technologies, there is an urgent need to propose a high-temperature, high-power-density SiC power semiconductor device fabrication method that can balance high-temperature environmental stability and high hermetic sealing performance. This method should also be characterized by low cost, simple process, and high yield to ensure long-term reliable operation of the device at 250°C and enhance its engineering application value in extreme application scenarios such as aerospace and new energy equipment. Summary of the Invention

[0008] To address the problems existing in the prior art, this invention provides a method for fabricating high-temperature, high-power-density SiC power semiconductor devices.

[0009] This invention is implemented as follows: a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device, comprising:

[0010] Both the lower and upper substrates are double-sided metallized ceramic plates that carry power-level current; both are silicon nitride ceramic copper-clad substrates prepared by AMB process, with a ceramic layer thickness of 0.32 mm and a copper layer thickness of 0.3 mm, and the surface is treated with electroless nickel-gold (ENIG).

[0011] A power chip assembly disposed between a lower substrate and an upper substrate is electrically interconnected with the metal layers of the upper and lower substrates via pads.

[0012] A copper-molybdenum alloy pad is disposed between the power chipset and the upper substrate. The pad contains 70% molybdenum and is electroplated with nickel and silver.

[0013] A ceramic airtight frame is disposed between the upper and lower substrates. The ceramic airtight frame is made of high-temperature co-fired alumina ceramic, and its upper and lower surfaces are respectively brazed with 0.2mm thick Kovar alloy to form a stress buffer layer. The frame body has alumina bosses inside, and the bosses have conductive pads that connect the inside and outside of the airtight cavity. The ceramic airtight frame and the upper and lower substrates together form an airtight system inside the module.

[0014] The module further includes:

[0015] A ceramic decoupling capacitor is disposed in the area between the lower substrate and the power chipset, and is connected in parallel with the DC input terminal of the power chip to suppress switching spike voltage and common-mode interference;

[0016] The upper substrate terminal and the lower substrate terminal are respectively connected to the copper layer of the upper substrate and the lower substrate, and are used for the introduction and extraction of external current of the module.

[0017] The module also includes:

[0018] The upper heat dissipation base plate and the lower heat dissipation base plate are respectively disposed on the outer side of the upper substrate and the lower substrate;

[0019] The surface of the heat dissipation base plate is provided with multiple cylindrical heat dissipation columns extending along the thickness direction to increase the heat exchange area and improve heat dissipation efficiency.

[0020] The module is covered with potting insulating material on all surfaces to enhance its insulation performance and environmental adaptability.

[0021] This invention provides a method for fabricating a high-temperature, high-power-density SiC power semiconductor device, comprising:

[0022] Step 1: Using a pressure silver sintering process, the power chipset is sintered onto the substrate;

[0023] Step 2: Using a pressure silver sintering process, the pad is sintered onto the power source of the chipset.

[0024] Step 3: Using vacuum formic acid reflow soldering, the terminals, decoupling capacitors, heat sink base plate, and ceramic airtight frame assembly are soldered onto the substrate.

[0025] Step 4: Use bonding wires to ultrasonically bond the gate and Kelvin source of the power chip to the conductive pads of the ceramic hermetic frame.

[0026] Step 5: Use Kapton tape to mask the areas that will be welded or crimped later, and apply insulation and potting to the other areas.

[0027] Step 6: Use vacuum formic acid reflow soldering process to weld the upper and lower substrates together.

[0028] Furthermore, the power chipset is sintered onto the substrate using a silver-pressed sintering process:

[0029] Nano silver paste or silver film is printed on the upper / lower substrates using a stencil, power chipsets are mounted, dried on a heating table, and sintered in a hot press.

[0030] Furthermore, the pad is sintered onto the power source of the chipset using a pressure silver sintering process:

[0031] Nano silver paste or silver film is printed onto the power source of the power chip assembly using a stencil, then pads are attached, the assembly is dried on a heating table, and finally sintered in a hot press.

[0032] Furthermore, the vacuum formic acid reflow soldering process is used to solder the terminals, decoupling capacitors, heat sink base plate, and ceramic hermetic frame assembly onto the substrate.

[0033] Place solder pads or print solder paste at the terminal soldering positions, ceramic airtight frame soldering positions, and decoupling capacitor soldering positions on the substrate; place solder pads between the heat sink base plate and the substrate; and reflow solder under a vacuum formic acid nitrogen atmosphere.

[0034] Furthermore, Kapton tape is used to mask the areas that will be subsequently welded or crimped, and to insulate and pot the other areas.

[0035] Use Kapton tape to mask the upper surface of the pad, the upper surface of the sealing ring on the upper side of the ceramic airtight frame, the areas of the substrate that will be soldered later, the power terminal screw interface, and the signal terminal crimp joint.

[0036] Then, the filling and sealing process is performed.

[0037] Using fluorinated dimethyl paraxylene as raw material, Parylene-HT thin films are deposited in the unmasked areas by chemical vapor deposition; subsequently, using alumina or silicon oxide as targets, inorganic thin films are deposited on the surface of the Parylene-HT thin film layer by magnetron sputtering or atomic layer deposition, forming a composite conformal coating in the unmasked areas.

[0038] Alternatively, a polyimide solution can be applied to the unmasked areas and then dried at high temperature.

[0039] Alternatively, ceramics or glass can be used to pot the unmasked areas.

[0040] Furthermore, the upper and lower substrates are welded together using a vacuum formic acid reflow soldering process:

[0041] High-temperature solder is applied to the upper surface of the pad for heat and electrical conduction, and high-temperature solder is applied to the upper surface of the sealing ring on the upper side of the ceramic airtight frame for airtight sealing. The cover is then closed by reflow welding under a vacuum formic acid and nitrogen atmosphere to achieve airtight sealing and conductive and heat-conducting connection of the core components.

[0042] Another object of the present invention is to provide a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device fabrication system comprising:

[0043] A power chipset sintering module is used to sinter power chipsets onto a substrate using a pressure silver sintering process.

[0044] The pad sintering module is used to sinter pads to the power source of the chipset using a pressure silver sintering process;

[0045] The component welding module is used to weld terminals, decoupling capacitors, heat sink base plates, and ceramic airtight frame components onto the substrate using a vacuum formic acid reflow soldering process.

[0046] The connection module is used to ultrasonically bond the gate and Kelvin source of the power chip to the conductive pads of the ceramic hermetic frame using bonding wires.

[0047] Masking modules are used to mask areas that will be welded or crimped later using Kapton tape, and to insulate and pot other areas.

[0048] The substrate welding module is used to weld the upper and lower substrates together using a vacuum formic acid reflow soldering process.

[0049] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0050] First, due to the addition of new ceramic structures and the requirement for high-temperature applications at 250 degrees Celsius, the traditional fabrication methods for double-sided cooled SiC power semiconductor devices are no longer suitable for the fabrication of ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor devices.

[0051] To address the aforementioned issues, a low-cost, rapid, high-yield, and simple fabrication method was developed for ceramic-sealed, double-sided cooled 250°C high-temperature SiC power semiconductor devices, while ensuring performance.

[0052] The advantages of the preparation method described in this invention are:

[0053] 1. Low requirements for sintering equipment: Due to the short sintering time, few sintering cycles, low sintering pressure, and the fact that all sintering is planar, this preparation method has low requirements for sintering equipment. It can use only a conventional hot press and heating table for sintering in air, and the subsequent vacuum formic acid reflow soldering process will remove the oxidation caused during sintering. The cost of the sintering equipment is only a fraction of that of a nitrogen-pressurized silver sintering furnace.

[0054] 2. Simple and fast process: Only two sintering, two welding, one bonding, and one potting are required to complete the complete fabrication of a double-sided cooled 250-degree high-temperature SiC power semiconductor device (including heat dissipation base plate) including heat dissipation base plate and insulating potting.

[0055] 3. Low-cost solution for 250-degree high-temperature applications: High-performance and expensive materials such as nano-silver and gold-tin are used only in small areas in some key locations; High-temperature solder is used instead of nano-silver at the heat dissipation base plate-substrate welding interface where the heat flow has been fully diffused, taking advantage of the thermal diffusion characteristics. This avoids the problems of high difficulty in large-area base plate sintering process, high material cost and high equipment requirements without significantly reducing heat dissipation performance.

[0056] 4. High-performance, high-yield process for 250°C high-temperature double-sided cooling packaging: Silver sintering is used at the chip-substrate and chip-pad interfaces, while the connections of other components and the capping of the upper and lower substrates are all done using 340°C reflow soldering. This process avoids insulation problems caused by solder remelting at the chip-substrate and chip-pad interfaces while meeting the 250°C application requirements, prevents damage to the chip from higher reflow temperatures, and avoids the hazards of uneven pressure distribution during capping sintering.

[0057] Second, the technical solution of the present invention fills the technical gap in the specific preparation method of a new packaging architecture in which a ceramic frame forms a hermetically sealed system inside a power semiconductor device at a 250-degree angle.

[0058] The technical solution of this invention fills the technical gap in the rapid, low-cost, and high-yield fabrication of high-performance 250-degree high-temperature hermetically sealed double-sided cooled power semiconductor devices (including heat dissipation base plates). Attached Figure Description

[0059] Figure 1 This is a flowchart of the high-temperature, high-power-density SiC power semiconductor device fabrication method provided in the embodiments of the present invention.

[0060] Figure 2 This is a structural diagram of a ceramic hermetically sealed double-sided cooled high-temperature SiC package provided in an embodiment of the present invention.

[0061] Figure 3 These are detailed step diagrams illustrating the preparation method provided in the embodiments of the present invention.

[0062] Figure 4 This is an internal appearance diagram of a ceramic hermetically sealed, double-sided cooled high-temperature SiC power semiconductor device prepared by the preparation method provided in this embodiment of the invention.

[0063] Figure 5 This is an appearance image of a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device prepared by the preparation method provided in this embodiment of the invention.

[0064] Figure 6 This is a structural block diagram of a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device fabrication system provided in an embodiment of the present invention.

[0065] Figure 7 This is a thermal simulation comparison diagram between an embodiment of the present invention and a module using a silver sintered connection heat dissipation base plate.

[0066] Figure 8 This is a high-temperature static characteristic data diagram provided in an embodiment of the present invention. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0068] like Figure 1 As shown, the method for fabricating a high-temperature, high-power-density SiC power semiconductor device provided in this embodiment of the invention includes the following steps:

[0069] S101 uses a pressure silver sintering process to sinter the power chipset onto the substrate;

[0070] S102 uses a pressure silver sintering process to sinter the pad to the power source of the chipset;

[0071] S103 uses a vacuum formic acid reflow soldering process to solder terminals, decoupling capacitors, heat sink base plate, and ceramic airtight frame assembly onto the substrate.

[0072] S104 uses bonding wires to ultrasonically bond the gate and Kelvin source of the power chip to the conductive pads on the ceramic hermetic frame boss.

[0073] S105, use Kapton tape to mask the parts that will be welded or crimped later, and to insulate and pot the other parts.

[0074] S106 uses a vacuum formic acid reflow soldering process to weld the upper and lower substrates together.

[0075] The embodiments of the present invention provide a method for sintering power chipsets onto a substrate using a silver-plated sintering process:

[0076] Nano silver paste is printed on the upper and lower substrates using a stencil. Power chipsets are then mounted on the nano silver paste, dried on a heating table, and sintered in a hot press.

[0077] The embodiments of this invention provide a method for sintering pads to the power source of the chipset using a silver-pressed sintering process:

[0078] Nano silver paste is printed onto the power source of the power chip assembly using a stencil, pads are attached to the nano silver paste, the mixture is dried on a heating table, and then sintered in a hot press.

[0079] The present invention provides a method for welding terminals, decoupling capacitors, heat sink base plates, and ceramic hermetic frame assemblies onto a substrate using a vacuum formic acid reflow soldering process.

[0080] Place solder pads or print solder paste at the terminal soldering positions, ceramic airtight frame soldering positions, and decoupling capacitor soldering positions on the substrate; place solder pads between the heat sink base plate and the substrate; and reflow solder under a vacuum formic acid nitrogen atmosphere.

[0081] This invention provides a method for using Kapton tape to mask areas that will subsequently require welding or crimping, and to insulate and pot other areas.

[0082] Use Kapton tape to mask the upper surface of the pad, the upper surface of the sealing ring on the upper side of the ceramic airtight frame, the areas of the substrate that will be soldered later, the power terminal screw interface, and the signal terminal crimp joint.

[0083] Then, the filling and sealing process is performed.

[0084] Using fluorinated dimer para-xylene as a raw material, a Parylene-HT thin film is deposited in the unmasked area by chemical vapor deposition. Subsequently, using alumina or silicon oxide as a target, an inorganic thin film is deposited on the surface of the Parylene-HT thin film layer by magnetron sputtering or atomic layer deposition, forming a composite conformal coating in the unmasked area.

[0085] Alternatively, a polyimide solution can be applied to the unmasked area and then dried at high temperature.

[0086] Alternatively, ceramics or glass can be used for potting in the unmasked areas.

[0087] The present invention provides a method for welding the upper and lower substrates together using a vacuum formic acid reflow soldering process:

[0088] Gold and tin solder sheets are applied to the upper surface of the pad, and high-temperature solder is applied to the upper surface of the sealing ring on the upper side of the ceramic airtight frame. The cap is then closed by reflow welding under a vacuum formic acid and nitrogen atmosphere.

[0089] It should be noted that the above materials have a wide range of options, some of which are listed below:

[0090] Substrate: Processes include, but are not limited to, copper / silver plating DBC, AMB, DPC, etc.

[0091] Metallization coating on substrate: including but not limited to silver plating, nickel-silver plating, nickel-gold plating, and gold plating.

[0092] Decoupling capacitors: including but not limited to ceramic capacitors, film capacitors, etc.

[0093] Ceramic airtight frame: The process includes, but is not limited to, high-temperature co-firing process and low-temperature co-firing process; the metallized area coating includes, but is not limited to, silver plating, nickel silver plating, nickel plating, nickel gold plating, gold plating, etc.; the ceramic substrate material includes, but is not limited to, alumina, aluminum nitride, silicon nitride, etc.

[0094] Power semiconductor chips include, but are not limited to, Si-based, SiC-based, and GaN-based power devices.

[0095] High-temperature solders include, but are not limited to, Pb92.5Sn5Ag2.5, Sn10Pb90, Sn5Pb95, Pb97.5Sn1.5Ag1, etc.

[0096] The pad materials include, but are not limited to, copper pads, copper diamond pads, silver diamond pads, molybdenum pads, copper-molybdenum-copper pads, etc.; their surface metallization includes, but is not limited to, silver plating, nickel-silver plating, nickel-gold plating, gold plating, etc.

[0097] Encapsulation materials include, but are not limited to: polyimide, pyrene, alumina film, modified glass, and special ceramics.

[0098] like Figure 6 As shown, the ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device fabrication system provided in this embodiment of the invention includes:

[0099] A power chipset sintering module is used to sinter power chipsets onto a substrate using a pressure silver sintering process.

[0100] The pad sintering module is used to sinter pads to the power source of the chipset using a pressure silver sintering process;

[0101] The component welding module is used to weld terminals, decoupling capacitors, heat sink base plates, and ceramic airtight frame components onto the substrate using a vacuum formic acid reflow soldering process.

[0102] The connection module is used to ultrasonically bond the gate and Kelvin source of the power chip to the conductive pads of the ceramic hermetic frame using bonding wires.

[0103] Masking modules are used to mask areas that will be welded or crimped later using Kapton tape, and to insulate and pot other areas.

[0104] The substrate welding module is used to weld the upper and lower substrates together using a vacuum formic acid reflow soldering process.

[0105] The purpose of this invention is to address the problem that traditional methods for fabricating double-sided cooled SiC power semiconductor devices are no longer suitable for the fabrication of a new 250-degree high-temperature packaging architecture for ceramic hermetically sealed double-sided cooled 250-degree high-temperature SiC power semiconductors. The invention aims to develop a rapid, low-cost, simple, and high-yield method for fabricating 250-degree high-temperature hermetically sealed double-sided cooled power semiconductor devices.

[0106] Specific examples:

[0107] A ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device packaging structure, as shown below Figure 2 As shown.

[0108] It includes a lower substrate 1, an upper substrate 2, a ceramic decoupling capacitor 3, a lower substrate terminal 11, an upper substrate terminal 21, a lower heat dissipation base plate 121, an upper heat dissipation base plate 221, a ceramic airtight frame 4, bonding wires 5, a power chipset 6, a pad 7, and an insulating potting material 8.

[0109] The substrate is made using the AMB process, the ceramic material is silicon nitride with a thickness of 0.32 mm, the copper layer has a thickness of 0.3 mm, and the surface treatment process for the copper layer is electroless nickel-gold plating (ENIG).

[0110] The ceramic airtight frame is an alumina ceramic frame prepared by high-temperature co-firing process. The upper and lower parts are brazed with 0.2mm Kovar as stress buffer layer and airtight welding ring. There is an 0.8mm thick alumina boss inside the frame. The boss has conductive pads connecting the inside and outside of the airtight cavity. The metal surface treatment process is electroless nickel-gold plating (ENIG).

[0111] The pad material is a copper-molybdenum alloy containing 70% molybdenum, and the surface treatment is electroplated nickel-silver.

[0112] The heat dissipation base plate and terminals are made of copper, and the surface treatment process is electroless nickel-gold plating (ENIG).

[0113] The module uses an AMB (Active Metal Brazed) process to fabricate upper and lower copper-clad ceramic substrates 1 and 2. The main body of the substrate is silicon nitride (Si3N4) with a thickness of 0.32 mm. Its excellent thermal conductivity (>90 W / m·K) and high mechanical strength ensure the consistency of thermal stress. The copper layer has a thickness of 0.3 mm and uses the ENIG (Electroless Nickel / Immersion Gold) process to improve the welding reliability and oxidation resistance.

[0114] The power chip assembly 6, located on the surface of the lower substrate, is electrically interconnected with the bonding wire 5 via a redistribution layer. A copper-molybdenum alloy pad 7, containing 70% molybdenum, is placed above the chip to effectively control the coefficient of thermal expansion (CTE≈8.5ppm / ℃), achieving thermomechanical matching between the chip and the upper substrate and preventing thermal fatigue failure. The pad is electroplated with nickel and silver to optimize silver sintering performance and electrical contact performance.

[0115] The module is hermetically sealed using a high-temperature co-fired alumina (Al2O3) ceramic hermetically sealed frame 4. This hermetically sealed frame, together with the upper and lower substrates, forms a hermetically sealed cavity, providing hermetical protection for the core components. A 0.8mm thick boss is provided within the frame, with metallized pads on the boss for conductive connection between the internal and external hermetically sealed cavities, ensuring electrical continuity between the internal chips and external control circuits, and providing stable high-temperature insulation performance.

[0116] The ceramic decoupling capacitor 3 is placed close to the welding area of ​​the lower substrate and connected in parallel with the main power circuit. It is mainly used to suppress voltage spikes and common-mode interference during the switching transient process. Its package position is close to the chipset to minimize parasitic inductance and improve the high-frequency operation stability of the module.

[0117] The upper and lower heat sink bases 121 and 221 are made of high thermal conductivity copper and feature columnar heat dissipation fins to enhance heat dissipation area and convective heat transfer capacity. This dual-sided cooling design breaks through the bottleneck of traditional single-sided heat dissipation, enabling bidirectional heat flow from the chip and significantly improving thermal resistance performance (typical thermal resistance <0.15K / W), thus meeting the operational requirements of high power density SiC chips.

[0118] The module potting uses a composite conformal coating potting material with high insulation strength and heat aging resistance to improve the overall high-temperature insulation performance of the module.

[0119] Example Preparation Steps Figure 3 , Figure 4 , Figure 5 As shown:

[0120] (1) Using a stencil, silver paste is printed on the DC+ metallization region 101 of the lower substrate 1, and the upper bridge power chips 61 and 62 are mounted to the DC+ metallization region 101 and sintered under pressure at 250 degrees; using a stencil, silver paste is printed on the AC metallization region 201 of the upper substrate, and the lower bridge power chips 63 and 64 are mounted to the AC metallization region 201 and sintered under pressure at 250 degrees.

[0121] (2) Print silver paste on the power source electrodes of power chips 61, 62, 63, and 64, and attach pads 71, 72, 73, and 74 to the power source electrodes of power chips 61, 62, 63, and 64 respectively, and sinter under pressure at 250 degrees.

[0122] (3) Attach solder pads between the lower substrate 1 and the lower heat sink 121. Attach solder pads between the DC+ power terminal 112 and the DC+ metallized region 101 of the lower substrate, between the DC- power terminal 111 and the DC- metallized region 102 of the lower substrate, between the upper bridge arm Kelvin source signal terminal 113 and the upper bridge arm Kelvin source metallized region 103 of the lower substrate, between the upper bridge arm gate signal terminal 112 and the upper bridge arm gate metallized region 104 of the lower substrate, and between the upper bridge arm Kelvin drain terminal 115 and the DC+ metallized region of the lower substrate. Attach solder pads between the upper bridge arm ceramic hermetically sealed frame 41 and the metallized regions 101, 102, and 103 of the lower substrate. Attach solder pads between the decoupling capacitor 3 and the DC+ metallized regions 101 and DC- metallized regions 102 of the lower substrate.

[0123] Solder pads are mounted between the upper substrate 2 and the upper heat sink 221. Solder pads are mounted between the AC power terminal 211 and the AC metallization region 201 of the upper substrate, between the lower bridge arm Kelvin source signal terminal 212 and the lower bridge arm Kelvin source metallization region 203 of the upper substrate, between the lower bridge arm gate signal terminal 213 and the lower bridge arm gate metallization region 202 of the upper substrate, and between the lower bridge arm Kelvin drain terminal 214 and the lower substrate AC metallization region 201. Solder pads are mounted between the lower bridge arm ceramic hermetic frame 42 and the metallization regions 201, 202, and 203 of the upper substrate.

[0124] The aforementioned solder pads are made of lead-tin-silver (Pb92.5Sn5Ag2.5) with a thickness of 0.1mm, and are reflow soldered at 340 degrees Celsius in a vacuum formic acid furnace.

[0125] (4) Use a cluster of 1mil diameter gold wires to ultrasonically bond the gates and Kelvin sources of the upper bridge arm power chip groups 61 and 62 to the corresponding conductive pad groups 411 of the upper bridge arm ceramic airtight frame boss; use a cluster of 1mil diameter gold wires to ultrasonically bond the gates and Kelvin sources of the lower bridge arm power chip groups 63 and 64 to the corresponding conductive pad groups 421 of the lower bridge arm ceramic airtight frame boss.

[0126] (5) Use Kapton tape to mask part of the signal terminals 113, 114, 115 and power terminals 111, 112 of the lower substrate; mask part of the DC-metallized area 102 of the lower substrate; mask the upper surface of the upper sealing ring 412 of the upper bridge arm ceramic airtight frame 41; and mask the upper surfaces of the upper bridge arm pads 71 ​​and 72.

[0127] Symmetrically, Kapton tape is used to mask a portion of the signal terminals 212, 213, 214 and power terminals 211 on the upper substrate; a portion of the AC metallization region 201 on the upper substrate is masked; the upper surface of the upper sealing ring 422 of the lower bridge arm ceramic hermetic frame 42 is masked; and the upper surfaces of the upper bridge arm pads 73 and 74 are masked.

[0128] A 15µm thick layer of Parylene-HT was deposited in the unmasked area using CVD, followed by a 90nm thick layer of alumina film deposited on it using ALD, forming a high-temperature resistant and highly insulating composite conformal coating.

[0129] (6) A 0.1mm thick lead-tin-silver (Pb92.5Sn5Ag2.5) solder pad is attached between the upper surface of the upper bridge arm ceramic airtight frame 41 of the lower substrate and the AC metallization area 201 of the upper substrate for airtight sealing; a 0.1mm thick gold-tin solder pad (Au80Sn20) is attached between the upper surface of the upper bridge arm pads 71 ​​and 72 of the lower substrate and the AC metallization area 201 of the upper substrate for thermal and electrical connection.

[0130] A 0.1mm thick lead-tin-silver (Pb92.5Sn5Ag2.5) solder pad is attached between the upper surface of the upper sealing ring 422 of the lower bridge arm ceramic hermetic frame 42 of the upper substrate and the DC-metallized area 102 of the lower substrate for hermetic sealing; a 0.1mm thick gold-tin solder pad (Au80Sn20) is attached between the upper surface of the lower bridge arm pads 73 and 74 of the upper substrate and the DC-metallized area 102 of the lower substrate for thermal and electrical connection.

[0131] Subsequently, the ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device (including heat dissipation base plate) was fabricated by refluxing at 340 degrees Celsius in a vacuum formic acid furnace.

[0132] In existing safety helmet technologies, traditional structures mostly provide only physical protection and lack intelligent sensing capabilities for the working environment and personnel status, making it difficult to meet the comprehensive monitoring needs for operational safety in high-risk industries such as mining, power, and firefighting. Furthermore, some smart helmets with sensing capabilities suffer from scattered sensor deployments, complex module connections, poor data synchronization performance, and instability under extreme conditions such as high temperature, high humidity, and strong electromagnetic interference. Communication modules often employ single-channel communication, which is prone to data transmission interruptions and significant latency in underground or confined spaces, affecting the real-time nature of emergency response.

[0133] To address the aforementioned technical issues, this invention employs a ring-shaped support frame 2 as a unified carrier for the functional modules. The ring structure provides full circumferential support for the cap's internal cavity, while simultaneously enabling standardized positioning and fixation of the main control board, temperature and humidity sensor, attitude sensor, gas detection sensor, and body temperature sensor. The support frame is quickly assembled to the main housing 1 via snap-fit ​​10, and modules are secured with screws to ensure connection stability under vibration and impact conditions. This structure simplifies wiring and layout between subsystems, improves system modularity and assembly efficiency, and avoids signal anomalies caused by loosening or misalignment.

[0134] The main control board 3 utilizes the MTK6761 chip platform, integrating a quad-core 64-bit Cortex-A53 architecture with a main frequency of up to 2.0GHz, providing strong edge computing capabilities. Without relying on external servers, the main control board can perform local parsing and preliminary anomaly detection of sensor data, reducing communication load and response latency. The processor embeds an Imagic ISP and a PowerVR GE8320 graphics core, adapting to high-definition video and image processing applications, providing hardware support for front-end visual inspection or subsequent AR expansion. The system I / O is rich, supporting I... 2 Interfaces such as C, UART, and USB facilitate standardized access to different sensors or execution modules.

[0135] To address the issues of centralized power management and poor battery life in traditional safety helmets, this invention features a connector 11 on the right side of the main control board 3, which interfaces with the power management module 5. The power module supports dual-cell lithium battery series connection and a high-efficiency boost / buck conversion design, integrating overcurrent, overtemperature, and undervoltage protection circuits. Unified power supply and management via the connector avoids exposed cables and voltage drop issues caused by long-distance transmission. Combined with the main control board's low-power scheduling logic, dynamic switching between standby and sensing states can be achieved, improving battery life and adapting to the work cycle requirements of different shifts.

[0136] To address the challenge of ensuring stable communication links, this solution utilizes the MT6761's built-in dual-SIM LTE communication module and Wi-Fi 5 wireless connectivity. The communication module 7 is securely connected to the left side of the main control board via screws and integrated with the processing core for communication control logic. This dual-mode concurrent structure dynamically switches between preferred links based on signal strength, ensuring continuous communication in complex environments such as mines and tunnels. It also supports Bluetooth 5.0, expanding short-range device interconnection capabilities for modules like intercoms and location markers, thus enhancing the overall system's information coverage.

[0137] Furthermore, to achieve comprehensive perception of the multi-dimensional status of workers, this invention utilizes five precisely deployed sensors to form a spatial collaborative perception network within the helmet. Specifically, a body temperature sensor 9 is positioned at the top of the support frame, close to the forehead, accurately reflecting the worker's physiological state; a posture sensor 8 is located on the left side to collect information on tilting, falls, and other events; a gas sensor 4 is located on the right side to detect local toxic gas leaks or oxygen deficiency; and a temperature and humidity sensor 6 is located at the bottom to monitor the environmental heat and humidity load. All sensors are connected via I... 2 The device connects to the main control board via C or SPI and utilizes the main control board's ADC or DMA channels to perform periodic polling sampling. Through modular installation and centralized data management, it solves the problems of numerous monitoring blind spots and uncoordinated responses in traditional equipment, thereby improving the overall accuracy of security response and system robustness.

[0138] The relevant evidence for the technical effects obtained by the embodiments of the present invention is as follows:

[0139] Figure 7 The results demonstrate the junction temperatures of power chips when the substrate and heat sink are connected using high-temperature solder pads and nano-silver sintering. When using low-cost lead-tin-silver solder pads to connect the substrate and heat sink interface, the highest junction temperature is only 2.9 degrees higher than that using silver sintering, while the cost and process difficulty are far lower than large-area silver sintering.

[0140] Figure 8 The high-temperature static characteristics of a ceramic hermetically sealed, double-sided cooled 250°C SiC power semiconductor module prepared using the method described in this embodiment are demonstrated. The output characteristics are normal between 25 and 250°C, and the insulation performance is good at 250°C, meaning the module prepared by this method can be used in high-temperature applications at 250°C.

[0141] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device, characterized in that, The preparation method includes the following steps: Step 1: Using a ceramic upper substrate and lower substrate that are both metallized and used to carry power stage current, a pressure silver sintering process is used to sinter the power chip assembly onto the metal layers of the upper substrate and lower substrate respectively; the power chip includes Si-based, SiC-based, GaN-based, diamond-based or gallium oxide-based chips. Step 2: Using a pressure silver sintering process, the metal pad is sintered onto the power source of the power chipset; Step 3: Using a decoupling capacitor, terminals, a heat dissipation base plate, and a ceramic hermetically sealed frame assembly with internal bosses, the bosses are provided with conductive pads connecting the inside and outside of the hermetically sealed frame assembly; using a reflow soldering process, the decoupling capacitor, the heat dissipation base plate, the ceramic hermetically sealed frame assembly, and the terminals are soldered to the substrate; wherein, the heat dissipation base plate is soldered to the outside of the substrate. Step 4: Using bonding wires, the gate and Kelvin source of the power chip are connected to the conductive pads of the ceramic hermetic frame assembly via ultrasonic bonding. Step 5: Use Kapton tape to mask the upper surface of the pad, the upper surface of the upper sealing ring of the ceramic airtight frame assembly, the area of ​​the substrate to be subsequently soldered, the power terminal screw interface, and the signal terminal crimp connector; then perform insulating potting on the unmasked areas, using any of the following processes: (1) Using fluorinated dimer para-xylene as raw material, Parylene-HT thin film is deposited in the unmasked area by chemical vapor deposition; then, using alumina or silicon oxide as target material, inorganic thin film is deposited on the surface of the Parylene-HT thin film layer by magnetron sputtering or atomic layer deposition to form a composite conformal coating in the unmasked area. (2) A coating process is used to coat the unmasked area with polyimide solution and then dry it at high temperature; (3) Use ceramic or glass materials to pot the unmasked areas; Step 6: Remove the Kapton tape mask and use a reflow soldering process to weld the inner metal layers of the upper and lower substrates to the upper surface of the pad and the upper sealing ring of the ceramic airtight frame assembly, so that the ceramic airtight frame assembly, the upper substrate, and the lower substrate together form an airtight system, and the power chip group achieves electrothermal interconnection with the metal layers of the upper and lower substrates through the pad.

2. The method for fabricating a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device according to claim 1, characterized in that, A decoupling capacitor is disposed in the area between the lower substrate and the power chipset, and is connected in parallel with the DC input terminal of the power chip to suppress switching spike voltage and common-mode interference. The upper substrate terminal and the lower substrate terminal are respectively connected to the metallization layer of the upper substrate and the lower substrate, and are used for the introduction and extraction of external current of the module.

3. The method for fabricating a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device according to claim 1, characterized in that, The upper heat dissipation base plate and the lower heat dissipation base plate are respectively disposed on the outer side of the upper substrate and the lower substrate, and exchange heat with the cooling medium; The module is covered with potting insulating material on all surfaces to enhance its insulation performance and environmental adaptability.

4. The method for fabricating a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device as described in claim 1, characterized in that, Place solder pads or print solder paste at the terminal soldering positions, ceramic airtight frame soldering positions, and decoupling capacitor soldering positions on the substrate; place solder pads between the heat sink base plate and the substrate; and reflow solder under a vacuum formic acid nitrogen atmosphere.

5. The method for fabricating a ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device as described in claim 1, characterized in that, The upper and lower substrates are welded together using a vacuum formic acid reflow soldering process. High-temperature solder is applied to the upper surface of the pad and to the upper surface of the sealing ring on the upper side of the ceramic airtight frame. The cap is then closed by reflow welding under a vacuum formic acid nitrogen atmosphere.

6. A ceramic hermetically sealed double-sided cooled high-temperature SiC power semiconductor device fabrication system implementing the fabrication method according to any one of claims 1-5, characterized in that, The ceramic hermetic double-sided cooling high-temperature SiC power semiconductor device fabrication system includes: A power chipset sintering module is used to sinter power chipsets onto a substrate using a pressure silver sintering process. The pad sintering module is used to sinter pads to the power source of the chipset using a pressure silver sintering process; The component welding module is used to weld terminals, decoupling capacitors, heat sink base plates, and ceramic airtight frame components onto the substrate using a vacuum formic acid reflow soldering process. The connection module is used to ultrasonically bond the gate and Kelvin source of the power chip to the conductive pads of the ceramic hermetic frame using bonding wires. Masking modules are used to mask areas that will be welded or crimped later using Kapton tape, and to insulate and pot other areas. The substrate welding module is used to weld the upper and lower substrates together using a vacuum formic acid reflow soldering process.

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