Thermal impedance monitoring process for power modules

Abstract

A thermal impedance monitoring process for a power module of a power converter for converting a DC current to an AC current, or converting an AC circuit to a DC current, where a semiconductor dissipates asymmetric losses between two half cycles of an AC frequency f of the AC current, said power module comprising at least a semiconductor die, a semiconductor die is attached to a stack of materials of layers for heat dissipation and / or electrical connection thereof, the process comprising: sampling and measuring a signal related to a junction temperature Tj of the semiconductor die at a frequency higher than twice the AC frequency of the AC current, calculating a duration [Delta] t = tTjmax-tTjmin between a moment tTjmax at which the junction temperature of the semiconductor die is at a maximum value and a moment tTjmin at which the junction temperature is at a minimum value in one cycle of the AC current, and storing the duration [Delta] t in a memory, repeating the step of sampling and measuring said signal and the step of calculating said duration at different times tx = t0 to tm during the operating life of the power module to provide a series of durations [Delta] t0 to [Delta] tm, and comparing the values of said durations [Delta] t0 to [Delta] tm for monitoring the evolution of said duration [Delta] t, and determining the evolution of the degradation of the thermal impedance of the power module.

Description

Technical Field

[0001] The present disclosure relates to the field of protection of power semiconductor modules from failure due to overheating, in particular due to thermal interface degradation, and maintenance of equipment using such modules. Background Art

[0002] Thermal interface degradation in power modules occurs due to delamination and voids in any substructure between the semiconductor die and the heat sink. This degradation increases the temperature of the semiconductor die, potentially leading to an unsafe temperature operating region. High temperatures can result in semiconductor breakdown and power module failure. Therefore, monitoring the thermal interface is important to maintain the power module within a safe temperature range and guide maintenance and replacement of the power module.

[0003] The degradation phenomenon is caused by Figure 1 The CTE mismatch and temperature transformation between different materials of the power module stack shown are caused, and the power module stack includes at least: a semiconductor tube core 3 (for example, silicon), a tube core attachment part 4 (for example, solder), a conductive layer 6 (for example, copper), an electrical insulator layer 7 and a heat sink 8 (for example, aluminum).

[0004] The power module 1 may further comprise elements such as a heat conducting layer 9 (e.g. copper), a bonding layer 10 (e.g. solder), a substrate 11 (e.g. copper), and a thermal interface 12 (e.g. graphite or thermal paste). In the case of double-sided cooling, a symmetrical material stack is also conceivable, in which the stack described above is repeated on the top side 5 of the semiconductor die 3.

[0005] Figure 2 It shows a crack 2 which may occur in a layer such as layer 4. Such a crack would lead to a reduction in the heat conduction of the layer.

[0006] In the literature Broeck et al., "In situ thermal impedance spectroscopy of Powerelectronic modules for localized degradation identification", PCIM Europe 2019; International Exhibition on Power Electronics, Intelligent Movement, Renewable Energy and Energy Management, May 7-9, 2019, Nuremberg, Germany; VDE ISBN: 978-3-8007-4938-6, a method of extracting the thermal impedance frequency response function of a power module without interrupting normal converter operation is disclosed. A small sinusoidal signal loss excitation is applied to the power device, the temperature response of the power device is extracted, and the two signals correlate, thereby estimating the thermal impedance at the excitation frequency. The method relies on phase information rather than amplitude and is therefore insensitive to measurement errors of loss and / or temperature. This requires, for example, a small signal loss excitation method that will affect torque pulsation for motor driver applications.

[0007] In the paper Polom et al., "Real-Time, In Situ Degradation Monitoring in Power Semiconductor Converters," 2019 IEEE Applied Power Electronics Conference and Expo (APEC), March 17-21, 2019, IEEE, DOI: 10.1109 / APEC.2019.872182, heat injection with certain frequency components (sine and square waves) is used to measure the spatiotemporal dynamic thermal response of semiconductor components as they degrade. The temperature of the semiconductor die is estimated using a TSEP (thermal sensitive electrical parameter), and a frequency response function (FRF) is calculated for each system identification experiment. The FRF segments are combined and a functional model is used to interpret the thermal interface degradation.

[0008] Xiang et al., "Condition Monitoring Power Module Solder Fatigue Using Inverter Harmonic Identification," IEEE Transactions on Power Electronics, Vol. 27, No. 1, January 2012, pp. 235-247, DOI: 10.1109 / TPEL.2011.2160988, describes a method for monitoring solder fatigue in inverters using IGBT power modules to detect changes in output harmonics. The method demonstrates that low-order harmonics caused by non-ideal switching are affected by device junction temperature, which in turn depends on module soldering conditions. This method lacks accuracy; therefore, the inverter controller is configured to induce harmonic resonance at a given frequency.

[0009] The JESD51-14 standard describes a method for measuring 'transient thermal resistance'. This method consists of measuring the junction temperature (cooling curve), preferably after the heating power is turned off. Although not recommended, in principle, a heating curve can also be used if there is a constant heating power during the heating pulse. In the first case, the measurement forces the power module to be turned off after operating under known thermal steady-state conditions. In both cases, the power loss should be known, which is difficult to estimate during online operation (in field applications).

[0010] Thermal impedance measurement is a powerful transient thermal response technique that can provide information about the degradation of different interfaces of the power module. This technique typically consists of the following items:

[0011] First, a starting steady-state thermal condition is applied to the power module using semiconductor switches as active devices. The starting condition is either a zero power condition or a condition where a known and measured constant power is dissipated in the semiconductor.

[0012] Second, a controlled power step increase (in case the starting condition is a zero power condition) or a power step decrease (in case the starting condition is a constant power condition) is applied and the evolution of the semiconductor temperature is recorded until a new steady-state thermal condition is reached.

[0013] Finally, the recorded temperature transient behavior is described by using an equivalent Foster and Kaul network, which represents the thermal structure of the power module through several RC elements. The fitting of the temperature transient using the Foster equation allows the extraction of the resistance and capacitance of the different parts of the power module, which provides information on the evolution of the thermal resistance and capacitance.

[0014] As discussed in Gerd Busse, “Lockin-Thermography: Principles,” NDE—Applications and Trends, January 2014 Conference: Quantitative Infrared Thermography 2014, DOI: 10.21611 / qirt.2014.e, lock-in thermography is a well-proven commercial technology for detecting material and system damage (e.g., delamination cracks, voids, etc. in composite materials).

[0015] Lock-in thermography uses a process in which a material or system to be thermally analyzed is stimulated with a non-steady-state signal (e.g., a pulsed signal or a sinusoidal signal) at a specific frequency (correlated with the material thickness or damage depth), for example using an infrared radiation source such as a set of halogen lamps. An image of the transient temperature response of the system / material is recorded, and specific software and algorithms are used to calculate the phase and amplitude between the response and the stimulus, thereby generating a phase image and an amplitude image. These techniques are used under thermally steady-state conditions.

[0016] Problems associated with prior art methods regarding thermal impedance monitoring are:

[0017] The power dissipated in the semiconductor must be known, i.e., must be measured or estimated. This can be a difficult task in cases where the semiconductor is integrated into a power converter;

[0018] - With the above-mentioned thermal measurement techniques (wherein the measurements are performed under steady-state thermal conditions), no information can be obtained about which layers of the power module stack are degraded. Summary of the Invention

[0019] The present disclosure proposes a measurement method using a phase lock technique in transient rather than steady-state conditions.

[0020] More precisely, the present disclosure proposes a thermal impedance monitoring process for a power module of a power converter for converting DC current into AC current or vice versa, wherein the semiconductor dissipates asymmetrical losses between two half-cycles of the AC frequency f of the AC current, the power module comprising at least a semiconductor die attached to a material stack of layers for heat dissipation and / or electrical connection thereof, the process comprising:

[0021] - sampling and measuring a signal related to the junction temperature Tj of the semiconductor die at a frequency that is 10 times higher than the AC frequency of the AC current,

[0022] - calculating a duration Δt=tTjmax-tTjmin between a time tTjmax at which the junction temperature of the semiconductor die is at a maximum value and a time tTjmin at which the junction temperature is at a minimum value in one cycle of the AC current, and storing the duration Δt in a memory,

[0023] - During the working life of the power module, at different times t x =t0 to t p The steps of sampling and measuring the signal and calculating the duration are repeated to provide a series of durations Δt t0 to Δt tp , and the duration Δt tp Value and Δt t0 Comparison is made for monitoring the duration Δt x to determine the evolution of the degradation of the thermal impedance of the power module.

[0024] This process may include measuring the AC frequency and the storage duration Δt tx and AC frequency f fund A combination of values.

[0025] The process may comprise modifying the AC frequency during dedicated operating periods of the converter to provide several different AC frequencies f m =f1,f2,…,f n , each AC frequency allows detecting the thermal impedance of a specific layer of the stack, repeating the sampling and measurement steps and calculating the duration Δt corresponding to these different AC frequencies txf1 , Δt txf2 ,……,Δt txfn Steps,

[0026] - repeating said steps of sampling and measuring said signal and calculating said duration during the operating life of the power module to provide a series of Δt0 to Δt1 for each of said different AC frequencies x value, and compare it to the AC frequency f m =f1,f2,…,f n The Δt at each of txfm value for monitoring Δt for each of the AC frequencies txfm to determine the evolution of the degradation of the thermal impedance of the specific layer.

[0027] The process may include measuring the time difference Δtmin between two consecutive minimum values of the junction temperature, and calculating the AC frequency as f=1 / Δtmin.

[0028] The signal related to the junction temperature Tj may be a temperature-sensitive electrical parameter of the semiconductor.

[0029] In this case, the signal may be an uncalibrated temperature-sensitive electrical parameter of the semiconductor.

[0030] The AC frequency can be lower than where l die is the thickness of the die, and D die is the diffusion coefficient of the die.

[0031] The AC frequency may be lower than 2 kHz.

[0032] The AC frequency may be below 1 kHz.

[0033] The AC frequency may be the fundamental frequency of the power supply to the converter or the fundamental output frequency f of the converter. fund .

[0034] The present disclosure also relates to a converter, comprising a sensor device on a power semiconductor switch die of the converter for sensing the temperature of the power semiconductor switch die, an analog-to-digital converter device, a sampling device, and a processor, the processor being provided with a memory for storing and executing software configured to perform the thermal impedance monitoring process described above. In particular, the sensor device can be designed to sense a temperature-sensitive electrical parameter of the die. The present disclosure also provides software including instructions for performing the thermal impedance monitoring process described above.

[0035] A detailed description of exemplary embodiments of the present disclosure will be discussed below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] [ Figure 1 ]

[0037] Figure 1 is an example of a conventional layer stack for a power module.

[0038] [ Figure 2 ]

[0039] Figure 2 This is a picture of a cracked solder layer.

[0040] [ Figure 3 ]

[0041] Figure 3 is a prior art graph of the surface temperature response phase shift versus defect depth.

[0042] [ Figure 4 ]

[0043] Figure 4 is an example of a Kaul network of stacked power modules.

[0044] [ Figure 5 ]

[0045] Figure 5 is a first Bode plot of a first example of a stacked defective layer.

[0046] [ Figure 6 ]

[0047] Figure 6 is a second Bode plot of a second example of a stacked defective layer.

[0048] [ Figure 7 ]

[0049] Figure 7 is a third Bode plot of a third example of a stacked defective layer.

[0050] [ Figure 8 ]

[0051] Figure 8 yes Figure 5 Extended Bode plot of the first example of a stacked defect layer.

[0052] [ Figure 9 ]

[0053] Figure 9 is a simplified schematic diagram of an example converter with a processor.

[0054] [ Figure 10A ]

[0055] Figure 10A is a plot of loss and junction temperature versus time for the original and degraded stacks.

[0056] [ Figure 10B ]

[0057] Figure 10B is a plot of loss and junction temperature versus time for the original and degraded stacks.

[0058] [ Figure 11 ]

[0059] Figure 11 Loss waveforms for different modulation types in a DC / AC converter according to different controls are shown.

[0060] [ Figure 12 ]

[0061] Figure 12 A graph of the equivalent phase shift versus fundamental frequency for the degradation of different layers is shown.

[0062] [ Figure 13A

[0063] Figure 13A Shows the process steps of this process.

[0064] Figure 13B

[0065] Figure 13B Shows the process steps of this process.

[0066] Figure 13C

[0067] Figure 13C Shows the process steps of this process. Detailed implementation mode

[0068] To characterize the behavior of a power module, the thermowave theory predicts that the surface of a homogeneous infinite material half-space subjected to a thermal excitation P0 = P0(1 + cos(ωt)) / 2 Due to the wave nature of the excitation, the heat propagation in the material can be analyzed according to wave theory, where a defect or interface located at a distance d below the material surface can be modeled by the reflection coefficient R (0 < R < 1) for thermowaves, and compared with the case of a semi-infinite body, it will change the phase of the surface heat response. In the case of the presence of a void or defect at the interface, the reflection coefficient is a function of the material properties and the contact resistance between different materials. The reflection coefficient is also frequency-dependent. As described in the literature Rigert "Induktions-Lockin-Thermografie: ein neues Verfahren zur Prüfung (A new method for non-destructive testing)" http: / / dx.doi.org / 10.18419 / opus-1734, Figure 3 The curves in show the influence of a defect with an intensity R at a depth d on the phase shift of the surface temperature response. The figure shows the influence of the defect depth d (normalized with the material parameter μ) and the reflection coefficient R (R = 0 => no defect (perfect transmission); R = 1 => strong defect (perfect reflection)).

[0069] It can be seen that when the defect is located at d < 1.55 μm and has a reflection coefficient R > 0.4, the phase shift of the surface temperature response changes from the semi-infinite body value of 45° to a lower value depending on R and the defect position.

[0070] Therefore, Figure 3 Shows the basic principle of lock-in thermography to characterize defects and interfaces in materials, including devices with module stacks.

[0071] ​​​​​Importantly, the value of μ is frequency-dependent: for defects located further away in the material, greater sensitivity is achieved when using lower excitation frequencies. Thus, by varying the excitation frequency, information can be obtained about the interface (degradation) of different layer stacks or interfaces.

[0072] While this simple model provides a good guide to using thermal waves to detect damage, a power semiconductor stack cannot be modeled as a semi-infinite body due to the different thermal properties of each layer of the stack. To more accurately analyze the system, the ID electrical equivalent of the thermal model can be used, for which the frequency response function can be analyzed.

[0073] Thermal Impedance: Electrical Equivalent Model:

[0074] Because heat conduction and electron conduction are both physical processes modeled by the same phenomenon (diffusion), the thermal impedance of semiconductor modules can be modeled by analogy with the scaled heat conduction and telegraph equations. Therefore, the electrical equivalent of the thermal system can be derived. The resistance and capacitance of the electrical equivalent are defined by analogy with the thermal resistance Rth and capacitance Cth using the following equations:

[0075]

[0076] Where 1 is the thickness;

[0077] A is the cross-sectional area;

[0078] λ is the thermal conductivity,

[0079]

[0080] where c is the specific heat capacity [J / g];

[0081] V is the volume [m 3 ];

[0082] ρ is the density [g / m 3 ].

[0083] In the case of a simple model of a power module consisting of a stack of different materials, each layer will represent a thermal resistance and a thermal capacitance. Thus, an electrical network called a Kaul network can represent the thermal system of a 5-layer stack, as Figure 4 As shown. loss Is from Figure 1 The heat flux of the semiconductor die 5 corresponds to the losses dissipated on the semiconductor die (the electrical equivalent is a current source), C th and R th are the equivalent capacitance and equivalent resistance of each layer starting from the tube core layer 3 and the heat dissipation layer 5, and Tamb is the ambient heat dissipation temperature.

[0084] Figure 4The total thermal impedance of the network can be calculated using the following equation, where s is the Laplace operator:

[0085] Z(s)

[0086]

[0087] For the case of a degraded layer, the new (increased) resistance R can be calculated using the percentage of voids f as described in the following equation: th,v Since the amount of material does not change, the heat capacity Cth remains unchanged:

[0088]

[0089] For example, in Figure 1 In the case of the described 9-layer stack and the material data in Table 1 below:

[0090] {Table 1}

[0091]

[0092] Thermal impedance can be plotted in a Bode plot, where the magnitude and phase are plotted as a function of the frequency of a sinusoidal type excitation. Figures 5 to 7 In the curve of Figure 1 A comparison is made between the original module (i.e., the non-degraded module) and the degraded module.

[0093] Figure 5 Layer 4 and layer 10 have 40% of the gap, according to Figure 1 Bode plot of a stack of . Figure 6 Layer 4 has 40% voids, according to Figure 1 Bode plot of a stack of . Figure 7 The layer 10 has 40% of the voids, according to Figure 1 Bode plots of a stack of 100 nm and 100 nm, respectively. These plots show that the magnitude and phase of the thermal impedance are modified due to degradation.

[0094] Figure 5 Curves 32 and 33, Figure 6 Curves 36, 37 and Figure 7 The curves 40, 41 represent the phase difference between the temperature variation of the die for the original layer represented by the dotted line and the degraded layer represented by the solid line. Figure 5 Curves 30 and 31, Figure 6 Curves 34, 35 and Figure 7 Curves 38 and 39 represent the magnitude of the temperature change of the die for the original layer represented by the dotted line and the degraded layer represented by the solid line.

[0095] like Figure 5 and Figure 6As shown, the effect of the degradation of the layer 4 located close to the excitation source can be best detected by the phase shift of the curve 33 relative to the curve 32 at about 100 Hz excitation, while Figure 7 It can be seen that a relatively lower excitation frequency of about 1 Hz to 10 Hz is required to detect the frequency shift between curves 40 and 41 corresponding to damage in layer 10 located farther away from the heat source. Note that no phase shift change is observed at 100 Hz when damage is introduced into layer 10. Therefore, by changing the excitation frequency, information about which layer is damaged can be obtained.

[0096] Power semiconductor die losses:

[0097] The previous section describes the thermal response of the system to sinusoidal excitation. In real application situations, the power dissipation does not necessarily follow a sinusoidal behavior. The purpose of this section is to describe the necessary conditions for the semiconductor operating point that produces a suitable thermal response of the system so that information about layer degradation can be obtained. In order to support loss distribution requirements, such as Figure 8 As in the example, plotted over a larger frequency range Figure 6 Bode plot of the signal with an interval of 1 Hz to 1 MHz.

[0098] In this example, Figure 8 The following information is shown:

[0099] - The magnitude of the Bode plot gives essentially the same information as the thermal impedance plot;

[0100] - Phase Information It is shown that the curves 42, 44 of the undegraded case and the curves 44, 45 of the degraded case merge at f>1 kHz. Therefore, no information about the degradation can be obtained by analyzing the phase response of the system above this frequency.

[0101] The reason why the degraded and non-degraded cases cannot be separated at f>1 kHz is because, in the high frequency range, the thermal impedance of the heat source (silicon die) acts as a filter to the electrical excitation. When noting that the thermal response time scale of the die is τ d =Rth d Cth d This is easy to understand when the magnitude of is . Using the following definition:

[0102]

[0103] In diffusion theory, (unit: ) is called the diffusion coefficient. is the heat pulse traveling through the die thickness l die The time scale required.

[0104] Using the values for Material 3 from Table 1, we find Use tube core thickness l d =0.14mm; τ d =4.01 10 -4 s. Therefore, the thermal system response bandwidth is limited by This is consistent with the restriction of Figure 8 The 1kHz value found in the Bode plot is of the same order of magnitude.

[0105] Therefore, the potential implication of the applicability of the present invention is that the electrical excitation frequency of interest should be significantly lower than That is, it is preferably lower than 2 kHz, and more preferably lower than 1 kHz.

[0106] Advantageously for the present invention, typical signal modulation strategies (such as PWM modulation in converters) typically operate at frequencies above 1 kHz (such as 5 kHz or 10 kHz). Therefore, the thermal system response will be weak in this frequency range and the temperature oscillations due to the PWM frequency will be weak, as in Figure 8 As can be seen from the amplitude of the Bode plot of <-60 dB. Therefore, the thermal system is advantageously not affected by the PWM excitation. For the use of the model described in the previous section, this proves that the losses can be averaged over the PWM period.

[0107] Advantageously for the present invention, the typical excitation frequency may be limited by load impedance, load requirements, or external control of the system so that the system is typically excited within the frequency range of interest, i.e., at frequencies below 1 kHz, such as 50 Hz, 60 Hz, 100 Hz, 400 Hz, or 1 Hz.

[0108] Another potential implication of this analysis is that low-frequency electrical excitation signals should not be used below τ d The power value decreases from the maximum power value to the zero power value within the time interval.

[0109] Therefore, to summarize the power semiconductor loss requirements within the present invention: the power semiconductor die loss waveform depends on the application in which the power module or system is installed.

[0110] The present invention relates to the case of DC / AC or AC / DC power converter topologies and to the case where the losses are low-frequency periodic pulsating waves with the following characteristics:

[0111] a. Maximum pulse duration of half a period of the fundamental frequency of the AC current, so that there is a zero-loss time interval.

[0112] and

[0113] b. At least one local maximum within a pulse or an asymmetric loss dissipation between two half-cycles.

[0114] and

[0115] c. The time difference between the last maximum value and the zero loss time is greater than where l d is the thickness of the semiconductor chip, D d is the thermal diffusivity of the semiconductor chip. This means that the low frequency of the modulation loss is lower than where ldie is the die thickness, and Ddie is the diffusion coefficient of the die.

[0116] As an example, for condition c, the semiconductor chip is a semiconductor chip with a thickness of l die =100μm silicon chip, the thermal diffusion coefficient of silicon is D die =4.89 10 -4 m 2 / s, so f die =4.89kHz, and τ die =205μs.

[0117] Figure 9 An example of a DC / AC power topology is shown in FIG, where a DC power source 51 is used to construct a three-phase AC power source 52 using a power semiconductor switch 1. The DC / AC power converter has a three-phase configuration supplied by a DC bus voltage. The semiconductor die can be any IGBT, diode, MOSFET, MISFET, and any arrangement of power converter topologies. In the following example, the semiconductor die of interest in the power module is placed in one leg at the high-side position.

[0118] In motor control applications, for a given load current, bus voltage, and during switching and conduction events, switching and conduction losses of semiconductor die 50 occur in normal operation of the power module.

[0119] The semiconductor die losses in power modules during DC / AC or DC / AC operation are proportional to the following operating point-dependent variables: cond Current, switching current I sw , switching voltage V sw , switching frequency f sw , junction temperature Tj, duty cycle modulation strategy / PWM technology.

[0120] In such applications, typically, periodic pulse loss waveforms in DC / AC or AC / DC applications are generated at a fundamental frequency, such as the grid frequency of 50 Hz or the motor rotation control frequency of 1 Hz to 2 kHz. In any strategy, losses in the semiconductor are only generated during the time corresponding to the first half-cycle of the fundamental frequency, and the semiconductor does not generate any losses during the second half-cycle of the fundamental frequency.

[0121] Consider that the power converter produces a sinusoidal current waveform at a fundamental frequency of 100 Hz on the output of phase ABC, and produces a chopped voltage waveform operating at a switching frequency of 20 kHz.

[0122] Figure 10A and 10B Represents the junction temperature and losses for pristine and degraded power modules at a fundamental AC frequency of 100 Hz. Figure 10A is an overall view of the power and junction temperature waves with respect to time, Figure 10B is an enlarged view of one loss cycle that also includes a measurement of the die temperature Tj duration. In this example, the Figure 10A The loss wave 70 in has only a positive sinusoidal shape. In other words, the loss at the fundamental frequency f f The inner value follows a sinusoidal shape between 0° and 180° (0 and π), and has a null value between 180° and 360° (π and 2π):

[0123]

[0124] Use thermal impedance to calculate Figure 10A The temperature response Tj of the die 71, 72 in the basic cycle has a minimum 71a, 72a and a maximum 71b, 72b. When the time between the minimum and maximum temperature points is measured, an indication of module degradation is given. In the example showing a single loss cycle Figure 10B It can be seen that the 100Hz AC current is Figure 1 The degraded power module with 40% voids in layer 4 has a duration Δt=td that is longer than the duration Δt=tp of the original power module. This can be explained by Figure 6 This can be explained by looking at the Bode plot of FIG. 1 , which shows a larger absolute phase angle of the degraded thermal impedance compared to the original thermal impedance at 100 Hz.

[0125] The important point is that, because a sudden power change will produce a bend in the temperature response, the start of the pulse corresponding to tTjmin can be identified by examining the temperature response alone. Therefore, it is advantageous that the information Δt=tTjmax-tTjmin is related to the phase angle between the temperature response and the power excitation.

[0126] Figure 11 The figure shows the losses in the fundamental frequency of a DC / AC power converter plotted for different modulation strategies when driving an electric motor. The different modulation strategies are: Sine 60, DPWM1 61, DPWM3 62, Space Vector 63. The losses are calculated taking into account both the conduction losses and the switching losses of the semiconductor die and are averaged over the modulation period.

[0127] The topology of the converter is not limited to the converters used as examples, but can be a multi-level topology such as NPC (Neutral Point Clamped Inverter), ANPC (Active Neutral Point Clamped Inverter), MMC (Modular Multilevel Converter), FC (Flying Capacitor) and other topologies of the prior art.

[0128] This shows that in an AC / DC or DC / AC power converter having a power module comprising at least a semiconductor die attached to a stack of material for heat dissipation and / or for electrical connection, wherein the semiconductor dissipates asymmetric losses between two half-cycles of an AC frequency, measuring a signal related to the temperature of the semiconductor at said frequency, measuring the duration Δt=tTjmax-tTjmin between the temperature Tjmax at which the junction temperature is a maximum and the temperature Tjmin at which the junction temperature is a minimum in the AC cycle, allows to obtain a measure of the degradation of at least one layer in the stack of layers between the die and the heat sink to which the die is attached by repeating such measurements during the lifetime of the power converter.

[0129] Therefore, because degradation is sensitive to the temperature increase time delay Δt, rather than the temperature magnitude or the power loss magnitude, thermal degradation estimation is insensitive to the accuracy of junction temperature measurement. Therefore, any signal related to the semiconductor temperature can be used if there is a monotonic relationship between the temperature and the signal. It is not necessary to estimate or measure power loss in the semiconductor, thus advantageously reducing the number of sensors and computing time, and improving the accuracy of degradation measurement.

[0130] To repeat the measurement and comparison during the life of the converter, the calculation of the temperature increase time delay Δt=tTjmax-tTjmin can be stored in memory at each iteration and compared to the initial and / or previous values, and the temperature increase time delay for tj can be monitored. x =t0 to t p This time delay Δt x The evolution of is used to obtain the degradation state of thermal impedance.

[0131] In addition to measuring the temperature increase time delay, the fundamental frequency f of the measured loss can also be measured and stored fund , and by the duration Δt(f fund ) to determine the degradation state.

[0132] Therefore, it is advantageous that the damage indicator Δt x The change in is sensitive to the fundamental frequency, so the degradation information of a specific stack layer can be obtained.

[0133] For example, the fundamental loss frequency can be measured using an AC load current probe, or given by a controller reference, or given by a user AC frequency request.

[0134] As discussed below, damage at different heights in the stack results in different phase shifts in the temperature increase curve and at different frequencies f fund,i The damage index Δti(f fund,i ) enables information to be obtained about the degradation evolution at different layers of the stack. Higher frequencies are used to monitor the degradation of stack layers closer to the semiconductor, and lower frequencies are used to monitor the degradation of stack layers further away from the semiconductor.

[0135] It is possible to introduce degradation in a particular layer by, for example, using Equation 4, measuring the phase shift associated with the degradation using the Z(s) estimate from Equation 3, and plotting the Z(s) as Figures 5 to 7 The Bode plots in [ 1 ] are used to determine the effect of degradation on the frequency response function for a specific layer of the stack.

[0136] As an example, according to Figure 6 , using one or several frequencies between 20 Hz and 500 Hz to monitor the degradation on layer 4 and one or several frequencies between 1 Hz and 10 Hz to monitor layer 10 to obtain Figure 7 curve.

[0137] In the case of several combinations of degradations, such as in Figure 5 As shown in the example of , the monitoring of the time delay at several frequencies enables the separation of several degradation contributions.

[0138] To support the relationship between Δt and the phase angle, as a first approximation, the change in the phase angle Ph due to degradation, expressed in angular units of degrees (°), i.e., the change from Δt=tp to Δt=td, can be approximated by the following equation:

[0139] Ph=(td-tp)·f f ·360. (7)

[0140] Figure 12 A comparison of the first order estimate of the phase Ph using equation (7) and the phase extracted from the calculation using the impedance method for the fundamental frequency is shown. In this figure, curve 80 is for Figure 1 The estimated phase curves for degraded layers 4 and 10 are shown in Figure 8, while curve 81 is the theoretical curve for these degraded layers. Curve 82 is the estimated phase curve for degraded layer 4, while curve 83 is the theoretical curve for this degraded layer. Curve 84 is the estimated phase curve for degraded layer 10, while curve 85 is the theoretical curve for this degraded layer 10. This shows that for frequencies above about 10 Hz, the first-order estimate shows a similar trend to the more rigorous model, thus demonstrating that the information in Δt is consistent with the Figures 5 to 8 The information in the phase of the Bode plot is the same.

[0141] Then, in case the fundamental frequency f of the AC current can be varied, the process can monitor the time difference for different fundamental frequencies. This gives the possibility to provide an estimate of which layers are degraded layers.

[0142] When measuring the time difference Δtmin between two consecutive minimum values of the junction temperature, the fundamental frequency can be calculated as f fund =1 / Δtmin.

[0143] Advantageously, this therefore allows recording the fundamental frequency without using additional sensors or obtaining fundamental frequency information from a separate algorithm. Advantageously, the algorithm for degradation analysis can therefore work independently of the control algorithm of the converter or any other operating conditions of the power module.

[0144] In the example, Figure 10A The time interval between two consecutive minima is Δtmin = 0.02 s, and therefore the fundamental frequency is found to be f fund =1 / Δtmin=50Hz.

[0145] The signal used to measure the temperature may be any thermally sensitive electrical parameter (TSEP) of the relevant semiconductor switch.

[0146] Therefore, degradation can be identified and quantified without any complicated prior TSEP calibration, reducing the complexity of the system.

[0147] For example, TSEP can have a value X between Xa and Xb corresponding to, for example, a temperature range of [-20°C; 200°C], and the relationship between temperature and TSEP is linear, such as:

[0148] T=XA+B in [Xa;Xb], where A and B are constants.

[0149] In this example, because only variable X is measured, TSEP does not need to be calibrated before implementing the method, that is, A and B do not need to be determined. In one sub-example, A>0, and the time tTjmax and time tTjmin when the junction temperature is maximum correspond to the time when X is at its maximum value and the time when it is at its minimum value, respectively. In another sub-example, A<0, and the time tTjmax and time tTjmin when the junction temperature is maximum correspond to the time when X is at its minimum value and the time when it is at its maximum value, respectively.

[0150] More generally, it is sufficient that the function T(X) increases or decreases monotonically, for example, its first derivative does not change sign in the interval [Xa; Xb]. Thus, it is advantageous that uncalibrated TSEPs with nonlinear temperature characteristics can also be used within the scope of the present disclosure.

[0151] exist Figure 13AThe process steps of the present disclosure are shown in FIG. , which includes:

[0152] - step 100 : sampling and measuring 100 a signal S related to the junction temperature Tj of the semiconductor die at a frequency 10 times higher than the AC frequency of the AC current,

[0153] - step 110 of calculating a duration Δt=tTjmax-tTjmin between a time instant tTjmax at which the junction temperature of the semiconductor die is at a maximum value and a time instant tTjmin at which the junction temperature is at a minimum value during one cycle of the AC current, and step 120 of storing the duration Δt in a memory,

[0154] - Step 130 for t=t0 to t p Compare the duration Δt with the value t0 to Δt tp for monitoring the evolution of the duration Δt to determine the evolution of degradation of the thermal impedance of the power module;

[0155] - Repeating 140, 150 sampling and measuring the signal and calculating the signal at different times tx=t0 to t p duration to provide a series of durations Δt t0 to Δt tp .

[0156] Step 100 also includes measuring the AC frequency, and step 120 also includes storing the duration Δt tx and AC frequency f fund A combination of values.

[0157] The measurement in step 100 can be performed using several means such as thermocouples, infrared imaging, TSEP, etc.

[0158] Since there may be some noise in the measurement, it may be necessary to average the Δt values and not strictly use the first Δt0 value measured for comparison, but rather use an average value over a few alternating measurement cycles at the beginning of product use. In this case, the average may be taken over approximately 2 to 10 alternations.

[0159] The repetition of sampling, measuring and comparing can be done periodically, i.e. daily, weekly, monthly or after a certain number of alternating changes in the AC frequency of use corresponding to the estimated degradation rate of the converter (e.g. tenths or hundreds of hours). tx and Δt o The repetition rate may also be accelerated when the difference between becomes greater than a predetermined warning value.

[0160] The method may also include Figure 13B One or more steps 260 are shown, wherein the AC frequency is modified during a dedicated operating period of the converter to provide a number of different AC frequencies f m =f1,f2,…,f n , each AC frequency allows detecting the thermal impedance of a specific layer of the stack, repeating the sampling and measuring of the TSEP signal S and frequency 200 and the calculation 210 of the duration Δt corresponding to these different AC frequencies txf1 , Δt txf2 ,……,Δt txfn ,

[0161] - one or more steps 230 of comparing said Δt at each of said AC frequencies t0fm to Δt tpfm a value for monitoring the evolution of Δt for each of said AC frequencies, thereby determining the evolution of the degradation of the thermal impedance of said specific layer,

[0162] - repeating said sampling and measuring of said signal and said calculating of said duration during the operating life of the power module to provide the time constants for said different AC frequencies f m A series of Δt for each of x =Δt0 to Δt p value, used to convert Δt x The value is compared with the Δt0 value.

[0163] Here, the repetition of sampling, measuring and comparing may be performed periodically, i.e. daily, weekly, monthly or after a certain number of alternations (e.g., one tenth or hundreds of hours) of the AC frequency of use of the converter associated with the estimated degradation rate. tx and Δt o The repetition rate may also be accelerated when the difference between becomes greater than a predetermined warning value.

[0164] Furthermore, tests using regulation of the AC frequency may be performed in specific scenarios such as tests on ramping of grid frequency or electrode rotation speed.

[0165] like Figure 13C As shown, the method may further comprise one or more steps: a step 300 of measuring the time difference Δtmin between two consecutive minimum values of the junction temperature, and a step 310 of calculating the AC frequency as f=1 / Δtmin. This avoids having to measure the frequency by another means other than the signal S related to the junction temperature Tj, which may be an uncalibrated temperature-sensitive electrical parameter of the semiconductor.

[0166] To continue this method, Figure 9 The converter shown may include a sensor device 53 on the power semiconductor switch die of the converter for sensing the TSEP signal of the power semiconductor switch die, an analog-to-digital converter device 54, a sampling device 55 and a processor 56, and the processor 56 is provided with the necessary storage device 57 and computing device for storing and running software configured to perform the thermal impedance monitoring process of the present disclosure.

Claims

1. A thermal impedance monitoring process for a power module of a power converter, wherein the power converter is used to convert DC current into AC current or convert AC current into DC current, wherein: The semiconductor dissipates asymmetric losses between two half-cycles of an AC frequency f of an AC current, the power module comprising at least a semiconductor die attached to a material stack of layers for heat dissipation and / or electrical connection of the semiconductor die, the thermal impedance monitoring process comprising the following steps: - sampling and measuring a signal related to the junction temperature Tj of the semiconductor die at a frequency that is 10 times higher than the AC frequency of the AC current, - calculating a duration Δt=tTjmax-tTjmin between the instant tTjmax at which the junction temperature of the semiconductor die is at its maximum value and the instant tTjmin at which the junction temperature is at its minimum value in one cycle of the AC current, and storing the duration Δt in a memory, - During the working life of the power module, at different times t x =t0 to t p The steps of sampling and measuring the signal and calculating the duration are repeated to provide a series of durations Δt t0 to Δt tp , and the duration Δt tp Value and Δt t0 Comparison is performed to monitor the duration Δt x The evolution of the degradation of the thermal impedance of the power module is determined.

2. The thermal impedance monitoring process of claim 1, comprising averaging the Δt measurements over a period for reducing noise in the measurements.

3. The thermal impedance monitoring process according to claim 1 or 2, comprising measuring the AC frequency and the storage duration Δt tx and AC frequency f fund A combination of values.

4. The thermal impedance monitoring process according to claim 3, comprising: The AC frequency is modified during dedicated operating periods of the converter to provide several different AC frequencies f m =f1,f2,…,f n , each AC frequency allows detecting the thermal impedance of a specific layer of the stack, repeating the steps of sampling and measurement and calculating the duration Δt corresponding to these different AC frequencies txfm =Δt txf1 , Δt txf2 ,……,Δt txfn Steps, - repeating the steps of sampling and measuring the signal and calculating the duration during the operating life of the power module to provide a series of Δt for each of the different AC frequencies 0fm to Δt xfm value, and for each of the AC frequencies the Δt tm Value and Δt t0 Comparison is made for monitoring the AC frequency f m =f1,f2,…,f n The evolution of Δt for each of these is used to determine the evolution of the degradation of the thermal impedance of said specific layer. 5 . The thermal impedance monitoring process according to claim 3 , comprising measuring a time difference Δt min between two consecutive minimum values of the junction temperature, and calculating the AC frequency as f=1 / Δt min .

6. The thermal impedance monitoring process according to any one of claims 1 to 5, wherein: The signal related to the junction temperature Tj is a temperature-sensitive electrical parameter of the semiconductor.

7. The thermal impedance monitoring process according to claim 6, wherein: The signal related to the junction temperature Tj is an uncalibrated temperature-sensitive electrical parameter of the semiconductor.

8. The thermal impedance monitoring process according to any one of claims 1 to 7, wherein: The AC frequency is lower than where l die is the thickness of the die, and D die is the diffusion coefficient of the die.

9. The thermal impedance monitoring process according to any one of claims 1 to 8, wherein: The AC frequency is lower than 2 kHz.

10. The thermal impedance monitoring process according to any one of claims 1 to 9, wherein: The AC frequency is below 1 kHz.

11. The thermal impedance monitoring process according to any one of claims 1 to 10, wherein: The AC frequency is the fundamental frequency of the power supply to the converter or the fundamental output frequency f of the converter. fund .

12. A converter, comprising a sensor device on a power semiconductor switch die of the converter for sensing the temperature of the power semiconductor switch die, an analog-to-digital converter device, a sampling device and a processor, the processor being provided with a storage device for storing and running software configured to perform the thermal impedance monitoring process according to any one of claims 1 to 11.

13. The converter according to claim 12, wherein The sensor device is designed to sense a temperature-sensitive electrical parameter of the power semiconductor switch die.

14. A persistent storage device comprising software comprising instructions for performing the thermal impedance monitoring process according to any one of claims 1 to 11 when executed by a processor.

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