Insulating substrate and semiconductor device

Abstract

The purpose of the present application is to provide a technique capable of suppressing, in a semiconductor device, a reduction in appearance quality due to plating residues and a poor insulation such as a short circuit between circuit patterns. The insulating substrate (2) includes a ceramic substrate (2b) and a circuit pattern (2a) bonded to the surface of the ceramic substrate (2b) and on which the semiconductor element (3) is to be mounted. On the rear surface side of the outer peripheral portion of the circuit pattern (2a) that is joined to the ceramic substrate (2b), a cut-out portion (8) that does not come into contact with the surface of the ceramic substrate (2b) is formed.

Description

Technical Field

[0001] The present disclosure relates to an insulating substrate and a semiconductor device. Background Art

[0002] For example, Patent Document 1 proposes a semiconductor device capable of improving the bonding reliability between a circuit pattern and a semiconductor element.

[0003] The insulating substrate mounted on the semiconductor device undergoes a plating process for soldering the circuit pattern formed on the surface of the ceramic substrate included in the insulating substrate to the semiconductor element, and a plating stripping process. In the plating process, the entire insulating substrate is plated. In the plating stripping process, only the areas required for soldering are masked with a resist material. For areas not requiring plating, the plating is dissolved and removed with a stripping solution, and then plating residue is removed by air blowing. Prior art literature Patent Literature

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2007-311527 Summary of the Invention Technical problem to be solved by the invention

[0005] However, when manufacturing circuit patterns, a tiny depression sometimes forms on the outer periphery of the circuit pattern's interface with the ceramic substrate. Because airflow does not effectively absorb wind in the depression, plating residue easily remains in the depression even after the plating stripping process. When manufacturing semiconductor devices with residual plating residue, the plating residue trapped in the depression can flow out due to the heat load during soldering and the flow of the sealing resin, potentially reducing the appearance quality of the semiconductor device. Furthermore, if the plating residue flows across the circuit pattern, it can cause insulation defects such as short circuits between the circuit patterns.

[0006] In the technology described in Patent Document 1, solder reservoir recesses are formed on the periphery of the circuit pattern. However, the solder reservoir recesses are limited to the function of accumulating solder used for joining the semiconductor element and the circuit pattern, and do not consider problems caused by plating residues.

[0007] Therefore, an object of the present disclosure is to provide a technology capable of suppressing degradation of appearance quality and insulation failure such as short circuits between circuit patterns caused by plating residues in a semiconductor device. Technical solutions to technical problems

[0008] The insulating substrate involved in the present disclosure includes: a ceramic substrate; and a circuit pattern, which is bonded to the surface of the ceramic substrate and is intended to carry a semiconductor element. A recessed portion that does not contact the surface of the ceramic substrate is formed on the back side of the outer periphery of the circuit pattern bonded to the ceramic substrate. Effects of the Invention

[0009] According to the present disclosure, during the plating stripping process performed before bonding a circuit pattern to a semiconductor element, the stripping solution easily penetrates the back side of the outer periphery of the circuit pattern. Furthermore, the airflow efficiency of the air blower used to remove plating residue is improved, thereby more effectively removing unwanted plating residue. This can prevent degradation of the appearance quality of semiconductor devices caused by plating residue and insulation defects such as short circuits between circuit patterns.

[0010] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 This is a cross-sectional view of a semiconductor device according to the second embodiment. Figure 3 This is a cross-sectional view of a semiconductor device according to a third embodiment. Figure 4 This is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 3. Figure 5 This is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 3. Figure 6 These are a plan view, a cross-sectional view taken along line AA, and a cross-sectional view taken along line BB of the semiconductor device according to the fourth embodiment, as viewed from above the semiconductor element. Figure 7 This is a plan view of a portion of the semiconductor device according to the first modification of the fourth embodiment as viewed from above the semiconductor element. Figure 8 This is a plan view of a portion of a semiconductor device according to a second modification of the fourth embodiment as viewed from above a semiconductor element. Figure 9 This is a plan view of a portion of a semiconductor device according to a third modification of the fourth embodiment as viewed from above the semiconductor element. DETAILED DESCRIPTION

[0012] <Implementation Method 1> Embodiment 1 will be described below using the drawings. Figure 1It is a cross-sectional view of the semiconductor device 100 according to the first embodiment.

[0013] like Figure 1 As shown, the semiconductor device 100 includes a base plate 1 , an insulating substrate 2 , a semiconductor element 3 , main terminals 4 , a resin case 5 , and a sealing resin 6 .

[0014] The base plate 1 has a rectangular shape in a plan view and is made of a material having a relatively high thermal conductivity, such as copper, a copper alloy, aluminum, or an aluminum alloy.

[0015] The insulating substrate 2 includes a surface circuit pattern 2a, a ceramic substrate 2b, and a back circuit pattern 2c. The ceramic substrate 2b is made of, for example, a ceramic such as Al2O3, AlN, or Si3N4. The surface circuit pattern 2a and the back circuit pattern 2c are made of, for example, a metal primarily composed of Cu. The surface circuit pattern 2a and the back circuit pattern 2c are respectively bonded to the surface and back of the ceramic substrate 2b using solder (not shown). The surface circuit pattern 2a is a circuit pattern on which the semiconductor element 3 is to be mounted, and is selectively formed. That is, a plurality of surface circuit patterns 2a are formed to form the circuit required for the semiconductor device 100.

[0016] On the surface circuit pattern 2a, the back electrode (e.g., collector electrode) of the semiconductor element 3 is bonded by a bonding material 7 made of a lead-free solder such as a Sn-Ag system, thereby mounting the semiconductor element 3. The semiconductor element 3 is a power semiconductor element made of, for example, Si, SiC, or GaN. Since the power semiconductor element generates high temperature during operation, it is important to ensure high heat dissipation. Figure 1 Although two semiconductor elements 3 are shown in FIG, the number is not limited to two, and one or more semiconductor elements may be sufficient.

[0017] Main terminals 4 mainly composed of Cu are bonded to surface electrodes (eg, emitter electrodes or gate electrodes) of the semiconductor element 3 via bonding materials 7 to form various wirings, thereby forming circuits required for the semiconductor device 100 .

[0018] Resin case 5 is formed from a highly heat-resistant resin such as PPS into a rectangular frame shape when viewed from above. Resin case 5 is secured to the outer periphery of base plate 1 using an adhesive (not shown) or the like, so as to surround the circuitry including semiconductor element 3. A sealing resin 6 such as epoxy resin is filled within resin case 5 to protect the circuitry including semiconductor element 3.

[0019] Next, we will explain the issues that arise when manufacturing the insulating substrate 2. During the manufacturing process of the insulating substrate 2, a plating step and a plating stripping step are performed for the purpose of soldering the surface circuit pattern 2a and the semiconductor element 3. In the plating step, the entire insulating substrate 2 is plated. In the plating stripping step, a resist material is used to mask only the areas required for soldering. For areas not requiring plating, the plating is dissolved and removed using a stripping solution, and then plating residue is removed using air blowing.

[0020] When manufacturing the surface circuit pattern 2a, a small depression may sometimes form on the outer periphery of the surface where the surface circuit pattern 2a meets the ceramic substrate 2b. Because the airflow is poorly received in the depression, plating residue is likely to remain in the depression even after the plating stripping process. When manufacturing the semiconductor device 100 while plating residue remains, the plating residue trapped in the depression may flow out due to the heat load during soldering and the flow of the sealing resin 6, potentially reducing the appearance quality of the semiconductor device 100. Furthermore, if the plating residue flows across the surface circuit patterns 2a, it may cause insulation defects such as short circuits between the surface circuit patterns 2a.

[0021] In contrast, in embodiment 1, Figure 1 As shown, a recessed portion 8 that does not contact the surface of the ceramic substrate 2b is formed on the back side of the outer periphery of the surface circuit pattern 2a that is bonded to the ceramic substrate 2b. The recessed portion 8 is formed over the entire outer periphery of the surface circuit pattern 2a.

[0022] Since the hollowed portion 8 is formed as an opening larger than the collapsed portion in the portion where the micro-collapse is formed, the plating stripping liquid can fully penetrate the back side of the outer periphery of the surface circuit pattern 2a and the air blowing effect can be improved. As a result, plating residue can be reduced.

[0023] As described above, the semiconductor device 100 according to the first embodiment includes the insulating substrate 2 , the semiconductor element 3 mounted on the surface of the surface circuit pattern 2 a , and the base plate 1 bonded to the back surface side of the ceramic substrate 2 b .

[0024] Insulating substrate 2 includes ceramic substrate 2b and surface circuit pattern 2a bonded to the surface of ceramic substrate 2b and intended to carry semiconductor element 3. A recessed portion 8 is formed on the back side of the outer periphery of surface circuit pattern 2a bonded to ceramic substrate 2b, so as not to contact the surface of ceramic substrate 2b.

[0025] Therefore, during the plating stripping process performed before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping liquid easily penetrates the back side of the outer periphery of the surface circuit pattern 2a. Furthermore, the airflow efficiency of the air blower used to remove the plating residue is improved, thereby more effectively removing the unnecessary plating residue. As a result, in the semiconductor device 100, it is possible to suppress degradation of the appearance quality caused by the plating residue and insulation defects such as short circuits between the surface circuit patterns 2a.

[0026] This can improve the durability and yield of the insulating substrate 2 and the semiconductor device 100 .

[0027] <Implementation Method 2> Next, a semiconductor device 200 according to the second embodiment will be described. Figure 2 2 is a cross-sectional view of a semiconductor device 200 according to Embodiment 2. In Embodiment 2, the same components as those described in Embodiment 1 are denoted by the same reference numerals, and their description is omitted.

[0028] like Figure 2 As shown, in the second embodiment, the cutout portion 8 is not formed on the surface circuit pattern 2a, and the cutout portion 9 is formed on the ceramic substrate 2b.

[0029] The cutout 9 is formed so as to be recessed downward in the portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a. Specifically, the cutout 9 extends from the portion of the ceramic substrate 2b that faces the entire periphery of the surface circuit pattern 2a to the outer periphery. The cutout 9 prevents the outer periphery of the surface circuit pattern 2a from contacting the surface of the ceramic substrate 2b.

[0030] Since the hollowed portion 9 is formed adjacent to the portion where the micro-collapse is formed, with an opening larger than the collapsed portion, the plating stripping liquid can fully penetrate the back side of the outer periphery of the surface circuit pattern 2a and the air blowing effect can be improved. As a result, plating residue can be reduced.

[0031] As described above, in the semiconductor device 200 according to the second embodiment, the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b and on which the semiconductor element 3 is mounted. A downwardly recessed portion 9 is formed in a portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a.

[0032] Therefore, during the plating stripping process performed before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping liquid easily penetrates the back side of the outer periphery of the surface circuit pattern 2a. Furthermore, the airflow efficiency of the air blower used to remove the plating residue is improved, thereby more effectively removing the unnecessary plating residue. As a result, in the semiconductor device 200, it is possible to suppress degradation of the appearance quality caused by the plating residue and insulation defects such as short circuits between the surface circuit patterns 2a.

[0033] <Implementation Method 3> Next, a semiconductor device 300 according to the third embodiment will be described. Figure 3 3 is a cross-sectional view of a semiconductor device 300 according to Embodiment 3. In Embodiment 3, the same components as those described in Embodiments 1 and 2 are denoted by the same reference numerals, and their description is omitted.

[0034] like Figure 3 As shown, in the third embodiment, the recessed portions 8 and 9 are not formed, and the outer periphery of the surface circuit pattern 2a is formed into a tapered shape 10 in which the width of the surface circuit pattern 2a narrows from the back surface bonded to the ceramic substrate 2b toward the surface on which the semiconductor element 3 is mounted. The tapered shape 10 is formed over the entire outer periphery of the surface circuit pattern 2a.

[0035] By forming the outer periphery of the surface circuit pattern 2a into a tapered shape 10, the outer periphery of the surface circuit pattern 2a faces upward, the stripping liquid can easily penetrate into the entire outer periphery of the surface circuit pattern 2a, and the wind receiving effect of the air blowing used to remove the plating residue is improved, thereby being able to more effectively remove unnecessary plating residue.

[0036] As described above, in the semiconductor device 300 according to the third embodiment, the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b and on which the semiconductor element 3 is to be mounted. The outer periphery of the surface circuit pattern 2a is formed into a tapered shape 10 in which the width of the surface circuit pattern 2a gradually narrows from the back surface bonded to the ceramic substrate 2b toward the surface on which the semiconductor element 3 is to be mounted.

[0037] Therefore, during the plating stripping process performed before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping liquid easily penetrates the entire periphery of the surface circuit pattern 2a, and the airflow efficiency of the air blower used to remove the plating residue is improved, thereby more effectively removing the unnecessary plating residue. As a result, in the semiconductor device 300, it is possible to suppress degradation of the appearance quality caused by the plating residue and insulation defects such as short circuits between the surface circuit patterns 2a.

[0038] <Variation of Embodiment 3> Next, Modifications 1 and 2 of the third embodiment will be described. Figure 4It is a cross-sectional view of a semiconductor device 400 according to Modification 1 of Embodiment 3. Figure 5 This is a cross-sectional view of a semiconductor device 500 according to a second modification of the third embodiment.

[0039] like Figure 4 As shown in FIG. 1 , the tapered shape 11 of the outer periphery of the surface circuit pattern 2a may also be formed into a curved surface shape. Figure 5 As shown in FIG. 1 , the tapered shape 12 of the outer peripheral portion of the surface circuit pattern 2 a may be formed in a stepped shape. In these cases, the same effects as those of the third embodiment can be obtained.

[0040] <Implementation Method 4> Next, a semiconductor device 600 according to a fourth embodiment will be described. Figure 6 (a) is a plan view of the semiconductor device 600 according to the fourth embodiment as viewed from above the semiconductor element 3 . Figure 6 (b) Yes Figure 6 (a) AA line cross-sectional view, Figure 6 (c) Yes Figure 6 (a) is a cross-sectional view taken along line BB. In the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals and their descriptions are omitted.

[0041] like Figure 6 As shown in FIG. 1 , in Embodiment 4, a cutout portion 13 is formed instead of the hollowed portions 8 and 9 and the tapered portions 10, 11, and 12. A plurality of cutout portions 13 are continuously formed along the entire periphery of the surface circuit pattern 2a. Specifically, the cutout portions 13 have a rectangular shape when viewed from above, with two cutout portions formed on each side of the surface circuit pattern 2a.

[0042] like Figure 6 As shown in (a), (b), and (c), the cutout portion 13 is formed to have the same thickness as the thickness of each surface circuit pattern 2a. Figure 6 As shown in (a) and (b), the portion of each surface circuit pattern 2a without the cutout portion 13 has the same width d2 as that of the conventional structure without the cutout portion 13.

[0043] In a conventional structure without cutouts 13, the width of one side of the outer periphery of each surface circuit pattern 2a is d2, and plating residue corresponding to the length of d2 is retained. Consequently, during semiconductor device manufacturing, the plating residue may flow across the length d1 between adjacent surface circuit patterns 2a, potentially causing insulation failures such as short circuits between the surface circuit patterns 2a. Here, d2 ≥ d1.

[0044] In contrast, in Embodiment 4, the length between adjacent cut portions 13 in the outer peripheral portion of each surface circuit pattern 2a, that is, the width d3 of one side in the outer peripheral portion of each surface circuit pattern 2a, is formed to be sufficiently shorter than the length d1 between adjacent surface circuit patterns 2a (d3 < d1). Therefore, plating residues having a length equivalent to d3 remain, and when the plating residues flow out in a manner crossing the length d1 between the surface circuit patterns 2a during the manufacture of the semiconductor device 600, contact between the plating residues and the adjacent surface circuit patterns 2a can be suppressed.

[0045] As described above, in the semiconductor device 600 according to Embodiment 4, the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a that is bonded to the surface of the ceramic substrate 2b and on which semiconductor elements 3 should be mounted. A plurality of continuous cut portions 13 are formed in the outer peripheral portion of the surface circuit pattern 2a. In addition, each cut portion 13 is formed in a rectangular shape in a top view.

[0046] Therefore, even when the plating residues flow out in a manner crossing between adjacent surface circuit patterns 2a during the manufacture of the semiconductor device 600, contact between the plating residues and the adjacent surface circuit patterns 2a can be suppressed. Thereby, in the semiconductor device 600, deterioration of the appearance quality caused by the plating residues and insulation defects such as short circuits between the surface circuit patterns 2a can be suppressed.

[0047] <Modifications of Embodiment 4> Next, Modifications 1 to 3 of Embodiment 4 will be described. Figure 7 FIG. is a top view obtained by observing a part of the semiconductor device 700 according to Modification 1 of Embodiment 4 from above the semiconductor element 3. Figure 8 FIG. is a top view obtained by observing a part of the semiconductor device 800 according to Modification 2 of Embodiment 4 from above the semiconductor element 3. Figure 9 FIG. is a top view obtained by observing a part of the semiconductor device 900 according to Modification 3 of Embodiment 4 from above the semiconductor element 3.

[0048] As Figure 7 shown, each cut portion 14 may also be formed in a triangular shape in a top view. In addition, as Figure 8 shown, each cut portion 15 may also be formed in a stepped shape in a top view. In addition, as Figure 9 [[ID=2 — 6]]shown, each cut portion 16 may also be formed in an arc shape in a top view. In these cases, the same effects as those in Embodiment 4 can also be obtained.

[0049] The present disclosure has been described in detail, but the above description is merely an example in all aspects and is not limited thereto. It can be understood that countless unillustrated modifications can be conceived.

[0050] The various embodiments can be freely combined, or can be appropriately modified or omitted. Label Description

[0051] 1 bottom plate 2 Insulating substrate 2a Surface circuit pattern 2b Ceramic substrate 3 Semiconductor components 8, 9 Excavation 10 cone shape 11 Surface Shape 12 Step shape 13, 14, 15, 16 incisions 100, 200, 300, 400, 500, 600, 700, 800, 900 semiconductor devices.

Claims

1. An insulating substrate, characterized in that include: Ceramic substrate; as well as a circuit pattern bonded to the surface of the ceramic substrate and having a semiconductor element mounted thereon; A recessed portion that does not contact the surface of the ceramic substrate is formed on the back side of the outer peripheral portion of the circuit pattern that is bonded to the ceramic substrate.

2. An insulating substrate, characterized in that include: Ceramic substrate; a circuit pattern bonded to the surface of the ceramic substrate and having a semiconductor element mounted thereon; A downwardly recessed portion is formed in a portion of the ceramic substrate adjacent to an outer periphery of the circuit pattern.

3. An insulating substrate, characterized in that include: Ceramic substrate; a circuit pattern bonded to the surface of the ceramic substrate and having a semiconductor element mounted thereon; The outer peripheral portion of the circuit pattern is formed in a tapered shape in which the width of the circuit pattern becomes narrower from the back surface bonded to the ceramic substrate toward the surface on which the semiconductor element is to be mounted.

4. The insulating substrate according to claim 3, wherein The tapered shape of the outer peripheral portion of the circuit pattern is formed into a curved surface shape.

5. The insulating substrate according to claim 3, wherein The tapered shape of the outer peripheral portion of the circuit pattern is formed in a step shape.

6. An insulating substrate, characterized in that include: Ceramic substrate; a circuit pattern bonded to the surface of the ceramic substrate and having a semiconductor element mounted thereon; A plurality of continuous cutouts are formed on the outer periphery of the circuit pattern.

7. The insulating substrate according to claim 6, wherein Each of the cutouts is formed in a rectangular shape, a triangular shape, a stepped shape, or an arc shape in a plan view.

8. The insulating substrate according to claim 7, wherein comprising a plurality of said circuit patterns, In the outer peripheral portion of each of the circuit patterns, a length between adjacent notches is shorter than a length between adjacent circuit patterns.

9. A semiconductor device, characterized in that: include: The insulating substrate according to any one of claims 1 to 8; the semiconductor element mounted on a surface of the circuit pattern; as well as A base plate is bonded to the back side of the ceramic substrate.

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