Sampling implementation method and system suitable for motor protection quick response

Abstract

The invention discloses a sampling implementation method and system suitable for motor protection quick response, belongs to the technical field of motor protection, and can increase the sampling frequency and improve the quick response of motor fault protection. Comprising the steps that motor phase current and bus voltage are collected, after anti-aliasing filtering is conducted, parallel sampling is conducted through a main ADC module and a redundant ADC module which are independently configured, and the following operations are synchronously executed based on a double-buffer-area framework: in a first buffer area, a compensation coefficient updating period is dynamically adjusted, and convergence is restrained; in the second buffer area, generating a voltage gradient prediction sequence, and compensating data abrupt change; when the harmonic frequency spectrum amplitude or the voltage gradient prediction sequence exceeds the limit, an oversampling mode is triggered, a redundant ADC module is allocated to load a multi-order digital filter, and an independent hardware acceleration unit is started to process harmonic compensation and gradient prediction in parallel; and generating a dynamic safety envelope, and if the gradient extreme value in the preset continuous window breaks through the safety envelope, generating an overvoltage fault signal.

Description

Technical Field

[0001] The present invention relates to the field of motor protection technology, and specifically to a motor protection rapid response method and system through dual ADC parallel sampling, dynamic harmonic analysis, and hardware acceleration, which is suitable for electric vehicles and high-precision industrial motor control. Background Art

[0002] With the rapid development of electric vehicles and automated equipment, motor control technology is playing an increasingly important role in modern industry and transportation. In closed-loop motor control systems, real-time monitoring of key physical quantities such as motor phase current, bus voltage, and rotor position is a core requirement for ensuring safe and efficient motor operation. In electric vehicle applications, motor stability directly impacts overall vehicle performance and safety. Therefore, developing an efficient motor protection mechanism is a significant technical challenge.

[0003] In related technologies, automotive motor controllers typically implement motor protection using software or hardware, but the reliability of these methods is often limited by sampling accuracy and speed. Specifically, during motor operation, common faults, such as phase current overcurrent and bus voltage overvoltage, often need to be detected and responded to quickly in a very short time. However, the sampling frequency of existing systems is generally low, usually related to the switching frequency of the power module, generally around 10kHz. This low sampling frequency is difficult to meet the needs of fault protection under rapidly changing motor operating conditions, and may cause the protection mechanism to respond slowly, thereby increasing the risk of motor damage.

[0004] Traditional motor protection systems have the following problems:

[0005] 1. Limited sampling frequency: The main ADC sampling frequency is typically 10kHz, which makes it difficult to capture transient faults (such as phase current overcurrent).

[0006] 2. Large algorithm delay: The Fourier transform processed by the software requires the accumulation of window data, resulting in millisecond-level delays.

[0007] 3. High false operation rate: Fixed threshold cannot distinguish between transient interference and real faults.

[0008] The existing technology:

[0009] For example, patent document (CN103743987B) determines ADC failure by detecting internal parameters of a microprocessor, but relies on software detection and has a slow response speed.

[0010] For example, patent document (CN118889314A) adopts harmonic injection, but does not solve the problem of fast response at the hardware level.

[0011] The present invention achieves an equivalent 100 kHz level fault capture capability through hardware reconstruction and algorithm optimization. Summary of the Invention

[0012] The present invention provides a sampling implementation method and system suitable for rapid response of motor protection, which can increase the sampling frequency and improve the rapid response of motor fault protection.

[0013] In order to achieve the above object, the present invention adopts the following technical solutions:

[0014] A sampling implementation method suitable for fast response of motor protection is applied to a motor closed-loop control system, comprising the following steps:

[0015] (1) Collect motor phase current and bus voltage, and after anti-aliasing filtering, sample them in parallel through the independently configured main ADC module and redundant ADC module;

[0016] (2) Based on the double buffer architecture, the following operations are performed synchronously:

[0017] In the first buffer, the harmonic spectrum amplitude is updated point by point using a sliding discrete Fourier transform. The compensation coefficient update period is dynamically adjusted based on the harmonic energy change rate, and the convergence is constrained by a pre-trained time series prediction model.

[0018] In the second buffer, a window switching threshold is predefined based on the bus voltage fluctuation rate and historical spectrum characteristics, a gradient extreme value pre-screening mechanism is used to generate a voltage gradient prediction sequence, and a pre-trigger buffer mechanism is used to compensate for data mutations.

[0019] (3) When the harmonic spectrum amplitude or voltage gradient prediction sequence exceeds the limit, the oversampling mode is triggered, the redundant ADC modules are assigned to load multi-order digital filters, and the independent hardware acceleration unit is enabled to process harmonic compensation and gradient prediction in parallel;

[0020] (4) Generate a dynamic safety envelope based on the bus voltage gradient prediction sequence and the rolling weighting of historical extreme values. If the gradient extreme value within the preset continuous window breaks through the safety envelope, an overvoltage fault signal is generated;

[0021] (5) In response to the overvoltage fault signal, the drive signal is blocked through the hardware interrupt controller, and the hierarchical trigger logic of the multi-stage discharge circuit is started.

[0022] Furthermore, the main ADC module and the redundant ADC module are synchronously executed by the following steps:

[0023] (1) The clock signals of the main ADC module and the redundant ADC module are processed by a fully digital phase-locked loop to obtain a synchronous clock signal. Its closed-loop transfer function is:

[0024]

[0025] Among them, K p Indicates the proportional control coefficient; K i Indicates the integral control coefficient; K d represents the differential control coefficient; ω n =2π·f bandwidth , expresses the natural frequency; f bandwidth Indicates the phase-locked loop bandwidth; f bandwidth ≥3f clk ;f clk Indicates the system main clock frequency;

[0026] (2) For the measurement frequency f m (t) and the reference frequency f r (t) Calculate the clock frequency deviation and obtain the deviation:

[0027]

[0028] Among them, C ppm Indicates the parts per million conversion factor;

[0029] (3) For continuous N th The deviation of each cycle δ(t) is compared with the threshold value. When |δ(t)|>δ th When , ADPLL reconfiguration instructions are generated, where δ th is the continuous cycle determination threshold.

[0030] Furthermore, the steps of dynamically adjusting the compensation coefficient update period in combination with the harmonic energy change rate are as follows:

[0031] (1) Based on the harmonic amplitude sequence A k (t) and time interval Δt are used to calculate the energy change rate. The specific formula is as follows:

[0032]

[0033] Among them, N h is the harmonic analysis order, Δt≤T clk / 2, represents the time window step, T clk =1 / f clk , represents the system clock period;

[0034] (2) Perform linear combination processing on the energy change rate E(t) and the clock deviation δ(t) to obtain the compensation coefficient update period:

[0035] T update (t)=α·E(t)+β·δ(t)+T base

[0036] Among them, α∈(0.08, 0.15) represents the energy change weight factor; β∈(0.02, 0.05) represents the clock deviation weight factor; T base <T clk , indicating the basic update cycle;

[0037] (3) Update period T for compensation coefficient update (t) threshold judgment processing is performed, when T update (t)<T th When the sampling frequency is increased to K·f clk , where: K≥3, represents the oversampling multiple, T th Indicates the update period threshold.

[0038] Furthermore, the voltage gradient prediction sequence is generated by the following steps:

[0039] (1) Based on voltage gradient sequence and compensation coefficient update period T update (t) is used to calculate the acceleration factor α(t). The specific formula is as follows:

[0040]

[0041] Among them, N w is the sliding window length; Δt≤T clk / 2, represents the time interval for gradient calculation;

[0042] (2) The acceleration factor a(t) and harmonic energy E(t) are normalized to obtain the mutation prediction coefficient β(t). The specific formula is as follows:

[0043]

[0044] in, Indicates the acceleration judgment threshold; E th =E rated ·T clk , represents the energy judgment threshold; f SW Indicates the switching frequency of the power device; E rated Indicates the rated working condition energy reference value; V rated Indicates the effective value of the motor's rated line voltage;

[0045] (3) Perform threshold comparison on the mutation prediction coefficient β(t). When β(t)>β th When , adjust the window length to η·N w , otherwise unchanged; where: β th ∈[0.6,0.8], represents the mutation judgment threshold, η∈(0.3,0.5), represents the window compression factor;

[0046] (4) Calculate the compressed gradient sequence according to the window length The specific formula is as follows:

[0047]

[0048] Among them, N new =η·N w , represents the adjusted window length; Resample(·): resampling function, using linear interpolation algorithm;

[0049] (5) According to the compression gradient sequence and the acceleration factor α(t), the voltage gradient prediction sequence is calculated The specific formula is as follows:

[0050]

[0051] Where: T clk , represents the system clock period, T clk =1 / f clk ;f clk is the main clock frequency; P: represents the historical data order; a i , b represents the parameters of the pre-trained time series prediction model, which is obtained through offline training of the LSTM network; M represents the number of prediction cycles; Represents the voltage gradient prediction sequence for the next M cycles.

[0052] Furthermore, the loading strategy of the multi-order digital filter includes:

[0053] (1) Based on harmonic energy E(t) and reference energy E base Perform logarithmic operation to obtain the dynamic filter order N filter (t), the specific formula is as follows:

[0054]

[0055] Among them, E base , represents the reference energy calibration value; N base , represents the order of the basic filter; Clip(x, a, b), represents the clipping function, the output value is limited to the interval [a, b]; N min , represents the minimum filter order; N max , represents the maximum filter order;

[0056] (2) For clock frequency f clk and filter order N filter (t) Perform proportional operation to obtain the cutoff frequency f c (t), the specific formula is as follows:

[0057]

[0058] Among them, γ≥1.2, represents the cutoff frequency adjustment coefficient;

[0059] (3) Update period T according to the compensation coefficient update (t), calculate the maximum allowed delay τ max (t), the specific formula is as follows:

[0060] τ max (t) = λ·T update (t)

[0061] Where λ≤0.3 represents the delay tolerance coefficient;

[0062] (4) According to the cut-off frequency f c (t), the maximum allowed delay τ max (t) and the current filter delay τ current , generate filter configuration instruction set C filter (t), the specific logic is:

[0063]

[0064] in, <IIR,f c (t), K p >Indicates IIR filter type, cutoff frequency, and gain coefficient; <FIR,f c (t), N filter (t)> represents the FIR filter type, cutoff frequency, and order.

[0065] Furthermore, a dynamic safety envelope is generated based on the rolling weighting of the bus voltage gradient prediction sequence and historical extreme values. If the gradient extreme value in a preset continuous window exceeds the safety envelope, the step of generating an overvoltage fault signal includes:

[0066] (1) Based on voltage gradient and the maximum allowed gradient Perform relative value calculation to obtain the transient overvoltage factor:

[0067]

[0068] in, Indicates the maximum allowable voltage gradient; α max Indicates the extreme value of acceleration;

[0069] (2) According to the voltage statistic μ V (k), σ V (k) and transient overvoltage factor τ(k) generate the envelope curve, and the specific formula is as follows:

[0070]

[0071] Among them, μ V (k): window voltage mean; σ V (k): window voltage standard deviation; H sup (k): upper bound of historical statistical data; c1≥3: upper envelope amplification coefficient; c2∈[0.4,0.6]: transient factor weight coefficient; c3≥2: lower envelope reduction coefficient; V ub (k): upper envelope; V lb (k): lower envelope;

[0072] (3) Real-time voltage gradient With the upper envelope V ub (k) Perform proportional comparison processing, when When , an overvoltage fault signal is generated, where c4∈[0.7, 0.9]: safety margin coefficient.

[0073] A sampling implementation system suitable for rapid response of motor protection, used in the above method, comprises:

[0074] The first acquisition module is used to collect motor phase current and bus voltage. After anti-aliasing filtering, the samples are collected in parallel by an independently configured main ADC module and a redundant ADC module. The following operations are performed synchronously based on a dual-buffer architecture: In the first buffer, the harmonic spectrum amplitude is updated point by point using a sliding discrete Fourier transform. The compensation coefficient update period is dynamically adjusted based on the harmonic energy change rate, and the convergence is constrained by a pre-trained time series prediction model. In the second buffer, a window switching threshold is predefined based on the bus voltage fluctuation rate and historical spectrum characteristics, and a gradient extreme value pre-screening mechanism is used to generate a voltage gradient prediction sequence. A pre-trigger buffer mechanism is used to compensate for data mutations.

[0075] The first trigger module is used to trigger the oversampling mode when the harmonic spectrum amplitude or voltage gradient prediction sequence exceeds the limit, allocate redundant ADC modules to load multi-order digital filters, and enable independent hardware acceleration units to parallelly process harmonic compensation and gradient prediction;

[0076] The first generation module is used to generate a dynamic safety envelope based on the bus voltage gradient prediction sequence and the rolling weight of historical extreme values. If the gradient extreme value in the preset continuous window exceeds the safety envelope, an overvoltage fault signal is generated;

[0077] The second trigger module is configured to block the driving signal through the hardware interrupt controller in response to the overvoltage fault signal and start the hierarchical trigger logic of the multi-stage discharge circuit.

[0078] Furthermore, the step of starting the hierarchical triggering logic of the multi-stage discharge circuit includes:

[0079] (1) Real-time voltage gradient The discharge weight is obtained by weighting the transient overvoltage factor τ(t):

[0080]

[0081] Among them, V safe =1.2V rated , represents the safety voltage threshold; τ safe =1.2, indicating the safety transient factor threshold; K indicates the transient factor weight coefficient;

[0082] (2) Perform multi-level threshold judgment processing on the discharge weight w(t) to generate the discharge level instruction:

[0083]

[0084] Among them, L1: primary discharge mode; L2: intermediate discharge mode; L3: advanced discharge mode; w th1 is the preset primary threshold; w th2 To preset advanced thresholds;

[0085] (3) Perform threshold judgment on the discharge level L(t). When L(t)≥L th When the multi-level trigger instruction is generated, the compensation coefficient update cycle is shortened to ρ·T nom and IIR filter fast channel activation operation, where L th is the preset switching action threshold; ρ≤0.3, represents the cycle compression factor; T nom is the nominal update period.

[0086] An electronic device, comprising:

[0087] one or more processors;

[0088] a storage device having one or more programs stored thereon;

[0089] When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 6.

[0090] A computer-readable storage medium and a computer program product. The computer-readable storage medium stores a computer program, and the computer program implements the above method when executed by a processing device.

[0091] Compared with the prior art, the present invention has the following beneficial effects:

[0092] In the first aspect, the present invention provides a sampling implementation method suitable for rapid response of motor protection, which is applied to the motor closed-loop control system. In the present invention, the parallel sampling of the main ADC and the redundant ADC is first used to break through the rate limit of a single module. The dual buffer architecture decouples data acquisition and processing. The first buffer uses a sliding discrete Fourier transform to achieve point-by-point update of the harmonic spectrum, eliminating the window accumulation delay of the traditional Fourier transform. At the same time, the compensation coefficient update period is dynamically adjusted by the harmonic energy change rate, and the analysis period is automatically shortened to the microsecond level when the current suddenly changes. The pre-trained time series prediction model further constrains the algorithm convergence direction and avoids time-consuming iterative calculations. The second buffer predefines the window switching threshold based on the historical spectrum characteristics according to the bus voltage fluctuation characteristics, and uses the gradient extreme value pre-screening mechanism to generate the voltage gradient prediction sequence. The pre-trigger buffer mechanism reserves processing resources before the data suddenly changes.

[0093] When harmonic amplitude or voltage gradient exceeds a certain limit, oversampling mode is immediately triggered. Configurable multi-order digital filters are applied to redundant ADCs to increase local sampling density. Independent hardware acceleration units perform harmonic compensation and gradient prediction in parallel, bypassing the instruction cycle delays of traditional software processing. A dynamic safety envelope is generated based on a rolling weighted combination of the voltage gradient prediction sequence and historical extreme values. A continuous window decision mechanism filters out sporadic interference signals. Ultimately, a hardware interrupt controller directly blocks the drive signal and initiates graded discharge, compressing the fault response path from millisecond latency at the software level to nanosecond action at the hardware level. This deep integration of hardware resource reconfiguration and algorithm acceleration enables the system to achieve transient fault capture capabilities equivalent to hundreds of kHz at a base sampling rate of 10 kHz, effectively reducing protection response time and increasing speed. Furthermore, the dynamic envelope and pre-trigger mechanism effectively reduce the probability of false tripping, keeping it below industrial safety thresholds. This forms a full-link acceleration mechanism from data acquisition, real-time analysis, to protection execution.

[0094] In the first technical solution, the main ADC module and the redundant ADC module are synchronized through specific steps. In this way, an adaptive clock synchronization system is constructed through the dynamic control mechanism of the fully digital phase-locked loop (ADPLL) and the multi-cycle joint determination of the frequency deviation. The closed-loop regulation characteristics of the digital PID control are used to convert the clock deviation of the main / redundant ADC into a quantifiable error signal. The proportional coefficient K in the phase-locked loop transfer function is p Provides fast response to instantaneous phase difference, the integral term K i Eliminate the accumulated static error, differential term K d Predicting future deviation trends, the three work together to enable the system to operate over a wide bandwidth (f bandwidth ≥3f clk ) range to achieve sub-nanosecond clock alignment accuracy.

[0095] The conversion factor C of parts per million in the frequency deviation calculation formula δ(t) ppm The physical clock difference is unified into a dimensionless index, so that the deviation threshold δ under different operating frequencies is th It is horizontally comparable, a feature that is consistent with continuous N th The combination of the two-cycle decision logic can not only suppress the impact of single-cycle interference pulses, but also quickly respond to continuous offsets. When the system detects that the clock deviation exceeds the tolerance, the ADPLL reconfiguration instruction dynamically corrects the gain parameters and phase compensation of the phase-locked loop. This process forms a cascade optimization with the initial phase-locking process - the initial phase-locking ensures coarse synchronization, and the dynamic reconfiguration achieves fine calibration. This allows the main / redundant ADC to maintain a clock synchronization error of less than ±0.05% under harsh operating conditions such as high temperature (>85°C) and high electromagnetic interference (EMI>100V / m) of the motor controller. Compared with traditional analog phase-locked loop solutions, the synchronization accuracy is improved by more than 5 times.

[0096] The order of magnitude improvement in synchronization accuracy also directly affects the timing consistency of the sampled data, allowing the current / voltage data sampled by the dual ADCs to be fully aligned in the time domain, laying the foundation for the subsequent algorithm-level fusion of gradient prediction and harmonic analysis.

[0097] In the first technical solution, a step is adopted to dynamically adjust the compensation coefficient update period based on the harmonic energy change rate. This is achieved by linearly combining the harmonic energy change rate with the clock deviation to generate a dynamic update period. When a sudden harmonic change occurs, the system automatically shortens the analysis window, forcing the sampling frequency to increase to oversampling mode. The intervention of redundant ADC modules allows the local sampling rate to exceed hardware limitations. The value ranges of the weighting factors α and β are designed to balance harmonic sensitivity and clock stability requirements.

[0098] In the first technical solution, a voltage gradient prediction sequence is generated through specific steps. This allows the acceleration factor calculation module to capture the second-order variation characteristics of the voltage gradient in real time. This is then combined with the harmonic energy variation through nonlinear normalization to generate a mutation prediction coefficient. This not only reflects the instantaneous dynamic characteristics of voltage variation but also correlates with the macroscopic state of the system energy level.

[0099] When this coefficient exceeds a threshold, a window length compression mechanism immediately activates. Using a resampling algorithm, the data dimension is reduced by over 50% while preserving critical gradient extremes. This process synergizes deeply with the time series processing capabilities of the pre-trained LSTM model. The compressed gradient sequence removes noise interference while retaining time-domain features sufficient to characterize sudden changes. This enables the model to accurately predict voltage gradient evolution for the next M cycles, even with limited computing resources. Dynamic window length adjustment forms a negative feedback loop with model prediction: as prediction error increases, the sudden change prediction coefficient increases, triggering a more aggressive window compression strategy to increase the model iteration frequency; conversely, as prediction error decreases, the window length is extended to enhance noise suppression. This allows the system to maintain high-precision long-window monitoring during the gradual voltage change phase and automatically switch to a short-window, fast-response mode at critical sudden change points.

[0100] In addition, the combination of gradient sequence compression and resampling function further eliminates the problem of information mutation point loss caused by traditional dimensionality reduction methods, ensuring that key transient features can still be effectively captured by the memory units of the LSTM model after dimensionality reduction.

[0101] In summary, the multi-feature closed-loop linkage mechanism of this solution enables voltage gradient prediction to achieve the coordinated optimization effect of high real-time performance, strong noise resistance, and high accuracy under the constraints of limited hardware resources, providing a high-confidence pre-judgment basis for subsequent overvoltage protection decisions.

[0102] In the first technical solution, a multi-order digital filter loading strategy is adopted. In this way, an adaptive balance is established between harmonic suppression and real-time performance through a dynamic filter configuration mechanism coupled with multiple parameters. Specifically, the order dynamic adjustment strategy based on the logarithmic operation of harmonic energy forms a cascade response with the cutoff frequency calculation driven by the clock frequency. When the harmonic energy E(t) suddenly increases, the cutoff frequency is calculated by log2(E(t) / E base ) due to the nonlinear amplification effect, the filter order N filter (t) Rapidly climbs to a higher order state (such as jumping from 4th order to 8th order), at which time the cutoff frequency f c (t) = γf clk / N filter The inverse regulation characteristic of (t) automatically compresses the passband range to form a steep transition band characteristic, effectively suppressing the interference of high-frequency noise on the gradient prediction sequence; at the same time, the compensation coefficient update period T update The synchronous shortening of (t) results in a maximum permissible delay τ max (t) = λT update (t) decreases proportionally, triggering the filter type switching condition τ current >τ max(t), forcing the system to give priority to IIR filters to take advantage of their low group delay characteristics (typical IIR delay is 1 / 3 of FIR). This allows the system to maintain a noise attenuation capability of more than 20dB under strong interference conditions while compressing the filtering processing time to less than 50μs.

[0103] This three-dimensional linkage mechanism of energy, frequency, and delay enables the system to automatically switch to the "high-order IIR" mode when encountering broadband noise caused by transient overcurrent, completing 80% noise energy filtering within 12μs; while in steady-state operation, it defaults to the low-order FIR filter, utilizing its linear phase characteristics to avoid signal distortion and reduce power consumption by 40%. More importantly, this collaborative design pre-calculates the weight coefficient K p With N filter (t) matching relationship, avoiding transient response instability during the filter reconstruction process—when switching from FIR to IIR, the initial conditions of the IIR are initialized using the filter state at the previous moment, keeping the fluctuation amplitude of the transient process within ±2%, ensuring the continuity of the protection judgment criteria. This can effectively improve the signal-to-noise ratio of bus voltage gradient prediction and effectively shorten fault determination delay, achieving a dual breakthrough in noise suppression and real-time response.

[0104] In the first technical solution, a dynamic safety envelope is generated based on the rolling weighting of the bus voltage gradient prediction sequence and the historical extreme values. If the gradient extreme value in the preset continuous window breaks through the safety envelope, an overvoltage fault signal is generated. The specific steps adopted are as follows. In this way, a protection decision system with adaptive noise tolerance can be formed through the nonlinear interaction between the transient overvoltage factor, the statistical envelope construction and the continuous window judgment. The transient overvoltage factor τ(t) integrates the differential terms of the absolute value of the voltage gradient, the acceleration extreme value ratio and the gradient change rate, and cross-dimensionally associates the time domain mutation characteristics with the frequency domain energy trend, so that the transient interference of a single dimension (such as the gradient spike caused by the switching noise) is replaced by the steady-state parameters of other dimensions (such as α max The dynamic envelope V ub During the construction of (k), historical statistical data H sup (k) and the real-time transient factor c2·τ(k), so that the envelope depends on the statistical confidence interval (μ V +c1σ V ) maintains stability, and automatically switches to the expansion mode dominated by τ(t) during transient conditions to achieve adaptive adjustment of the protection threshold. The nested effect of continuous window judgment and safety margin coefficient c4 further enhances the reliability of the fault signal: when the voltage gradient When the envelope is first breached, the system doesn't immediately trigger protection. Instead, it continuously monitors the rolling weighted trend of gradient extremes within subsequent windows. The safety margin buffer introduced by c4∈[0,7,0,9] allows brief over-limit transients (such as surge voltage during motor startup) to be identified as tolerable events, while truly safety-threatening sustained overvoltages trigger protection due to the accumulation of consecutive window over-limits. This decouples the "false trip-missed detection" conflict caused by a single threshold comparison in traditional solutions.

[0105] In addition, this solution uses the rolling weighting of the gradient prediction sequence and the historical extreme value to predict the fault risk by its changing trend before the voltage reaches the physical limit. Specifically, the differential term in the transient overvoltage factor τ(t) Real-time capture of the acceleration of voltage gradient changes. When the bus voltage shows an abnormal upward trend (such as exponential voltage climb caused by power device breakdown), the differential term will increase significantly before the actual voltage value breaks through the traditional fixed threshold, triggering the envelope V ub (k) dynamic expansion. At this time, the real-time voltage gradient Compare the threshold c4·V with the expanded envelope ub The time difference between (k) and (k) is the core source of delay compression—the system identifies risks through the gradient change rate 50-100μs before the voltage reaches the critical point of physical damage. At the same time, the continuous window judgment mechanism does not simply wait for multiple cycles to confirm. Instead, it superimposes the gradient extreme value attenuation factor of the historical window (such as an exponential weight of 0.8) and the current over-limit state through rolling weighting. This allows true faults to meet the cumulative trigger conditions in the second or third window period, while short-term interference is automatically filtered out due to weight attenuation. In summary, the advance judgment based on trend prediction can achieve a paradigm shift from passive threshold response to active trend interception, thereby effectively shortening fault detection delay.

[0106] In the second aspect, the present invention provides a sampling implementation system suitable for rapid response of motor protection, comprising: a first acquisition module, a first trigger module, a first generation module

[0107] In a third aspect, the present invention provides an electronic device comprising one or more processors; a storage device on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any technical solution of the first aspect.

[0108] In a fourth aspect, the present invention provides a computer-readable storage medium and a computer program product, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any technical solution of the first aspect is implemented.

[0109] Among them, the technical effects brought about by any design method in the second to fourth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0110] Figure 1 A flow chart of a sampling implementation method for rapid response of motor protection provided by an embodiment of the present invention;

[0111] Figure 2 A schematic structural diagram of a sampling implementation system for rapid response of motor protection provided by an embodiment of the present invention;

[0112] Figure 3 is a schematic structural diagram of an electronic device suitable for implementing some embodiments of the present invention. DETAILED DESCRIPTION

[0113] Specific embodiments of the present invention will now be mentioned in detail. Although the present invention is described in conjunction with these specific embodiments, it should be appreciated that the present invention is not intended to be limited to these specific embodiments. On the contrary, these embodiments are intended to cover substitutions, changes, or equivalent embodiments that may be included within the spirit and scope of the invention defined by the claims. In the following description, a large number of specific details are set forth in order to provide a comprehensive understanding of the present invention. The present invention may be implemented without some or all of these specific details.

[0114] Application Overview: With the rapid development of electric vehicles and automated equipment, motor control technology is playing an increasingly important role in modern industry and transportation. In closed-loop motor control systems, real-time monitoring of key physical quantities such as motor phase current, bus voltage, and rotor position is a core requirement for ensuring safe and efficient motor operation. In electric vehicle applications, motor stability directly impacts the performance and safety of the entire vehicle. Therefore, developing an efficient motor protection mechanism is a significant technical challenge.

[0115] In related technologies, automotive motor controllers typically implement motor protection using software or hardware, but the reliability of these methods is often limited by sampling accuracy and speed. Specifically, during motor operation, common faults, such as phase current overcurrent and bus voltage overvoltage, often need to be detected and responded to quickly in a very short time. However, the sampling frequency of existing systems is generally low, usually related to the switching frequency of the power module, generally around 10kHz. This low sampling frequency is difficult to meet the needs of fault protection under rapidly changing motor operating conditions, and may cause the protection mechanism to respond slowly, thereby increasing the risk of motor damage.

[0116] In response to the above technical problems, the overall idea of ​​the technical solution provided by the present invention is as follows: a sampling implementation method suitable for fast response of motor protection is provided, which is applied to the motor closed-loop control system, including the following steps: collecting motor phase current and bus voltage, and sampling in parallel through independently configured main ADC module and redundant ADC module after anti-aliasing filtering, and synchronously performing the following operations based on the double buffer architecture: in the first buffer, the harmonic spectrum amplitude is updated point by point using sliding discrete Fourier transform, and the compensation coefficient update period is dynamically adjusted in combination with the harmonic energy change rate, and the convergence is constrained by the pre-trained time series prediction model; in the second buffer, based on the bus voltage fluctuation rate and historical frequency The spectral characteristics predefine the window switching threshold, and the gradient extreme value pre-screening mechanism is used to generate the voltage gradient prediction sequence, and the pre-trigger buffer mechanism is used to compensate for data mutations. When the harmonic spectrum amplitude or the voltage gradient prediction sequence exceeds the limit, the oversampling mode is triggered, the redundant ADC module is assigned to load the multi-order digital filter, and the independent hardware acceleration unit is enabled to parallelly process the harmonic compensation and gradient prediction. The dynamic safety envelope is generated based on the rolling weighting of the bus voltage gradient prediction sequence and the historical extreme values. If the gradient extreme value in the preset continuous window exceeds the safety envelope, an overvoltage fault signal is generated. In response to the overvoltage fault signal, the drive signal is locked through the hardware interrupt controller, and the hierarchical trigger logic of the multi-stage discharge circuit is started.

[0117] This method first utilizes parallel sampling of the primary and redundant ADCs to overcome the rate limitations of a single module. A dual-buffer architecture decouples data acquisition and processing. The first buffer uses a sliding discrete Fourier transform to achieve point-by-point updates of the harmonic spectrum, eliminating the window accumulation delay of traditional Fourier transforms. The compensation coefficient update cycle is dynamically adjusted by the harmonic energy change rate, automatically shortening the analysis cycle to microseconds in the event of a sudden current change. A pre-trained time series prediction model further constrains the algorithm's convergence direction, avoiding time-consuming iterative calculations. The second buffer predefines a window switching threshold based on historical spectral characteristics, targeting bus voltage fluctuations. A gradient extreme value pre-screening mechanism is used to generate a voltage gradient prediction sequence. A pre-trigger buffering mechanism reserves processing resources before data mutations occur.

[0118] When harmonic amplitude or voltage gradient exceeds a certain limit, oversampling mode is immediately triggered. Configurable multi-order digital filters are applied to redundant ADCs to increase local sampling density. Independent hardware acceleration units perform harmonic compensation and gradient prediction in parallel, bypassing the instruction cycle delays of traditional software processing. A dynamic safety envelope is generated based on a rolling weighted combination of the voltage gradient prediction sequence and historical extreme values. A continuous window decision mechanism filters out sporadic interference signals. Ultimately, a hardware interrupt controller directly blocks the drive signal and initiates graded discharge, compressing the fault response path from millisecond latency at the software level to nanosecond action at the hardware level. This deep integration of hardware resource reconfiguration and algorithm acceleration enables the system to achieve transient fault capture capabilities equivalent to hundreds of kHz at a base sampling rate of 10 kHz, effectively reducing protection response time and increasing speed. Furthermore, the dynamic envelope and pre-trigger mechanism effectively reduce the probability of false tripping, keeping it below industrial safety thresholds. This forms a full-link acceleration mechanism from data acquisition, real-time analysis, to protection execution.

[0119] After introducing the basic principles of this application, various non-limiting implementation methods of this application will be specifically introduced in conjunction with the accompanying drawings. Figure 1 The embodiment of the present application provides a sampling implementation method suitable for fast response of motor protection, which is applied to a motor closed-loop control system and includes the following steps:

[0120] S101: The motor phase current and bus voltage are collected and, after anti-aliasing filtering, sampled in parallel by the independently configured main ADC module and redundant ADC module. The following operations are performed synchronously based on the dual buffer architecture:

[0121] In the first buffer, the harmonic spectrum amplitude is updated point by point using a sliding discrete Fourier transform. The compensation coefficient update period is dynamically adjusted in combination with the harmonic energy change rate, and the convergence is constrained by a pre-trained time series prediction model.

[0122] In the second buffer, a window switching threshold is predefined based on the bus voltage fluctuation rate and historical spectrum characteristics, a gradient extreme value pre-screening mechanism is used to generate a voltage gradient prediction sequence, and a pre-trigger buffer mechanism is used to compensate for data mutations.

[0123] Specifically, in some embodiments, the execution subject of the sampling implementation method for motor protection rapid response can implement synchronous execution of the main ADC module and the redundant ADC module through the following steps:

[0124] The first step is to perform full digital phase-locked loop processing on the clock signals of the main ADC module and the redundant ADC module to obtain a synchronized clock signal. Its closed-loop transfer function is:

[0125]

[0126] Among them, K p Indicates the proportional control coefficient; K i Indicates the integral control coefficient; K d represents the differential control coefficient; ω n =2π·f bandwidth , expresses the natural frequency; f bandwidth Indicates the phase-locked loop bandwidth; f bandwidth ≥3f clk ;f clk Indicates the system main clock frequency;

[0127] The second step is to measure the frequency f m (k) and the reference frequency f r (t) Calculate the clock frequency deviation and obtain the deviation:

[0128]

[0129] Among them, C ppm Indicates the parts per million conversion factor, δ th Frequency deviation threshold;

[0130] The third step is to th The deviation of each cycle δ(t) is compared with the threshold value. When |δ(t)|>δ th When , ADPLL reconfiguration instructions are generated, where δ th is the continuous cycle determination threshold.

[0131] In this way, an adaptive clock synchronization system is constructed by combining the dynamic control mechanism of the all-digital phase-locked loop (ADPLL) with the multi-cycle determination of the frequency deviation. It uses the closed-loop regulation characteristics of the digital PID control to convert the clock deviation of the main / redundant ADC into a quantifiable error signal. p Provides fast response to instantaneous phase difference, the integral term K i Eliminate the accumulated static error, differential term K d Predicting future deviation trends, the three work together to enable the system to operate over a wide bandwidth (f bandwidth ≥3f clk ) range to achieve sub-nanosecond clock alignment accuracy.

[0132] The conversion factor C of parts per million in the frequency deviation calculation formula δ(t) ppm The physical clock difference is unified into a dimensionless index, so that the deviation threshold δ under different operating frequencies is th It is horizontally comparable, a feature that is consistent with continuous N thThe combination of the two-cycle decision logic can not only suppress the impact of single-cycle interference pulses, but also quickly respond to continuous offsets. When the system detects that the clock deviation exceeds the tolerance, the ADPLL reconfiguration instruction dynamically corrects the gain parameters and phase compensation of the phase-locked loop. This process forms a cascade optimization with the initial phase-locking process - the initial phase-locking ensures coarse synchronization, and the dynamic reconfiguration achieves fine calibration. This allows the main / redundant ADC to maintain a clock synchronization error of less than ±0.05% under harsh operating conditions such as high temperature (>85°C) and high electromagnetic interference (EMI>100V / m) of the motor controller. Compared with traditional analog phase-locked loop solutions, the synchronization accuracy is improved by more than 5 times.

[0133] The order of magnitude improvement in synchronization accuracy also directly affects the timing consistency of the sampled data, allowing the current / voltage data sampled by the dual ADCs to be fully aligned in the time domain, laying the foundation for the subsequent algorithm-level fusion of gradient prediction and harmonic analysis.

[0134] In some embodiments, the compensation coefficient update period can be dynamically adjusted in combination with the harmonic energy change rate by the following steps:

[0135] The first step is based on the harmonic amplitude sequence A k (t) and time interval Δt are used to calculate the energy change rate. The specific formula is as follows:

[0136]

[0137] Among them, N h is the harmonic analysis order, Δt≤T clk / 2, represents the time window step, T clk =1 / f clk , represents the system clock period;

[0138] In the second step, the energy change rate E(k) and the clock deviation δ(t) are linearly combined to obtain the compensation coefficient update period:

[0139] T update (t)=α·E(t)+β·δ(t)+T base

[0140] Among them, α∈(0.08, 0.15) represents the energy change weight factor; β∈(0.02, 0.05) represents the clock deviation weight factor; T base <T clk , indicating the basic update cycle;

[0141] The third step is to update the compensation coefficient period T update (t) performs threshold judgment processing, when T update (t)<T th When the sampling frequency is increased to K·fclk , where: K≥3, represents the oversampling multiple, T th Indicates the update period threshold.

[0142] In this way, by linearly combining the harmonic energy change rate and clock deviation to generate a dynamic update period, the system automatically shortens the analysis window when the harmonics suddenly change, forcing the sampling frequency to increase to oversampling mode. At this time, the intervention of the redundant ADC module enables the local sampling rate to break through the hardware limitation, and the value range design of the weight factors α and β balances the harmonic sensitivity and clock stability requirements.

[0143] In some embodiments, the voltage gradient prediction sequence may be generated by the following steps:

[0144] The first step is based on the voltage gradient sequence and compensation coefficient update period T update (t) is used to calculate the acceleration factor α(t). The specific formula is as follows:

[0145]

[0146] Among them, N w is the sliding window length; Δt≤T clk / 2, represents the time interval for gradient calculation;

[0147] In the second step, the acceleration factor α(t) and harmonic energy E(t) are normalized to obtain the mutation prediction coefficient β(t). The specific formula is as follows:

[0148]

[0149] in, Indicates the acceleration judgment threshold; E th =E rated ·T clk , represents the energy judgment threshold; f SW Indicates the switching frequency of the power device; E rated Indicates the rated working condition energy reference value; V rated Indicates the effective value of the motor's rated line voltage;

[0150] The third step is to perform threshold comparison on the mutation prediction coefficient β(t). When β(t)>β th When , adjust the window length to η·N W , otherwise unchanged; where: β th ∈[0.6, 0.8], represents the mutation judgment threshold, η·(0.3, 0.5), represents the window compression factor;

[0151] The fourth step is to calculate the compressed gradient sequence according to the window length The specific formula is as follows:

[0152]

[0153] Among them, N new =η·N w , represents the adjusted window length; Resample(·): resampling function, using linear interpolation algorithm;

[0154] Step 5: According to the compressed gradient sequence and the acceleration factor α(t), the voltage gradient prediction sequence is calculated The specific formula is as follows:

[0155]

[0156] Where: T clk , represents the system clock period, T clk =1 / f clk ;f clk is the main clock frequency; P: represents the historical data order; a i , b represents the parameters of the pre-trained time series prediction model, which is obtained through offline training of the LSTM network; M represents the number of prediction cycles; Represents the voltage gradient prediction sequence for the next M cycles.

[0157] In this way, the acceleration factor calculation module can capture the second-order change characteristics of the voltage gradient in real time, and generate a mutation prediction coefficient after nonlinear normalization fusion with the harmonic energy change. In this way, it not only reflects the instantaneous dynamic characteristics of the voltage change, but also relates to the macroscopic state of the system energy level.

[0158] When this coefficient exceeds a threshold, a window length compression mechanism immediately activates. Using a resampling algorithm, the data dimension is reduced by over 50% while preserving critical gradient extremes. This process synergizes deeply with the time series processing capabilities of the pre-trained LSTM model. The compressed gradient sequence removes noise interference while retaining time-domain features sufficient to characterize sudden changes. This enables the model to accurately predict voltage gradient evolution for the next M cycles, even with limited computing resources. Dynamic window length adjustment forms a negative feedback loop with model prediction: as prediction error increases, the sudden change prediction coefficient increases, triggering a more aggressive window compression strategy to increase the model iteration frequency; conversely, as prediction error decreases, the window length is extended to enhance noise suppression. This allows the system to maintain high-precision long-window monitoring during the gradual voltage change phase and automatically switch to a short-window, fast-response mode at critical sudden change points.

[0159] In addition, the combination of gradient sequence compression and resampling function further eliminates the problem of information mutation point loss caused by traditional dimensionality reduction methods, ensuring that key transient features can still be effectively captured by the memory units of the LSTM model after dimensionality reduction.

[0160] In summary, the multi-feature closed-loop linkage mechanism of this solution enables voltage gradient prediction to achieve the coordinated optimization effect of high real-time performance, strong noise resistance, and high accuracy under the constraints of limited hardware resources, providing a high-confidence pre-judgment basis for subsequent overvoltage protection decisions.

[0161] S102: When the harmonic spectrum amplitude or voltage gradient prediction sequence exceeds the limit, trigger the oversampling mode, allocate redundant ADC modules to load multi-order digital filters, and enable independent hardware acceleration units to process harmonic compensation and gradient prediction in parallel;

[0162] Specifically, in some embodiments, the loading strategy of the multi-order digital filter includes:

[0163] The first step is based on the harmonic energy E(t) and the reference energy E base Perform logarithmic operation to obtain the dynamic filter order N filter (t), the specific formula is as follows:

[0164]

[0165] Among them, E base , represents the reference energy calibration value; N base , represents the order of the basic filter; Clip(x, a, b), represents the clipping function, the output value is limited to the interval [a, b]; N min , represents the minimum filter order; N max , represents the maximum filter order;

[0166] The second step is to adjust the clock frequency f clk and filter order N filter (t) Perform proportional operation to obtain the cutoff frequency f c (t), the specific formula is as follows:

[0167]

[0168] Among them, γ≥1.2, represents the cutoff frequency adjustment coefficient;

[0169] The third step is to update the period T according to the compensation coefficient. update (t), calculate the maximum allowed delay τ max (t), the specific formula is as follows:

[0170] τ max (t) = λ·T update (t)

[0171] Where λ≤0.3 represents the delay tolerance coefficient;

[0172] The fourth step is to determine the cutoff frequency f c (t), the maximum allowed delay τ max (t) and the current filter delay τ current , generate filter configuration instruction set C filter (t), the specific logic is:

[0173]

[0174] in, <IIR,f c (t), K p >Indicates IIR filter type, cutoff frequency, and gain coefficient; <FIR,f c (t), N filter (t)> represents the FIR filter type, cutoff frequency, and order.

[0175] In this way, an adaptive balance is established between harmonic suppression and real-time performance through a dynamic filter configuration mechanism coupled with multiple parameters. Specifically, the order dynamic adjustment strategy based on the logarithmic operation of harmonic energy forms a cascade response with the cutoff frequency calculation driven by the clock frequency. When the harmonic energy E(t) suddenly increases, the harmonic energy E(t) is adjusted by log2(E(t) / E base ) due to the nonlinear amplification effect, the filter order N filter (t) Rapidly climbs to a higher order state (such as jumping from 4th order to 8th order), at which time the cutoff frequency f c (t) = γf clk / N filter The inverse regulation characteristic of (t) automatically compresses the passband range to form a steep transition band characteristic, effectively suppressing the interference of high-frequency noise on the gradient prediction sequence; at the same time, the compensation coefficient update period T update The synchronous shortening of (t) results in a maximum permissible delay τ max (t) = λT update (t) decreases proportionally, triggering the filter type switching condition τ current >τ max (t), forcing the system to give priority to IIR filters to take advantage of their low group delay characteristics (typical IIR delay is 1 / 3 of FIR). This allows the system to maintain a noise attenuation capability of more than 20dB under strong interference conditions while compressing the filtering processing time to less than 50μs.

[0176] This three-dimensional linkage mechanism of energy, frequency, and delay enables the system to automatically switch to the "high-order IIR" mode when encountering broadband noise caused by transient overcurrent, completing 80% noise energy filtering within 12μs; while in steady-state operation, it defaults to the low-order FIR filter, utilizing its linear phase characteristics to avoid signal distortion and reduce power consumption by 40%. More importantly, this collaborative design pre-calculates the weight coefficient K p With N filter (t) matching relationship, avoiding transient response instability during the filter reconstruction process—when switching from FIR to IIR, the initial conditions of the IIR are initialized using the filter state at the previous moment, keeping the fluctuation amplitude of the transient process within ±2%, ensuring the continuity of the protection judgment criteria. This can effectively improve the signal-to-noise ratio of bus voltage gradient prediction and effectively shorten fault determination delay, achieving a dual breakthrough in noise suppression and real-time response.

[0177] S103: Generate a dynamic safety envelope based on the bus voltage gradient prediction sequence and historical extreme value rolling weighting. If the gradient extreme value within a preset continuous window exceeds the safety envelope, generate an overvoltage fault signal;

[0178] Specifically, in some embodiments, a dynamic safety envelope may be generated based on a rolling weighted bus voltage gradient prediction sequence and historical extreme values ​​through the following steps. If the extreme gradient value within a preset continuous window exceeds the safety envelope, an overvoltage fault signal is generated:

[0179] The first step is based on the voltage gradient and the maximum allowed gradient Perform relative value calculation to obtain the transient overvoltage factor:

[0180]

[0181] in, Indicates the maximum allowable voltage gradient; α max Indicates the extreme value of acceleration;

[0182] The second step is to use the voltage statistic μ V (k), σ V (k) and transient overvoltage factor τ(k) generate the envelope curve, the specific formula is as follows:

[0183]

[0184] Among them, μ V (k): window voltage mean; σ V (k): window voltage standard deviation; H sup(k): upper bound of historical statistical data; c1≥3: upper envelope amplification coefficient; c2∈[0.4, 0.6]: transient factor weight coefficient; c3≥2: lower envelope reduction coefficient; V ub (k): upper envelope; V lb (k): lower envelope;

[0185] The third step is to convert the real-time voltage gradient With the upper envelope V ub (k) Perform proportional comparison processing, when When , an overvoltage fault signal is generated, where c4∈[0.7, 0.9]: safety margin coefficient.

[0186] In this way, a protection decision system with adaptive noise tolerance can be formed through the nonlinear interaction between transient overvoltage factor, statistical envelope construction and continuous window judgment. The transient overvoltage factor τ(t) combines the differential terms of the absolute value of the voltage gradient, the ratio of the acceleration extreme value and the gradient change rate, and cross-dimensionally associates the time domain mutation characteristics with the frequency domain energy trend, so that the transient interference in a single dimension (such as the gradient spike caused by switching noise) is replaced by the steady-state parameters of other dimensions (such as α max The dynamic envelope V ub During the construction of (k), historical statistical data H sup (k) and the real-time transient factor c2·τ(k), so that the envelope depends on the statistical confidence interval (μ V +c1σ V ) maintains stability, and automatically switches to the expansion mode dominated by τ(t) during transient conditions to achieve adaptive adjustment of the protection threshold. The nested effect of continuous window judgment and safety margin coefficient c4 further enhances the reliability of the fault signal: when the voltage gradient When the envelope is first breached, the system doesn't immediately trigger protection. Instead, it continuously monitors the rolling weighted trend of the gradient extremes within subsequent windows. The safety margin buffer introduced by c4∈[0.7,0.9] allows brief over-limit transients (such as surge voltage during motor startup) to be identified as tolerable events, while truly safety-threatening sustained overvoltages trigger protection due to the accumulation of consecutive window over-limits. This decouples the "false trip-missed detection" conflict caused by a single threshold comparison in traditional solutions.

[0187] In addition, this solution uses the rolling weighting of the gradient prediction sequence and the historical extreme value to predict the fault risk by its changing trend before the voltage reaches the physical limit. Specifically, the differential term in the transient overvoltage factor τ(t) Real-time capture of the acceleration of voltage gradient changes. When the bus voltage shows an abnormal upward trend (such as exponential voltage climb caused by power device breakdown), the differential term will increase significantly before the actual voltage value breaks through the traditional fixed threshold, triggering the envelope V ub (k) dynamic expansion. At this time, the real-time voltage gradient Compare the threshold c4·V with the expanded envelope ub The time difference between (k) and (k) is the core source of delay compression—the system identifies risks through the gradient change rate 50-100μs before the voltage reaches the critical point of physical damage. At the same time, the continuous window judgment mechanism does not simply wait for multiple cycles to confirm. Instead, it superimposes the gradient extreme value attenuation factor of the historical window (such as an exponential weight of 0.8) and the current over-limit state through rolling weighting. This allows true faults to meet the cumulative trigger conditions in the second or third window period, while short-term interference is automatically filtered out due to weight attenuation. In summary, the advance judgment based on trend prediction can achieve a paradigm shift from passive threshold response to active trend interception, thereby effectively shortening fault detection delay.

[0188] S104: In response to the overvoltage fault signal, the drive signal is blocked through the hardware interrupt controller, and the hierarchical triggering logic of the multi-stage discharge circuit is started.

[0189] Specifically, in some embodiments, the step of starting the hierarchical triggering logic of the multi-stage discharge circuit includes:

[0190] The first step is to calculate the real-time voltage gradient The discharge weight is obtained by weighting the transient overvoltage factor τ(t):

[0191]

[0192] Among them, V safe =1.2V rated , represents the safety voltage threshold; τ safe =1.2, indicating the safety transient factor threshold; K indicates the transient factor weight coefficient;

[0193] The second step is to perform multi-level threshold judgment processing on the discharge weight w(t) and generate the discharge level instruction:

[0194]

[0195] Among them, L1: primary discharge mode; L2: intermediate discharge mode; L3: advanced discharge mode; w th1 is the preset primary threshold; w th2 To preset advanced thresholds;

[0196] The third step is to perform threshold judgment on the discharge level L(t). When L(t)≥Lth When the multi-level trigger instruction is generated, the compensation coefficient update cycle is shortened to ρ·T nom and IIR filter fast channel activation operation, where L th is the preset switching action threshold; ρ≤0.3, represents the cycle compression factor; T nom is the nominal update period.

[0197] See also Figure 2 Based on the same inventive concept as the sampling implementation method for rapid response of motor protection in the aforementioned embodiment, an embodiment of the present invention provides a sampling implementation system for rapid response of motor protection, comprising:

[0198] The first acquisition module 201 is used to collect motor phase current and bus voltage. After anti-aliasing filtering, the current and bus voltage are sampled in parallel by an independently configured main ADC module and a redundant ADC module. The following operations are performed synchronously based on a dual-buffer architecture: in the first buffer, the harmonic spectrum amplitude is updated point by point using a sliding discrete Fourier transform, the compensation coefficient update period is dynamically adjusted based on the harmonic energy change rate, and the convergence is constrained by a pre-trained time series prediction model. In the second buffer, a window switching threshold is predefined based on the bus voltage fluctuation rate and historical spectrum characteristics, a gradient extreme value pre-screening mechanism is used to generate a voltage gradient prediction sequence, and a pre-trigger buffer mechanism is used to compensate for data mutations.

[0199] The first trigger module 202 is configured to trigger an oversampling mode when the harmonic spectrum amplitude or voltage gradient prediction sequence exceeds a limit, allocate redundant ADC modules to load multi-order digital filters, and enable independent hardware acceleration units to process harmonic compensation and gradient prediction in parallel;

[0200] The first generating module 203 is configured to generate a dynamic safety envelope based on a bus voltage gradient prediction sequence and a rolling weighted historical extreme value, and to generate an overvoltage fault signal if the extreme gradient value within a preset continuous window exceeds the safety envelope;

[0201] The second trigger module 204 is configured to block the driving signal through the hardware interrupt controller in response to the overvoltage fault signal and start the hierarchical triggering logic of the multi-stage discharge circuit.

[0202] In some embodiments, the first acquisition module 201 is specifically configured to:

[0203] The clock signals of the main ADC module and the redundant ADC module are processed by a fully digital phase-locked loop to obtain a synchronous clock signal. The closed-loop transfer function is:

[0204]

[0205] Among them, K p Indicates the proportional control coefficient; Ki Indicates the integral control coefficient; K d represents the differential control coefficient; ω n =2π·f bandwidth , expresses the natural frequency; f bandwidth Indicates the phase-locked loop bandwidth f bandwidth ≥3f clk ;f clk Indicates the system main clock frequency;

[0206] For the measurement frequency f m (t) and the reference frequency f r (t) Calculate the clock frequency deviation and obtain the deviation:

[0207]

[0208] Among them, C ppm Indicates the parts per million conversion factor, δ th Frequency deviation threshold;

[0209] For continuous N th The deviation of each cycle δ(t) is compared with the threshold value. When |δ(t)|>δ th When , ADPLL reconfiguration instructions are generated, where δ th is the continuous cycle determination threshold.

[0210] In some embodiments, the first acquisition module 201 is further configured to:

[0211] Based on the harmonic amplitude sequence A k (t) and time interval Δt are used to calculate the energy change rate. The specific formula is as follows:

[0212]

[0213] Among them, N h is the harmonic analysis order, Δt≤T clk / 2, represents the time window step, T clk =1 / f clk , represents the system clock period;

[0214] The energy change rate E(t) and the clock deviation δ(t) are linearly combined to obtain the compensation coefficient update period:

[0215] T update (t)=α·E(t)+β·δ(t)+T base

[0216] Among them, α∈(0.08, 0.15) represents the energy change weight factor; β∈(0.02, 0.05) represents the clock deviation weight factor; T base<T clk , indicating the basic update cycle;

[0217] Update period T for compensation coefficient update (t) performs threshold judgment processing, when T update (t)<T th When the sampling frequency is increased to K·f clk , where: K≥3, represents the oversampling multiple, T th Indicates the update period threshold.

[0218] In some embodiments, the first acquisition module 201 is further configured to:

[0219] Based on voltage gradient sequence and compensation coefficient update period T update (t) is used to calculate the acceleration factor α(t). The specific formula is as follows:

[0220]

[0221] Among them, N w is the sliding window length; Δt≤T clk / 2, represents the gradient calculation time interval;

[0222] The acceleration factor α(t) and harmonic energy E(t) are normalized to obtain the mutation prediction coefficient β(t). The specific formula is as follows:

[0223]

[0224] in, Indicates the acceleration judgment threshold; E th =E rated ·T clk , represents the energy judgment threshold; f sw Indicates the switching frequency of the power device; E rated Indicates the rated working condition energy reference value; V rated Indicates the effective value of the motor's rated line voltage;

[0225] The mutation prediction coefficient β(t) is subjected to threshold comparison processing. When β(t)>β th When , adjust the window length to η·N w , otherwise unchanged; where: β th ∈[0.6, 0.8], represents the mutation judgment threshold, η∈(0.3, 0.5), represents the window compression factor;

[0226] Calculate the compressed gradient sequence according to the window length The specific formula is as follows:

[0227]

[0228] Among them, N new =η·N W , represents the adjusted window length; Resample(·): resampling function, using linear interpolation algorithm;

[0229] According to the compressed gradient sequence and the acceleration factor a(t), the voltage gradient prediction sequence is calculated The specific formula is as follows:

[0230]

[0231] Where: T clk , represents the system clock period, T clk =1 / f clk ;f clk is the main clock frequency; P: represents the historical data order; a i , b represents the parameters of the pre-trained time series prediction model, which is obtained through offline training of the LSTM network; M represents the number of prediction cycles; Represents the voltage gradient prediction sequence for the next M cycles.

[0232] In some embodiments, the first trigger module 202 is specifically configured to:

[0233] Based on harmonic energy E(t) and reference energy E base Perform logarithmic operation to obtain the dynamic filter order N fiter (t), the specific formula is as follows:

[0234]

[0235] Among them, E base , represents the reference energy calibration value; N base , represents the order of the basic filter; Clip(x, a, b), represents the clipping function, the output value is limited to the interval [a, b]; N min , represents the minimum filter order; N max , represents the maximum filter order;

[0236] For clock frequency f clk and filter order N filter (t) Perform proportional operation to obtain the cutoff frequency f c (t), the specific formula is as follows:

[0237]

[0238] Among them, γ≥1.2, represents the cutoff frequency adjustment coefficient;

[0239] According to the compensation coefficient update period T update (t), calculate the maximum allowed delay τ max (t), the specific formula is as follows:

[0240] τ max (t) = λ·T update (t)

[0241] Where λ≤0.3 represents the delay tolerance coefficient;

[0242] According to the cut-off frequency f c (t), the maximum allowed delay τ max (t) and the current filter delay τ current , generate filter configuration instruction set C filter (t), the specific logic is:

[0243]

[0244] in, <IIR,f c (t), K p >Indicates IIR filter type, cutoff frequency, and gain coefficient; <FIR,f c (t), N filter (t)> represents the FIR filter type, cutoff frequency, and order.

[0245] In some embodiments, the first generating module 203 is specifically configured to:

[0246] Based on voltage gradient and the maximum allowed gradient Perform relative value calculation to obtain the transient overvoltage factor:

[0247]

[0248] in, Indicates the maximum allowable voltage gradient; α max Indicates the extreme value of acceleration;

[0249] According to the voltage statistic μ V (k), σ V (k) and transient overvoltage factor τ(k) generate the envelope curve, the specific formula is as follows:

[0250]

[0251] Among them, μ V (k): window voltage mean; σ V (k): window voltage standard deviation; H sup(k): upper bound of historical statistical data; c1≥3: upper envelope amplification coefficient; c2∈[0.4,0.6]: transient factor weight coefficient; c3≥2: lower envelope reduction coefficient; V ub (k): upper envelope; V lb (k): lower envelope;

[0252] The real-time voltage gradient With the upper envelope V ub (k) Perform proportional comparison processing, when When , an overvoltage fault signal is generated, where c4∈[0.7,0.9]: safety margin coefficient.

[0253] In some embodiments, the second trigger module 204 is specifically configured to:

[0254] Real-time voltage gradient The discharge weight is obtained by weighting the transient overvoltage factor τ(t):

[0255]

[0256] Among them, V safe =1.2V rated , represents the safety voltage threshold; τ safe =1.2, indicating the safety transient factor threshold; K indicates the transient factor weight coefficient;

[0257] Perform multi-level threshold judgment processing on the discharge weight w(t) to generate the discharge level instruction:

[0258]

[0259] Among them, L1: primary discharge mode; L2: intermediate discharge mode; L3: advanced discharge mode; w th1 is the preset primary threshold; w th2 To preset advanced thresholds;

[0260] Perform threshold judgment on the discharge level L(t). When L(t)≥L th When the multi-level trigger instruction is generated, the compensation coefficient update cycle is shortened to ρ·T nom and IIR filter fast channel activation operation, where L th is the preset switching action threshold; ρ≤0.3, represents the cycle compression factor; T nom is the nominal update period.

[0261] It is understandable that the modules and references in the sampling implementation system for motor protection rapid response are Figure 1The steps in the sampling implementation method for rapid response of motor protection described above correspond to each other. Therefore, the operations, features and beneficial effects described above for the method are also applicable to the sampling implementation system for rapid response of motor protection and the modules contained therein, and will not be repeated here.

[0262] See also Figure 3 Based on the inventive concept of a sampling implementation method suitable for rapid response of motor protection in the aforementioned embodiment, an embodiment of the present invention provides an electronic device. The electronic device may include but is not limited to mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), etc., and fixed terminals such as digital TVs, desktop computers, etc. The electronic device includes a processing device 301 (such as a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to the program stored in ROM 302 (read-only memory) or the program loaded from storage device 308 into RAM 303 (random access memory). Various programs and data required for the operation of the electronic device are also stored in RAM 303. The processing device 301, ROM 302 and RAM 303 are connected to each other via a bus 304. The input / output interface (i.e., I / O interface 305) is also connected to the bus 304.

[0263] Typically, the following devices may be connected to the I / O interface 305: an input device 306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 309. The communication device 309 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data.

[0264] In particular, according to some embodiments of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, some embodiments of the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. In some such embodiments, the computer program can be downloaded and installed from the network via the communication device 309, or installed from the storage device 308, or installed from the ROM 302. When the computer program is executed by the processing device 301, the above-mentioned functions defined in the method of some embodiments of the present application are performed.

[0265] It should be noted that the computer-readable medium described in some embodiments of the present invention may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. The computer-readable storage medium may be an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In some embodiments of the present application, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or component. In some embodiments of the present application, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0266] In some embodiments, the client and server can communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol), and can be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an adhoc peer-to-peer network), as well as any currently known or future developed network.

[0267] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device. The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device can implement the method steps of any of the above technical solutions.

[0268] Computer program code for performing the operations of some embodiments of the present application can be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0269] The flow charts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0270] The units or modules described in some embodiments of the present application may be implemented in software or hardware, wherein the names of these units or modules do not constitute limitations on the modules themselves.

[0271] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0272] Some embodiments of the present invention further provide a computer program product, including a computer program, which, when executed by a processor, implements any of the above-mentioned sampling implementation methods applicable to rapid response of motor protection.

[0273] Although the present invention has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made thereto. Therefore, such modifications and improvements, without departing from the spirit of the present invention, are intended to be within the scope of protection claimed herein.

Claims

1. A sampling implementation method suitable for fast response of motor protection, applied to motor closed-loop control system, characterized in that: The following steps are involved: (1) Collect motor phase current and bus voltage, and after anti-aliasing filtering, sample them in parallel through the independently configured main ADC module and redundant ADC module; (2) Based on the double buffer architecture, the following operations are performed synchronously: In the first buffer, the harmonic spectrum amplitude is updated point by point using a sliding discrete Fourier transform. The compensation coefficient update period is dynamically adjusted in combination with the harmonic energy change rate, and the convergence is constrained by a pre-trained time series prediction model. In the second buffer, a window switching threshold is predefined based on the bus voltage fluctuation rate and historical spectrum characteristics, a gradient extreme value pre-screening mechanism is used to generate a voltage gradient prediction sequence, and a pre-trigger buffer mechanism is used to compensate for data mutations. (3) When the harmonic spectrum amplitude or voltage gradient prediction sequence exceeds the limit, the oversampling mode is triggered, the redundant ADC modules are assigned to load multi-order digital filters, and the independent hardware acceleration unit is enabled to process harmonic compensation and gradient prediction in parallel; (4) Generate a dynamic safety envelope based on the bus voltage gradient prediction sequence and the rolling weighting of historical extreme values. If the gradient extreme value within the preset continuous window breaks through the safety envelope, an overvoltage fault signal is generated; (5) In response to the overvoltage fault signal, the drive signal is blocked through the hardware interrupt controller, and the hierarchical trigger logic of the multi-stage discharge circuit is started.

2. The sampling implementation method for rapid response of motor protection according to claim 1, characterized in that: The main ADC module and the redundant ADC module are synchronously executed by the following steps: (1) The clock signals of the main ADC module and the redundant ADC module are processed by a fully digital phase-locked loop to obtain a synchronous clock signal. Its closed-loop transfer function is: Among them, K p Indicates the proportional control coefficient; K i Indicates the integral control coefficient; L d represents the differential control coefficient; ω n =2π·f bandwidth , expresses the natural frequency; f bandwidth Indicates the phase-locked loop bandwidth; f bandwidth ≥3f clk ;f clk Indicates the system main clock frequency; (2) For the measurement frequency f m (t) and the reference frequency f r (t) Calculate the clock frequency deviation and obtain the deviation: Among them, C ppm Indicates the parts per million conversion factor; (3) For continuous N th The deviation of each cycle δ(t) is compared with the threshold value. When |δ(t)|>δ th When , ADPLL reconfiguration instructions are generated, where δ th is the continuous cycle determination threshold.

3. The sampling implementation method for rapid response of motor protection according to claim 1, characterized in that: The steps of dynamically adjusting the compensation coefficient update period in combination with the harmonic energy change rate are as follows: (1) Based on the harmonic amplitude sequence A k (t) and time interval Δt are used to calculate the energy change rate. The specific formula is as follows: Among them, N h is the harmonic analysis order, Δt≤T clk / 2, represents the time window step, T clk =1 / f clk , represents the system clock period; (2) Perform linear combination processing on the energy change rate E(t) and the clock deviation δ(t) to obtain the compensation coefficient update period: T update (t)=α·E(t)+β·δ(t)+T base Among them, α∈(0.08, 0.15) represents the energy change weight factor; β∈(0.02, 0.05) represents the clock deviation weight factor; T base <T clk , indicating the basic update cycle; (3) Update period T for compensation coefficient update (t) performs threshold judgment processing, when T update (t)<T th When the sampling frequency is increased to K·f clk , where: K≥3, represents the oversampling multiple, T th Indicates the update period threshold.

4. The sampling implementation method for rapid response of motor protection according to claim 1, characterized in that: The voltage gradient prediction sequence is generated by the following steps: (1) Based on voltage gradient sequence and compensation coefficient update period T update (t) is used to calculate the acceleration factor α(t). The specific formula is as follows: Among them, N w is the sliding window length; Δt≤T clk / 2, represents the gradient calculation time interval; (2) The acceleration factor α(t) and harmonic energy E(t) are normalized to obtain the mutation prediction coefficient β(t). The specific formula is as follows: in, Indicates the acceleration judgment threshold; E th =E rated ·T clk , represents the energy judgment threshold; f sw Indicates the switching frequency of the power device; E rated Indicates the rated working condition energy reference value; V rated Indicates the effective value of the motor's rated line voltage; (3) Perform threshold comparison on the mutation prediction coefficient β(t). When β(t)>β th When , adjust the window length to η·N w , otherwise unchanged; where: β th ∈[0.6, 0.8], represents the mutation judgment threshold, η∈(0.3, 0.5), represents the window compression factor; (4) Calculate the compressed gradient sequence according to the window length The specific formula is as follows: Among them, N new =η·N w , represents the adjusted window length; Resample(·): resampling function, using linear interpolation algorithm; (5) According to the compression gradient sequence and the acceleration factor α(t), the voltage gradient prediction sequence is calculated The specific formula is as follows: Where: T clk , represents the system clock period, T clk =1 / f clk ;f clk is the main clock frequency; P: represents the historical data order; a i , b represents the parameters of the pre-trained time series prediction model, which is obtained through offline training of the LSTM network; M represents the number of prediction cycles; Represents the voltage gradient prediction sequence for the next M cycles.

5. The sampling implementation method for rapid response of motor protection according to claim 1, characterized in that: The loading strategy of the multi-order digital filter includes: (1) Based on harmonic energy E(t) and reference energy E base Perform logarithmic operation to obtain the dynamic filter order N filter (t), the specific formula is as follows: Among them, E base , represents the reference energy calibration value; N base , represents the order of the basic filter; Clip(x, a, b), represents the clipping function, the output value is limited to the interval [a, b]; N min , represents the minimum filter order; N max , represents the maximum filter order; (2) For clock frequency f clk and filter order N filter (t) Perform proportional operation to obtain the cutoff frequency f c (t), the specific formula is as follows: Among them, γ≥1.2, represents the cutoff frequency adjustment coefficient; (3) Update period T according to the compensation coefficient update (t), calculate the maximum allowed delay τ max (t), the specific formula is as follows: t max (t)=λ·T update (t) Where λ≤0.3 represents the delay tolerance coefficient; (4) According to the cut-off frequency f c (t), the maximum allowed delay τ max (t) and the current filter delay τ current , generate filter configuration instruction set C filter (t), the specific logic is: in, <IIR,f c (t), K p >Indicates IIR filter type, cutoff frequency, and gain coefficient; <FIR,f c (t),N filter (t)> represents the FIR filter type, cutoff frequency, and order.

6. The sampling implementation method for rapid response of motor protection according to claim 1, characterized in that: A dynamic safety envelope is generated based on the rolling weighting of the busbar voltage gradient prediction sequence and historical extreme values. If the gradient extreme value within a preset continuous window exceeds the safety envelope, an overvoltage fault signal is generated, including the following steps: (1) Based on voltage gradient and the maximum allowed gradient Perform relative value calculation to obtain the transient overvoltage factor: in, Indicates the maximum allowable voltage gradient; α max Indicates the extreme value of acceleration; (2) According to the voltage statistic μ V (k), σ V (k) and transient overvoltage factor τ(k) generate the envelope curve, the specific formula is as follows: Among them, μ V (k): window voltage mean; σ V (k): window voltage standard deviation; H sup (k): upper bound of historical statistical data; c1≥3: upper envelope amplification coefficient; c2∈[0.4, 0.6]: transient factor weight coefficient; c3≥2: lower envelope reduction coefficient; V ub (k): upper envelope; V lb (k): lower envelope; (3) Real-time voltage gradient With the upper envelope V ub (k) Perform proportional comparison processing, when When , an overvoltage fault signal is generated, where c4∈[0.7,0.9]: safety margin coefficient.

7. A sampling implementation system suitable for rapid response of motor protection, used in the method according to any one of claims 1 to 6, characterized in that: include: The first acquisition module is used to collect motor phase current and bus voltage. After anti-aliasing filtering, the samples are collected in parallel by an independently configured main ADC module and a redundant ADC module. The following operations are performed synchronously based on a dual-buffer architecture: In the first buffer, the harmonic spectrum amplitude is updated point by point using a sliding discrete Fourier transform. The compensation coefficient update period is dynamically adjusted based on the harmonic energy change rate, and the convergence is constrained by a pre-trained time series prediction model. In the second buffer, a window switching threshold is predefined based on the bus voltage fluctuation rate and historical spectrum characteristics, and a gradient extreme value pre-screening mechanism is used to generate a voltage gradient prediction sequence. A pre-trigger buffer mechanism is used to compensate for data mutations. The first trigger module is used to trigger the oversampling mode when the harmonic spectrum amplitude or voltage gradient prediction sequence exceeds the limit, allocate redundant ADC modules to load multi-order digital filters, and enable independent hardware acceleration units to parallelly process harmonic compensation and gradient prediction; The first generation module is used to generate a dynamic safety envelope based on the bus voltage gradient prediction sequence and the rolling weight of historical extreme values. If the gradient extreme value in the preset continuous window exceeds the safety envelope, an overvoltage fault signal is generated; The second trigger module is configured to block the driving signal through the hardware interrupt controller in response to the overvoltage fault signal and start the hierarchical trigger logic of the multi-stage discharge circuit.

8. The sampling implementation system suitable for rapid response of motor protection according to claim 7, characterized in that: The step of starting the hierarchical triggering logic of the multi-stage discharge circuit includes: (1) Real-time voltage gradient The discharge weight is obtained by weighting the transient overvoltage factor τ(t): Among them, V safe =1.2V rated , represents the safety voltage threshold; τ safe =1.2, indicating the safety transient factor threshold; K indicates the transient factor weight coefficient; (2) Perform multi-level threshold judgment processing on the discharge weight w(t) to generate the discharge level instruction: Among them, L1: primary discharge mode; L2: intermediate discharge mode; L3: advanced discharge mode; w th1 is the preset primary threshold; w th2 To preset advanced thresholds; (3) Perform threshold judgment on the discharge level L(t). When L(t)≥L th When the multi-level trigger instruction is generated, the compensation coefficient update cycle is shortened to ρ·T nom and IIR filter fast channel activation operation, where L th is the preset switching action threshold; ρ≤0.3, represents the cycle compression factor; T nom is the nominal update period.

9. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 6.

10. A computer-readable storage medium and a computer program product, characterized in that: The computer-readable storage medium stores a computer program, which implements the method according to any one of claims 1 to 6 when executed by a processing device.

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