An anti-radiation hardened numerically controlled oscillator, clock data recovery circuit, and device

Abstract

The application discloses an anti-radiation reinforced digital controlled oscillator, a clock data recovery circuit and equipment. The anti-radiation reinforced digital controlled oscillator is connected with an anti-radiation reinforced circuit unit between a digital-analog converter (DAC) and a voltage controlled oscillator (VCO). The anti-radiation reinforced circuit unit comprises a voltage replication unit and a multiplexer. The voltage replication unit is used for replicating a control voltage signal output by the digital-analog converter (DAC) and generating a replication voltage signal to be sent to the multiplexer. When the digital-analog converter (DAC) is subjected to single particle bombardment, the output of the multiplexer is switched from the control voltage signal to the replication voltage signal. The application aims to solve the problem that the traditional DCO type clock data recovery circuit is easily affected by single particles when running in a radiation environment, resulting in single particle function interruption and causing space task failure. The anti-radiation reinforced ability of the DCO type clock data recovery circuit when running in a radiation environment is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to an anti-radiation reinforced digital controlled oscillator, clock data recovery circuit and equipment. BACKGROUND

[0002] Clock and Data Recovery circuit is the core sub-module in serial communication interface. DCO (Digital-Controlled Oscillator) type clock data recovery circuit is a common clock data recovery circuit. The traditional DCO type clock data recovery circuit includes an analog-to-digital converter, a serial-to-parallel module, a Bang-Bang phase detector and a digital controlled oscillator (Digital-Controlled Oscillator). The digital controlled oscillator includes a digital-to-analog converter (Digital-to-Analog Converter, DAC) and a voltage controlled oscillator (Voltage Controlled Oscillator, VCO). The working process of the traditional digital controlled oscillator type clock data recovery circuit is as follows: the analog-to-digital converter samples the data information and the edge information of the high-speed signal, the serial-to-parallel module parallelizes the collected high-speed signal and reduces the rate at the same time, the Bang-Bang phase detector phase detects the data information and the edge information, and obtains whether the sampling point of the clock at this time is leading or lagging, and finally adjusts the phase of the clock through negative feedback, so that the sampling point of the clock is at the best position in the center of the sampling window, so as to recover the data and the clock. However, the traditional DCO type clock data recovery circuit is susceptible to single particle effects and causes single particle function interruption when running in a radiation environment, resulting in a space mission failure. The most sensitive module is the digital-to-analog converter in the digital controlled oscillator. SUMMARY

[0003] The technical problem to be solved by the present application is: in view of the above problems of the prior art, an anti-radiation reinforced digital controlled oscillator, clock data recovery circuit and equipment are provided. The present application aims to solve the problem that the traditional digital controlled oscillator is susceptible to single particle effects and causes single particle function interruption when running in a radiation environment, resulting in a space mission failure, and to improve the anti-radiation reinforcement capability of the digital controlled oscillator when running in a radiation environment.

[0004] In order to solve the above technical problems, the technical scheme adopted by the present application is:

[0005] The application discloses a kind of anti-radiation reinforced digital control oscillator, including digital-analog converter DAC and voltage-controlled oscillator VCO, anti-radiation reinforced circuit unit is connected between the digital-analog converter DAC and voltage-controlled oscillator VCO, the anti-radiation reinforced circuit unit includes voltage replication unit and multiplexer MUX, control voltage signal Vctrl0 output by the digital-analog converter DAC is sent into the input pin of multiplexer MUX and the input end of voltage replication unit respectively, the voltage replication unit is used to replicate control voltage signal Vctrl0, and generates copy voltage signal Vctrl1 and is sent into another input pin of multiplexer MUX, and when digital-analog converter DAC is subjected to single particle bombardment, the output of multiplexer MUX is switched from control voltage signal Vctrl0 to copy voltage signal Vctrl1.

[0006] Optionally, the voltage replication unit includes a transmission gate TG, a capacitor C1, an operational amplifier AMP, two comparators COMP1 and COMP2, an XOR gate and a delay module delay, control voltage signal Vctrl0 output by the digital-analog converter DAC is sequentially sent through the transmission gate TG, the capacitor C1 is grounded, the intermediate node between the transmission gate TG and the capacitor C1 is used as the output end of copy voltage signal Vctrl1 and another input pin of multiplexer MUX, and the operational amplifier AMP, high voltage VH and low voltage VL are obtained through the operational amplifier AMP and its feedback circuit, and are compared with control voltage signal Vctrl0 through comparators COMP1 and COMP2 respectively, the two comparison results are input into the XOR gate to obtain selection signal S1 of multiplexer MUX, and selection signal S1 is connected to the control end of the transmission gate TG after being delayed by the delay module delay.

[0007] Optionally, the feedback circuit includes a switch and three resistors connected in series between the power supply and the ground, one end of the switch is connected to the power supply, the other end is sequentially connected to the ground through the three resistors, the control end of the switch is connected to the output end of the operational amplifier AMP, the intermediate node between the first resistor and the switch is used as the output end of high voltage VH, the intermediate node between the first two resistors is used as the negative feedback output end and connected to the negative feedback input end of the operational amplifier AMP, and the intermediate node between the last two resistors is used as the output end of low voltage VL.

[0008] Optionally, the resistance ratio of the three resistors is 1:1:79, and the resistor with larger resistance value is located at the ground side, so that the voltage of high voltage VH is 81 / 80×Vctrl1, and the voltage of low voltage VL is 79 / 80×Vctrl1, wherein Vctrl1 is copy voltage signal.

[0009] Further, the application also provides a clock data recovery circuit, comprising the clock data recovery circuit unit with the digitally controlled oscillator, wherein the digitally controlled oscillator is the anti-radiation reinforced digitally controlled oscillator.

[0010] Optionally, the clock data recovery circuit unit comprises an analog-to-digital converter, a serial-to-parallel module and a Bang-Bang phase detector, wherein the output clock of the digitally controlled oscillator is used as the clock of the analog-to-digital converter to make the analog-to-digital converter sample the data information and the edge information of the high-speed signal, the serial-to-parallel module is used to convert the serial high sampling signal into a parallel analog signal to realize the signal speed reduction output, and the Bang-Bang phase detector is used to phase detect the data information and the edge information in the output parallel analog signal to obtain whether the sampling point of the clock at this time is leading or lagging and output the phase detection code to the digitally controlled oscillator.

[0011] Further, the application also provides an electronic device, comprising a device body and a circuit module arranged in the device body, wherein the circuit module comprises the clock data recovery circuit.

[0012] Compared with the prior art, the application mainly has the following beneficial effects: the anti-radiation reinforced circuit unit composed of the voltage replication unit and the multiplexer is used to realize the radiation reinforcement design of the digitally controlled oscillator, the anti-radiation reinforced circuit unit is connected between the digital-to-analog converter DAC and the voltage-controlled oscillator VCO, the anti-radiation reinforced circuit unit comprises the voltage replication unit and the multiplexer, the voltage replication unit is used to replicate the control voltage signal output by the digital-to-analog converter DAC and generate a replication voltage signal to be sent to the multiplexer, and the output of the multiplexer is switched from the control voltage signal to the replication voltage signal when the digital-to-analog converter DAC is subjected to single particle bombardment, so as to avoid the influence of the single particle function interruption, and meanwhile, if the voltage replication unit is subjected to single particle bombardment, no matter which voltage signal is selected by the multiplexer, the single particle function interruption will not be affected, thereby the problem that the traditional digitally controlled oscillator is easily affected by the single particle and generates the single particle function interruption in the radiation environment, resulting in the failure of the space task can be solved, and the anti-radiation reinforcement capability of the digitally controlled oscillator in the radiation environment is improved. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 It is a circuit principle schematic diagram of the traditional DCO type clock data recovery circuit.

[0014] Figure 2 It is a circuit principle schematic diagram of the anti-radiation reinforced digitally controlled oscillator in the embodiment of the application. DETAILED DESCRIPTION

[0015] In order to make the person skilled in the art better understand the technical solutions of the present application, the technical solutions of the present application will be further described in detail below with reference to the drawings in the embodiments of the present application.

[0016] As shown in the figure, Figure 2 The anti-radiation reinforced digital controlled oscillator of the embodiment includes a digital-to-analog converter DAC and a voltage controlled oscillator VCO, and an anti-radiation reinforcement circuit unit is connected between the digital-to-analog converter DAC and the voltage controlled oscillator VCO. The anti-radiation reinforcement circuit unit includes a voltage replication unit and a multiplexer MUX. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC is sent to an input pin of the multiplexer MUX and an input end of the voltage replication unit. The voltage replication unit is used to replicate the control voltage signal Vctrl0 and generate a replicated voltage signal Vctrl1 sent to another input pin of the multiplexer MUX, and when the digital-to-analog converter DAC is subjected to single particle bombardment, the multiplexer MUX switches the output from the control voltage signal Vctrl0 to the replicated voltage signal Vctrl1. Once the digital-to-analog converter DAC is subjected to single particle bombardment, the voltage replication unit switches the output of the multiplexer MUX from the control voltage signal Vctrl0 to the replicated voltage signal Vctrl1, thereby avoiding single particle functional interruption, so that the digital controlled oscillator has the anti-single particle functional interruption function.

[0017] As shown in the figure, Figure 2 The voltage replication unit of the embodiment includes a transmission gate TG, a capacitor C1, an operational amplifier AMP, two comparators COMP1 and COMP2, an XOR gate and a delay module delay. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC passes through the transmission gate TG and the capacitor C1 connected to ground in sequence. An intermediate node between the transmission gate TG and the capacitor C1 serves as the replicated voltage signal Vctrl1 and is connected to another input pin of the multiplexer MUX and an input end of the operational amplifier AMP. High voltage VH and low voltage VL are obtained through the operational amplifier AMP and its feedback circuit, and are compared with the control voltage signal Vctrl0 through the comparators COMP1 and COMP2 respectively. After the two comparison results are input into the XOR gate, the selection signal S1 of the multiplexer MUX is obtained. The selection signal S1 is connected to the control end of the transmission gate TG after being delayed by the delay module delay. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC is replicated to generate the replicated voltage signal Vctrl1 and stored in the capacitor C1. After being fully charged, the transmission gate TG is used as a partition to ensure that the value of the replicated voltage signal Vctrl1 is equal to that of the control voltage signal Vctrl0, but they are not interconnected.

[0018] As shown in the figure, Figure 2As shown in the figure, the feedback circuit of the embodiment comprises a switch and three resistors connected in series between the power supply and the ground, one end of the switch is connected to the power supply, the other end is connected to the ground through the three resistors in turn, the control end of the switch is connected to the output end of the operational amplifier AMP, the first resistor of the three resistors and the middle node of the switch serve as the output end of the high voltage VH, the middle node of the first two resistors serves as the negative feedback output end and is connected to the negative feedback input end of the operational amplifier AMP, and the middle node of the last two resistors serves as the output end of the low voltage VL.

[0019] As Figure 2 shown in the figure, the resistance ratio of the three resistors of the embodiment is 1:1:79, and the resistor with larger resistance value is located at the ground side, so that the voltage of the high voltage VH is 81 / 80xVctrl1, and the voltage of the low voltage VL is 79 / 80xVctrl1, wherein Vctrl1 is the copy voltage signal. The comparison level of the copy voltage signal Vctrl1 is obtained by the operational amplifier AMP with unit gain negative feedback: high voltage VH (81 / 80xVctrl1) and low voltage VL (79 / 80xVctrl1).

[0020] The working process of the voltage replication unit of the embodiment is as follows: the control voltage signal Vctrl0 output by the digital-to-analog converter DAC is copied to generate a replication voltage signal Vctrl1 by the transmission gate TG and stored in the capacitor C1, and the replication voltage signal Vctrl1 is compared by the unit-gain negative feedback operational amplifier AMP to obtain a high voltage VH (81 / 80 x Vctrl1) and a low voltage VL (79 / 80 x Vctrl1). The high voltage VH and the low voltage VL are compared with the control voltage signal Vctrl0 by the comparators COMP1 and COMP2 respectively, and if the control voltage signal Vctrl0 simultaneously satisfies being less than the high voltage VH and greater than the low voltage VL, the comparators COMP1 and COMP2 both output a logic "1". If greater than the high voltage VH or less than the low voltage VL, one of the two comparators COMP1 and COMP2 outputs a logic "1" and the other outputs a logic "0". The outputs of the two comparators COMP1 and COMP2 are connected to the two ends of the two-input exclusive-OR gate, and the output selection signal S1 of the exclusive-OR gate is a logic "1" once the two inputs are different. The output selection signal S1 of the exclusive-OR gate is connected to the control port of the multiplexer MUX, and the selection signal S1 is a logic "0" to select the control voltage signal Vctrl0 output to the voltage-controlled oscillator VCO, and the selection signal S1 is a logic "1" to select the replication voltage signal Vctrl1 output to the voltage-controlled oscillator VCO. At the same time, the selection signal S1 is delayed by the delay module to obtain a signal delay selection signal S1_delay to avoid compensating the replication voltage signal Vctrl1 during the continuous process of the single event effect. In a conventional DCO type clock data recovery circuit, once the digital-to-analog converter DAC is subjected to single particle bombardment in a radiation environment, the control signal Vctrl output to the high-gain voltage-controlled oscillator VCO will change, causing the clock frequency to change greatly. After the single particle effect ends, the clock frequency slowly recovers. However, due to the large initial clock frequency deviation, the clock data recovery circuit has a high probability of converging to the wrong frequency during the recovery process, resulting in the interruption of the function of the clock data recovery circuit. The anti-radiation hardened digital-controlled oscillator in the embodiment will not. In the anti-radiation hardened digital-controlled oscillator in the embodiment, the digital-to-analog converter DAC subjected to single particle bombardment in a radiation environment will change the control voltage signal Vctrl0, which will make the control voltage signal Vctrl0 voltage value greater than VH (or less than VL), and the comparators COPM1 and COMP2 output a logic "0" and a logic "1". At this time, the selection control signal S1 of the multiplexer MUX changes to a logic "1", and the output voltage of the multiplexer MUX is the replication voltage signal Vctrl1.When other modules such as the operational amplifier AMP, the comparators COPM1 and COMP2 and the logic gate are bombarded, the control voltage signal Vctrl0 and the replica control signal Vctrl1 are not affected, and no matter which output is selected by the multiplexer MUX, Vctrl is not affected. It can be seen that the radiation-hardened digital controlled oscillator of the embodiment realizes the radiation-hardened design of the digital controlled oscillator through the radiation-hardened circuit unit composed of the voltage replication unit and the multiplexer, can solve the problem that the traditional digital controlled oscillator is easily affected by single particles and causes single particle function interruption and causes space task failure when operating in a radiation environment, and improves the radiation-hardening capability of the digital controlled oscillator when operating in a radiation environment.

[0021] In addition, the embodiment also provides a clock data recovery circuit, and the clock data recovery circuit of the embodiment comprises a clock data recovery circuit unit with a digital controlled oscillator. Figure 1 The clock data recovery circuit unit in the embodiment comprises an analog-to-digital converter, a serial-to-parallel module and a Bang-Bang phase discriminator, the output clock clock of the digital controlled oscillator is used as the clock of the analog-to-digital converter to enable the analog-to-digital converter to sample the data information and the edge information of the high-speed signal, the serial-to-parallel module is used to convert the serial high-speed sampling signal into a parallel low-speed signal to realize signal speed reduction output, and the Bang-Bang phase discriminator is used to phase-discriminate the data information and the edge information in the output parallel low-speed signal to obtain whether the sampling point of the clock at this time is leading or lagging and output the phase-discriminated code to the digital controlled oscillator.

[0022] In addition, the embodiment also provides an electronic device comprising a device body and a circuit module arranged in the device body, and the circuit module comprises the clock data recovery circuit.

[0023] The above only describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-described embodiments, and any technical solution falling within the concept of the present application belongs to the protection scope of the present application. It should be noted that for ordinary skilled persons in the art, some improvements and decorations without departing from the principles of the present application are also considered to be within the protection scope of the present application.

Claims

1. A radiation-hardened numerically controlled oscillator, comprising a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), characterized in that, A radiation-hardened circuit unit is connected between the digital-to-analog converter (DAC) and the voltage-controlled oscillator (VCO). This radiation-hardened circuit unit includes a voltage replication unit and a multiplexer (MUX). The control voltage signal Vctrl0 output from the DAC is fed into one input pin of the multiplexer and the input of the voltage replication unit. The voltage replication unit replicates the control voltage signal Vctrl0 and generates a replicated voltage signal Vctrl1, which is then fed into the other input pin of the multiplexer. When the DAC is subjected to a single-event bombardment, the multiplexer switches the output of the multiplexer from the control voltage signal Vctrl0 to the replicated voltage signal Vctrl1. The voltage replication unit includes a transmission gate TG, a capacitor C1, an operational amplifier AMP, and two... The digital-to-analog converter (DAC) outputs a control voltage signal Vctrl0, which is grounded sequentially through a transmission gate TG and a capacitor C1. The intermediate node between the transmission gate TG and the capacitor C1 serves as a replica voltage signal Vctrl1, and is simultaneously connected to another input pin of the multiplexer MUX and the input of the operational amplifier AMP. The high voltage VH and low voltage VL are obtained through the operational amplifier AMP and its feedback circuit, and are compared with the control voltage signal Vctrl0 through comparators COMP1 and COMP2, respectively. The two comparison results are input to the XOR gate to obtain the selection signal S1 of the multiplexer MUX. The selection signal S1 is delayed by the delay module and then connected to the control terminal of the transmission gate TG.

2. The radiation-hardened numerically controlled oscillator according to claim 1, characterized in that, The feedback circuit includes a switch and three resistors connected in series between the power supply and ground. One end of the switch is connected to the power supply, and the other end is grounded through the three resistors in sequence. The control terminal of the switch is connected to the output terminal of the operational amplifier AMP. The middle node of the first resistor and the switch serves as the output terminal of the high voltage VH. The middle nodes of the first two resistors serve as the negative feedback output terminal and are connected to the negative feedback input terminal of the operational amplifier AMP. The middle nodes of the last two resistors serve as the output terminal of the low voltage VL.

3. The radiation-hardened numerically controlled oscillator according to claim 2, characterized in that, The resistance ratio of the three resistors is 1:1:79, and the resistor with the larger resistance value is located on the ground side, so that the voltage of the high voltage VH is 81 / 80×Vctrl1 and the voltage of the low voltage VL is 79 / 80×Vctrl1, where Vctrl1 is the replicated voltage signal.

4. A clock data recovery circuit, comprising a clock data recovery circuit unit with a digitally controlled oscillator, characterized in that, The numerically controlled oscillator is the radiation-hardened numerically controlled oscillator as described in any one of claims 1 to 3.

5. The clock data recovery circuit according to claim 4, characterized in that, The clock data recovery circuit unit includes an analog-to-digital converter, a serial-to-parallel converter module, and a Bang-Bang phase detector. The output clock of the numerically controlled oscillator (CNC) serves as the clock for the CNC, enabling the CNC to sample the data information (data) and edge information of the high-speed signal. The serial-to-parallel converter module converts the serial high-sampled signal into a parallel analog signal to achieve signal deceleration. The Bang-Bang phase detector performs phase detection on the data information and edge information in the output parallel analog signal to determine whether the current clock sampling point is leading or lagging, and outputs the phase detection code to the CNC oscillator.

6. An electronic device, comprising a device body and a circuit module disposed within the device body, characterized in that, The circuit module includes the clock data recovery circuit as described in claim 5.

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