Heterojunction bipolar transistor and preparation method thereof, radio frequency module and communication equipment

Abstract

The embodiment of the invention provides a heterojunction bipolar transistor and a preparation method thereof, a radio frequency module and communication equipment. The heterojunction bipolar transistor comprises a semiconductor layer; the emitter structures are arranged on the semiconductor layer at intervals, and a gap is formed between every two adjacent emitter structures in the emitter structures; the base metal comprises a first finger part which is arranged in the gap and is in contact connection with the semiconductor layer; the isolation structure comprises a first isolation structure, and the first isolation structure is filled in the gap and covers the first finger part; the isolation structure is made of an insulating material; and the emitting electrode connecting metal is arranged on one side, back to the semiconductor layer, of the plurality of emitting electrode structures and the first isolation structure, and the emitting electrode connecting metal is in contact connection with the plurality of emitting electrode structures. According to the embodiment of the invention, the distance between the emitting electrode connecting metal and the first finger part of the base electrode metal can be increased by arranging the first isolation structure, so that the effect of reducing parasitic capacitance is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a heterojunction bipolar transistor and a preparation method thereof, a radio frequency module and a communication device. Background Art

[0002] As RF amplifiers operate at higher frequencies, parasitic capacitance in HBT (heterojunction bipolar transistor) products has an increasingly significant impact on performance. In existing HBT processes, the M1 metal crosses the base metal when connecting to the emitter metal, resulting in significant parasitic capacitance between the M1 and base metals. Summary of the Invention

[0003] Therefore, in order to overcome the problem of large parasitic capacitance of heterojunction bipolar transistors in the prior art, an embodiment of the present invention provides a heterojunction bipolar transistor and a preparation method thereof, a radio frequency module and a communication device. By setting a first isolation structure, the distance between the emitter connection metal and the first finger of the base metal can be increased, thereby achieving the effect of reducing parasitic capacitance.

[0004] An embodiment of the present invention provides a heterojunction bipolar transistor, comprising: a semiconductor layer; a plurality of emitter structures, which are arranged on the semiconductor layer at intervals, with a gap formed between two adjacent emitter structures in the plurality of emitter structures; a base metal, the base metal comprising a first finger portion arranged in the gap and in contact with the semiconductor layer; an isolation structure, the isolation structure comprising a first isolation structure, the first isolation structure filling the gap and covering the first finger portion; the isolation structure being made of an insulating material; an emitter connection metal, which is arranged on a side of the plurality of emitter structures and the first isolation structure facing away from the semiconductor layer, and the emitter connection metal is in contact with the plurality of emitter structures.

[0005] An embodiment of the present invention provides a method for fabricating a heterojunction bipolar transistor, comprising step S1: providing a first basic structure, the first basic structure comprising: a semiconductor layer; a plurality of emitter structures disposed on the semiconductor layer at intervals, with a gap formed between adjacent two emitter structures in the plurality of emitter structures; and a base metal, the base metal comprising a first finger disposed in the gap and in contact with the semiconductor layer;

[0006] Step S2: preparing an isolation structure; the isolation structure includes a first isolation structure; step S2 includes forming the first isolation structure in the gap, and filling the gap with the first isolation structure and covering the first finger; the isolation structure is made of an insulating material;

[0007] Step S3: forming an emitter connection metal on the first isolation structure and the emitter structure on a side facing away from the semiconductor layer, so as to make the emitter connection metal contact and connect.

[0008] An embodiment of the present invention further provides a radio frequency module, comprising the aforementioned heterojunction bipolar transistor or a heterojunction bipolar transistor manufactured using the aforementioned method for manufacturing the heterojunction bipolar transistor.

[0009] The above-described embodiments of the present invention have at least one or more of the following beneficial effects: (1) By providing a first isolation structure filled in the gap, the spacing between the emitter connection metal and the first finger portion can be increased, thereby reducing parasitic capacitance. (2) A second dielectric layer is provided between the base connection metal and the semiconductor bevel, which can increase the distance between the semiconductor bevel and the base connection metal, thereby reducing parasitic capacitance between the base connection metal and the collector layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0011] Figure 1 A schematic top view of a first basic structure in a heterojunction bipolar transistor provided by one embodiment of the present invention.

[0012] Figure 2 for Figure 1 Schematic diagram of the structure of the AA section.

[0013] Figure 3 for Figure 1 Schematic diagram of the structure of the middle BB section.

[0014] Figure 4 A heterojunction bipolar transistor provided by an embodiment of the present invention and Figure 2 Schematic diagram of the structure from the same perspective.

[0015] Figure 5 A heterojunction bipolar transistor provided by an embodiment of the present invention and Figure 3 Schematic diagram of the structure from the same perspective.

[0016] Figure 6 The structure obtained after one step in the method for preparing a heterojunction bipolar transistor provided by one embodiment of the present invention corresponds to Figure 2 Schematic diagram of the perspective structure.

[0017] Figure 7 for Figure 6 The structure shown corresponds to Figure 3 Schematic diagram of the perspective structure.

[0018] Figure 8The structure obtained after another step in the method for preparing a heterojunction bipolar transistor provided by one embodiment of the present invention corresponds to Figure 2 Schematic diagram of the perspective structure.

[0019] Figure 9 for Figure 8 The structure shown corresponds to Figure 3 Schematic diagram of the perspective structure.

[0020] Figure 10 The structure obtained after another step in the method for preparing a heterojunction bipolar transistor provided by one embodiment of the present invention corresponds to Figure 2 Schematic diagram of the perspective structure.

[0021] Figure 11 for Figure 10 The structure shown corresponds to Figure 3 Schematic diagram of the perspective structure.

[0022] Figure 12 The structure obtained after another step in the method for preparing a heterojunction bipolar transistor provided by one embodiment of the present invention corresponds to Figure 2 Schematic diagram of the perspective structure.

[0023] Figure 13 for Figure 12 The structure shown corresponds to Figure 3 Schematic diagram of the perspective structure.

[0024] Figure 14 Schematic diagram of the structure of a heterojunction bipolar transistor in related technology.

[0025] Figure 15 Figure 14 The structural schematic diagram of the heterojunction bipolar transistor from another perspective is shown.

[0026] [Description of Reference Numerals]

[0027] 100. Heterojunction bipolar transistor; 101. First basic structure; 10. Semiconductor layer; 11. First surface; 12. Semiconductor bevel; 13. Substrate layer; 14. Subcollector layer; 15. Etch stop layer; 16. Collector layer; 17. Base layer; 18. Emitter layer; 20. Emitter structure; 21. Emitter step; 22. Emitter metal; 23. Gap; 30. Base metal; 31. First finger; 32. Connector; 33. Second finger; 40. Isolation structure; 41. First isolation structure; 42. Second isolation structure; 43. Passivation layer material; 431. First opening; 432. Second opening; 44. Dielectric layer material; 441. Third opening; 442. Fourth opening Mouth; 45, passivation layer; 451, first passivation layer; 452, second passivation layer; 453, contact opening; 46, dielectric layer; 461, first dielectric layer; 462, second dielectric layer; 50, emitter connection metal; 60, base connection metal; 70, collector metal; 80, collector connection metal; 91, third passivation layer; 100a, another heterojunction bipolar transistor; 10a, base platform; 12a, base slope; 21a, emitter step layer; 22a, emitter contact metal layer; 31a, base metal layer finger; 32a, base metal layer end; 50a, wiring metal; 60a, base layer connection metal; 91a, first silicon nitride layer; 92a, second silicon nitride layer. DETAILED DESCRIPTION

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0032] An embodiment of the present invention provides a heterojunction bipolar transistor 100. In order to prevent the position of part of the hierarchical structure from being blocked by each hierarchical structure, the position of the part of the hierarchical structure is first represented by Figures 1 to 3 The first basic structure 101 included in the heterojunction bipolar transistor 100 provided by an embodiment of the present invention is shown. Figure 1 Schematic diagram of the top view of the first basic structure 101. Figure 1 The AA cross-sectional structure of the first basic structure 101 is shown as follows: Figure 2 gesture. Figure 1 The BB cross-sectional structure of the first basic structure 101 is shown as follows: Figure 3 gesture. Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 For Figure 2 Schematic diagram of the structure from the same perspective. Figure 5 、 Figure 7 、 Figure 9 、 Figure 11 、 Figure 13 For Figure 3 Schematic diagram of the structure from the same perspective.

[0033] Reference Figure 1 、 Figure 2 and Figure 3The first base structure 101 includes a semiconductor layer 10, a plurality of emitter structures 20, a base metal 30, and a collector metal 70. The semiconductor layer 10 has a first surface 11. The plurality of emitter structures 20 are arranged on the first surface 11 in a manner spaced apart from each other along a first direction, with a gap 23 formed between two adjacent emitter structures 20. The base metal 30 includes a first finger 31 disposed within the gap 23 and in contact with the semiconductor layer 10.

[0034] In some embodiments, the semiconductor layer 10 specifically includes a substrate layer 13, a sub-collector layer 14 (sub-collector), an etch stop layer 15, a collector layer 16 (collector), a base layer 17 (base), and an emitter layer 18, which are stacked in sequence. The emitter layer 18 is primarily made of InGaP and can serve as an etch stop layer to protect the base layer 17 during the etching process. The first surface 11 is specifically the surface of the emitter layer 18 facing away from the base layer 17. The specific configuration of the semiconductor layer 10 can refer to the configuration of the epitaxial layer structure of a conventional HBT. The collector metal 70 is connected to the sub-collector layer 14. In this embodiment, each emitter structure 20 includes an emitter step 21 (which can be referred to as EM) and an emitter metal 22 (which can be referred to as EC). The base metal 30 (which can be referred to as BC) includes, for example, multiple fingers, wherein the finger located between two adjacent emitter structures 20 is referred to as the first finger 31, and the fingers other than the first finger 31 (i.e., located outside the multiple emitter structures 20) are referred to as the second finger 33. The semiconductor layer 10 is provided with a third passivation layer 91 covering the first surface 11. The surface of the base metal 30 facing away from the semiconductor layer 10 is exposed outside the third passivation layer 91. The third passivation layer 91 can be made of SiN (silicon nitride).

[0035] Reference Figure 4The heterojunction bipolar transistor 100 provided in an embodiment of the present invention further includes an isolation structure 40 and an emitter connection metal 50. The isolation structure includes a first isolation structure 41, which fills the gap 23 and covers the first finger 31. The emitter connection metal 50 is arranged on the side of the multiple emitter structures 20 and the first isolation structure 41 facing away from the semiconductor layer 10, and the emitter connection metal 50 is in contact with the multiple emitter structures 20. The isolation structure 40 is made of an insulating material, that is, the first isolation structure 41 is made of an insulating material. The first isolation structure 41 can be an organic insulating material or an inorganic insulating material, or a combination of an organic insulating material and an inorganic insulating material. The first isolation structure 41 can fill part of the depth of the gap 23 or the entire depth of the gap 23. It can also be understood that the height from the surface of the first isolation structure 41 facing away from the semiconductor layer 10 to the first surface 11 (semiconductor layer 10) can be less than the height from the surface of the emitter structure 20 facing away from the semiconductor layer 10 to the first surface 11 (semiconductor layer 10). Alternatively, the height from the surface of the first isolation structure 41 facing away from the semiconductor layer 10 to the first surface 11 (semiconductor layer 10) can be equal to the height from the surface of the emitter structure 20 facing away from the semiconductor layer 10 to the first surface 11 (semiconductor layer 10). In some embodiments, when the first isolation structure 41 fills a portion of the depth of the gap 23, the filling depth is greater than or equal to 1150 angstroms.

[0036] Figure 14 The structure of another heterojunction bipolar transistor 100a in the related art is shown, which includes a base platform 10a (Base Pedestal, base base), an emitter step layer 21a and an emitter contact metal layer 22a, a base metal layer finger 31a between two groups of emitter step layers 21a and the emitter contact metal layer 22a, and a wiring metal 50a connected to the emitter contact metal layer 22a. Figure 14 The surface of the base metal layer finger 31a facing away from the base platform 10a is exposed from the first silicon nitride layer 91a. The second silicon nitride layer 92a covers the base metal layer finger 31a. There is only one layer of the second silicon nitride layer 92a between the wiring metal 50a and the base metal layer finger 31a. The thickness of the second silicon nitride layer 92 is generally 250 angstroms ( 1 Angstrom=10 -10 The emitter connection metal 50 is thin, so a large parasitic capacitance is generated between the connection metal 50a and the base metal layer finger 31a. In this embodiment, by providing a first isolation structure 41 filling the gap 23, the spacing between the emitter connection metal 50 and the first finger 31 can be increased, thereby reducing the parasitic capacitance. In this embodiment of the present invention, the line width of the emitter connection metal 50 (the width along the direction in which the multiple emitter structures 20 are arranged) can be less than 2 microns.

[0037] In some embodiments, the heterojunction bipolar transistor 100 further includes a passivation layer 45 and a dielectric layer 46. The passivation layer 45 includes a first passivation layer 451, and the dielectric layer 46 includes a first dielectric layer 461. The first passivation layer 451 covers the surface of the first finger 31 facing away from the semiconductor layer 10 and covers the side surfaces of two adjacent emitter structures 20 facing the gap 23. The first dielectric layer 461 is disposed on the side of the first passivation layer 451 facing away from the semiconductor layer 10. The first passivation layer 451 and the first dielectric layer 461 are made of different materials. The first passivation layer 451 and the first dielectric layer 461 together constitute the first isolation structure 41. For example, the first passivation layer 451 can be an inorganic insulating material, and the first dielectric layer 461 can be an organic insulating material. For another example, the first passivation layer 451 can be a silicon nitride material, and the first dielectric layer 461 can be formed of a material such as PBO (polybenzoxazole) or PI (polyimide). In some embodiments, the first dielectric layer 461 may be formed of a photosensitive dielectric material, and the photosensitive dielectric material may be PBO.

[0038] In some embodiments, when the first passivation layer 451 is made of silicon nitride material, it can be formed by a deposition process and can be prepared using existing steps in the traditional HBT device production process. When the first dielectric layer 461 is made of an organic insulating material, it can be formed by coating, curing and other processes, which can achieve a better filling effect. Moreover, when the first dielectric layer 461 is made of an organic insulating material, its dielectric constant is smaller than that of the silicon nitride material, and therefore it is more conducive to reducing parasitic capacitance. That is, in some embodiments, the dielectric constant of the first dielectric layer 461 is smaller than the dielectric constant of the first passivation layer 451. In some embodiments, the thickness of the first passivation layer 451 ranges from 150 to 1000 angstroms, specifically 250 angstroms. This thickness range of the first passivation layer 451 can increase the protection of the first finger 31. In some embodiments, the thickness of the first dielectric layer 461 is greater than or equal to 1000 angstroms, specifically 3000 to 10000 angstroms.

[0039] Of course, in some embodiments, the first isolation structure 41 may also be formed of a single material. For example, in some embodiments, the first isolation structure 41 is formed of silicon nitride material.

[0040] In some embodiments, the thickness of the emitter metal 22 can be increased to increase the thickness of the first isolation structure 41 filling the gap 23, thereby further reducing parasitic capacitance. Specifically, the distance between the surface of the emitter metal 22 facing away from the semiconductor layer 10 and the surface of the base metal 30 facing away from the semiconductor layer 10 is greater than or equal to 3000 angstroms. In short, the height of the emitter metal 22 above the base metal 30 is greater than 3000 angstroms.

[0041] In some embodiments, combined Figure 1 and Figure 3 The semiconductor layer 10 further includes a semiconductor slope 12 adjacent to the first surface 11. The base metal 30 further includes a connecting portion 32 disposed on the first surface 11, and the connecting portion 32 is connected to the first finger portion 31. Figure 5 The passivation layer 45 further includes a second passivation layer 452 covering the semiconductor bevel 12, and the dielectric layer 46 further includes a second dielectric layer 462 covering the second passivation layer 452. The isolation structure 40 further includes a second isolation structure 42, and the second dielectric layer 462 and the second passivation layer 452 together constitute the second isolation structure 42. The heterojunction bipolar transistor 100 further includes a base connection metal 60, which is connected to the base metal 30 and extends to the side of the second dielectric layer 462 facing away from the second passivation layer 452.

[0042] In the related art, refer to Figure 15 In another heterojunction bipolar transistor 100a, the base connection metal 60a is connected to the base metal layer end 32a through an opening in the second silicon nitride layer 92a and is led out along the base region bevel 12a. In this case, the base connection metal 60a and the base region bevel 12a are separated only by the second silicon nitride layer 92a, which also generates a large parasitic capacitance. In this embodiment of the present application, a second dielectric layer 462 is provided between the base connection metal 60 and the semiconductor bevel 12, which can increase the distance between the semiconductor bevel 12 and the base connection metal 60 and reduce the parasitic capacitance between the base connection metal 60 and the collector layer 16.

[0043] In some embodiments, the thickness of the second dielectric layer 462 is greater than or equal to 5000 angstroms.

[0044] In some embodiments, the first passivation layer 451 and the second passivation layer 452 in the passivation layer 45 may be formed simultaneously, that is, the first passivation layer 451 and the second passivation layer 452 may be different portions of the same passivation layer material. In some embodiments, the first dielectric layer 461 and the second dielectric layer 462 in the dielectric layer 46 may be formed simultaneously, that is, the first dielectric layer 461 and the second dielectric layer 462 may be different portions of the same dielectric layer material.

[0045] In some embodiments, a passivation layer 45 covers the semiconductor layer 10 and the plurality of emitter structures 20, and the passivation layer 45 has a contact opening 453 (from Figure 5 (as viewed in the middle), the multiple emitter structures 20 are spaced apart from each other along the first direction, and the surfaces of the multiple emitter structures 20 facing away from the semiconductor layer 10 are connected to the emitter connection metal 50 through the contact opening 453. The distance between the outermost edges of the multiple emitter structures 20 facing each other in the first direction is less than the width of the contact opening 453 along the first direction. Figure 4, Figure 4 The two emitter structures 20 are spaced apart along the first direction, and the passivation layer 45 also covers the sidewalls of the plurality of emitter structures 20. The distance between the outermost edges of the plurality of emitter structures 20 opposite to each other in the first direction is Figure 4 The distance between the left edge of the emitter structure 20 on the left and the right edge of the emitter structure 20 on the right is smaller than the width of the contact opening 453 along the first direction. Figure 4 From the perspective of , the top surfaces of the multiple emitter structures 20 are completely exposed outside the passivation layer 45 , which can ensure the effective line width of the emitter connection metal 50 connecting the multiple emitter structures 20 .

[0046] Reference Figures 6 to 13 An embodiment of the present invention further provides a method for manufacturing a heterojunction bipolar transistor 100, comprising:

[0047] Step S1: Provide a first basic structure 101, the first basic structure 101 includes: a semiconductor layer 10; a plurality of emitter structures 20, which are arranged on a first surface 11 at intervals, and a gap 23 is formed between two adjacent emitter structures 20 in the plurality of emitter structures 20; a base metal 30, the base metal 30 includes a first finger 31 arranged in the gap 23 and in contact with the semiconductor layer 10.

[0048] Step S2: Prepare an isolation structure 40; the isolation structure 40 includes a first isolation structure 41; Step S2 specifically includes forming the first isolation structure 41 in the gap 23, and allowing the first isolation structure 41 to fill the gap 23 and cover the first finger 31. The isolation structure 40 is made of an insulating material;

[0049] Step S3 : forming an emitter connection metal 50 on the side of the first isolation structure 41 and the emitter structure 20 facing away from the semiconductor layer 10 , so that the emitter connection metal 50 is in contact with each other.

[0050] The specific configuration of the first infrastructure 101 in step S1 can refer to Figures 1 to 3 As shown in . The preparation of the isolation structure 40 in step S2 can be designed and selected based on the material of the first isolation structure 41. For example, in some embodiments, step S2 specifically includes step S21: forming a first passivation layer 451, so that the first passivation layer 451 covers the surface of the first finger 31 facing away from the semiconductor layer 10 and covers the side surfaces of the two adjacent emitter structures 20 facing the gap 23; and step S22: forming a first dielectric layer 461 on the first passivation layer 451; the material of the first passivation layer 451 is different from the material of the first dielectric layer 461. The first passivation layer 451 and the first dielectric layer 461 together constitute the first isolation structure 41.

[0051] For example, the first passivation layer 451 can be made of an inorganic insulating material, specifically silicon nitride, and can be formed by deposition. Thus, it can cover the surface of the first finger 31 and the sides of the multiple emitter structures 20, ensuring multi-directional coverage and insulation, protecting the first finger 31 and the semiconductor material exposed outside the first finger 31, and preventing the first dielectric layer 461 from directly contacting the semiconductor material and affecting device reliability. The first dielectric layer 461 can be made of an organic insulating material and can be formed by coating and curing to facilitate filling the gap 23. The first dielectric layer 461 can specifically be formed of a photosensitive dielectric material.

[0052] Of course, in other embodiments, the same material may be used to form the first isolation structure 41 in step S2, for example, only silicon nitride material may be used to form the first isolation structure 41. In this case, the first isolation structure 41 may be formed by a single deposition or multiple depositions.

[0053] In some embodiments, the semiconductor layer 10 has a first surface 11 and a semiconductor bevel 12 adjacent to the first surface 11. The base metal 30 further includes a connecting portion 32 disposed on the first surface 11, the connecting portion 32 being connected to the first finger 31. The isolation structure 40 further includes a second isolation structure 42. In some embodiments, the isolation structure 40 preparation step S2 specifically includes:

[0054] S23: depositing a passivation layer material 43 on the semiconductor layer 10 so that the passivation layer material 43 covers the semiconductor layer 10, the base metal 30 and the plurality of emitter structures 20;

[0055] S24: performing photolithography on the passivation layer material 43 to form a passivation layer 45 ; the passivation layer 45 includes a first passivation layer 451 located in the gap 23 and a second passivation layer 452 located on the semiconductor inclined surface 12 ;

[0056] S25: coating the dielectric layer material 44 on the passivation layer material 43 so that the dielectric layer material 44 covers the passivation layer 45 and fills the gap 23;

[0057] S26: The dielectric layer material 44 is photolithographically processed and cured to form a dielectric layer 46; the portion of the dielectric layer 46 filling the gap 23 forms a first dielectric layer 461, and the portion of the dielectric layer 46 covering the second passivation layer 452 forms a second dielectric layer 462; the first dielectric layer 461 and the first passivation layer 451 together constitute the first isolation structure 41, and the second dielectric layer 462 and the second passivation layer 452 together constitute the second isolation structure 42.

[0058] The step S2 may further include, for example, a step S4 : forming a base connection metal 60 on the second dielectric layer 462 , and connecting the base connection metal 60 to the connection portion 32 of the base metal 30 .

[0059] The structure obtained after step S23 can be referred to Figure 6 and Figure 7 , the structure obtained after step S24 can refer to Figure 8 and Figure 9 , the structure obtained after step S25 can refer to Figure 10 and Figure 11 In step S23, the passivation layer material 43 is, for example, silicon nitride. In step S24, for example, a layer of photoresist material is first provided on the passivation layer material 43, and the photoresist material is exposed and developed using a mask with a specific pattern, and then the passivation layer material 43 is photoetched, and the portion of the passivation layer material 43 exposed outside the photoresist is removed to form Figure 8 The first opening 431 in the passivation layer 43 exposes the collector metal 70 to form Figure 9 The second opening 432 in the passivation layer 43 exposes the connection portion 32 of the base metal 30 outside the passivation layer material 43. In this embodiment, the portion within the gap 23 is referred to as the first passivation layer 451, and the portion covering the semiconductor bevel 12 is referred to as the second passivation layer 452, depending on the corresponding region on the semiconductor layer 10. From a formation process perspective, the first passivation layer 451 and the second passivation layer 452 are actually two parts of the same passivation layer.

[0060] In step S25, the dielectric layer material 44 is a photosensitive dielectric material such as PBO or photosensitive PI, and is coated to fill the gap 23. In step S26, for example, a layer of photoresist material is placed on the dielectric layer material 44, and a photomask with a specific pattern is used to expose and develop the photoresist material, and then photolithography is performed. The portion of the dielectric layer material 44 exposed outside the photoresist is removed to form a Figure 12 The third opening 441 in the dielectric layer 44 exposes the collector metal 70 to form Figure 13 The fourth opening 442 in the dielectric layer 44 exposes the connection portion 32 of the base metal 30 outside the dielectric layer material 44. This allows the base connection metal 60 to be connected to the connection portion 32 through the first opening 431 and the third opening 441. The collector connection metal 80 can be connected to the collector metal 70 through the second opening 432 and the fourth opening 442. In some embodiments, the width of the third opening 441 is greater than or equal to the width of the first opening 431. The width of the fourth opening 442 is greater than or equal to the width of the second opening 432.

[0061] Through the above steps S23 to S26, the first passivation layer 451 and the second passivation layer 452 are formed simultaneously, and the first dielectric layer 461 and the second dielectric layer 462 are formed simultaneously. Thus, an isolation structure is formed in the gap 23 and on the semiconductor slope 12, thereby achieving the effect of reducing parasitic capacitance at multiple locations.

[0062] In some embodiments, the dielectric layer material 44 is a photosensitive dielectric material, and then step S26 is followed by step S27 of back-etching the dielectric layer material 44 and the passivation layer 45 using a first mask, so that the surface of the plurality of emitter structures 20 facing away from the semiconductor layer 10 is exposed from the passivation layer 45; the first mask has a first window, and the distance between the two outermost edges of the plurality of emitter structures 20 facing each other along the first direction is less than the width of the first window along the first direction. The structure after step S27 is completed can be referred to Figure 12 and Figure 13 .

[0063] The distance between the two outermost edges of the plurality of emitter structures 20 opposite to each other along the first direction is referred to as Figure 12 In the figure, the width of the first window along the first direction is greater than W1, so that the dielectric layer 46 and the passivation layer 45 of the passivation layer located on the top of the multiple emitter structures 20 are all within the first window. The dielectric layer 46 and the passivation layer 45 on the top of the multiple emitter structures 20 can be etched back through this first window. In step S27, since the dielectric layer material 44 itself is made of a photosensitive dielectric material, it is not necessary to set a photoresist layer and directly etch back, which can reduce the process steps and reduce the process difficulty. However, this embodiment is not limited to this. In some embodiments, a photosensitive medium can also be used to control exposure and development methods to achieve a structure identical to the structure obtained in step S27.

[0064] During the coating process of the aforementioned step S25, due to the fluidity of the material, the thickness of the surface at a higher position will be thinner. For example, the thickness of the dielectric layer located at the top of the multiple emitter structures 20 is thinner. Therefore, when etching back in step S27, the passivation layer and the dielectric layer located at the top of the multiple emitter structures 20 are etched first. When the passivation layer at the top of the multiple emitter structures 20 is completely etched and the tops of the multiple emitter structures 20 are exposed from the passivation layer, the dielectric layer at other positions in the first window has not been completely etched and is retained. After step S28, step S3 is performed again. The emitter connection metal 50 formed in step S3 is separated from the first finger 31 by a first isolation structure 41, which can make the parasitic capacitance between the emitter connection metal 50 and the first finger 31 smaller.

[0065] In some embodiments, the emitter structure 20 of the first base structure 101 provided in step S1 can be arranged higher so that when the emitter structure 20 is exposed from the passivation layer, more of the dielectric layer is retained in the remaining portion. Specifically, each of the multiple emitter structures 20 includes an emitter step 21 and an emitter metal 22 sequentially stacked on the first surface 11. The distance between the surface of the emitter metal 22 facing away from the semiconductor layer 10 and the surface of the base metal 30 facing away from the semiconductor layer 10 is greater than or equal to 3000 angstroms, that is, the emitter metal 22 is thickened in step S1.

[0066] Some embodiments of the present invention further provide a radio frequency module, including the heterojunction bipolar transistor 100 provided in any of the aforementioned embodiments, or a heterojunction bipolar transistor produced by the heterojunction bipolar transistor production method provided in any of the aforementioned embodiments. The radio frequency module, for example, integrates an radio frequency switch, a filter, etc. The radio frequency module provided in this embodiment has at least the same effects as the heterojunction bipolar transistor 100, and will not be further described here.

[0067] Some embodiments of the present invention further provide a communication device including the aforementioned radio frequency module, such as a mobile phone, a WiFi wireless router, etc. The communication device has at least the same effect as the aforementioned heterojunction bipolar transistor 100 and will not be described in detail here.

[0068] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A heterojunction bipolar transistor, characterized in that: include: semiconductor layer; a plurality of emitter structures, arranged on the semiconductor layer at intervals, with a gap formed between two adjacent emitter structures in the plurality of emitter structures; a base metal, the base metal comprising a first finger portion disposed in the gap and in contact with the semiconductor layer; an isolation structure, the isolation structure comprising a first isolation structure, the first isolation structure filling the gap and covering the first finger; The isolation structure is made of insulating material; An emitter connection metal is disposed on a side of the plurality of emitter structures and the first isolation structure facing away from the semiconductor layer, and the emitter connection metal is in contact with and connected to the plurality of emitter structures.

2. The heterojunction bipolar transistor according to claim 1, wherein: It includes a passivation layer and a dielectric layer, the passivation layer includes a first passivation layer, the first passivation layer covers the surface of the first finger facing away from the semiconductor layer and covers the side surfaces of the two adjacent emitter structures facing the gap; the dielectric layer includes a first dielectric layer, the first dielectric layer is arranged on the side of the first passivation layer facing away from the semiconductor layer; the first passivation layer and the first dielectric layer together constitute the first isolation structure, and the first passivation layer and the first dielectric layer are made of different materials.

3. The heterojunction bipolar transistor according to claim 2, wherein: The first dielectric layer is formed of a photosensitive dielectric material.

4. The heterojunction bipolar transistor according to claim 2, wherein: The thickness of the first dielectric layer is greater than or equal to 1000 angstroms.

5. The heterojunction bipolar transistor according to claim 2, wherein: The dielectric constant of the first dielectric layer is lower than the dielectric constant of the first passivation layer.

6. The heterojunction bipolar transistor according to claim 1, wherein: Each of the multiple emitter structures includes an emitter step and an emitter metal stacked sequentially on the semiconductor layer; the distance between the surface of the emitter metal facing away from the semiconductor layer and the surface of the base metal facing away from the semiconductor layer is greater than or equal to 3000 angstroms.

7. The heterojunction bipolar transistor according to claim 2, wherein: The semiconductor layer has a first surface and a semiconductor bevel adjacent to the first surface; the base metal also includes a connecting portion arranged on the first surface, the connecting portion being connected to the first finger; the passivation layer also includes a second passivation layer covering the semiconductor bevel, and the dielectric layer also includes a second dielectric layer covering the second passivation layer; the isolation structure also includes a second isolation structure, and the second dielectric layer and the second passivation layer together constitute the second isolation structure; the heterojunction bipolar transistor also includes a base connection metal, the base connection metal is connected to the base metal and extends to the side of the second dielectric layer facing away from the second passivation layer.

8. The heterojunction bipolar transistor according to claim 1, wherein: It also includes a passivation layer covering the semiconductor layer and the multiple emitter structures; the passivation layer has a contact opening, the multiple emitter structures are arranged to be spaced apart from each other along a first direction, the surfaces of the multiple emitter structures facing away from the semiconductor layer are connected to the emitter connection metal through the contact opening, and the distance between the two outermost edges of the multiple emitter structures relative to each other in the first direction is less than the width of the contact opening along the first direction.

9. The heterojunction bipolar transistor according to claim 7, wherein: The thickness of the second dielectric layer is greater than or equal to 5000 angstroms.

10. A method for preparing a heterojunction bipolar transistor, characterized in that: include: Step S1: Providing a first basic structure, the first basic structure comprising: a semiconductor layer; a plurality of emitter structures spaced apart from each other and arranged on the semiconductor layer, with a gap formed between two adjacent emitter structures; a base metal, the base metal comprising a first finger portion arranged in the gap and in contact with the semiconductor layer; Step S2: preparing an isolation structure; the isolation structure includes a first isolation structure; step S2 includes forming the first isolation structure in the gap, and filling the gap with the first isolation structure and covering the first finger; the isolation structure is made of an insulating material; Step S3: forming an emitter connection metal on the first isolation structure and the emitter structure on a side facing away from the semiconductor layer, so as to make the emitter connection metal contact and connect.

11. The method for preparing a heterojunction bipolar transistor according to claim 10, wherein: The semiconductor layer has a first surface and a semiconductor slope adjacent to the first surface; the base metal further includes a connecting portion provided on the first surface, the connecting portion being connected to the first finger; the isolation structure further includes a second isolation structure; The step S2 specifically includes: Step S23: depositing a passivation layer material on the semiconductor layer, so that the passivation layer material covers the semiconductor layer, the base metal and the multiple emitter structures; Step S24: performing photolithography on the passivation layer material to form a passivation layer; the passivation layer includes a first passivation layer located in the gap and a second passivation layer located on the semiconductor oblique surface; Step S25: coating a dielectric layer material on the passivation layer material, so that the dielectric layer material covers the passivation layer and fills the gap; Step S26: performing photolithography and curing on the dielectric layer material to form a dielectric layer; the portion of the dielectric layer filling the gap forms a first dielectric layer, and the portion of the dielectric layer covering the second passivation layer forms a second dielectric layer; The first dielectric layer and the first passivation layer together constitute the first isolation structure, and the second dielectric layer and the second passivation layer together constitute the second isolation structure.

12. The method for preparing a heterojunction bipolar transistor according to claim 11, wherein: The dielectric layer material is a photosensitive dielectric material; after step S26, step S27 is also included: using a first mask to back-etch the dielectric layer and the passivation layer so that the surfaces of the multiple emitter structures facing away from the semiconductor layer are exposed from the passivation layer and the dielectric layer; the first mask has a first window; the multiple emitter structures are arranged at intervals along a first direction; the distance between the two outermost edges of the multiple emitter structures opposite to each other in the first direction is less than the width of the first window along the first direction.

13. A radio frequency module, characterized in that: The invention comprises the heterojunction bipolar transistor according to any one of claims 1 to 9 or the heterojunction bipolar transistor manufactured by the method for manufacturing the heterojunction bipolar transistor according to any one of claims 10 to 12.

14. A communication device, characterized in that: Including the radio frequency module as described in claim 13.

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