DDR4 SDRAM fixed bit error test method and device based on high-energy particles

Abstract

The invention relates to a DDR4SDRAM fixed bit error test method and device based on high-energy particles, and the method comprises the steps: S1, obtaining a DDR4SDRAM sample device, and selecting a target radiation source and radiation energy; s2, irradiating the sample device from the initial particle fluence according to the target radiation source and the irradiation energy; s3, judging whether the irradiated sample device has a fixed position error or not, if the fixed position error does not occur, increasing the particle fluence according to the initial particle fluence to irradiate the sample device, repeating S3, and if the fixed position error occurs, recording the particle fluence reaching a damage threshold value and determining the number of the fixed position errors; and S4, carrying out annealing curve measurement on the sample device, obtaining an annealing curve according to the particle fluence reaching the damage threshold, and determining an optimal device according to the damage threshold and the annealing curve. According to the method, the fixed bit error of the DDR4SDRAM can be effectively evaluated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a DDR4 SDRAM fixed bit error test method and device based on high-energy particles. Background Art

[0002] Building high-performance, high-capacity storage and computing systems onboard satellites to achieve on-orbit data storage and real-time data processing has become a widely accepted industry consensus. At the same time, these missions tend to, or can only, utilize lower-cost, less ruggedized Commercial Off-the-Shelf (COTS) components. High-performance DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory) will be widely used in these computing and storage devices, becoming a critical component influencing system reliability.

[0003] Dynamic random access memory (SDRAM) has experienced rapid development over the past decade. Significant changes in transistor morphology and process geometries have potentially made it sensitive to the space radiation environment, including solar proton events (SPEs) faced by high-orbit satellites and protons trapped in the Earth's magnetic field by inner radiation belts, particularly within the intense proton radiation environment of the South Atlantic Anomaly (SAA) faced by satellites in medium and low-orbit orbits. Compared to failures caused by single-event upsets (SEEs), hard damage that cannot be recovered through power cycling is more damaging and has a longer-lasting impact. DDR4 SDRAM stuck-at-bit errors manifest as repeated, long-term errors at certain locations within a memory cell. Especially in on-orbit applications, SEEs and stuck-at-bit errors may exhibit similar symptoms, leading to misjudgments, but their mechanisms and properties differ. Currently, commercial-grade DDR4 SDRAM is often the only choice for high-performance aerospace electronic equipment designs. Therefore, ground-based testing and screening methods tailored to devices from different manufacturers and production batches are necessary to identify the optimal device to minimize the impact of hard damage from stuck-at-bit errors in on-orbit aerospace applications, which could compromise the safe operation of aerospace electronic systems. Currently, the main evaluation methods in China still focus on temperature cycling, cycle aging tests, and single-event upsets. There is no publicly available, mature test and evaluation method for hard damage such as DDR4 SDRAM stuck-bit errors. Summary of the Invention

[0004] The purpose of the present invention is to provide a DDR4 SDRAM stuck-bit error test method and device based on high-energy particles, which can effectively evaluate DDR4 SDRAM stuck-bit errors.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] The DDR4 SDRAM stuck-bit error test method based on high-energy particles includes:

[0007] S1. Obtain a DDR4 SDRAM sample device, select the target radiation source, and irradiation energy;

[0008] S2. irradiating the sample device from an initial particle fluence according to the target radiation source and irradiation energy;

[0009] S3, determining whether a stuck-bit error occurs in the sample device after irradiation; if no stuck-bit error occurs, irradiating the sample device with an increased particle fluence according to the initial particle fluence, and repeating S3; if a stuck-bit error occurs, recording the particle fluence that reaches the damage threshold and determining the number of stuck-bit errors;

[0010] S4. Measure the annealing curve of the sample device, obtain the annealing curve according to the particle fluence that reaches the damage threshold, and determine the optimal device according to the damage threshold and the annealing curve.

[0011] Optionally, select the target radiation source and irradiation energy including:

[0012] disassembling the sample device to obtain a silicon crystal die;

[0013] Measuring the silicon crystal die using focused ion beam technology and an electron microscope to obtain a distance from the edge of the substrate to the active area;

[0014] The maximum atomic displacement distribution of the incident particles in the silicon substrate is calculated, and the target radiation source and irradiation energy are selected based on whether the distance from the substrate edge to the active area and the maximum atomic displacement distribution are within a preset range.

[0015] Optionally, determining whether a fixed bit error occurs in the sample device after irradiation includes: determining whether a fixed bit error occurs in the sample device after irradiation by performing a full-address checkerboard cyclic read-write check.

[0016] Optionally, recording the particle fluence that reaches the damage threshold includes:

[0017] If an error occurs at the same fixed physical address during multiple full-address checkerboard cyclic read and write cycles, and the error does not disappear after power is cycled, a damage event of a fixed bit error is determined, and the particle fluence reaching the damage threshold is recorded.

[0018] Optionally, measuring the annealing curve of the sample device includes:

[0019] S41, presetting an initial self-refresh interval for the sample device, performing a checkerboard cycle read and write test at the initial self-refresh interval, and obtaining the number of fixed bit errors at the initial self-refresh interval;

[0020] S42, gradually reducing the self-refresh interval, running a checkerboard cyclic read and write test, and obtaining the number of fixed-bit errors when the self-refresh interval is gradually reduced;

[0021] S43, determining whether the fixed bit error has disappeared, if so, obtaining the annealing curve, if not, continuing to determine whether the predetermined total annealing time has been reached, if so, obtaining the annealing curve, if not, returning to S41.

[0022] Optionally, obtaining an annealing curve includes:

[0023] Calculating an error cross section according to the number of error bits, the total number of bits on the chip, and the particle fluence that reaches the damage threshold, and drawing the annealing curve according to the error cross section;

[0024] The calculation method of the error section is:

[0025]

[0026] Among them, σ 固定位 is the error section, N 错误比特数量 is the number of error bits, C 芯片总比特数 is the total number of bits on the chip, F 高能粒子注量 is the particle fluence that reaches the damage threshold.

[0027] The present invention also provides a device for implementing a DDR4 SDRAM fixed bit error test method based on high-energy particles, comprising: a host computer and a slave computer;

[0028] The upper computer is used to send instructions to the lower computer;

[0029] The lower computer is used to execute the corresponding program after receiving the corresponding instruction and report the error status, error count, working voltage and working current parameters of the sample device, and visualize the distribution of error information and the change characteristics of electrical parameters.

[0030] The beneficial effects of the present invention are as follows: the present invention provides a test method and apparatus for evaluating the sensitivity of fixed-bit errors of DDR4 SDRAMs from different manufacturers and batches. The method is applicable to DDR4 SDRAMs with the same packaging and electrical interface specifications, and can effectively identify the physical address distribution and error pattern characteristics of fixed-bit errors in the chip. The method selects appropriate particle types, energy, and flux in the test to effectively identify fixed-bit errors. By comparing the damage injection threshold and the annealing characteristic information of fixed-bit errors under different self-refresh interval conditions, a reliable basis can be provided for the screening of commercial-grade DDR4 SDRAM chips, thereby determining the optimal device. The method provides a standardized ground test method for the selection and evaluation of DDR SDRAM devices in high-performance aerospace electronic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 This is a flow chart of a DDR4 SDRAM stuck-bit error test method based on high-energy particles according to an embodiment of the present invention;

[0033] Figure 2 The range parameters of 5MeV protons in silicon material calculated using the Monte Carlo method according to an embodiment of the present invention;

[0034] Figure 3 This is a flow chart of annealing curve measurement under different self-refresh levels, temperatures, and time conditions according to an embodiment of the present invention;

[0035] Figure 4 This is a flow chart of extracting and analyzing error data through a checkerboard loop read and write test according to an embodiment of the present invention;

[0036] Figure 5 Schematic diagram of a DDR4 SDRAM stuck-bit error test device based on high-energy particles according to an embodiment of the present invention;

[0037] Figure 6 This is a distribution diagram of the number of stuck bit errors in each bank of a DDR4 SRAM according to an embodiment of the present invention;

[0038] Figure 7 This is an annealing curve diagram of the 5MeV proton irradiated sample M5 of the device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Example 1:

[0042] This embodiment provides a DDR4 SDRAM stuck-bit error test method based on high-energy particles, including:

[0043] S1. Obtain a DDR4 SDRAM sample device, select the target radiation source, and irradiation energy;

[0044] S2. irradiating the sample device from an initial particle fluence according to the target radiation source and irradiation energy;

[0045] S3. Determine whether a stuck-bit error occurs in the sample device after irradiation. If no stuck-bit error occurs, irradiate the sample device with an increased particle fluence based on the initial particle fluence, and repeat S3. If a stuck-bit error occurs, record the particle fluence that reaches the damage threshold and determine the number of stuck-bit errors.

[0046] S4. Measure the annealing curve of the sample device, obtain the annealing curve according to the particle fluence that reaches the damage threshold, and determine the optimal device according to the damage threshold and the annealing curve.

[0047] Specifically, the irradiation test was conducted using this particle source. Since the damage mechanism of fixed-bit errors is the change in electrical properties caused by lattice defects caused by atomic displacement, the test was conducted under no-bias conditions after the device was removed from the package and exposed to the silicon substrate. At the same time, in order to avoid the possible obstruction of particles by air, the test was conducted in a vacuum environment as much as possible. Several particle fluence levels need to be determined before the test is carried out, which can range from 1×10 7 p / cm 2 After injection, the test work of fixing the bit errors begins.

[0048] Furthermore, the target radiation source and irradiation energy are selected as follows:

[0049] Disassemble the sample device to obtain silicon crystal bare wafers;

[0050] The distance from the substrate edge to the active area is obtained by measuring the silicon crystal die using focused ion beam technology and electron microscope;

[0051] The maximum atomic displacement distribution of the incident particles in the silicon substrate is calculated, and the target radiation source and irradiation energy are selected based on whether the distance from the substrate edge to the active area and the maximum atomic displacement distribution are within the preset range.

[0052] Specifically, a sample of the device to be tested is first taken for a destructive disassembly test to observe the internal structure. After the silicon crystal die is removed by chip depackaging, the device array area is observed using focused ion beam (Focused Ion Beam) technology and an electron microscope in the storage array area S1. The distance from the edge of the chip substrate to the active area (Active Aera) is determined. This is because the flip-package characteristics of the device mean that particles can only be incident from the back of the device to conduct the test without affecting the electrical testability. After obtaining the precise distance from the substrate edge to the active area, the maximum atomic displacement distribution of the incident particles in the silicon substrate is calculated to select the appropriate irradiation source and irradiation energy.

[0053] Furthermore, determining whether a fixed bit error occurs in the sample device after irradiation includes determining whether a fixed bit error occurs in the sample device after irradiation by performing a full-address checkerboard cyclic read-write check.

[0054] Furthermore, recording the particle fluence that reaches the damage threshold includes:

[0055] If an error occurs at the same fixed physical address during multiple full-address checkerboard cyclic read and write cycles, and the error does not disappear after power is cycled, a damage event of a fixed bit error is determined, and the particle dose that reaches the damage threshold is recorded.

[0056] Furthermore, measuring the annealing curve of the sample device includes:

[0057] S41, presetting an initial self-refresh interval for the sample device, performing a checkerboard cyclic read and write test under the initial self-refresh interval, and obtaining the number of fixed bit errors under the initial self-refresh interval;

[0058] S42, gradually reducing the self-refresh interval, running a checkerboard cyclic read and write test, and obtaining the number of fixed-bit errors when the self-refresh interval is gradually reduced;

[0059] S43, determine whether the fixed bit error disappears, if it disappears, obtain the annealing curve, if not, continue to determine whether the predetermined total annealing time is reached, if so, obtain the annealing curve, if not, return to S41.

[0060] Furthermore, obtaining the annealing curve includes:

[0061] Calculating an error cross section according to the number of error bits, the total number of bits on the chip, and the particle fluence that reaches the damage threshold, and drawing the annealing curve according to the error cross section;

[0062] The calculation method of the error section is:

[0063]

[0064] Among them, σ 固定位 is the error section, N 错误比特数量 is the number of error bits, C 芯片总比特数 is the total number of bits on the chip, F 高能粒子注量 is the particle fluence that reaches the damage threshold.

[0065] The present embodiment will be further described below with reference to the accompanying drawings:

[0066] Figure 1 This is a schematic diagram of the fixed bit error test process of DDR4 SDRAM according to an embodiment of the present invention. S1: Take a sample of the device to be tested for destructive disassembly test to observe the internal structure. After taking out the silicon crystal die through the chip unpacking method, observe the device array area in the storage array area using the focused ion beam (Focused Ion Beam) technology and electron microscope. S2: Determine the distance from the edge of the substrate to the active area (Active Aera) of the chip. This is because the inverted packaging characteristics of the device result in that the test can only be carried out by incident particles from the back of the device without affecting the electrical testability. After obtaining the precise distance from the edge of the substrate to the active area, calculate the maximum atomic displacement distribution of the incident particles in the silicon substrate to select a suitable irradiation source and irradiation energy; Figure 2 For example, the range parameters of 5MeV protons in silicon materials are calculated using the Monte Carlo method, including the maximum range, atomic displacement, and linear energy transfer data. If the distribution position of the particle's maximum atomic displacement is close to the measured distance from the edge of the DDR4 SDRAM device substrate to the active area, the optimal test particle type and energy conditions can be determined. The particle source is further used to carry out irradiation tests. Since the damage mechanism of fixed-bit errors is the change in electrical properties caused by lattice defects caused by atomic displacement, the device is removed from the package and the silicon substrate is exposed. After the device is tested to be working normally, the test can be carried out under no-bias conditions. At the same time, in order to avoid the possible blocking effect of air on the particles, the test is carried out in a vacuum environment as much as possible. S3: Before the test is carried out, several particle fluence levels need to be determined, which can be from 1×10 7 p / cm 2After the injection, the test for fixed-bit errors begins. S4: The high-energy particle injection is then increased by one or two orders of magnitude. After reaching a test point at a certain injection level, the sample is removed for testing (multiple samples from the same batch can also be prepared and observed at different injection levels). The test method is to perform a full-address checkerboard cyclic write and then read verification to observe whether a fixed-bit error occurs. S5: If a fixed-bit error does not occur, the irradiation injection is continued to increase until the next observation point and then continue observation. S6: If an error is found at a fixed physical address during multiple read-write cycles, and the error does not disappear after power is cycled, it is considered that a fixed-bit error damage event has occurred. The particle injection that reaches the damage threshold is recorded and the post-irradiation test phase begins. S7: The number of error bits is determined through multiple full-address cyclic read-write cycles, and the average and standard error are calculated. Room temperature annealing or high-temperature annealing tests are performed according to actual needs. S8: Annealing curves are measured under different self-refresh levels, temperatures, and time conditions. S9: Compare the damage threshold and annealing curves of different DDR4 SDRAM devices under the same test conditions (e.g., different manufacturers, production batches, and undergoing different degrees of cycle aging experiments), and select the device with a high damage threshold and fast annealing speed as the optimal device.

[0067] Since this type of error is affected by the device operating conditions, it is necessary to further adjust different operating parameter levels to fully measure the radiation damage characteristics. This step includes several sub-processes such as Figure 3 SS1: After the irradiation test, the irradiated device will be refreshed for the first time. refi Set to 7.9 microseconds under the device standard X1 condition. SS2: Run multiple rounds of checkerboard cycle read and write tests to record the number of errors. SS3: Then gradually reduce the self-refresh interval T refi To X2: 3.95 microseconds and X4: 1.925 microseconds or set more levels as needed, SS4: run the checkerboard loop read and write test to determine the T refi The number of errors under the working conditions, SS5: Determine whether the fixed-bit error disappears, SS6: If not, continue to determine whether the predetermined total annealing time has been reached, SS7: If not, continue the fixed-interval annealing test and repeat steps SS1-SS5. The post-irradiation test can be terminated after the maximum time interval is reached or the fixed-bit error disappears, and the annealing curves at different refresh levels are plotted as parameters for device evaluation.

[0068] Example 2:

[0069] This embodiment provides a DDR4 SDRAM fixed bit error test device based on high-energy particles, including: a host computer and a slave computer;

[0070] The upper computer is used to send instructions to the lower computer;

[0071] The lower computer is used to execute the corresponding program after receiving the corresponding instructions and report the error status, error count, working voltage and current parameters of the sample device, and visualize the distribution of error information and the change characteristics of electrical parameters.

[0072] Specifically, the DDR4 SDRAM test software and hardware system is the key support in the test process. Its basic hardware and software structure is as follows: Figure 5 As shown in the figure, the test system is divided into the upper computer and the lower computer.

[0073] The lower computer includes:

[0074] (1) SoC, which includes programmable logic (PL) and processing system (PS);

[0075] (2) FGBA-96 test fixture;

[0076] (3) DDR4 cache;

[0077] (4) Gigabit Ethernet port physical layer chip (PHY);

[0078] (5) CAN interface communication module;

[0079] (6)Serial communication module;

[0080] The host computer includes:

[0081] (1) SoC status monitoring program module;

[0082] (2) DDR4 basic operating parameters and command issuing program module;

[0083] (3)PL DDR4 data high-speed transmission and storage program module;

[0084] (4) Error data, electrical data storage and visualization program modules;

[0085] (5) The PL communicates with the DDR4 SDRAM device under test through the XPIO interface in the NOC bus;

[0086] (6) The PS is used to process test data and upload data through the Gigabit Ethernet port.

[0087] The DDR4 basic operating parameters and command issuing module includes:

[0088] (a) Command control system based on CAN bus communication;

[0089] (b) Instruction design includes data pattern, test method, number of cycles and test switch signal.

[0090] The error data, electrical data storage and visualization module includes:

[0091] (a)MySQL database interaction program;

[0092] (b) Graphical interactive interface subroutine;

[0093] (c) Visual drawing subroutine for error information distribution and electrical parameter change characteristics.

[0094] The lower computer utilizes the programmable logic (PL) in the SoC (8) and an IP core to implement communication between the XPIO interface on the NOC bus and the DDR4 SDRAM device under test (DUT) (6). This device is placed in an FGBA-96 test fixture (7), allowing for flexible assembly and disassembly of the DUT without soldering. The processing system (PS) in the SoC processes and uploads test data. Its basic components include several DDR4 buffers (5) for temporarily storing data from the DUT. Because DDR4 SDRAM typically has a capacity of several Gbits and a large data volume, traditional serial communication performance is insufficient for testing. Therefore, Ethernet functionality is implemented using the PS and a Gigabit Ethernet physical layer chip (PHY). The CAN interface is used to upload DUT electrical parameters such as voltage and current and to receive test command information from the upper computer. The serial port is used to upload the test system's operating status, including the startup process and device connection status.

[0095] The host computer control program can be run on a personal computer. The SoC status monitoring module ① receives and processes various status information reported by the SoC on the slave computer. It verifies that the test system has booted properly and that the DUT is secured in the test fixture and connected properly. The DDR4 basic operating parameter and command distribution module ② includes a command control system implemented using CAN bus communication. The command design includes instructions such as data pattern (all 0s, all 1s, and checkerboard test), test method (single read / write or cyclic read / write), number of cycles, and test switch signals. After receiving the corresponding command, the slave computer executes the corresponding program and reports parameters such as the DUT error status, error count, operating voltage, and operating current to the device. The PL DDR4 high-speed data transmission and storage module ③ includes high-speed transmission of the DUT's internal data based on the TCP / IP protocol. The error data, electrical data storage, and visualization module ④ includes a MySQL database program for storing detailed error data. A graphical interactive interface subroutine can export data from specific test cycles according to user needs. A subroutine for visualizing the distribution of error information and the changing characteristics of electrical parameters is used to observe the error distribution.

[0096] The experimental results of high-energy particle irradiation obtained by the device of this embodiment are as follows:

[0097] The focused ion beam test was used to measure the distance from the edge of the silicon substrate to the active area of ​​a DDR4 SDRAM sample to be tested. The simulation calculation was used to find that the peak atomic displacement of 5MeV protons was located near 215um, which was close to the measurement result of the device. Therefore, this proton energy was used for the test. For comparison, protons with energies of 3MeV and 80MeV were used as the reference group. The atomic displacement peak of 3MeV protons theoretically cannot reach the active area of ​​the device, so it cannot cause errors. 80MeV protons completely penetrate the active area due to their long range, so they cannot deposit more energy in the active area or cause more atomic displacements. The results of the test using multiple samples are shown in Table 1. It can be seen that fixed bit errors were not found under 3MeV and 80MeV proton irradiation. Three fluence levels were set in the 5MeV irradiation test, and it was found that only at 1×10 11 p / cm 2 Fixed bit errors occur under the conditions of high-intensity injection, and the corresponding fixed bit error damage threshold is recorded. The test system described in this embodiment is used to extract and analyze the error data, and it is found that the error distribution in the address space of DDR4 SDRAM Bank Group (BG) number distribution is slightly different, and the distribution in each bank is relatively uniform, such as Figure 6 shown.

[0098] like Figure 4 As shown, the checkerboard loop read and write test is used to extract and analyze error data, specifically including the following: SSA: Divide the entire address space of DDR4 SDRAM into several data blocks of equal size from low to high address bits; SSB: Write the 4-digit hexadecimal number 5555 to the address of the odd block and the 4-digit hexadecimal number AAAA to the address of the even block; SSC: After writing all addresses, read the data at these addresses and compare and verify with the written data. The verification range is the entire address space of the chip; SSD: Report the total number of errors, addresses, and error types (0 to 1 errors or 1 to 0 errors) through the test system Ethernet; SSE: Write the odd blocks to AAAA and the even blocks to 5555 starting from the low address again; SSF: After writing all addresses, verify the entire memory space and report the total number of errors, addresses, and error types (0 to 1 errors or 1 to 0 errors) through the test system Ethernet; SSH: Determine whether the predetermined test cycle has been reached; SSI: If the predetermined test cycle has been reached, calculate the error mean and standard error. If the predetermined test cycle has not been reached, return to SSA.

[0099] Table 1

[0100]

[0101] Table 2

[0102]

[0103] Table 2 shows the typical stuck-at-bit error failure modes detected in the post-irradiation test, which are divided into stuck-at-0 and stuck-at-1 failure types:

[0104] Fixed 0: writing 1 and reading 0 is an error.

[0105] Fixed 1: Writing 0 and reading 1 is wrong.

[0106] Both error modes are single-bit errors, and the two error modes have a 1:1 correspondence in terms of total volume.

[0107] Figure 7 The figure shows the annealing curve for device sample M5 irradiated with 5MeV protons. Annealing was performed at room temperature for approximately 96 hours, with irradiation testing performed every 24 hours using a test system to determine the number of stuck-on bit errors. Subsequently, high-temperature annealing tests were performed in a constant-temperature oven at 85°C to obtain a stuck-on bit error annealing curve. Annealing tests demonstrated that high temperature accelerates the annealing of stuck-on bit damage in DDR4 SDRAM devices. Furthermore, at a x4 refresh interval, stuck-on bit errors decreased by approximately two orders of magnitude, while a x2 refresh interval had minimal impact on stuck-on bit errors. The stuck-on bit error characteristic curve for this device was plotted. The error cross section is calculated as follows:

[0108]

[0109] The purpose of this formula is to draw the annealing curve, which is the calculation method of the vertical coordinate of the annealing curve. 固定位 is the error section, N 错误比特数量 is the number of error bits, C 芯片总比特数 is the total number of bits on the chip, F 高能粒子注量 is the particle fluence that reaches the damage threshold.

[0110] The embodiments described above are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by persons skilled in the art should fall within the scope of protection defined by the claims of the present invention.

Claims

1. A DDR4 SDRAM fixed bit error test method based on high-energy particles, characterized in that: include: S1. Obtain a DDR4 SDRAM sample device, select the target radiation source, and irradiation energy; S2. irradiating the sample device from an initial particle fluence according to the target radiation source and irradiation energy; S3, determining whether a stuck-bit error occurs in the sample device after irradiation; if no stuck-bit error occurs, irradiating the sample device with an increased particle fluence according to the initial particle fluence, and repeating S3; if a stuck-bit error occurs, recording the particle fluence that reaches the damage threshold and determining the number of error bits; S4. Measure the annealing curve of the sample device, obtain the annealing curve according to the particle fluence that reaches the damage threshold, and determine the optimal device according to the damage threshold and the annealing curve.

2. The DDR4 SDRAM stuck bit error test method based on high-energy particles according to claim 1, characterized in that: Select target radiation source and irradiation energy including: disassembling the sample device to obtain a silicon crystal die; Measuring the silicon crystal die using focused ion beam technology and an electron microscope to obtain a distance from the edge of the substrate to the active area; The maximum atomic displacement distribution of the incident particles in the silicon substrate is calculated, and the target radiation source and irradiation energy are selected based on whether the distance from the substrate edge to the active area and the maximum atomic displacement distribution are within a preset range.

3. The DDR4 SDRAM fixed bit error test method based on high-energy particles according to claim 1, characterized in that: Determining whether a fixed bit error occurs in the sample device after irradiation includes: determining whether a fixed bit error occurs in the sample device after irradiation through full-address checkerboard cyclic read and write verification.

4. The DDR4 SDRAM fixed bit error test method based on high-energy particles according to claim 3, characterized in that: Recording the particle fluence that reaches the damage threshold includes: If an error occurs at the same fixed physical address during multiple full-address checkerboard cyclic read and write cycles, and the error does not disappear after power is cycled, a damage event of a fixed bit error is determined, and the particle dose that reaches the damage threshold is recorded.

5. The DDR4 SDRAM stuck bit error test method based on high-energy particles according to claim 1, characterized in that: Measuring the annealing curve of the sample device includes: S41, presetting an initial self-refresh interval for the sample device, performing a checkerboard cycle read and write test at the initial self-refresh interval, and obtaining the number of fixed bit errors at the initial self-refresh interval; S42, gradually reducing the self-refresh interval, running a checkerboard cyclic read and write test, and obtaining the number of fixed-bit errors when the self-refresh interval is gradually reduced; S43, determining whether the fixed bit error has disappeared, if so, obtaining the annealing curve, if not, continuing to determine whether the predetermined total annealing time has been reached, if so, obtaining the annealing curve, if not, returning to S41.

6. The DDR4 SDRAM fixed bit error test method based on high-energy particles according to claim 5, characterized in that: Obtaining the annealing curve includes: calculating an error cross section according to the number of error bits, the total number of bits on the chip, and the particle fluence reaching the damage threshold, and drawing the annealing curve according to the error cross section; The calculation method of the error section is: Among them, σ 固定位 is the error section, N 错误比特数量 is the number of error bits, C 芯片总比特数 is the total number of bits on the chip, F 高能粒子注量 is the particle fluence that reaches the damage threshold.

7. A device for implementing the DDR4 SDRAM fixed bit error test method based on high-energy particles according to any one of claims 1 to 6, characterized in that: include: Upper computer and lower computer; The upper computer is used to send instructions to the lower computer; The lower computer is used to execute the corresponding program after receiving the corresponding instruction and report the error status, error count, working voltage and working current parameters of the sample device, and visualize the distribution of error information and the change characteristics of electrical parameters.

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