Cml latch, divide-by-two circuit, and device hardened against single event upsets

Abstract

The application discloses an anti-single-event upset reinforced CML latch, a frequency division circuit and equipment, the CML latch of the application comprises a latch circuit composed of NMOS transistors, PMOS transistors for inhibiting the "1 to 0" jump of single-event upset are connected to both input sides of the latch circuit, the signal connected to the gate of one PMOS transistor is a frequency division clock signal clk180-o obtained by current mode to CMOS conversion of the 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the signal connected to the gate of the other PMOS transistor is a frequency division clock signal clk0-o obtained by current mode to CMOS conversion of the 0-degree phase frequency division clock signal clk0 output by the latch circuit. The application aims at achieving anti-single-event upset reinforcement for the CML latch with low overhead, and improving the anti-radiation reinforcement performance of the CML latch.

Description

TECHNICAL FIELD

[0001] The present application relates to the anti-radiation hardening technology in the field of circuit, in particular to a CML latch, a frequency division circuit and equipment for anti-single event upset hardening. BACKGROUND

[0002] With the reduction of process size, space radiation effects, especially single event effects, are becoming more and more serious, which brings challenges to aerospace circuit design. In the design of integrated circuits for aerospace, anti-radiation hardening design is often needed, which can be divided into digital integrated circuit hardening and analog integrated circuit hardening. Relatively speaking, digital integrated circuit hardening design is more general and therefore favored by researchers. There are extensive researches on different process nodes, from architecture to circuit to layout. Analog circuit hardening is less researched due to its difficulty and poor generality.

[0003] The latch is often used in high-speed frequency divider used in analog circuits. Because of the high speed requirement, a design different from the digital structure latch is needed. The commonly used latch in digital circuits is composed of two head-to-tail connected inverters, and its stable working points are power supply and ground voltage respectively. A large voltage change is needed to complete the flip of the latch state, which is difficult to apply directly in analog circuits. The commonly used latch in analog circuits increases current source or resistance for current limiting on the basis of digital latch, and uses large size transistors to reduce the steady-state voltage difference of the latch and the voltage change required for flip, thereby improving the speed of the latch. Although there are many solutions for digital latch hardening, such as DICE, TMR, DHC, LEAP, and RC filter, etc. But because of the speed, structure and other limitations, it is difficult to directly transplant to the hardening design of CML (current mode logic) latch commonly used in frequency divider. It is necessary to propose corresponding hardening measures according to the characteristics of analog circuits.

[0004] As shown in Figure 1 The traditional high-speed clock frequency division circuit is composed of two CML latches Latch L and Latch R with the same structure connected head to tail, and a pair of differential clocks clk and clkz are inputted, and four-phase clocks clk0, clk90, clk180 and clk270 after frequency division are outputted through the CML latches Latch L and Latch R.

[0005] As shown in Figure 2As shown, the CML latch includes a pair of resistors R1, R2 and three pairs of NMOS transistors (M1, M2), (M3, M4) and (M5, M6), wherein the pair of NMOS transistors (M5, M6) is controlled by the differential clock clk, clkz for selecting whether the input side NMOS transistors (M3, M4) are turned on or the hold side NMOS transistors (M1, M2) are turned on.

[0006] According to the principle of single particle effect, the PN junction with reverse bias is a sensitive point of single particle effect. In the main part of the CML latch, only NMOS transistors are present, so single particle effect occurs only when the NMOS transistors are turned off and the storage node stores "1", that is, the storage node flips, i.e., "1" flips to "0". The circuit is configured to work at 28GHz. At 0.5ns, a double exponential current source is injected into the drain of the M1 transistor in the Latch R to simulate single particle effect. The result is shown in Fig. 1. Figure 3 As shown in Fig. 1, clk0 / clk90 / clk180 / clk270 are the original output clocks of the affected frequency division circuit, referred to as original clocks, and clk0-o / clk90-o / clk180-o / clk270-o are the clocks after current-mode-to-CMOS conversion, referred to as output clocks. It can be found that there is obvious clock jitter after current injection. When charge is injected into the drain of the M1 transistor, the potential of the drain is lowered, resulting in a decrease in the maximum amplitude of the clk180 signal. When the clk180 signal is transmitted to the corresponding Latch L, the lower amplitude affects the normal operation of the M4 transistor in the Latch L, resulting in an increase in the minimum value of the clk90 signal, which exceeds the conversion margin. The converted output clk90-o produces single particle flip, forming a long "1" signal, and the corresponding clk270-o forms a long "0" signal. SUMMARY

[0007] The technical problem to be solved by the present application is to provide an anti-single particle flip reinforced CML latch, a frequency division circuit and a device to solve the above problems in the prior art. The present application aims to achieve anti-single particle flip reinforcement for the CML latch with low overhead and improve the anti-radiation reinforcement performance of the CML latch.

[0008] To solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0009] The anti-single event upset hardened CML latch comprises a latch circuit composed of NMOS transistors, PMOS transistors are connected to both input sides of the latch circuit for suppressing the "1→0" jump of single event upset, and the gate ck2_o of one of the PMOS transistors is connected to a current-mode-to-CMOS converted frequency division clock signal clk180-o of a 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the gate ckz2_o of the other PMOS transistor is connected to a current-mode-to-CMOS converted frequency division clock signal clk0-o of a 0-degree phase frequency division clock signal clk0 output by the latch circuit.

[0010] Optionally, the latch circuit comprises resistors R1-R2, NMOS transistors M1-M6 and PMOS transistors M7-M8, the latch circuit has two power supply terminals in1 and in2, the power supply terminal in1 is connected to the output terminal y of the first output clock signal through the resistor R2, the power supply terminal in2 is connected to the output terminal yz of the second output clock signal through the resistor R1, the output terminal y is connected to the drain of the NMOS transistors M4, M2 and the gate of the NMOS transistor M1, the output terminal yz is connected to the drain of the NMOS transistors M1, M3 and the gate of the NMOS transistor M2, the gate of the NMOS transistor M3 is the input terminal a of the third clock signal, the gate of the NMOS transistor M4 is the input terminal az of the fourth clock signal, the sources of the NMOS transistors M1, M2 are connected to the drain of the NMOS transistor M5, the sources of the NMOS transistors M3, M4 are connected to the drain of the NMOS transistor M6, the gate of the NMOS transistor M5 is connected to the input clock signal ckz, the gate of the NMOS transistor M6 is connected to the input clock signal ck, the clock signal ckz and the clock signal ck are a pair of differential clock signals, and the sources of the NMOS transistors M5, M6 are connected to each other.

[0011] Optionally, the PMOS transistors comprise a PMOS transistor M7 connected to the drain of the NMOS transistor M3 and a PMOS transistor M8 connected to the drain of the NMOS transistor M4, the gate ck2_o of the PMOS transistor M7 is connected to a current-mode-to-CMOS converted frequency division clock signal clk180-o of a 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the gate ckz2_o of the PMOS transistor M8 is connected to a current-mode-to-CMOS converted frequency division clock signal clk0-o of a 0-degree phase frequency division clock signal clk0 output by the latch circuit.

[0012] Optionally, the drains of the PMOS transistors M7 and M8 are connected to a power supply port vdda.

[0013] Optionally, a current source is connected to the source of the NMOS transistors M5 and M6 for providing a tail current for the latch circuit.

[0014] Further, the application also provides a divide-by-two circuit, which is composed of two CML latches Latch L and Latch R with the same structure connected in head-to-tail mode, the input of the CML latches Latch L and Latch R is a pair of differential clock clk and clkz, the CML latch Latch L includes two output ports for outputting the divide-by-two four-phase clock clk90 and clk270, the CML latch Latch R includes two output ports for outputting the divide-by-two four-phase clock clk0 and clk180, and the CML latches Latch L and Latch R are the anti-single event upset hardened CML latches.

[0015] Optionally, the input end a of the CML latch Latch L is used for inputting the divide-by-two clock signal clk0 with 0-degree phase, the input end az is used for inputting the divide-by-two clock signal clk180 with 180-degree phase, the output end y is used for outputting the divide-by-two clock signal clk90 with 90-degree phase, and the output end yz is used for outputting the divide-by-two clock signal clk270 with 270-degree phase; the input end a of the CML latch Latch R is used for inputting the divide-by-two clock signal clk270 with 270-degree phase, the input end az is used for inputting the divide-by-two clock signal clk90 with 90-degree phase, the output end y is used for outputting the divide-by-two clock signal clk0 with 0-degree phase, and the output end yz is used for outputting the divide-by-two clock signal clk180 with 180-degree phase.

[0016] Further, the application also provides an electronic device, which includes a device body and a circuit module arranged in the device body, and the circuit module includes the anti-single event upset hardened CML latch.

[0017] Compared with the prior art, the present application has the following advantages: the CML latch of the present application comprises a latch circuit composed of NMOS transistors, both input sides of the latch circuit are connected with PMOS transistors for inhibiting the "1→0" jump of single event upset, and the gate ck2_o of one of the PMOS transistors is connected with the current-mode-to-CMOS converted frequency division clock signal clk180-o of the 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the gate ckz2_o of the other PMOS transistor is connected with the current-mode-to-CMOS converted frequency division clock signal clk0-o of the 0-degree phase frequency division clock signal clk0 output by the latch circuit, the present application can realize the single event upset hardening of the CML latch with a lower cost, and improve the anti-radiation hardening performance of the CML latch. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is a circuit schematic diagram of a traditional high-speed clock frequency division circuit.

[0019] Figure 2 It is a circuit schematic diagram of a traditional CML latch.

[0020] Figure 3 It is a four-phase clock output and converted four-phase clock output schematic diagram of a traditional high-speed clock frequency division circuit, wherein (a) is the original four-phase clock output, and (b) is the converted four-phase clock output.

[0021] Figure 4 It is a circuit schematic diagram of the CML latch in the embodiment of the present application.

[0022] Figure 5 It is a four-phase clock output and converted four-phase clock output schematic diagram of the frequency division circuit in the embodiment of the present application, wherein (a) is the original four-phase clock output, and (b) is the converted four-phase clock output. DETAILED DESCRIPTION

[0023] In order to make the person in the art better understand the technical scheme of the present application, the technical scheme of the present application will be further described in detail below in combination with the drawings in the embodiment of the present application.

[0024] As Figure 4As shown in the figure, the anti-single event upset hardened CML latch in the embodiment includes a latch circuit composed of NMOS transistors, both input sides of the latch circuit are connected with PMOS transistors for suppressing the "1→0" jump of single event upset, and the gate ck2_o of one of the PMOS transistors is connected with the current-mode-to-CMOS converted frequency division clock signal clk180-o of the 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the gate ckz2_o of the other PMOS transistor is connected with the current-mode-to-CMOS converted frequency division clock signal clk0-o of the 0-degree phase frequency division clock signal clk0 output by the latch circuit.

[0025] As shown in the figure, Figure 4 As shown in the figure, the latch circuit in the embodiment includes resistors R1-R2, NMOS transistors M1-M6 and PMOS transistors M7-M8, the latch circuit has two power supply ends of power supply end in1 and power supply end in2, the power supply end in1 is connected to the output end y of the first route output clock signal through the resistor R2, the power supply end in2 is connected to the output end yz of the second route output clock signal through the resistor R1, the output end y is connected with the drain of NMOS transistors M4 and M2 and the gate of M1, the output end yz is connected with the drain of NMOS transistors M1 and M3 and the gate of M2, the gate of NMOS transistor M3 is the input end a of the third route clock signal, the gate of NMOS transistor M4 is the input end az of the fourth route clock signal, the source of NMOS transistors M1 and M2 is commonly connected with the drain of NMOS transistor M5, the source of NMOS transistors M3 and M4 is commonly connected with the drain of NMOS transistor M6, the gate of NMOS transistor M5 is connected with the input clock signal ckz, the gate of NMOS transistor M6 is connected with the input clock signal ck, the clock signal ckz and the clock signal ck are a pair of differential clock, and the sources of NMOS transistors M5 and M6 are connected with each other.

[0026] As shown in the figure, Figure 4As shown, the PMOS transistor in the embodiment includes the PMOS transistor M7 connected to the drain of the NMOS transistor M3 and the PMOS transistor M8 connected to the drain of the NMOS transistor M4, the gate ck2_o of the PMOS transistor M7 is connected to the current-mode-to-CMOS converted frequency-divided clock signal clk180-o output by the latch circuit, and the gate ckz2_o of the PMOS transistor M8 is connected to the current-mode-to-CMOS converted frequency-divided clock signal clk0-o output by the latch circuit. By adding the two PMOS transistors M7 and M8 to suppress the "1→0" jump, the control signals of the PMOS transistors M7 and M8 are the converted frequency-divided clock signals clk180-o (ck2_o) and clk0-o (ckz2_o), respectively. When the drain of the NMOS transistor M1 is bombarded to lower the potential, the NMOS transistor M7 will increase the injection current to offset the charge collection caused by the single event effect, and help the bombarded node to maintain the "1" potential. As shown in FIG. 2, the PMOS transistor M7 and the PMOS transistor M8 in the embodiment are connected to the power port vdda. The sources of the NMOS transistors M5 and M6 in the embodiment are connected to the current source for providing the tail current for the latch circuit, which can resist the PVT (process, voltage and temperature) disturbance. Figure 4

[0027] In addition, the embodiment further provides a frequency division by two circuit, which is composed of two CML latches L and R with the same structure connected in head-to-tail manner, the inputs of the CML latches L and R are a pair of differential clocks clk and clkz, the CML latch L includes two output ports for outputting the frequency-divided four-phase clocks clk90 and clk270, the CML latch R includes two output ports for outputting the frequency-divided four-phase clocks clk0 and clk180, and the CML latches L and R are the CML latches with the single event upset resistance as described above.

[0028] ​In the embodiment, the input end a of the CML latch L is used for inputting the frequency division clock signal clk0 of 0 degree phase, the input end az is used for inputting the frequency division clock signal clk180 of 180 degree phase, the output end y is used for outputting the frequency division clock signal clk90 of 90 degree phase, and the output end yz is used for outputting the frequency division clock signal clk270 of 270 degree phase; the input end a of the CML latch R is used for inputting the frequency division clock signal clk270 of 270 degree phase, the input end az is used for inputting the frequency division clock signal clk90 of 90 degree phase, the output end y is used for outputting the frequency division clock signal clk0 of 0 degree phase, and the output end yz is used for outputting the frequency division clock signal clk180 of 180 degree phase.

[0029] In order to verify the anti-single event upset hardened characteristics of the anti-single event upset hardened CML latch in the embodiment, the circuit of the anti-single event upset hardened CML latch in the embodiment is configured to work at 28GHz, at 0.5ns, the drain of the NMOS transistor M1 in the CML latch R is subjected to double exponential current source injection to simulate single particle effect, the current setting is the same as that of the original circuit, and finally the four-phase clock output of the final obtained frequency division circuit and the converted output diagram are as shown in Figure 3 Figure 5 It can be known from Figure 5 that the original clock amplitude changes little, and the converted output clock has little influence, which indicates that the hardened scheme of the anti-single event upset hardened CML latch in the embodiment is effective. Compared with the original circuit, the hardened circuit achieves obvious anti-single event upset effect at a lower overhead, and the area is only increased by 0.2%.

[0030] In addition, the embodiment also provides an electronic device, which comprises a device body and a circuit module arranged in the device body, and the circuit module comprises the anti-single event upset hardened CML latch described above.

[0031] The above only describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-described embodiments. Any technical scheme falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principles of the present application shall also be considered as the protection scope of the present application.​

Claims

1. A single event upset hardened CML latch comprising a latch circuit constructed of NMOS transistors, characterized in that, The two input sides of the latch circuit are connected with PMOS transistors for inhibiting the "1→0" jump of single event upset, and the gate ck2_o of one PMOS transistor is connected with the current-mode-to-CMOS converted frequency division clock signal clk180-o of the 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the gate ckz2_o of the other PMOS transistor is connected with the current-mode-to-CMOS converted frequency division clock signal clk0-o of the 0-degree phase frequency division clock signal clk0 output by the latch circuit; the latch circuit comprises resistors R1-R2, NMOS transistors M1-M6 and PMOS transistors M7-M8, and has two power supply ends, i.e., a power supply end in1 and a power supply end in2, the power supply end in1 is connected to the output end y of the first route output clock signal through the resistor R2, the power supply end in2 is connected to the output end yz of the second route output clock signal through the resistor R1, the output end y is connected with the drain of the NMOS transistor M4, the drain of the NMOS transistor M2 and the gate of the NMOS transistor M1, the output end yz is connected with the drain of the NMOS transistor M1, the drain of the NMOS transistor M3 and the gate of the NMOS transistor M2, the gate of the NMOS transistor M3 is the input end a of the third route clock signal, the gate of the NMOS transistor M4 is the input end az of the fourth route clock signal, the source of the NMOS transistor M1 and the source of the NMOS transistor M2 are commonly connected with the drain of the NMOS transistor M5, the source of the NMOS transistor M3 and the source of the NMOS transistor M4 are commonly connected with the drain of the NMOS transistor M6, the gate of the NMOS transistor M5 is connected with the input clock signal ckz, the gate of the NMOS transistor M6 is connected with the input clock signal ck, the clock signal ckz and the clock signal ck are a pair of differential clock, and the source of the NMOS transistor M5 and the source of the NMOS transistor M6 are connected with each other; the PMOS transistor comprises the PMOS transistor M7 connected with the drain of the NMOS transistor M3 and the PMOS transistor M8 connected with the drain of the NMOS transistor M4, the gate ck2_o of the PMOS transistor M7 is connected with the current-mode-to-CMOS converted frequency division clock signal clk180-o of the frequency division clock signal clk180 output by the latch circuit, and the gate ckz2_o of the PMOS transistor M8 is connected with the current-mode-to-CMOS converted frequency division clock signal clk0-o of the frequency division clock signal clk0 output by the latch circuit.

2. The single event upset hardened CML latch of claim 1, wherein, The drains of the PMOS transistor M7 and the PMOS transistor M8 are connected to the power supply port vdda.

3. The single event upset hardened CML latch of claim 1, wherein, The sources of the NMOS transistor M5 and the NMOS transistor M6 are connected with current sources for providing tail current for the latch circuit.

4. A divide-by-two circuit, the divide-by-two circuit being composed of two CML latches Latch L, Latch R of the same structure connected head to tail, an input of the CML latches Latch L, Latch R being a pair of differential clocks clk, clkz, and the CML latch Latch L including two output ports for outputting a divided-by-two four-phase clock clk90 and clk270, the CML latch Latch R including two output ports for outputting a divided-by-two four-phase clock clk0 and clk180, characterized in that, The CML latch Latch L and Latch R are the anti-single event upset reinforced CML latch of any one of claims 1-3.

5. The frequency division circuit of claim 4, wherein, The input end a of the CML latch L is used for inputting the frequency division clock signal clk0 of 0 degree phase, the input end az is used for inputting the frequency division clock signal clk180 of 180 degree phase, the output end y is used for outputting the frequency division clock signal clk90 of 90 degree phase, and the output end yz is used for outputting the frequency division clock signal clk270 of 270 degree phase; the input end a of the CML latch R is used for inputting the frequency division clock signal clk270 of 270 degree phase, the input end az is used for inputting the frequency division clock signal clk90 of 90 degree phase, the output end y is used for outputting the frequency division clock signal clk0 of 0 degree phase, and the output end yz is used for outputting the frequency division clock signal clk180 of 180 degree phase.

6. An electronic device comprising a device body and a circuit module provided in the device body, characterized by comprising: The circuit module comprises the anti-single event upset reinforced CML latch of any one of claims 1-3.

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