Low stray fractional frequency division circuit and phase-locked loop circuit of hybrid MASH structure

Abstract

The invention discloses a low-spurious fractional frequency division circuit and phase-locked loop circuit of a hybrid MASH structure, the low-spurious fractional frequency division circuit comprises a Sigma-Delta modulator, a feedback frequency division circuit and a random jitter circuit, the Sigma-Delta modulator is composed of an MASH1-1 circuit and a modulation circuit of a second-order single-ring structure, the MASH1-1 circuit is used for obtaining an overflow carry signal through accumulation aiming at decimal bit input of a frequency division coefficient, and the modulation circuit of the second-order single-ring structure is used for generating a switching control signal through accumulation and addition of the carry signal and a random dither signal aiming at integer bit input of the frequency division coefficient. The invention aims to ensure that the proportion of N and N + 1 frequency division is controllable in the switching process of the frequency dividing circuit modulator, and also ensure that the whole switching process is random so as to reduce the system quantization noise introduced by the circuit as much as possible and reduce the stray introduced by the phase-locked loop circuit.

Description

Technical Field

[0001] The present invention relates to a phase-locked loop circuit in the technical field of electronic circuits, and in particular to a low-spurious fractional frequency division circuit and a phase-locked loop circuit with a hybrid MASH structure. Background Art

[0002] Phase-locked loop circuits with fractional frequency division capabilities can achieve precise division ratio clock outputs. These circuits are typically implemented using phase interpolation circuits, digital delay-locked loops, and sigma-delta modulators. The sigma-delta modulator is a technology used for high-precision analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC). Its core principle is to improve signal resolution and signal-to-noise ratio (SNR) through oversampling and noise shaping. Sigma-delta modulators are widely used due to their simple structure, digitization capability, and ability to achieve high-precision fractional frequency division. However, the traditional MASH (Multi-Stage Noise S-Haping) architecture used to implement sigma-delta modulators generates significant quantization noise when performing integration and differentiation functions, which ultimately introduces significant spurious signals into the phase-locked loop circuit. Summary of the Invention

[0003] The technical problem to be solved by the present invention is as follows: In response to the above-mentioned problems in the prior art, a low-spurious fractional frequency division circuit and a phase-locked loop circuit with a hybrid MASH structure are provided. The present invention aims to ensure that the ratio of N and N+1 frequency divisions during the switching process of the Sigma-Delta modulator is controllable, while at the same time ensuring that the entire switching process is random to minimize the system quantization noise introduced by the circuit and reduce the spurious introduced by the phase-locked loop circuit.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A low-spurious fractional frequency division circuit with a hybrid MASH structure comprises a Sigma-Delta modulator, a feedback frequency division circuit, and a random dither circuit. The Sigma-Delta modulator comprises a MASH1-1 circuit and a modulation circuit with a second-order single-loop structure. The random dither circuit is used to generate a random dither signal and send it to the modulation circuit with the second-order single-loop structure. The MASH1-1 circuit is used to obtain an overflow carry signal by accumulating the decimal input of the frequency division coefficient and send it to the modulation circuit with the second-order single-loop structure. The modulation circuit with the second-order single-loop structure is used to generate a switching control signal for switching between two frequency division ratios, N and N+1, by accumulating the integer input of the frequency division coefficient and adding the carry signal and the random dither signal. Optionally, the MASH1-1 circuit includes two stages of first-order modulators, each modulator includes an adder and a quantizer, and the quantization error of each stage will be passed to the next stage for processing. One input of the first full adder is the decimal place of the frequency division coefficient. The decimal place input of the frequency division coefficient is accumulated and summed with the clock signal after passing through the first full adder, and the result of each accumulation and summation is sent to the second full adder of the next stage to be accumulated and summed with the clock signal, and delayed by the delay module as another input of the first full adder. The output of the second full adder is delayed by the delay module as another input of the second full adder. The accumulation and summation of the first full adder and the second full adder are performed synchronously, and the carry signal output ends of the first full adder and the second full adder are both connected to the input end of the modulation circuit of the second-order single-ring structure.

[0005] Optionally, the modulation circuit of the second-order single-loop structure includes a third full adder and a fourth full adder, a total of two stages of N-bit full adders, one input of the third full adder is the integer bit input of the frequency division coefficient, the overflow carry signal of the first full adder, and the switching control signal result of the previous beat output of the modulation circuit of the second-order single-loop structure subtracted, the output code value of the third full adder is delayed by a delay module and serves as another input of the third full adder, the input of the fourth full adder is the output code value of the third full adder, the overflow carry signal of the second full adder, and the switching control signal result of the previous beat output of the modulation circuit of the second-order single-loop structure subtracted, the output of the fourth full adder is delayed by a delay module, and a random jitter signal is added to generate a switching control signal for switching between the two frequency division ratios of N and N+1, and the signal of the output of the fourth full adder after being delayed by the delay module serves as another input of the fourth full adder.

[0006] Optionally, the N-bit full adder is formed by cascading N 1-bit adders, the first input terminal of the 1-bit adder is connected to the sum output terminal Sum of the 1-bit adder through a trigger, the second input terminal is connected to the one-bit input signal Bi of the N-bit full adder, the third input terminal is connected to the input signal Cin of the N-bit full adder or the output terminal Cout of the previous stage 1-bit adder, and the output terminal Cout is connected to the third input terminal of the next stage 1-bit adder or serves as the output terminal of the N-bit full adder.

[0007] Optionally, the random jitter circuit is a linear shift feedback register.

[0008] Optionally, the linear shift feedback register includes n stages of D flip-flops D0 to D1 connected in cascade sequence. n-1 and n-1 registers, and the nth level D flip-flop D n-1 The output end of is connected to the input end of the first stage D flip-flop D0, and the 1st to nth stage D flip-flops D0 to D n-1There is an adder in series between any adjacent D flip-flops, and any i-th level D flip-flop D i One input of the previous adder is the D flip-flop D of the i-1th stage i-1 , the other input is the i-1th register h i-1 , and the input terminals of n-1 registers are connected to the nth level D flip-flop D n-1 connected to the output terminal.

[0009] Optionally, the feedback frequency division circuit includes a dual-mode pre-divider, a pulse counter and a counter, the output end of the Sigma-Delta modulator, the dual-mode pre-divider and the pulse counter are connected in sequence and the output end of the pulse counter serves as the output end of the feedback frequency division circuit, the input end of the counter is respectively connected to the dual-mode pre-divider and the pulse counter, and the output end of the counter is connected to the control end of the dual-mode pre-divider so that the dual-mode divider processes N and N+1 divisions.

[0010] Optionally, the counter is a swallowing counter.

[0011] Optionally, the modulus P of the pulse counter is greater than the modulus S of the swallowing counter.

[0012] In addition, the present invention also provides a phase-locked loop circuit, including a pulse source PULSE, two current sources I, a phase detector PFD, a low-pass filter LPF, a voltage-controlled oscillator VCO and a frequency dividing circuit. The phase detector PFD is used to capture the phase difference between the output voltage signal Vdiv of the frequency dividing circuit and the reference signal Vref output by the pulse source PULSE and output control signals u and d for respectively controlling the two current sources I connected in series. The middle node between the two current sources I is connected to the input end of the low-pass filter LPF, so that after the high-frequency components are filtered out by the low-pass filter LPF, an output signal Vout regulated by the control voltage is generated through the voltage-controlled oscillator VCO. The output signal Vout also serves as the input of the frequency dividing circuit to generate the output voltage signal Vdiv. The frequency dividing circuit is a low-spurious fractional frequency dividing circuit with a hybrid MASH structure.

[0013] Compared with the prior art, the present invention primarily achieves the following beneficial effects: the Sigma-Delta modulator in the low-spurious fractional frequency division circuit of the hybrid MASH structure of the present invention comprises a MASH1-1 circuit and a second-order single-loop modulation circuit. The MASH1-1 circuit is used to accumulate the decimal inputs of the frequency division coefficient to obtain an overflow carry signal and send it to the second-order single-loop modulation circuit. The second-order single-loop modulation circuit is used to accumulate the integer inputs of the frequency division coefficient, add the carry signal, and perform a random dithering signal to generate a switching control signal for switching between two frequency division ratios, N and N+1. The modulator of the present invention controls the frequency division ratio of the feedback frequency division circuit in the phase-locked loop to achieve switching between the two frequency division ratios, N and N+1. Precise fractional frequency division is achieved by controlling the ratio of the N division to the N+1 division. During the switching process, the Sigma-Delta modulator can ensure that the ratio of the N and N+1 divisions is controllable and that the entire switching process is random, thereby reducing system quantization noise introduced by the circuit and reducing spurious signals introduced by the phase-locked loop circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the circuit structure of the phase-locked loop circuit in an embodiment of the present invention.

[0015] Figure 2 Schematic diagram of the circuit structure of a low-spurious fractional frequency division circuit in an embodiment of the present invention.

[0016] Figure 3 Schematic diagram of the circuit structure of an N-bit full adder in an embodiment of the present invention.

[0017] Figure 4 Schematic diagram of the circuit structure of the linear shift feedback register in an embodiment of the present invention.

[0018] Figure 5 Schematic diagram of the circuit structure of the feedback frequency division circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] like Figure 1 As shown, this embodiment provides a phase-locked loop circuit, including a pulse source PULSE, a charge pump (current is I), a phase detector PFD, a low-pass filter LPF, a voltage-controlled oscillator VCO and a frequency division circuit ( Figure 1(Indicated by the dashed box in the figure), the phase detector PFD is used to capture the phase difference between the output voltage signal Vdiv of the frequency divider circuit and the reference signal Vref output by the pulse source PULSE, and output control signals u and d to respectively control the two current sources I connected in series. The middle node between the two current sources I is connected to the input of the low-pass filter LPF, so that after the high-frequency components are filtered out by the low-pass filter LPF, the output signal Vout regulated by the control voltage is generated through the voltage-controlled oscillator VCO. The output signal Vout also serves as the input of the frequency divider circuit to generate the output voltage signal Vdiv. The Sigma-Delta modulator controls the frequency division ratio of the feedback frequency divider circuit in the phase-locked loop, switching between the two frequency division ratios of N and N+1. Accurate fractional frequency division is achieved by controlling the ratio of the N division and the N+1 division. Therefore, the modulator is required to ensure that the ratio of the N and N+1 divisions is controllable during the switching process, and at the same time, the entire switching process is required to be random. This can minimize the system quantization noise introduced by the circuit and increase the spurious signals that are difficult for the phase-locked loop to filter. Therefore, as Figure 2 As shown, the frequency division circuit in this embodiment is a low-spurious fractional frequency division circuit of a hybrid MASH structure, including a Sigma-Delta modulator, a feedback frequency division circuit and a random jitter circuit. The Sigma-Delta modulator is composed of a MASH1-1 circuit and a modulation circuit of a second-order single-loop structure. The random jitter circuit is used to generate a random jitter signal and send it to the modulation circuit of the second-order single-loop structure. The MASH1-1 circuit is used to obtain an overflow carry signal by accumulating the decimal input of the frequency division coefficient and send it to the modulation circuit of the second-order single-loop structure. The modulation circuit of the second-order single-loop structure The circuit is used to generate a switching control signal for switching between the two frequency division ratios of N and N+1 by accumulating, adding a carry signal and a random jitter signal to the integer bit input of the frequency division coefficient. The addition of the random jitter signal can ensure that the Sigma-Delta modulator is sufficiently random, making the entire modulation process random and reducing the generation of quantization noise. In the switching process, the Sigma-Delta modulator can ensure that the ratio of N and N+1 frequency divisions is controllable, and at the same time, it can also ensure that the entire switching process is random, thereby reducing the system quantization noise introduced by the circuit and reducing the spurious introduced by the phase-locked loop circuit.

[0021] like Figure 2As shown, the MASH1-1 circuit in this embodiment includes two-stage first-order modulators, each modulator includes an adder and a quantizer, and the quantization error of each stage will be passed to the next stage for processing. One input of the first full adder is the decimal place of the frequency division coefficient. The decimal place input of the frequency division coefficient is accumulated and summed with the clock signal after passing through the first full adder, and the result of each accumulation and summation is sent to the second full adder of the next stage to be accumulated and summed with the clock signal, and delayed by the delay module as another input of the first full adder, and the output of the second full adder is delayed by the delay module as another input of the second full adder, and the accumulation and summation of the first full adder and the second full adder are performed synchronously, and the carry signal output ends overflowing from the first full adder and the second full adder are both connected to the input end of the modulation circuit of the second-order single-ring structure.

[0022] like Figure 2 As shown, the modulation circuit of the second-order single-ring structure in this embodiment includes two stages of N-bit full adders, namely a third full adder and a fourth full adder. One input of the third full adder is the integer bit input of the frequency division coefficient, the overflow carry signal of the first full adder, and the switching control signal obtained by subtracting the previous output of the modulation circuit of the second-order single-ring structure. The output code value of the third full adder is delayed by a delay module and serves as another input of the third full adder. The input of the fourth full adder is the output code value of the third full adder, the overflow carry signal of the second full adder, and the switching control signal obtained by subtracting the previous output of the modulation circuit of the second-order single-ring structure. The output of the fourth full adder is delayed by a delay module and a random jitter signal is added to generate a switching control signal for switching between the two frequency division ratios of N and N+1. The output of the fourth full adder, after being delayed by the delay module, serves as another input of the fourth full adder. The second-stage full adder (fourth full adder) in the second-stage modulation circuit (a two-stage single-loop structure) differs from the first-stage full adder (third full adder) in that it is delayed by one clock and summed with random jitter. In contrast, the first-stage full adder directly sums the output, the carry from the second stage of MASH1-1, and the feedback code value, and feeds this sum into the second-stage input. All full adders in the two-stage modulation circuit also perform synchronous accumulation and summing operations with the clock signal. The two-stage single-loop modulation circuit requires a feedback loop to feed the final output code value back to each full adder stage through summation, achieving high-order modulation.

[0023] like Figure 3 As shown, the N-bit full adder of this embodiment is formed by cascading N 1-bit adders, and the first input end of the 1-bit adder is connected through a trigger ( Figure 3 Indicated as Z -1) is connected to the sum output terminal Sum of the 1-bit adder, the second input terminal is connected to the one-bit input signal Bi of the N-bit full adder, the third input terminal is connected to the input signal Cin of the N-bit full adder or the output terminal Cout of the previous stage 1-bit adder, and the output terminal Cout is connected to the third input terminal of the next stage 1-bit adder or serves as the output terminal of the N-bit full adder.

[0024] As an optional implementation, the random jitter circuit in this embodiment is a linear shift feedback register. Figure 4 As shown, the linear shift feedback register in this embodiment includes n stages of D flip-flops D0 to D1 connected in cascade. n-1 and n-1 registers, and the nth level D flip-flop D n-1 The output end of is connected to the input end of the first stage D flip-flop D0, and the 1st to nth stage D flip-flops D0 to D n-1 There is an adder in series between any adjacent D flip-flops, and any i-th level D flip-flop D i One input of the previous adder is the D flip-flop D of the i-1th stage i-1 , the other input is the i-1th register h i-1 , and the input terminals of n-1 registers are connected to the nth level D flip-flop D n-1 The linear shift feedback register uses a series connection of D flip-flops to achieve sequence scrolling. It also uses an exclusive OR operation to determine the relationship between the n-1th bit and the i-th bit, and then feeds back to the i-th bit, ultimately generating a random jitter signal.

[0025] like Figure 5 As shown, the feedback frequency division circuit in this embodiment includes a dual-mode pre-divider, a pulse counter, and a counter. The output end of the Sigma-Delta modulator, the dual-mode pre-divider, and the pulse counter are connected in sequence, and the output end of the pulse counter serves as the output end (OUT) of the feedback frequency division circuit. The input end of the counter is connected to the dual-mode pre-divider and the pulse counter respectively. The output end of the counter is connected to the control end (Control) of the dual-mode pre-divider so that the dual-mode divider processes N and N+1 frequency divisions. Figure 5 As shown, the counter in this embodiment is a swallowing counter. Figure 5 In the equation, 1 / P indicates that the modulus of the pulse counter is P, and 1 / S indicates that the modulus of the swallow counter is S, and the modulus P of the pulse counter is greater than the modulus S of the swallow counter.

[0026] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A low-spurious fractional frequency division circuit with a hybrid MASH structure, characterized in that: The invention comprises a Sigma-Delta modulator, a feedback frequency division circuit and a random jitter circuit. The Sigma-Delta modulator is composed of a MASH1-1 circuit and a modulation circuit with a second-order single-loop structure. The random jitter circuit is used to generate a random jitter signal and send it to the modulation circuit with the second-order single-loop structure. The MASH1-1 circuit is used to obtain an overflow carry signal by accumulating the decimal input of the frequency division coefficient and send it to the modulation circuit with the second-order single-loop structure. The modulation circuit with the second-order single-loop structure is used to generate a switching control signal for switching between two frequency division ratios, N and N+1, by accumulating the integer input of the frequency division coefficient, adding the carry signal and the random jitter signal.

2. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 1, characterized in that: The MASH1-1 circuit includes two stages of first-order modulators, each modulator includes an adder and a quantizer. The quantization error of each stage will be passed to the next stage for processing. One input of the first full adder is the decimal place of the frequency division coefficient. The decimal place input of the frequency division coefficient is accumulated and summed with the clock signal after passing through the first full adder, and the result of each accumulation and summation is sent to the second full adder of the next stage to be accumulated and summed with the clock signal, and delayed by the delay module as another input of the first full adder. The output of the second full adder is delayed by the delay module as another input of the second full adder. The accumulation and summation of the first full adder and the second full adder are performed synchronously, and the carry signal output ends of the first full adder and the second full adder are both connected to the input end of the modulation circuit with a 2nd-order single-ring structure.

3. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 2, characterized in that: The modulation circuit of the second-order single-loop structure includes two stages of N-bit full adders, namely a third full adder and a fourth full adder. One input of the third full adder is an integer bit input of a frequency division coefficient, an overflow carry signal of the first full adder, and a switching control signal obtained by subtracting the output of the previous cycle of the modulation circuit of the second-order single-loop structure. The output code value of the third full adder is delayed by a delay module and serves as another input of the third full adder. The input of the fourth full adder is an output code value of the third full adder, an overflow carry signal of the second full adder, and a switching control signal obtained by subtracting the output of the previous cycle of the modulation circuit of the second-order single-loop structure. The output of the fourth full adder is delayed by a delay module and a random jitter signal is added to generate a switching control signal for switching between frequency division ratios of N and N+1. The output of the fourth full adder, after being delayed by the delay module, serves as another input of the fourth full adder.

4. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 3, characterized in that: The N-bit full adder is formed by cascading N 1-bit adders. The first input terminal of the 1-bit adder is connected to the sum output terminal Sum of the 1-bit adder through a trigger, the second input terminal is connected to the single-bit input signal Bi of the N-bit full adder, the third input terminal is connected to the input signal Cin of the N-bit full adder or the output terminal Cout of the previous stage 1-bit adder, and the output terminal Cout is connected to the third input terminal of the next stage 1-bit adder or serves as the output terminal of the N-bit full adder.

5. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 1, characterized in that: The random jitter circuit is a linear shift feedback register.

6. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 5, characterized in that: The linear shift feedback register includes n stages of D flip-flops D0 to D1 connected in cascade sequence. n-1 and n-1 registers, and the nth level D flip-flop D n-1 The output end of is connected to the input end of the first stage D flip-flop D0, and the 1st to nth stage D flip-flops D0 to D n-1 There is an adder in series between any adjacent D flip-flops, and any i-th level D flip-flop D i One input of the previous adder is the D flip-flop D of the i-1th stage i-1 , the other input is the i-1th register h i-1 , and the input terminals of n-1 registers are connected to the nth level D flip-flop D n-1 connected to the output terminal.

7. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 1, characterized in that: The feedback frequency division circuit includes a dual-mode pre-divider, a pulse counter and a counter. The output end of the Sigma-Delta modulator, the dual-mode pre-divider and the pulse counter are connected in sequence, and the output end of the pulse counter serves as the output end of the feedback frequency division circuit. The input end of the counter is respectively connected to the dual-mode pre-divider and the pulse counter. The output end of the counter is connected to the control end of the dual-mode pre-divider so that the dual-mode divider processes N and N+1 frequency divisions.

8. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 7, characterized in that: The counter is a swallowing counter.

9. The low-spurious fractional frequency division circuit of the hybrid MASH structure according to claim 8, characterized in that: The modulus value P of the pulse counter is greater than the modulus value S of the swallowing counter.

10. A phase-locked loop circuit, characterized in that: The invention comprises a pulse source PULSE, two current sources I, a phase detector PFD, a low-pass filter LPF, a voltage-controlled oscillator VCO and a frequency dividing circuit. The phase detector PFD is used to capture the phase difference between the output voltage signal Vdiv of the frequency dividing circuit and the reference signal Vref output by the pulse source PULSE and output control signals u and d for respectively controlling the two current sources I connected in series. The middle node between the two current sources I is connected to the input end of the low-pass filter LPF, so that after the high-frequency components are filtered out by the low-pass filter LPF, an output signal Vout regulated by the control voltage is generated through the voltage-controlled oscillator VCO. The output signal Vout also serves as the input of the frequency dividing circuit to generate the output voltage signal Vdiv. The frequency dividing circuit is a low-spurious fractional frequency dividing circuit of the hybrid MASH structure as described in any one of claims 1 to 9.

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