Simulation scheduling method and simulation scheduling device for software simulation platform

Abstract

The application relates to a simulation scheduling method and a simulation scheduling device for a software simulation platform. Based on the application, the software simulation platform can comprise a platform interface, a host adapter simulation module and an HBM simulation module corresponding to a bus interface of an integrated circuit chip, a host adapter and an HBM in sequence. For continuous multiple host write requests received by the platform interface, if the addresses of the multiple write data are continuous, the multiple write data are aggregated in one on-chip write request by the host adapter simulation module, and are transferred to the HBM simulation module at one time, so that even if the host driver is limited to the fixed receiving bandwidth of the platform interface, the data to be written into the integrated circuit chip is split into multiple write data of smaller granularity, the host adapter simulation module can also avoid the increase of the data transfer times between multiple software modules of the software simulation platform through the aggregation of the multiple write data, and the software simulation efficiency on the integrated circuit chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit chip design, and in particular, to a simulation scheduling method for a software simulation platform and a simulation scheduling device for a software simulation platform. BACKGROUND

[0002] In the design phase of an integrated circuit chip, the integrated circuit chip can be simulated by software to evaluate the working performance of the integrated circuit chip after it is taped out. The software simulation of the integrated circuit chip can simulate the working process of the integrated circuit chip by using a software simulation platform without the real existence of the integrated circuit chip.

[0003] The integrated circuit chip can be usually deployed in a heterogeneous architecture, and a host chip in the heterogeneous architecture can write data (such as command data and calculation data) to the integrated circuit chip by running a host driver to drive the integrated circuit chip to complete the task assigned by the host chip. Therefore, in the process of software simulation of the integrated circuit chip supporting the heterogeneous architecture, the host driver also writes data to the software simulation platform. The software simulation platform can run multiple software modules, and the software simulation platform can simulate the working process of the integrated circuit chip completing the corresponding task by transferring data between the multiple software modules through writing data.

[0004] However, the software simulation platform has a fixed receiving bandwidth that cannot be configured, and the fixed receiving bandwidth is usually smaller than the physical transmission bandwidth between the host chip and the integrated circuit chip, so that the software simulation platform can only receive data written by the host driver in a small granularity that does not exceed the fixed receiving bandwidth. Moreover, each time the host driver writes data, the data needs to be transferred between the multiple software modules of the software simulation platform, so that the small granularity of data writing increases the number of data transfers between the multiple software modules of the software simulation platform, and thus the software simulation efficiency is not high due to the increase in the number of data transfers between the multiple software modules.

[0005] Therefore, how to improve the software simulation efficiency of the integrated circuit chip becomes a technical problem to be solved in the prior art. SUMMARY

[0006] Embodiments of the present application provide a simulation scheduling method for a software simulation platform and a simulation scheduling device for a software simulation platform, which help to improve the software simulation efficiency of the integrated circuit chip.

[0007] In one embodiment of the present application, a simulation scheduling method for a software simulation platform is provided. The software simulation platform is configured to simulate an integrated circuit chip by running multiple software modules. The multiple software modules include a platform interface, a host adapter simulation module, and an HBM simulation module that correspond to a bus interface, a host adapter, and an HBM of the integrated circuit chip, respectively. The software simulation platform allocates module memory space to the host adapter simulation module. The simulation scheduling method includes the following steps performed by the host adapter simulation module:

[0008] In response to each host write request to the HBM received from the platform interface, performing an address continuity check on the write data of the host write request; wherein the address continuity check is used to determine whether there is currently stored write data in the module memory space that is continuous with the address of the current write data;

[0009] Based on the detection result of the address continuity detection, the current write data is stored in the module memory space; wherein, if the detection result is yes or the module memory space is empty, the current write data is stored in the module memory space in an appending manner; if the detection result is no and the module memory space is not empty, the current write data is stored in the module memory space in an eviction manner, wherein the eviction manner is used to aggregate all the write data stored in the module memory space before the current write data is stored in one on-chip write request and transfer it to the HBM simulation module;

[0010] In response to the completion of storing the write data in the module memory space, a host write response for the host write request is generated to the platform interface.

[0011] In some examples, optionally, the simulation scheduling method further includes the following steps performed by the host adapter simulation module: in response to the completion of the storage of the current write data in the module memory space, detecting the data storage of the currently stored write data in the module memory space; if the data storage of the currently stored write data in the module memory space is greater than or equal to a preset data storage threshold, then all the currently stored write data in the module memory space are aggregated into one on-chip write request and transferred to the HBM simulation module.

[0012] In some examples, optionally, the fixed receiving bandwidth of the platform interface is smaller than the physical transmission bandwidth of the bus interface, the single data volume of the write data of each write request is limited to be smaller than or equal to the fixed receiving bandwidth, and the data inventory threshold is set to be equal to the physical transmission bandwidth.

[0013] In some examples, optionally, the simulation scheduling method further includes the following steps performed by the host adapter simulation module: in response to each host read request for the HBM received from the platform interface, detecting the stored write data hit by the current host read request in the module memory space; if there is currently stored write data hit by the current host read request in the module memory space, then all the current stored write data in the module memory space are aggregated into one on-chip write request and transferred to the HBM simulation module.

[0014] In some examples, optionally, the simulation scheduling method further includes the following steps performed by the host adapter emulation module: in response to each host read request for the HBM received from the platform interface, transmitting a corresponding on-chip read request to the HBM emulation module to trigger the HBM emulation module to generate an on-chip read response including read hit data of this host read request; wherein the on-chip read response is used to trigger the host adapter emulation module to generate a host read response including read hit data to the platform interface.

[0015] In some examples, optionally, the simulation scheduling method further includes the following steps performed by the host adapter simulation module: in response to a doorbell notification received from the platform interface, detecting whether there is currently stored write data in the module memory space; if there is currently stored write data in the module memory space, then all the stored write data currently in the module memory space are aggregated in one write request and transmitted to the HBM simulation module.

[0016] In some examples, optionally, the integrated circuit chip further includes a command processor, the doorbell notification is used to remind the command processor to start a task, and the multiple software modules further include a command processor simulation module corresponding to the command processor; the simulation scheduling method further includes the following steps performed by the host adapter simulation module: passing the doorbell notification to the HBM simulation module so that the command processor simulation module obtains the doorbell notification from the HBM simulation module; wherein a notification response to the doorbell notification is generated by the command processor simulation module.

[0017] In another embodiment of the present application, a simulation scheduling device for a software simulation platform is provided. The software simulation platform is configured to simulate an integrated circuit chip by running multiple software modules. The multiple software modules include a platform interface, a host adapter simulation module, and an HBM simulation module corresponding to a bus interface, a host adapter, and an HBM of the integrated circuit chip, respectively. The software simulation platform allocates module memory space to the host adapter simulation module, and the simulation scheduling device includes the following units running in the host adapter simulation module:

[0018] a continuity detection unit configured to, in response to each host write request to the HBM received from the platform interface, perform an address continuity check on the write data of the host write request; wherein the address continuity check is used to determine whether there is currently stored write data in the module memory space that is continuous with the address of the current write data;

[0019] A write data aggregation unit is configured to store the current write data into the module memory space based on a detection result of the address continuity detection; wherein, if the detection result is yes or the module memory space is empty, the current write data is stored in the module memory space in an appending manner; if the detection result is no and the module memory space is not empty, the current write data is stored in the module memory space in an eviction manner, wherein the eviction manner is used to aggregate all the write data stored in the module memory space before the current write data is stored into one on-chip write request and transfer it to the HBM simulation module;

[0020] The write response generating unit is configured to generate a host write response for the current host write request to the platform interface in response to completion of storing the current write data in the module memory space.

[0021] In some examples, optionally, the write data aggregation unit is further configured to: in response to the completion of storage of the current write data in the module memory space, detect the data stock of the currently stored write data in the module memory space; if the data stock of the currently stored write data in the module memory space is greater than or equal to a preset data stock threshold, then, all the currently stored write data in the module memory space are aggregated into one on-chip write request and transferred to the HBM simulation module.

[0022] In some examples, optionally, the fixed receiving bandwidth of the platform interface is smaller than the physical transmission bandwidth of the bus interface, the single data volume of the write data of each write request is limited to be smaller than or equal to the fixed receiving bandwidth, and the data inventory threshold is set to be equal to the physical transmission bandwidth.

[0023] In some examples, optionally, the simulation scheduling apparatus further comprises, running in the host adapter emulation module, a read hit detection unit configured to, in response to each host read request received from the platform interface for the HBM, detect stored write data in the module memory space hit by the host read request; the write data aggregation unit is further configured to, if there is currently stored write data in the module memory space hit by the host read request, aggregate all the currently stored write data in the module memory space into one on-chip write request and transfer to the HBM emulation module.

[0024] In some examples, optionally, the simulation scheduling apparatus further comprises, running in the host adapter emulation module, a read request pushing unit configured to, in response to each host read request received from the platform interface for the HBM, transmit a corresponding on-chip read request to the HBM emulation module to trigger the HBM emulation module to generate an on-chip read response including read hit data of the host read request; wherein the on-chip read response is used to trigger the host adapter emulation module to generate a host read response including the read hit data to the platform interface.

[0025] In some examples, optionally, the write data aggregation unit is further configured to, in response to a doorbell notification received from the platform interface, detect whether there is currently stored write data in the module memory space; if there is currently stored write data in the module memory space, aggregate all the currently stored write data in the module memory space into one write request and transfer to the HBM emulation module.

[0026] In some examples, optionally, the integrated circuit chip further comprises a command processor, the doorbell notification is used to remind the command processor to start a task, and the plurality of software modules further comprises a command processor emulation module corresponding to the command processor; the simulation scheduling apparatus further comprises, running in the host adapter emulation module, a notification pushing unit configured to transmit the doorbell notification to the HBM emulation module, so that the command processor emulation module obtains the doorbell notification from the HBM emulation module; wherein a notification response to the doorbell notification is generated by the command processor emulation module.

[0027] In another embodiment of the present application, a non-transitory computer readable storage medium is provided, which stores instructions that, when executed by a processor, cause the processor to implement the simulation scheduling method as described in the foregoing embodiments.

[0028] In another embodiment of the present application, a computer program product is provided, comprising computer-executable instructions, which, when executed by a processor, implement the simulation scheduling method as described in the aforementioned embodiment.

[0029] Based on the embodiments of the present application, the multiple software modules run by the software simulation platform may include a platform interface, a host adapter simulation module, and an HBM simulation module that correspond to the bus interface, the host adapter, and the HBM of the integrated circuit chip in sequence. In this case, for multiple consecutive host write requests received by the platform interface, if the addresses of the corresponding multiple write data are continuous, the multiple write data with continuous addresses are aggregated by the host adapter simulation module into an on-chip write request and transferred to the HBM simulation module at one time. Thus, even if the host driver is limited by the fixed receiving bandwidth of the platform interface and splits the data to be written to the integrated circuit chip into multiple write data of smaller granularity and writes them to the software simulation platform, the host adapter simulation module can avoid an increase in the number of data transfers between multiple software modules of the software simulation platform by aggregating the multiple write data, thereby improving the software simulation efficiency of the integrated circuit chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following drawings are only provided for schematic illustration and explanation of the present application and do not limit the scope of the present application:

[0031] Figure 1 is a schematic diagram of an exemplary structure of an integrated circuit chip used as a simulation object in an embodiment of the present application;

[0032] Figure 2 This is an exemplary schematic diagram of a software simulation platform for simulating an integrated circuit chip in an embodiment of the present application;

[0033] Figure 3 Schematic diagram of the principle of write data aggregation of a software simulation platform for simulating integrated circuit chips in an embodiment of the present application;

[0034] Figure 4 Schematic diagram of an exemplary flow chart of a simulation scheduling method for a software simulation platform in an embodiment of the present application;

[0035] Figure 5 Schematic diagram of the optimization principle of write data aggregation of a software simulation platform for simulating integrated circuit chips in an embodiment of the present application;

[0036] Figure 6 Schematic diagram of an optimization process of a simulation scheduling method for a software simulation platform in an embodiment of the present application;

[0037] Figure 7 Schematic diagram of the extended principle of write data aggregation of a software simulation platform for simulating integrated circuit chips in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of this application more clear, the application is further described in detail below with reference to the accompanying drawings and examples.

[0039] For example, in an embodiment of the present application, the integrated circuit chip serving as the simulation object may be any processor chip such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Units).

[0040] Illustratively, in an embodiment of the present application, the host chip in the heterogeneous architecture where the integrated circuit chip is located may be a CPU.

[0041] Figure 1 This is an exemplary structural diagram of the integrated circuit chip used as the simulation object in the embodiments of this application. Figure 1 In an embodiment of the present application, the integrated circuit chip 20 may include a bus interface 21, a host adapter (HA) 22, a high bandwidth memory (HBM) 23, a command processor (CP) 26, and at least two core partitions 27.

[0042] For example, in an embodiment of the present application, the bus interface 21 of the integrated circuit chip 20 can be used for data exchange between the host chip 10 and the integrated circuit chip 20 via a physical bus. For example, the physical bus can be a bus with a physical transmission bandwidth greater than or equal to 512 bytes, such as PCIE (Peripheral Component Interconnect Express).

[0043] Exemplarily, in the embodiments of the present application, the bus interface 21 of the integrated circuit chip 20 can refer to the modular hardware of the integrated bus slot and the bus controller. For example, if the bus interface 21 of the integrated circuit chip 20 is connected to the host chip 10 through the PCIE bus, the PCIE bus slot and the PCIE bus controller can be integrated in the bus interface 21.

[0044] Exemplarily, in the embodiments of the present application, the data interaction between the host chip 10 and the integrated circuit chip 20 through the physical bus and the bus interface 21 can include read-write operations and control operations. For example, the host chip 10 can write the task data of a computing task to the integrated circuit chip 20, which can include the instruction data for indicating the task description of the computing task and the computing data as the processing object of the computing task. For another example, the host chip 10 can read the result data of the computing data of the computing task processed from the integrated circuit chip 20, and the host chip 10 can also read the state data of the integrated circuit chip 20 during the execution of the computing task and the intermediate data of the integrated circuit chip 20 during the execution of the computing task, etc. from the integrated circuit chip 20. For yet another example, the host chip 10 can send various control notifications to the integrated circuit chip 20 to trigger or control the timing or progress of the computing task of the integrated circuit chip 20.

[0045] Exemplarily, in the embodiments of the present application, the read-write of the integrated circuit chip 20 by the host chip 10 through the physical bus and the bus interface 21 can be executed by the host driver running in the host chip 10. For example, the host driver can generate the host write request for the host chip 10 to write data to the integrated circuit chip 20 and the host read request for the host chip 10 to read data from the integrated circuit chip 20, and the host write request and the host read request can be sent to the HA 22 of the integrated circuit chip 20 through the physical bus and the bus interface 21, and be converted by the HA 22 into the corresponding on-chip write request and on-chip read request to be transferred inside the integrated circuit chip 20.

[0046] Exemplarily, in the embodiments of the present application, the control operation of the integrated circuit chip 20 by the host chip 10 through the physical bus and the bus interface 21 can be implemented by the host notification such as the DoorBell notification generated by the host driver, and the host notification can also be sent to the HA 22 of the integrated circuit chip 20 through the physical bus and the bus interface 21, and be transferred inside the integrated circuit chip 20 from the HA 22.

[0047] For example, in the embodiments of the present application, the HBM 23 of the integrated circuit chip 20 can be viewed as the memory mapping space of the host chip 10 within the integrated circuit chip 20, or as a cache space for data exchanged between the integrated circuit chip 20 and the host chip 10. Therefore, write data (e.g., task data including instruction data and computational data) sent by the host chip 10 to the integrated circuit chip 20 can be written to the HBM 23. That is, the host driver of the host chip can generate the host write request described above to the HBM 23 of the integrated circuit chip 20. Similarly, read data (e.g., result data, status data, or intermediate data) that the host chip 10 intends to read from the integrated circuit chip 20 can come from the HBM 23. That is, the host driver of the host chip 10 can generate the host read request described above to the HBM 23 of the integrated circuit chip 20. Furthermore, regardless of whether the control object of a control notification generated by the host driver of the host chip 10 is the HBM 23, the control notification can be first cached in the HBM 23 and then transferred to the control object.

[0048] For example, in an embodiment of the present application, the instruction data in the write data (i.e., task data) sent by the host chip 10 to the integrated circuit chip 20 can be obtained by the CP 26 from the HBM 23. Furthermore, the CP 26 can assign computing tasks to at least two core partitions 27 based on the instruction data. For example, the CP 26 can assign multiple computing tasks to different core partitions 27, or split the same computing task into multiple subtasks and assign them to different core partitions 27.

[0049] For example, in an embodiment of the present application, the computing data in the write data (i.e., task data) sent by the host chip 10 to the integrated circuit chip 20 can be obtained from the HBM 23 by the core partition 27 based on the computing task assigned by the CP 26, that is, the core partition 27 can obtain the computing data corresponding to the assigned computing task from the HBM 23.

[0050] Exemplarily, in an embodiment of the present application, each kernel partition 27 may include multiple kernel clusters, for example, multiple stream processor clusters (SPCs) for performing computing operations such as reduce operations using kernel functions. The multiple kernel clusters in each kernel partition 27 may be used to process the corresponding computing data obtained from HBM 23 based on the computing tasks dispatched by CP 26, and the result data obtained by each kernel partition 27 from processing the computing data may be written into HBM 23.

[0051] Illustratively, in an embodiment of the present application, the read data obtained by the host chip 10 from the integrated circuit chip 20 may include result data written into the HBM 23 by the core partition 27 after completing a computing task.

[0052] For example, in an embodiment of the present application, the read data obtained by the host chip 10 from the integrated circuit chip 20 may include data used to represent the task allocation status of the CP 26 and the task completion status of the kernel partition 27.

[0053] For example, in an embodiment of the present application, when a computing task can be collaboratively completed by multiple core partitions 27, each core partition 27 can store the interim result data obtained from its own processing of the computing data in the HBM 23 as intermediate data, which can then be retrieved from the HBM 23 by other core partitions 27 for subsequent processing. In this case, the read data obtained by the host chip 10 from the integrated circuit chip 20 can include the interim result data generated by the core partitions 27.

[0054] For example, in an embodiment of the present application, the HA 22, the HBM 23, the CP 26, and at least two core partitions 27 may be interconnected via a NOC (Network On Chip) 25 in the integrated circuit chip 20. That is, the data transfer path between the HA 22, the HBM 23, the CP 26, and the core partitions 27 in the integrated circuit chip 20 may include the NOC 25.

[0055] Figure 2 This is an exemplary schematic diagram of a software simulation platform for simulating an integrated circuit chip in an embodiment of the present application. Figure 2 In the embodiment of the present application, the software simulation platform 30 is used to simulate the following by running multiple software modules: Figure 1 The integrated circuit chip 20 shown in the figure, and the multiple software modules run by the software simulation platform 30 may include: a platform interface 31 corresponding to the bus interface 21 of the integrated circuit chip 20, a host adapter simulation module (referred to as HA simulation module) 32 corresponding to the HA 22 of the integrated circuit chip 20, a high-bandwidth memory simulation module (referred to as HBM simulation module) 33 corresponding to the HBM 23 of the integrated circuit chip 20, a command processor simulation module (referred to as CP simulation module) 36 corresponding to the CP 26 of the integrated circuit chip 20, a kernel simulation module 37 corresponding to the kernel partition 27 of the integrated circuit chip 20, and a simulation module set 35 corresponding to each hardware part in the NOC 25 of the integrated circuit chip 20, and the interaction logic between the multiple software modules is the same as the hardware interaction topology of the corresponding hardware parts in the integrated circuit chip 20.

[0056] Exemplarily, in the embodiment of the present application, the host driver 100 can access the software emulation platform 30 as if interacting with the integrated circuit chip 20, i.e., the software emulation platform 30 can be perceived by the host driver 100 as the integrated circuit chip 20. Therefore, the platform interface 31 can be perceived by the host driver 100 as the bus interface 21 of the integrated circuit chip 20, the host write request generated by the host driver 100 is still targeted at the HBM 23 in the integrated circuit chip 20 as a write operation, and the HA emulation module 32 of the software emulation platform 30 can simulate the HA 22 in the integrated circuit chip 20 to convert the host write request received from the platform interface 31 into an on-chip write request, so as to transfer the on-chip write request carrying the write data to the HBM emulation module 33 corresponding to the HBM 23 through the emulation module set 35 according to the hardware interaction topology between the HA 22 and the HBM 23.

[0057] Exemplarily, in the embodiment of the present application, the solidified receiving bandwidth of the platform interface 31 of the software emulation platform 30 is less than the physical transmission bandwidth of the bus interface 21. For example, the software emulation platform 30 can select an open source platform such as QEMU (QuickEmulator) and the like, and the solidified receiving bandwidth of the platform interface 31 provided by the open source platform is usually 8 Bytes. In this case, if the physical bus connected by the bus interface 21 of the integrated circuit chip 20 selects a bus with a physical transmission bandwidth greater than or equal to 512 Bytes such as PCIE and the like, then the solidified receiving bandwidth of the platform interface 31 of the software emulation platform 30 is at most 1 / 64 of the physical transmission bandwidth of the bus interface 21.

[0058] Exemplarily, in the embodiment of the present application, for task data with a data amount exceeding 8 Bytes, the host driver 100 can only split the task data into multiple write data sent by multiple host write requests. In this case, if each write data is transferred in the software emulation platform 30 according to the generation of data transfer in the integrated circuit chip 20, then compared with the write data with the granularity of the physical transmission bandwidth, the number of data transfers between multiple software modules of the software emulation platform 30 is increased.

[0059] Exemplarily, in the embodiment of the present application, the software emulation platform 30 can run multiple software modules by using a software thread, and the multiple software modules can be called asynchronously by the software thread.

[0060] For example, in an embodiment of the present application, the software simulation platform 30 can run multiple software modules through a virtual machine, and the virtual machine can run multiple software modules in an asynchronous manner such as a serial call, for example, by periodically looping and calling multiple software modules using a software thread. Therefore, the transfer of write data in the software simulation platform 30 does not occur continuously through instant interaction like a hardware module, but may occur intermittently and delayed during the serial call process to multiple software modules. Therefore, each data transfer in the software simulation platform 30 will result in a longer time-consuming than in the integrated circuit chip 20, and further, the longer time-consuming will accumulate more as the number of data transfers in the software simulation platform 30 increases, resulting in low software simulation efficiency.

[0061] Still see Figure 2 In an embodiment of the present application, the software simulation platform 30 can allocate module memory space 320 for the HA simulation module 32, and the module memory space 320 can be used to cache at least one write data received by the HA simulation module 32 from the interface platform (that is, at least one write data corresponding to at least one host write request generated by the host driver 100). If the addresses of at least two write data corresponding to at least two host write requests from the host driver 100 to the HBM simulation module 33 are continuous, then it can be considered that these at least two write data are obtained by the host driver 100 from larger granularity (for example, physical transmission bandwidth as granularity or larger granularity) write data (for example, complete task data) split in order to adapt to the fixed receiving bandwidth of the platform interface 31. At this time, at least two write data with continuous addresses can be first cached in the module memory space 320 of the HA simulation module 32, and then aggregated into a granularity larger than the fixed receiving bandwidth and transferred to the HBM simulation module 33, thereby reducing the number of data transfers in the software simulation platform 30.

[0062] Figure 3 This is a schematic diagram of the principle of data aggregation for writing in a software simulation platform for simulating integrated circuit chips in an embodiment of the present application. Figure 3 In an embodiment of the present application, the HA simulation module 32 of the software simulation platform 30 may process a host write request to the HBM received from the platform interface 31 in the following manner:

[0063] In response to each host write request to the HBM received from the platform interface 31 (i.e., a host write request generated by the host driver 100 to the HBM 23), an address continuity check is performed on the write data of the current host write request. The address continuity check is used to determine whether there is currently stored write data in the module memory space 320 that is address-contiguous with the current write data, that is, to determine whether there is currently in the module memory space 320 write data corresponding to a previous host write request before the current host write request, and whether the current write data and the previous write data have address-contiguous relationships.

[0064] If the result of the address continuity check is yes, that is, the result of the address continuity check indicates that there is currently stored write data in the module memory space 320 that is continuous with the address of the current write data, then it can be considered that the current write data and the currently stored write data in the module memory space 320 (that is, the write data corresponding to the previous host write request before the current host write request, or the write data corresponding to the previous host write request and an earlier host write request) are associated write data. Therefore, the current write data is stored in the module memory space 320 in an appended manner, so as to be stored together with the stored write data in the module memory space 320 and serve as a reference for address continuity check for the next host write request;

[0065] If the address continuity check result indicates that the module memory space is empty, that is, the address continuity check result indicates that there is no write data currently stored in the module memory space 320, then the write data is still stored in the module memory space 320 in an appended manner to serve as a reference for address continuity check in the next host write request;

[0066] If the result of the address continuity check is negative and the module memory space is not empty, that is, the result of the address continuity check indicates that write data corresponding to the previous host write request before the current host write request currently exists in the module memory space 320, but the address of the current write data is not continuous with that write data, then it can be considered that the current write data is not associated with the write data currently stored in the module memory space 320. Therefore, the current write data is stored in the module memory space 320 in an eviction manner. The eviction manner is used to aggregate the write data stored in the module memory space 320 before the current write data is stored (that is, the write data corresponding to the previous host write request before the current host write request, or even the write data corresponding to the historical host write request earlier than the previous host write request) so that all the write data stored in the module memory space 320 before the current write data is stored is aggregated into one on-chip write request and transferred to the HBM emulation module 33. Then, the current write data is stored in the module memory space 320 that has been cleared due to the aggregation out of the storage.

[0067] In response to the completion of the storage of the current write data in the module memory space 320, a host write response for the current host write request is generated to the platform interface 31, so that when the host write response is fed back to the host driver 100 through the platform interface 31, the host driver 100 is prompted to continuously generate the next host write request. That is, the continuity of the host write request generated by the host driver 100 will not be affected by the way in which each write data is stored in the module memory space 320. For example, the host driver 100 will not suspend the generation of the next host write request due to any write data being temporarily stored in the module memory space 320 for transmission.

[0068] For example, in an embodiment of the present application, an on-chip write request may carry write data cached in the module memory space 320 that is discontinuous with the previous and next write data, or may carry aggregated data of at least two write data with continuous addresses.

[0069] Figure 4 This is an exemplary flow chart of the simulation scheduling method for the software simulation platform in the embodiment of the present application. Figure 4 In the embodiments of the present application, based on Figure 3 Based on the principle shown, the simulation scheduling method for the software simulation platform may include the following steps performed by the HA simulation module:

[0070] S410: In response to each host write request to the HBM received from the platform interface, perform an address continuity check on the write data of the host write request; wherein the address continuity check is used to determine whether there is currently stored write data in the module memory space of the HA simulation module with an address that is continuous with the address of the write data of the current write;

[0071] S430: Based on the detection result of the address continuity detection of the current write data, the current write data is stored in the module memory space; wherein, if the detection result is yes or the module memory space is empty, the current write data is stored in the module memory space in an appending manner; if the detection result is no and the module memory space is not empty, the current write data is stored in the module memory space in an eviction manner, wherein the eviction manner is used to aggregate all the write data stored in the module memory space before the current write data is stored in one on-chip write request and transfer it to the HBM simulation module;

[0072] S450: In response to the completion of storing the current write data in the module memory space, a host write response for the current host write request is generated to the platform interface.

[0073] like Figure 4 The above-mentioned process shown may be a process executed in a loop.

[0074] Based on the above-mentioned simulation scheduling method of the embodiment of the present application, for the host write requests generated by the host driver to the HBM multiple times continuously received by the platform interface, if the addresses of the corresponding multiple write data are continuous, the multiple write data with continuous addresses can be aggregated by the HA simulation module of the software simulation platform into an on-chip write request and transferred to the HBM simulation module at one time. Thus, even if the host driver is limited by the fixed receiving bandwidth of the platform interface and splits the data to be written into the integrated circuit chip into multiple write data of smaller granularity and writes them into the software simulation platform, the HA simulation module can avoid an increase in the number of data transfers between multiple software modules of the software simulation platform by aggregating the multiple write data, thereby improving the software simulation efficiency of the integrated circuit chip. According to actual measurements, the use of the above-mentioned simulation scheduling method can increase the software simulation efficiency by at least 4 times.

[0075] For example, in an embodiment of the present application, although the software simulation platform 30 only has a fixed receiving bandwidth limitation on the platform interface 31, and there is no data transfer amount limitation within the platform, the amount of write data transferred in a single time within the integrated circuit chip 20 is not infinite. Therefore, in order to make the simulation process of the software simulation platform 30 closer to the actual working process of the integrated circuit chip 20, the aggregate data amount of write data carried by the same on-chip write request can be set with appropriate restrictions. For example, the aggregate data amount of write data carried by the same on-chip write request can be limited by the physical transmission bandwidth of the bus interface 21 of the integrated circuit chip 20.

[0076] Figure 5 This is a schematic diagram of the optimization principle of write data aggregation for the software simulation platform used to simulate integrated circuit chips in the embodiment of this application. Figure 5 In an embodiment of the present application, the HA simulation module 32 of the software simulation platform 30 may also be used to:

[0077] In response to the completion of storing the write data in the module memory space 320, a write data storage amount detection is performed on the module memory space 320, where the write data storage amount detection is used to determine the data storage amount of the currently stored write data in the module memory space 320;

[0078] If the data storage amount of the currently stored write data in the module memory space 320 is greater than or equal to the preset data storage threshold, that is, the data storage amount of the currently stored write data in the module memory space 320 is sufficient, then the currently stored write data in the module memory space 320 (that is, the current write data and the write data corresponding to at least one host write request before the current host write request) is aggregated out of the warehouse, so that all the stored write data including the current write data in the module memory space 320 are aggregated in one on-chip write request and transferred to the HBM simulation module 33, and the module memory space 320 is cleared due to the aggregation out of the warehouse.

[0079] Figure 6 This is a schematic diagram of the optimization process of the simulation scheduling method for the software simulation platform in the embodiment of this application. Figure 6 In an embodiment of the present application, the simulation scheduling method may further include the following steps performed by the HA simulation module after S430:

[0080] S470, in response to the completion of storage of the current write data in the module memory space, detect the data storage amount of the currently stored write data in the module memory space; wherein, if the data storage amount of the currently stored write data in the module memory space is greater than or equal to the preset data storage threshold, then all the currently stored write data in the module memory space are aggregated into one on-chip write request and transferred to the HBM simulation module.

[0081] For example, in an embodiment of the present application, the write data inventory detection of the module memory space can be triggered only in response to the completion of the storage of the current write data in the module memory space in an appending manner, and the write data inventory detection of the module memory space may not be triggered after the storage of the current write data in the module memory space in an expelling manner is completed.

[0082] For example, in an embodiment of the present application, the data storage threshold may be set to be equal to the physical transmission bandwidth of the bus interface 21 of the integrated circuit chip 20 serving as the simulation object.

[0083] Figure 7 This is a schematic diagram of the extended principle of write data aggregation for the software simulation platform for simulating integrated circuit chips in the embodiment of this application. Figure 7 In an embodiment of the present application, the HA simulation module 32 of the software simulation platform 30 may also be used to:

[0084] In response to each host read request to the HBM received from the platform interface 31 (i.e., a host read request generated by the host driver 100 to the HBM), the module memory space 320 is detected for stored write data that is hit by the current host read request. For example, by matching the read address of the host read request with the write address of the stored write data in the module memory space 320, it is determined whether there is stored write data that is hit by the current host read request.

[0085] If there is currently stored write data in the module memory space 320 that is hit by the current host read request, for example, there is currently stored write data in the module memory space 320 whose write address matches the read address of the current read request, then the current stored write data in the module memory space 320 (including the write data hit by the current host read request and other write data stored together due to continuous addresses) is aggregated out of the warehouse, so that all the current stored write data in the module memory space 320 are aggregated in one on-chip write request and transferred to the HBM simulation module 33, and the module memory space 320 is cleared due to the aggregation out of the warehouse.

[0086] For example, in an embodiment of the present application, all stored write data in the module memory space 320 is aggregated out of the storage due to at least a portion of being hit by a host read request. This is because the host read request targets the HBM, and therefore the hit data must be read from the HBM emulation module 33 that emulates the HBM. Accordingly, the read response to the host read request should also be generated by the HBM emulation module 33 emulating the HBM. That is, the HA emulation module 32 of the software emulation platform 30 can also be used to:

[0087] In response to each host read request to the HBM received from the platform interface 31, a corresponding on-chip read request is transmitted to the HBM simulation module 33 to trigger the HBM simulation module 33 to generate an on-chip read response including the read hit data of this host read request; wherein, the on-chip read response is used to trigger the HA simulation module 32 to generate a host read response including the read hit data to the platform interface 31.

[0088] See also Figure 7 In an embodiment of the present application, the HA simulation module 32 of the software simulation platform 30 may also be used to:

[0089] In response to a doorbell notification received from the platform interface 31 , detecting whether there is currently stored write data in the module memory space 320 ;

[0090] If there is currently stored write data in the module memory space 320, then the currently stored write data in the module memory space 320 is aggregated out of the warehouse, so that all the currently stored write data in the module memory space 320 are aggregated in one write request and transmitted to the HBM simulation module 33, and the module memory space 320 is cleared due to the aggregation out of the warehouse.

[0091] For example, in the embodiment of the present application, the doorbell notification can be generated by the host driver 100 to the CP to instruct the CP to start task allocation. However, as mentioned above, the HBM is a cache space for interactive data between the integrated circuit chip and the host chip. Therefore, the doorbell notification generated to the CP can also be sent to the HBM first, just like writing data, and then the CP can retrieve it from the HBM. Accordingly, in the embodiment of the present application, the HA simulation module 32 of the software simulation platform 30 can also be used to:

[0092] The doorbell notification is passed to the HBM simulation module 33 so that the CP simulation module can obtain the doorbell notification from the HBM simulation module 33; wherein, the notification response to the doorbell notification is generated by the CP simulation module, and the notification response generated by the CP simulation module can be stored in the HBM simulation module 33, and then passed from the HBM simulation module 33 to the HA simulation module 32, and finally fed back to the host driver 100 by the HA simulation module 32 through the platform interface 31.

[0093] Illustratively, in an embodiment of the present application, the simulation scheduling method for a software simulation platform may further include the above-mentioned processing steps for host read requests and doorbell notifications.

[0094] In another embodiment of the present application, a simulation scheduling device for a software simulation platform is further provided. The simulation scheduling device may include the following units running in the HA simulation module of the software simulation platform:

[0095] The continuity detection unit is configured to, in response to each host write request to the HBM received from the platform interface (i.e., a host write request generated by the host driver to the HBM), perform an address continuity check on the write data of the current host write request; wherein the address continuity check is used to determine whether there is currently stored write data in the module memory space of the HA simulation module that is address-contiguous with the current write data, that is, to determine whether there is currently in the module memory space write data corresponding to the previous host write request before the current host write request, and whether the current write data and the previous write data are address-contiguous;

[0096] The write data aggregation unit is configured to store the current write data into the module memory space based on the detection result of the address continuity detection of the current write data; wherein, if the detection result of the address continuity detection is yes, that is, there is currently stored write data in the module memory space that is continuous with the address of the current write data, then it can be considered that the current write data and the current stored write data in the module memory space (that is, the write data corresponding to the previous host write request before the current host write request, or the write data corresponding to the previous host write request and the earlier host write request) are associated write data, and therefore, the current write data is stored in the module memory space in an additive manner, so as to be stored together with the stored write data in the module memory space and serve as a reference for address continuity detection for the next host write request; if the detection result of the address continuity detection indicates that the module memory space is empty, that is, there is currently no stored write data in the module memory space, then the current write data is still stored in the module memory space in an additive manner, This is used as a reference for address continuity detection for the next host write request; if the detection result of the address continuity detection is negative, and the module memory space is not empty, that is, the module memory space currently contains write data corresponding to the previous host write request before the current host write request, but the address of the current write data is not continuous with that of the write data, then it can be considered that the current write data is not associated with the currently stored write data in the module memory space. Therefore, the current write data is stored in the module memory space in an eviction manner. The eviction manner is used to aggregate the write data stored in the module memory space before the current write data is stored (that is, the previous host write request before the current host write request, or even the write data corresponding to the historical host write request earlier than the previous host write request) so that all the stored write data in the module memory space before the current write data is stored are aggregated in one on-chip write request and transferred to the HBM simulation module. Then, the current write data is stored in the module memory space that has been cleared due to the aggregation out of the warehouse;

[0097] The write response generation unit is configured to generate a host write response for the current host write request to the platform interface in response to the completion of the storage of the current write data in the module memory space, so as to prompt the host driver to continuously generate the next host write request when the host write response is fed back to the host driver through the platform interface. That is, the continuity of the host write request generated by the host driver will not be affected by the way in which each write data is stored in the module memory space 320. For example, the host driver will not suspend the generation of the next host write request due to the temporary storage of any write data in the module memory space.

[0098] Based on the above-mentioned simulation scheduling device of the embodiment of the present application, for host write requests generated by the host driver to the HBM multiple times continuously and received by the platform interface, if the addresses of the corresponding multiple write data are continuous, the multiple write data with continuous addresses can be aggregated into a single on-chip write request by the HA simulation module of the software simulation platform and transferred to the HBM simulation module at one time. Therefore, even if the host driver is limited by the fixed receiving bandwidth of the platform interface and splits the data to be written to the integrated circuit chip into multiple write data of smaller granularity and writes them to the software simulation platform, the HA simulation module can avoid an increase in the number of data transfers between multiple software modules of the software simulation platform by aggregating the multiple write data, thereby improving the software simulation efficiency of the integrated circuit chip.

[0099] Exemplarily, in an embodiment of the present application, the write data aggregation unit may be further configured as follows:

[0100] In response to the completion of storing the write data in the module memory space, performing a write data storage detection on the module memory space, wherein the write data storage detection is used to determine the data storage of the currently stored write data in the module memory space;

[0101] If the data storage amount of the currently stored write data in the module memory space is greater than or equal to the preset data storage threshold, that is, the data storage amount of the currently stored write data in the module memory space is sufficient, then the currently stored write data in the module memory space (that is, the current write data and the write data corresponding to at least one host write request before the current host write request) is aggregated out of the warehouse, so that all the stored write data in the module memory space including the current write data are aggregated in one on-chip write request and transferred to the HBM simulation module, and the module memory space is cleared due to the aggregation out of the warehouse.

[0102] For example, in an embodiment of the present application, the write data inventory detection of the module memory space can be triggered only in response to the completion of the storage of the current write data in the module memory space in an appending manner, and the write data inventory detection of the module memory space may not be triggered after the storage of the current write data in the module memory space in an expelling manner is completed.

[0103] For example, in an embodiment of the present application, the data storage threshold may be set to be equal to the physical transmission bandwidth of the bus interface of the integrated circuit chip serving as the simulation object.

[0104] Exemplarily, in an embodiment of the present application, the simulation scheduling apparatus for a software simulation platform may further include a read hit detection unit running in the HA simulation module, configured to:

[0105] In response to each host read request to the HBM received from the platform interface (i.e., a host read request generated by the host driver to the HBM), detecting stored write data hit by the current host read request in the module memory space, for example, by matching a read address of the host read request with a write address of the stored write data in the module memory space, to determine whether there is stored write data hit by the current host read request;

[0106] If there is currently stored write data in the module memory space that is hit by this host read request, for example, there is currently stored write data in the module memory space whose write address matches the read address of this read request, then the current stored write data in the module memory space (including the write data hit by this host read request and other write data stored together due to continuous addresses) is aggregated out of the warehouse, so that all the current stored write data in the module memory space are aggregated in one on-chip write request and transferred to the HBM simulation module, and the module memory space is cleared due to the aggregation out of the warehouse.

[0107] Exemplarily, in an embodiment of the present application, the simulation scheduling device for the software simulation platform may further include a read request pushing unit running in the HA simulation module, configured to:

[0108] In response to each host read request to the HBM received from the platform interface, a corresponding on-chip read request is transmitted to the HBM emulation module to trigger the HBM emulation module to generate an on-chip read response including the read hit data of this host read request; wherein the on-chip read response is used to trigger the HA emulation module to generate a host read response including the read hit data to the platform interface.

[0109] Exemplarily, in an embodiment of the present application, the write data aggregation unit may be further configured as follows:

[0110] In response to a doorbell notification received from the platform interface, detecting whether there is currently stored write data in the module memory space;

[0111] If there is currently stored write data in the module memory space, the currently stored write data in the module memory space is aggregated out of the warehouse, so that all the currently stored write data in the module memory space are aggregated in one write request and transmitted to the HBM simulation module, and the module memory space is cleared due to the aggregation out of the warehouse.

[0112] Exemplarily, in an embodiment of the present application, the simulation scheduling device for the software simulation platform may further include a notification push unit running in the HA simulation module, which is configured to pass the doorbell notification to the HBM simulation module so that the CP simulation module can obtain the doorbell notification from the HBM simulation module; wherein, the notification response to the doorbell notification is generated by the CP simulation module, and the notification response generated by the CP simulation module can be stored in the HBM simulation module, and then passed from the HBM simulation module to the HA simulation module, and finally fed back to the host driver by the HA simulation module through the platform interface.

[0113] Another embodiment of the present application further provides an electronic device, such as a server, which may include a processor (such as a CPU) that can be used to execute the simulation scheduling method in the aforementioned embodiment.

[0114] Another embodiment of the present application further provides a non-transitory computer-readable storage medium, which stores instructions. When these instructions are executed by a processor (eg, a CPU), the processor can implement the simulation scheduling method in the aforementioned embodiment.

[0115] Another embodiment of the present application further provides a computer program product, including computer-executable instructions, which, when executed by a processor (eg, a CPU), implement the simulation scheduling method in the aforementioned embodiment.

[0116] It can be understood that, in the embodiments of the present application, the various parts of the content exemplified can be in an "and / or" relationship. In this article, the meaning of "and / or" refers to the context in which it is connected, which can be a common limiting relationship of "and", or can also be an alternative limiting relationship of "or". Therefore, the various parts of the content with an "and / or" relationship can be understood as including different combinations of situations in which "and / or" between each two parts of the content respectively represents a common limiting relationship of "and" or an alternative limiting relationship of "or", and this combination of different situations can be considered to be basically equivalent to the limiting scope of "at least one of the parts".

[0117] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A simulation scheduling method for a software simulation platform, characterized in that: The software simulation platform is used to simulate an integrated circuit chip by running multiple software modules, wherein the multiple software modules include a platform interface, a host adapter simulation module, and an HBM simulation module corresponding to the bus interface, host adapter, and HBM of the integrated circuit chip in sequence. The software simulation platform allocates module memory space to the host adapter simulation module, and the simulation scheduling method includes the following steps performed by the host adapter simulation module: In response to each host write request to the HBM received from the platform interface, performing an address continuity check on the write data of the host write request; wherein the address continuity check is used to determine whether there is currently stored write data in the module memory space that is continuous with the address of the current write data; Based on the detection result of the address continuity detection, the current write data is stored in the module memory space; wherein, if the detection result is yes or the module memory space is empty, the current write data is stored in the module memory space in an appending manner; if the detection result is no and the module memory space is not empty, the current write data is stored in the module memory space in an eviction manner, wherein the eviction manner is used to aggregate all the write data stored in the module memory space before the current write data is stored in one on-chip write request and transfer it to the HBM simulation module; In response to the completion of storing the current write data in the module memory space, generating a host write response for the current host write request to the platform interface; The simulation scheduling method further includes the following steps performed by the host adapter simulation module: In response to each host read request to the HBM received from the platform interface, the stored write data hit by the current host read request is detected in the module memory space; wherein, if there is currently stored write data hit by the current host read request in the module memory space, then all the currently stored write data in the module memory space are aggregated into an on-chip write request and transferred to the HBM simulation module.

2. The simulation scheduling method according to claim 1, characterized in that: The simulation scheduling method further includes the following steps performed by the host adapter simulation module: In response to the completion of storing the current write data in the module memory space, detecting the amount of data currently stored in the module memory space; If the data stock of the currently stored write data in the module memory space is greater than or equal to the preset data stock threshold, then all the currently stored write data in the module memory space are aggregated into one on-chip write request and transferred to the HBM simulation module.

3. The simulation scheduling method according to claim 2, characterized in that: The fixed receiving bandwidth of the platform interface is smaller than the physical transmission bandwidth of the bus interface, the single data volume of the write data of each write request is limited to be smaller than or equal to the fixed receiving bandwidth, and the data storage threshold is set to be equal to the physical transmission bandwidth.

4. The simulation scheduling method according to claim 1, characterized in that: The simulation scheduling method further includes the following steps performed by the host adapter simulation module: In response to each host read request for the HBM received from the platform interface, a corresponding on-chip read request is transmitted to the HBM emulation module to trigger the HBM emulation module to generate an on-chip read response including read hit data of this host read request; wherein the on-chip read response is used to trigger the host adapter emulation module to generate a host read response including read hit data to the platform interface.

5. The simulation scheduling method according to claim 1, characterized in that: The simulation scheduling method further includes the following steps performed by the host adapter simulation module: In response to a doorbell notification received from the platform interface, detecting whether there is currently stored write data in the module memory space; If there is currently stored write data in the module memory space, all the currently stored write data in the module memory space are aggregated into one write request and transmitted to the HBM simulation module.

6. The simulation scheduling method according to claim 5, characterized in that: The integrated circuit chip further includes a command processor, the doorbell notification is used to remind the command processor to start a task, and the plurality of software modules further include a command processor simulation module corresponding to the command processor; The simulation scheduling method further includes the following steps performed by the host adapter simulation module: The doorbell notification is transmitted to the HBM emulation module, so that the command processor emulation module obtains the doorbell notification from the HBM emulation module; wherein a notification response to the doorbell notification is generated by the command processor emulation module.

7. A simulation scheduling device for a software simulation platform, characterized in that: The software simulation platform is used to simulate an integrated circuit chip by running multiple software modules, wherein the multiple software modules include a platform interface, a host adapter simulation module, and an HBM simulation module corresponding to the bus interface, host adapter, and HBM of the integrated circuit chip in sequence. The software simulation platform allocates module memory space to the host adapter simulation module, and the simulation scheduling device includes the following units running in the host adapter simulation module: a continuity detection unit configured to, in response to each host write request to the HBM received from the platform interface, perform an address continuity check on the write data of the host write request; wherein the address continuity check is used to determine whether there is currently stored write data in the module memory space that is continuous with the address of the current write data; A write data aggregation unit is configured to store the current write data into the module memory space based on a detection result of the address continuity detection; wherein, if the detection result is yes or the module memory space is empty, the current write data is stored in the module memory space in an appending manner; if the detection result is no and the module memory space is not empty, the current write data is stored in the module memory space in an eviction manner, wherein the eviction manner is used to aggregate all the write data stored in the module memory space before the current write data is stored into one on-chip write request and transfer it to the HBM simulation module; a write response generating unit configured to generate a host write response for the current host write request to the platform interface in response to completion of storing the current write data in the module memory space; The simulation scheduling apparatus further includes a read hit detection unit running in the host adapter simulation module, wherein the read hit detection unit is configured to, in response to each host read request to the HBM received from the platform interface, detect stored write data in the module memory space that is hit by the host read request; The write data aggregation unit is further configured to: if there is currently stored write data in the module memory space that is hit by the current host read request, then all the currently stored write data in the module memory space are aggregated into one on-chip write request and transferred to the HBM simulation module.

8. An electronic device, characterized in that: The method comprises a processor configured to execute the simulation scheduling method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores instructions, which, when executed by a processor, enable the processor to implement the simulation scheduling method according to any one of claims 1 to 6.

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