Digital integrated circuit optimization method and system

Abstract

The invention relates to the technical field of integrated circuit optimization, in particular to a digital integrated circuit optimization method and system. The method comprises the following steps: acquiring process parameter data, and constructing a parameter space response curve of the process parameter data; generating a process precision dense grid based on the parameter space response curve; extracting a layout topological structure of the process precision dense grid; performing time sequence frequency spectrum conversion on the process parameter data to obtain circuit time sequence frequency spectrum data; constructing a circuit three-dimensional tensor by using the process parameter data, the circuit time sequence frequency spectrum data and the layout topological structure, and detecting a path tensor track to obtain circuit track data; therefore, by introducing high-precision data modeling and dynamic constraint in each link, the limitation of a traditional circuit optimization method is broken through, the precision, stability and performance of integrated circuit design are greatly improved, and a finer and more efficient circuit optimization process is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit optimization, and in particular to a digital integrated circuit optimization method and system. Background Art

[0002] During process parameter optimization, existing methods typically use linear interpolation or statistical fitting to construct the parameter space. However, these methods fail to fully consider the nonlinear coupling relationships between parameters, resulting in local optimal solutions and an inability to effectively obtain a global optimal solution. Furthermore, the high-dimensional nature of process parameter data makes it difficult for traditional optimization methods to effectively reduce the dimensionality, significantly increasing computational complexity and impacting optimization efficiency. Secondly, during circuit timing analysis, existing techniques primarily rely on static timing analysis (STA) or Monte Carlo simulation methods. However, these methods are unable to accurately characterize the dynamic behavior of circuits under varying process fluctuations. Especially at the nanoscale, the thermal-mechanical-electrical coupling effects of circuits lead to highly nonlinear timing variations, making it difficult for existing methods to accurately predict the true performance of circuits under complex environments. Furthermore, current digital integrated circuit optimization methods often ignore the interactions between cross-domain physical fields, such as the interactions between thermal, stress, and electric fields, and instead optimize only a single physical field. This results in incomplete optimization results, which in turn affects the long-term reliability of the circuits. Furthermore, existing methods for anomaly detection primarily rely on rule-based or traditional pattern matching approaches, which struggle to adapt to the complexity of circuit structures in modern processes. In particular, their ability to detect cross-level and cross-domain interference is limited, making it difficult to promptly identify and optimize potential design flaws. Existing methods fail to fully exploit the correlations of high-dimensional data during circuit optimization, resulting in relatively one-sided optimization strategies and an inability to form a complete parameter causal chain. This results in a lack of global constraints on the optimization results, which in turn affects the convergence and adaptability of the optimization. Summary of the Invention

[0003] Based on this, it is necessary to provide a digital integrated circuit optimization method and system to solve at least one of the above technical problems.

[0004] To achieve the above object, a digital integrated circuit optimization method is provided, the method comprising the following steps:

[0005] Step S1: Acquire process parameter data and construct a parameter space response curve of the process parameter data; generate a process precision dense grid based on the parameter space response curve;

[0006] Step S2: extracting the layout topology of the process precision dense grid; performing time series spectrum conversion on the process parameter data to obtain circuit time series spectrum data; constructing a circuit three-dimensional tensor using the process parameter data, circuit time series spectrum data, and layout topology, and detecting the path tensor trajectory to obtain circuit trajectory data;

[0007] Step S3: extracting circuit trajectory multi-physics field data based on the circuit trajectory data; performing thermal-mechanical-electrical joint constraints on the circuit trajectory multi-physics field data to obtain circuit optimized trajectory data;

[0008] Step S4: Perform digital circuit tunneling detection on the circuit optimization trajectory data to obtain digital circuit cross-domain violation data; perform abnormal hotspot detection on the digital circuit cross-domain violation data, and generate a digital integrated circuit optimization report.

[0009] The beneficial effect of the present invention is that, by acquiring process parameter data and constructing a parameter space response curve, a comprehensive response to changes in different process parameters is ensured, and a dense grid of process precision is further generated based on this response curve to carefully capture tiny process changes, thereby providing high-precision data support for circuit design. By combining process parameter data with circuit timing spectrum data and layout topology, and constructing a three-dimensional circuit tensor on this basis, it is possible to achieve an organic fusion of information on each dimension of the circuit, forming a comprehensive multi-dimensional data model, which is convenient for subsequent in-depth analysis of circuit trajectory data. In this process, path tensor manifold analysis effectively compresses high-dimensional data into low-dimensional space, maintains the integrity of key information, and reveals the potential physical laws and performance bottlenecks in circuit design through manifold analysis. Then, through the extraction of multi-physics field data and the application of thermal-mechanical-electrical joint constraints, the multiple physical effects of the circuit are comprehensively optimized, further improving the reliability and stability of the circuit. Finally, by detecting tunneling and cross-domain violations in the circuit optimization trajectory data, we ensure that the circuit design meets process requirements while avoiding performance issues caused by physical parameter mismatches or design defects. At the same time, the abnormal hotspot detection function enables timely error diagnosis and feedback, providing accurate decision-making support for efficient circuit optimization and production. Therefore, by introducing high-precision data modeling and dynamic constraints at each stage, this invention breaks through the limitations of traditional circuit optimization methods, greatly improving the accuracy, stability, and performance of integrated circuit design, and ensuring a more refined and efficient circuit optimization process.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Setting the measurement range of the high-precision source meter to 0.1V-1.5V, with a minimum change of 0.05V;

[0012] Step S12: setting the measurement range of the electron microscope to 130nm-180nm and the EUV process range to 5nm-50nm;

[0013] Step S13: Acquire historical simulation data; use a high-precision source meter and an electron microscope to collect process parameter data from the historical simulation data;

[0014] Step S14: obtaining a sequential power consumption table; extracting sequential power consumption data from the sequential power consumption table;

[0015] Step S15: constructing a parameter space response curve based on the timing power consumption data and the process parameter data, and generating a process precision dense grid of the parameter space response curve, wherein the process precision dense grid is 0.1σ.

[0016] Through precise measurement and data acquisition, the present invention significantly improves the accuracy and controllability of process parameters, thereby optimizing the design and manufacturing process of integrated circuits. From a data-level analysis perspective, the measurement range of the high-precision source meter and electron microscope is precisely set to ensure accurate capture of process parameters. Through this precise control, not only can subtle changes in various parameters in the circuit be accurately obtained, but the stability and reliability of the measurement results can also be ensured, providing a solid foundation for subsequent data analysis. By acquiring historical simulation data and combining it with data acquisition from the high-precision source meter and electron microscope, in-depth mining of process parameter data is achieved. This process enables a strong comparison between the process data collected in actual testing and the historical simulation data, further verifying the adaptability of the simulation model to the actual process. By extracting timing power consumption data, the power consumption performance of the circuit in the working state is deeply analyzed. This data helps to reveal the response characteristics of the circuit performance under different operating conditions and provides a specific data basis for subsequent optimization. By combining timing power consumption data and process parameter data to construct a parameter space response curve, the influence of process parameters on circuit performance can be effectively revealed. By generating a dense process precision grid, we can more precisely capture subtle changes in process parameters, ensuring that every detail in the process optimization process can be effectively controlled. This dense grid is generated with a 0.1σ standard, making the control of process parameters more refined, thereby greatly improving the accuracy and stability of circuit design and reducing the risk of circuit failure due to parameter fluctuations.

[0017] Preferably, the process precision dense grid construction in step S1 includes:

[0018] The collected process parameter data is used as the input axis;

[0019] The time series power consumption data is used as the output axis;

[0020] Forming a parameter space response curve based on the collected process parameter data and timing power consumption data;

[0021] Analyze the sudden change region of the parameter space response curve where the curvature change is greater than 0.15 / nm and obtain the circuit second-order derivative matrix;

[0022] A process precision dense grid is created based on the fact that the spacing between adjacent sampling points of the circuit second-order derivative matrix is ​​less than 3 nm, where the process precision dense grid is 0.1σ.

[0023] The present invention forms a clear input-output relationship by constructing the collected process parameter data as the input axis and the time-series power consumption data as the output axis. This process effectively connects data of different dimensions and constructs a parameter space response curve, thereby revealing how process parameters affect the power consumption characteristics of the circuit. By analyzing the curvature changes in the parameter space response curve, especially identifying the mutation area with a curvature greater than 0.15 / nm, it is possible to effectively capture the sensitive response of small changes in process parameters to circuit performance. This process further analyzes the mechanism of the impact of process parameter changes on circuit performance by generating the circuit second-order derivative matrix, providing a theoretical basis for circuit optimization. The introduction of the second-order derivative matrix can reveal higher-order nonlinear changes, thereby helping designers identify key factors in the process. Subsequently, by setting the spacing between adjacent sampling points based on the circuit second-order derivative matrix to less than 3nm, a fine process precision dense grid is created. The grid refinement is set to 0.1σ, which not only improves the fine-grained control capability of process parameters, but also ensures that every detail in the design process can be accurately optimized. The beneficial effect of this method is that by precisely controlling the relationship between process parameters and timing power consumption, potential problems can be identified in advance during the circuit design stage, avoiding performance fluctuations or failures caused by process fluctuations. It also provides a scientific basis for efficient and low-power operation of the circuit.

[0024] Preferably, obtaining the circuit trace data in step S2 includes:

[0025] Constructing a circuit three-dimensional tensor from process parameter data, circuit timing spectrum data and process parameter data;

[0026] Perform manifold isometric projection according to the circuit three-dimensional tensor to form a circuit manifold projection;

[0027] Perform 8-layer deep autoencoder feature compression based on circuit manifold projection to obtain circuit feature compression data;

[0028] Path tensor manifold analysis is performed on the circuit feature compressed data to obtain circuit trajectory data.

[0029] The process parameter data, circuit timing spectrum data and process parameter data of the present invention are constructed into a three-dimensional circuit tensor, which provides a comprehensive perspective for data integration. Based on the three-dimensional tensor, high-dimensional data can be effectively mapped to a low-dimensional space through manifold isometric projection. This process helps to maintain the geometric structure characteristics of the original data while reducing the dimension of the data and reducing redundant information. Then, an 8-layer deep autoencoder is applied for feature compression, so that the complex features of the circuit can be efficiently extracted and represented, thereby reducing the amount of calculation and memory overhead, while retaining the key information that is crucial in circuit design. The deep autoencoder learns the implicit rules of the data through nonlinear mapping, so that the compressed circuit feature data can still have good representation capabilities in a lower dimension. Finally, the circuit feature compression data is processed by path tensor manifold analysis to obtain the trajectory data of the circuit. This step can reveal the change trend and evolution trajectory of the circuit in the parameter space, providing data support for further optimization and improvement. In summary, the beneficial effect of this process is to improve the accuracy and efficiency of circuit design through efficient data dimensionality reduction, feature compression and manifold analysis. It can extract valuable information from a larger data space and provide a concise way to analyze and predict the performance of circuits in complex environments, providing a scientific basis for subsequent circuit optimization and performance improvement.

[0030] Preferably, the constructing of the circuit three-dimensional tensor includes:

[0031] The process parameter data is converted into 128 feature vectors;

[0032] The first dimension is constructed based on the process parameter data, where the sample size is set to 10k;

[0033] The second dimension is constructed based on the process parameter data, where the feature is set to 512;

[0034] Construct the third dimension based on the layout topology, where the dimension is set to 3;

[0035] The first-dimensional circuit tensor, the second-dimensional circuit tensor, and the third-dimensional circuit tensor are aligned according to the [N samples × M features × K dimensions] structure to obtain the three-dimensional circuit tensor.

[0036] This invention transforms high-dimensional raw data into low-dimensional data that can be effectively processed and analyzed by constructing 128 feature vectors from process parameter data. This not only reduces information redundancy but also enhances the efficiency of subsequent data analysis and feature extraction. Furthermore, the first dimension is constructed with N = 10k, ensuring a sufficient number of samples to capture the diversity of process parameters, thereby improving the robustness and generalization of the model. The second dimension is constructed from circuit timing spectrum data with M = 512 dimensions, taking into account the circuit's performance characteristics in both the time and frequency domains, fully reflecting the circuit's behavior in dynamic environments and providing a strong basis for timing analysis. The third dimension is constructed based on the layout topology with K = 3 dimensions, embedding the circuit's spatial layout information into a tensor, enabling the model to capture circuit design details in the spatial domain. Through this multi-dimensional and multi-level data integration, process parameter data, timing spectrum data, and layout topology are organically combined to form a three-dimensional circuit tensor with a structure of [N samples × M features × K dimensions]. This not only achieves efficient data alignment but also reveals circuit complexity across multiple dimensions. The beneficial effect of this process is that, through the systematic construction and analysis of multidimensional circuit data, it can comprehensively describe the performance characteristics and design details of the circuit, providing more accurate and rich data support for subsequent circuit optimization and prediction. In addition, this three-dimensional tensor construction method provides structured data input for subsequent machine learning, data mining, and intelligent optimization algorithms. This enables the model to more effectively capture the underlying patterns and interrelationships in each dimension when processing and analyzing circuit performance, thereby improving the efficiency and accuracy of circuit design.

[0037] Preferably, step S3 includes the following steps:

[0038] Step S31: performing subspace independent tensor division according to the circuit trace data, and performing matrix constraint decoupling to obtain circuit multi-space decoupling data;

[0039] Step S32: performing correlation hologram analysis on the circuit multi-space decoupling data to obtain a circuit parameter causal chain;

[0040] Step S33: Perform thermal-mechanical-electrical joint constraints on the circuit parameter causal chain to obtain circuit optimization trajectory data.

[0041] By partitioning the subspace into independent tensors and decoupling matrix constraints, the present invention effectively decomposes and separates the complex relationships and multidimensional dependencies within circuit trajectory data. The core of this process lies in compressing high-dimensional data into a low-dimensional space while ensuring that the inherent correlations between the data are not lost, thereby achieving accurate modeling of multidimensional circuit data. This decoupling process yields multi-dimensional circuit decoupled data, providing a simplified and efficient data representation for subsequent analysis. Next, in step S32, correlation hologram analysis is used to deeply explore the multi-dimensional circuit decoupled data and construct causal chains between circuit parameters. The introduction of hologram analysis effectively captures the multivariate interactions within the circuit system and, by revealing the causal relationships between individual circuit parameters, provides comprehensive and clear guidance for circuit optimization. Finally, in step S33, thermal-mechanical-electrical joint constraints are applied based on the circuit parameter causal chains, jointly analyzing data from multiple physical fields, including thermal, mechanical, and electrical, to optimize the circuit trajectory data. This process effectively integrates multi-physics constraints and more comprehensively reflects the circuit's performance under multi-physics conditions, providing more accurate and comprehensive data support for optimizing circuit design. Overall, this multi-level data processing and optimization method not only improves the accuracy of circuit design, but also effectively reduces potential errors and energy consumption in the design, providing technical support for more efficient and accurate circuit optimization.

[0042] Preferably, step S33 includes the following steps:

[0043] Step S331: Obtain circuit space domain;

[0044] Step S332: Mapping the circuit space domain to a three-dimensional grid for discretization to obtain a circuit mapping three-dimensional space;

[0045] Step S333: defining the fiber bundle structure in the circuit mapping three-dimensional space and recording the states of the three fields of heat, force, and electricity to obtain circuit fiber bundle state data;

[0046] Step S334: performing thermal field phase constraint on the circuit fiber cluster state data to obtain circuit thermal field constraint data; performing force-electric nonlinear interaction constraint on the circuit fiber cluster state data to obtain circuit force-electric joint constraint data;

[0047] Step S335: performing constraint field fusion on the circuit thermal field constraint data and the circuit force-electricity combined constraint data to obtain the circuit thermal-force-electricity constraint data;

[0048] Step S336: performing causal trajectory fusion optimization based on the circuit thermal-mechanical-electrical constraint data and the circuit trajectory multi-physics field data to obtain circuit optimized trajectory data.

[0049] The present invention provides a more accurate spatial description for circuit design through circuit space domain acquisition and three-dimensional grid discretization processing. Through this discretization method, the physical characteristics of the circuit can be fine-grained modeled in a clear three-dimensional space, laying the foundation for subsequent multi-physical field analysis. By mapping the circuit into three-dimensional space, the fiber bundle structure is defined and the state data of the three physical fields of heat, force and electricity are recorded. This operation effectively associates the complex circuit system structure with the behavior of the physical field, providing rich multi-dimensional data for subsequent analysis. The fiber bundle state data is processed with thermal field phase constraints and force-electric nonlinear interaction constraints to accurately characterize the interaction relationship between heat, force and electric fields, which is crucial for optimizing circuit design. Through the combined constraints of thermal field and force-electricity, the comprehensive performance of the circuit under the action of multiple physical fields can be effectively simulated, further improving the accuracy and feasibility of the design. By integrating the thermal field constraint data and the force-electricity combined constraint data, a global comprehensive description of the multi-physical field effects of the circuit is provided, further ensuring the physical consistency of the circuit design. By fusion-optimizing the causal trajectory of thermal-mechanical-electrical constraint data with multi-physics data on circuit trajectories, we can not only deeply explore the circuit's behavioral patterns in complex physical environments, but also achieve multi-dimensional optimization of circuit design, thereby obtaining more accurate circuit optimization trajectory data. Overall, this process, through multi-physics constraint fusion and causal trajectory optimization, improves the stability and performance of circuit design under multi-physics conditions, making it adaptable to more complex application scenarios, and achieving design optimization with higher precision, reducing potential risks caused by physical field interactions.

[0050] Preferably, step S4 includes the following steps:

[0051] Step S41: Perform digital circuit tunneling detection on the circuit optimization trace data to obtain digital circuit cross-domain violation data;

[0052] Step S42: performing field intensity gradient analysis on the digital circuit cross-domain violation data to obtain digital circuit field intensity analysis data;

[0053] Step S43: performing abnormal hotspot detection on the digital circuit field strength analysis data and generating a digital integrated circuit optimization report.

[0054] The present invention uses digital circuit tunneling detection to identify cross-domain violation data, which can accurately capture potential defects in circuit design, especially electrical short circuits or interference problems caused in high-frequency or complex circuits. Through this detection, design errors that cause performance degradation in the circuit can be discovered and corrected in a timely manner, avoiding the accumulation of adverse effects, thereby ensuring the reliability of the circuit. By performing field intensity gradient analysis on cross-domain violation data, the electric field distribution in the circuit can be deeply analyzed, and areas with drastic changes in electric field intensity can be further identified. These areas are often the source of circuit performance bottlenecks or potential faults. The results of field intensity analysis provide a quantitative basis for optimizing circuit design, helping engineers to accurately adjust circuit layout or component parameters and reduce unstable factors in the design. Abnormal hotspot detection identifies abnormal hotspot areas in the circuit design by screening and processing field intensity analysis data. These areas cause problems such as local overheating and signal interference, thereby affecting the stability and work efficiency of the entire circuit. By generating an abnormality report, detailed optimization suggestions can be provided to engineers, helping them to discover and correct potential risk points in the design phase. In general, this process can not only significantly improve the accuracy of circuit design and reduce potential faults through multi-level detection and analysis of circuit optimization trajectory data, but also provide strong data support for the execution of digital integrated circuit optimization tasks, making the final design of the circuit more efficient and stable, and meeting the expected performance requirements.

[0055] Preferably, step S43 includes the following steps:

[0056] Step S431: setting the field intensity gradient abnormality threshold;

[0057] Step S432: Filtering the digital circuit field strength analysis data using the field strength gradient abnormality threshold to obtain digital circuit field strength screening data;

[0058] Step S433: performing abnormal condition cluster analysis on the digital circuit field strength screening data, and generating a digital integrated circuit optimization report.

[0059] The present invention uses a field intensity gradient anomaly threshold as a key criterion for data screening. This threshold is determined based on the electric field intensity distribution patterns and performance requirements in circuit design, effectively identifying areas within the circuit that may cause failures or performance degradation. This method can identify potential areas of electric field anomalies during the design phase, reducing the risk of electrical failures caused by improper field intensity distribution. Secondly, the anomaly threshold is used to filter digital circuit field intensity analysis data, obtaining field intensity data that meets design standards and removing anomaly data that does not meet the threshold conditions. This screening process not only improves data accuracy but also allows subsequent analysis to focus on high-risk and high-impact areas within the circuit. Finally, based on the filtered field intensity data, cluster analysis of anomaly conditions is performed to further identify hotspots that cause failures or unstable performance under specific conditions. This cluster analysis not only helps engineers gain a more detailed understanding of potential circuit issues but also provides more specific guidance for circuit optimization, enabling rapid location and correction of problem areas. By generating reports, engineers can obtain detailed analysis results and optimization recommendations, further improving the design efficiency and reliability of digital integrated circuits. Overall, this process can improve the accuracy and predictability of circuit design, ensure the stability of circuit design in production and use, and minimize problems caused by design defects.

[0060] The present invention further provides a digital integrated circuit optimization system for executing the digital integrated circuit optimization method described above, the digital integrated circuit optimization system comprising:

[0061] The process parameter data acquisition and response grid construction module is used to obtain process parameter data and construct the parameter space response curve of the process parameter data; generate a process precision dense grid based on the parameter space response curve;

[0062] A 3D tensor construction module that fuses layout topology and timing data is used to extract the layout topology structure of the process precision dense grid; the process parameter data is converted into a time series spectrum to obtain circuit timing spectrum data; the process parameter data, circuit timing spectrum data and layout topology are used to construct a circuit 3D tensor, and the path tensor trajectory is detected to obtain circuit trajectory data;

[0063] The multi-physics data extraction and joint constraint optimization module is used to extract circuit trajectory multi-physics data based on circuit trajectory data; perform thermal-mechanical-electrical joint constraints on the circuit trajectory multi-physics data to obtain circuit optimized trajectory data;

[0064] The digital circuit anomaly detection and hotspot analysis module is used to perform digital circuit tunneling detection on circuit optimization trajectory data to obtain digital circuit cross-domain violation data; perform abnormal hotspot detection on digital circuit cross-domain violation data and generate a digital integrated circuit optimization report.

[0065] The beneficial effect of the present invention is that, by acquiring process parameter data and constructing a parameter space response curve, a comprehensive response to changes in different process parameters is ensured, and a dense grid of process precision is further generated based on this response curve to carefully capture tiny process changes, thereby providing high-precision data support for circuit design. By combining process parameter data with circuit timing spectrum data and layout topology, and constructing a three-dimensional circuit tensor on this basis, it is possible to achieve an organic fusion of information on each dimension of the circuit, forming a comprehensive multi-dimensional data model, which is convenient for subsequent in-depth analysis of circuit trajectory data. In this process, path tensor manifold analysis effectively compresses high-dimensional data into low-dimensional space, maintains the integrity of key information, and reveals the potential physical laws and performance bottlenecks in circuit design through manifold analysis. Then, through the extraction of multi-physics field data and the application of thermal-mechanical-electrical joint constraints, the multiple physical effects of the circuit are comprehensively optimized, further improving the reliability and stability of the circuit. Finally, by detecting tunneling and cross-domain violations in the circuit optimization trajectory data, we ensure that the circuit design meets process requirements while avoiding performance issues caused by physical parameter mismatches or design defects. At the same time, the abnormal hotspot detection function enables timely error diagnosis and feedback, providing accurate decision-making support for efficient circuit optimization and production. Therefore, by introducing high-precision data modeling and dynamic constraints at each stage, this invention breaks through the limitations of traditional circuit optimization methods, greatly improving the accuracy, stability, and performance of integrated circuit design, and ensuring a more refined and efficient circuit optimization process. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 A schematic flow chart of the steps of a digital integrated circuit optimization method;

[0067] Figure 2 for Figure 1 Detailed implementation steps of step S3 in FIG.

[0068] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0069] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative work are within the scope of protection of the present invention.

[0070] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller approaches.

[0071] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items.

[0072] To achieve this, please refer to Figures 1 to 2 , a digital integrated circuit optimization method, the method comprising the following steps:

[0073] Step S1: Acquire process parameter data and construct a parameter space response curve of the process parameter data; generate a process precision dense grid based on the parameter space response curve;

[0074] Step S2: extracting the layout topology of the process precision dense grid; performing time series spectrum conversion on the process parameter data to obtain circuit time series spectrum data; constructing a circuit three-dimensional tensor using the process parameter data, circuit time series spectrum data, and layout topology, and detecting the path tensor trajectory to obtain circuit trajectory data;

[0075] Step S3: extracting circuit trajectory multi-physics field data based on the circuit trajectory data; performing thermal-mechanical-electrical joint constraints on the circuit trajectory multi-physics field data to obtain circuit optimized trajectory data;

[0076] Step S4: Perform digital circuit tunneling detection on the circuit optimization trajectory data to obtain digital circuit cross-domain violation data; perform abnormal hotspot detection on the digital circuit cross-domain violation data, and generate a digital integrated circuit optimization report.

[0077] The beneficial effect of the present invention is that, through a series of sophisticated data processing and analysis technologies, a complete process from process parameter acquisition to digital circuit optimization is realized. First, when acquiring process parameter data, high-precision sensors are used to collect key process variables, such as threshold voltage (Vth) and line width (CD), and a parameter space response curve is constructed in combination with statistical analysis and machine learning regression models to characterize the nonlinear influence of process parameters on manufacturing accuracy. On this basis, an adaptive grid subdivision algorithm is used to generate a high-density process precision grid to ensure the continuity and accuracy of parameter changes in space. Subsequently, in the layout topology structure extraction link, the circuit layout information is analyzed in combination with the graph neural network (GNN), and the timing signal is converted into spectrum data using Fourier transform to form a circuit timing spectrum feature set. Based on this, a three-dimensional tensor containing process parameters, circuit timing spectrum and layout topology is constructed, and path tensor analysis is performed through the manifold learning method to obtain circuit trajectory data, revealing the characteristic evolution of circuit behavior in high-dimensional space. In the multi-physics field data extraction stage, the finite element method (FEM) is used to simulate the thermal-mechanical-electric field distribution, and temperature, stress and parasitic parameter data are extracted based on simulation tools such as ICEMD, Ansys and StarRC. Then, a joint constraint model is established in combination with the U(1)×SU(2) gauge field theory. The circuit trajectory is optimized through Yang-Mills discretization to ensure circuit stability and reliability. Finally, in the digital circuit anomaly detection process, tunneling effect modeling and deep learning anomaly detection algorithm are combined to perform cross-domain violation analysis on the optimized trajectory data, and field intensity gradient calculation is used to identify abnormal hot spots. Cluster analysis and hologram correlation modeling are used to generate optimization reports to guide circuit manufacturing and design adjustments. Therefore, by integrating high-dimensional manifold analysis, multi-physics field simulation and intelligent optimization methods, the present invention solves the problems of difficult to accurately model process parameters and circuit optimization being limited to single physical field analysis in traditional methods, thereby improving the accuracy and reliability of digital circuit manufacturing.

[0078] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a flow chart of steps of a digital integrated circuit optimization method according to the present invention. In this example, the digital integrated circuit optimization method includes the following steps:

[0079] Step S1: Acquire process parameter data and construct a parameter space response curve of the process parameter data; generate a process precision dense grid based on the parameter space response curve;

[0080] In an embodiment of the present invention, in this step, process parameter data is first acquired, and then the data is analyzed and processed to construct a parameter space response curve for the process parameter data. The specific technical means is to collect process parameters such as temperature, pressure, time, speed and other relevant manufacturing process parameters in an experimental or simulation environment, and use this data for regression analysis or interpolation to establish a mathematical model that reflects the impact of process parameters on product performance or quality. This response curve characterizes the relationship between process parameters and process performance, and can reveal the degree of influence and change trend of each process parameter on the final result. Next, based on the constructed response curve, a dense grid of process precision is generated through density analysis and numerical optimization methods. The core technical means of this step is to utilize the variation range of process parameters and the characteristics of the response curve to subdivide the parameter space using gridding technology, thereby obtaining a high-precision discretized grid, in which each grid point represents the state of a specific process parameter combination. By setting appropriate resolution and grid spacing, it is ensured that the density of the grid can fully capture the subtle changes in the process parameter space, thereby improving process control accuracy.

[0081] Step S2: extracting the layout topology of the process precision dense grid; performing time series spectrum conversion on the process parameter data to obtain circuit time series spectrum data; constructing a circuit three-dimensional tensor using the process parameter data, circuit time series spectrum data, and layout topology, and detecting the path tensor trajectory to obtain circuit trajectory data;

[0082] In an embodiment of the present invention, by extracting the layout topology of a dense process precision grid, this process involves obtaining layout-related geometric information from the process precision grid. The specific technical means is to use computer-aided design (CAD) tools or simulation software to model the layout and extract geometric elements such as nodes, edges, and faces and the topological relationships between them. This topological information can reveal the spatial structure of the circuit layout and further provide support for circuit performance analysis. Next, the process parameter data is converted through time series spectrum to obtain circuit time series spectrum data. This process uses spectrum analysis technology for time domain signals, usually using mathematical methods such as fast Fourier transform (FFT) or wavelet transform to convert time series data from the time domain to the frequency domain, thereby obtaining the response characteristics of the circuit at different frequencies. These time series spectrum data reflect the characteristics of the circuit that change over time in the time domain, and can reveal frequency-related problems that occur during the operation of the circuit, such as signal distortion, noise interference, etc. Next, the process parameter data, circuit time series spectrum data, and layout topology are integrated into a three-dimensional circuit tensor. Specifically, this process combines multidimensional data from different sources (such as spatial information of process parameters, temporal characteristics of timing spectra, and geometric topology of the layout) into a unified three-dimensional tensor representation through multidimensional data fusion technology. This allows the associations and interactions between the various parameters to be analyzed within a unified mathematical framework. Finally, the constructed three-dimensional circuit tensor is analyzed using the path tensor manifold analysis method to generate circuit trajectory data. Manifold analysis uses the idea of ​​mathematical manifolds to reduce high-dimensional data to a low-dimensional representation, thereby extracting the main patterns and trends in the data. In this process, a tensor manifold learning algorithm is used to reduce the dimensionality of the three-dimensional tensor and learn the paths to obtain circuit trajectory data. These trajectory data can reveal the overall behavior pattern of the circuit under the combined influence of factors such as process parameters, timing characteristics, and layout structure.

[0083] Step S3: extracting circuit trajectory multi-physics field data based on the circuit trajectory data; performing thermal-mechanical-electrical joint constraints on the circuit trajectory multi-physics field data to obtain circuit optimized trajectory data;

[0084] In an embodiment of the present invention, multi-physics field data extraction is performed based on circuit trajectory data, and this process relies on multi-physics field modeling technology. Specifically, by extracting features related to multiple physical fields such as electricity, heat, and force from the circuit trajectory data, numerical simulation methods such as finite element analysis (FEA), finite difference method (FDM) or computational fluid dynamics (CFD) are used to couple and model the physical phenomena of the circuit, such as the electric field, thermal field and force field. These physical field data characterize the response characteristics of the circuit under different physical effects, such as current density distribution, temperature distribution and mechanical deformation, through numerical simulation or experimental data. These multi-physics field data reflect the complex behavior of the circuit under actual working conditions, including thermal effects, material stress and voltage changes caused by current. These multi-physics field data provide a basis for subsequent circuit optimization, can help identify potential problems of the circuit under multiple physical effects, and provide a decision basis for the optimization process. Next, thermal-mechanical-electrical joint constraints are performed based on the circuit trajectory multi-physics field data. This step applies multi-physics field coupling technology, by incorporating the interactive relationship between the three physical fields of heat, force and electricity into the optimization constraints. The finite element method (FEM) or other coupled analysis techniques are usually used to jointly solve the equations of various physical fields (such as the heat conduction equation, the mechanical equilibrium equation, the electric field equation, etc.) to establish a comprehensive mathematical model that can describe the interactions and constraints between heat, force, and electricity. These joint constraints can effectively capture the dynamic changes of the circuit under the action of different physical fields. For example, the thermal effect generated when current passes through causes the material to expand, which in turn affects the mechanical behavior of the circuit, which in turn affects the electrical performance of the circuit. Finally, the circuit optimization trajectory data obtained is further optimized by multi-objective optimization algorithms (such as genetic algorithms, particle swarm optimization, etc.) under the joint constraints of the three physical fields of heat, force, and electricity.

[0085] Step S4: Perform digital circuit tunneling detection on the circuit optimization trajectory data to obtain digital circuit cross-domain violation data; perform abnormal hotspot detection on the digital circuit cross-domain violation data, and generate a digital integrated circuit optimization report.

[0086] In an embodiment of the present invention, digital circuit tunneling detection is performed on circuit optimization trajectory data. This step utilizes a tunneling effect detection algorithm to identify potential cross-domain violations in the circuit. Tunneling refers to the phenomenon of electrons passing through unauthorized areas or crossing potential obstacles at extremely small scales, which often occurs in nanoscale circuit designs. Tunneling detection technology is based on the principles of quantum mechanics and uses a quantitative model based on electric field and potential energy analysis to establish a mathematical model of tunneling probability to predict and identify anomalies in circuit design. For digital circuit optimization trajectory data, tunneling detection analyzes the potential differences between different regions in the circuit and the current flow path to identify areas that may cause performance loss or electrical interference. The resulting digital circuit cross-domain violation data is then further processed using anomaly hotspot detection technology. Anomaly hotspot detection methods mainly include statistical outlier detection and supervised and unsupervised learning methods based on machine learning. By performing cluster analysis and outlier analysis on the performance data of different regions in the circuit design, or using deep learning networks (such as autoencoders and convolutional neural networks) to identify areas that do not meet design specifications, those that cause functional failure, excessive power consumption, or heat accumulation are detected. Finally, a report is generated that summarizes all detected abnormal hotspots and violations and provides them to designers. These reports typically include the location of the violation, the type of violation, and the impact, helping engineers quickly locate problem areas and make appropriate optimization adjustments.

[0087] Preferably, step S1 includes the following steps:

[0088] Step S11: Setting the measurement range of the high-precision source meter to 0.1V-1.5V, with a minimum change of 0.05V;

[0089] Step S12: setting the measurement range of the electron microscope to 130nm-180nm and the EUV process range to 5nm-50nm;

[0090] Step S13: Acquire historical simulation data; use a high-precision source meter and an electron microscope to collect process parameter data from the historical simulation data;

[0091] Step S14: obtaining a sequential power consumption table; extracting sequential power consumption data from the sequential power consumption table;

[0092] Step S15: constructing a parameter space response curve based on the timing power consumption data and the process parameter data, and generating a process precision dense grid of the parameter space response curve, wherein the process precision dense grid is 0.1σ.

[0093] In an embodiment of the present invention, a high-precision mapping relationship between process parameters and circuit performance is established through refined experimental measurement and data analysis methods. During the process parameter data acquisition stage, a high-precision source meter (SMU) is used to measure key electrical characteristics such as threshold voltage (Vth). The measurement range is set to 0.1V to 1.5V, with a minimum step of 0.05V to ensure the accuracy and resolution of data acquisition. In addition, an electron microscope (SEM) is used to measure the key geometric dimensions of the process. The measurement range of the standard process line width (CD) is set to 130nm to 180nm, while the extreme ultraviolet lithography (EUV) process range is controlled to 5nm to 50nm to meet the analysis requirements of advanced process nodes. Data acquisition not only relies on real-time measurement, but is also supplemented by historical simulation data to improve data integrity and modeling accuracy. In the process of extracting timing power consumption data, a power consumption time series is constructed based on the timing power consumption table (including parameters such as clock cycle, dynamic power consumption, and static leakage power consumption), and the power consumption spectrum characteristics are extracted using Fourier transform to characterize the evolution trend of circuit power consumption under different working conditions. Subsequently, the process parameter data and timing power consumption data are input into the parameter space modeling framework. High-dimensional interpolation methods (such as Kriging interpolation or Gaussian process regression) are used to construct parameter space response curves to accurately describe the impact of process variables on circuit characteristics. On this basis, adaptive meshing technology is used to generate a high-precision process dense grid with a resolution of 0.1σ to ensure statistical coverage of the process fluctuation range and provide fine-grained data support for subsequent optimization and analysis.

[0094] Preferably, the process precision dense grid construction in step S1 includes:

[0095] The collected process parameter data is used as the input axis;

[0096] The time series power consumption data is used as the output axis;

[0097] Forming a parameter space response curve based on the collected process parameter data and timing power consumption data;

[0098] Analyze the sudden change region of the parameter space response curve where the curvature change is greater than 0.15 / nm and obtain the circuit second-order derivative matrix;

[0099] A process precision dense grid is created based on the fact that the spacing between adjacent sampling points of the circuit second-order derivative matrix is ​​less than 3 nm, where the process precision dense grid is 0.1σ.

[0100] In an embodiment of the present invention, a parameter space response curve is constructed to accurately characterize the influence of process parameters on circuit performance, and based on second-order derivative matrix analysis and dense grid generation, the process precision control strategy is optimized. First, the collected process parameter data (including threshold voltage Vth, line width CD, etc.) is used as the input axis, and the timing power consumption data (including dynamic power consumption, static leakage power consumption and switching activity factor, etc.) is used as the output axis. A high-dimensional interpolation method (such as Kriging interpolation or radial basis function interpolation) is used to establish a parameter space response curve to fit the nonlinear mapping relationship between process parameters and circuit power consumption characteristics. In the curvature analysis stage, the numerical differentiation method is used to calculate the first-order derivative and second-order derivative of the parameter space response curve, and the circuit second-order derivative matrix is ​​constructed to evaluate the sensitivity of different process parameter areas. If the curvature change exceeds 0.15 / nm, it indicates that the area is more sensitive to process fluctuations, resulting in instability in circuit performance, so refined sampling is required. Based on the second-order derivative matrix, high-density sampling is performed in areas with spacing less than 3nm between adjacent sampling points using Delaunay triangulation or Voronoi diagram partitioning techniques to improve resolution in critical process regions. Subsequently, the subdivision scale of the dense process precision grid is set to 0.1σ using standard deviation normalization to ensure that the grid distribution covers the process drift range and optimizes sampling uniformity in the parameter space.

[0101] Preferably, obtaining the circuit trace data in step S2 includes:

[0102] Constructing a circuit three-dimensional tensor from process parameter data, circuit timing spectrum data and process parameter data;

[0103] Perform manifold isometric projection according to the circuit three-dimensional tensor to form a circuit manifold projection;

[0104] Perform 8-layer deep autoencoder feature compression based on circuit manifold projection to obtain circuit feature compression data;

[0105] The detection path tensor trajectory is performed according to the circuit feature compression data to obtain the circuit trajectory data.

[0106] In an embodiment of the present invention, a three-dimensional tensor data structure is constructed by utilizing process parameter data (including threshold voltage Vth, line width CD, etc.), circuit timing spectrum data (covering clock delay, propagation delay, signal integrity parameters, etc.) and spatial distribution information corresponding to the process parameter data to fully characterize the impact of process fluctuations on circuit performance. The three-dimensional tensor adopts a standardized tensor storage format and combines principal component analysis (PCA) or non-negative matrix decomposition (NMF) for dimensionality reduction to reduce redundant information interference. In the manifold learning stage, the circuit three-dimensional tensor is nonlinearly reduced in dimensionality based on manifold isometric projection (Isomap or t-SNE) and embedded into a low-dimensional manifold space to maintain the global topological structure while optimizing the mapping relationship between the circuit process parameters and the performance. Subsequently, an 8-layer deep autoencoder (DAE) is used to perform feature compression on the manifold projection data, extract low-dimensional implicit features through the encoder part, and reconstruct the original data using the decoder to ensure information integrity, thereby obtaining high-resolution circuit feature compression data. Finally, based on the path tensor manifold analysis method, a multi-scale tensor path parsing framework is constructed to extract key circuit trajectory information, quantify the nonlinear characteristics of the signal propagation path, and combine it with time series prediction models (such as LSTM or Transformer) to analyze the circuit trajectory evolution trend.

[0107] Preferably, the constructing of the circuit three-dimensional tensor includes:

[0108] The process parameter data is converted into 128 feature vectors;

[0109] The first dimension is constructed based on the process parameter data, where the sample size is set to 10k;

[0110] The second dimension is constructed based on the process parameter data, where the feature is set to 512;

[0111] Construct the third dimension based on the layout topology, where the dimension is set to 3;

[0112] The first-dimensional circuit tensor, the second-dimensional circuit tensor, and the third-dimensional circuit tensor are aligned according to the [N samples × M features × K dimensions] structure to obtain the three-dimensional circuit tensor.

[0113] In an embodiment of the present invention, the process parameter data is subjected to feature vector quantization processing, and the process parameters are mapped to 128-dimensional feature vectors using statistical feature extraction, principal component analysis (PCA) and orthogonal matching pursuit (OMP) methods to retain the discrimination of the process parameters in multidimensional space. Subsequently, in the tensor construction process, the process parameter data is expanded in the first dimension according to the sampling scale N=10k, and the data distribution is optimized by Latin hypercube sampling (LHS) and kernel density estimation (KDE) to ensure that the data covers the key process variable space of the circuit operation and improve the generalization capability. In the time series spectrum dimension, the dynamic frequency response of the key nodes of the circuit is analyzed based on the time domain-frequency domain joint transform (such as short-time Fourier transform STFT, wavelet transform WT), and a second-dimensional tensor is established according to the channel structure of M=512 to characterize the evolution law of the circuit timing signal under different load, temperature and process deviation conditions. Furthermore, in the layout topology dimension, using an adjacency matrix and a minimum spanning tree (MST)-based network optimization method, the physical layout information is modeled in the third dimension based on a spatial discretization method with K=3 to accurately describe the impact of circuit layout, metal interconnects, and parasitic parameters on signal propagation paths. Ultimately, the first-dimensional circuit tensor (process parameters), the second-dimensional circuit tensor (timing spectrum), and the third-dimensional circuit tensor (layout topology) are normalized, scale-aligned, and multi-dimensional tensor splicing is performed. The data is stored in the format of [N samples × M features × K dimensions], and high-order tensor decompositions (such as CP decomposition and Tucker decomposition) are applied to reduce the dimensionality of the data to improve computational efficiency and reduce storage redundancy.

[0114] As an example of the present invention, refer to Figure 2 As shown, in this example, step S3 includes:

[0115] Step S31: performing subspace independent tensor division according to the circuit trace data, and performing matrix constraint decoupling to obtain circuit multi-space decoupling data;

[0116] Step S32: performing correlation hologram analysis on the circuit multi-space decoupling data to obtain a circuit parameter causal chain;

[0117] Step S33: Perform thermal-mechanical-electrical joint constraints on the circuit parameter causal chain to obtain circuit optimization trajectory data.

[0118] In an embodiment of the present invention, based on the circuit trajectory data, non-negative tensor decomposition (NTF) or independent component analysis (ICA) is first used to decouple the circuit multivariate signal to eliminate redundant information and collinearity in the circuit state. Subsequently, through the subspace independent tensor partitioning method, dimensionality reduction algorithms such as spectral clustering or local linear embedding (LLE) are used to identify the main change trends of the circuit trajectory in the high-dimensional feature space, and construct local subspaces so that circuit characteristics of different physical properties can be modeled separately. At the same time, the constraint matrix decomposition (Constraint Matrix Factorization) method is used to impose matrix constraints within the tensor subspace to maintain the independence and resolvability between physical variables, ensuring that the decoupled data can accurately reflect the independent change patterns under different circuit states. Based on holographic mapping theory, correlation holography is used to perform multi-scale analysis on decoupled circuit data. The Gram Matrix is ​​used to measure the similarity of circuit states, and time series entropy analysis is combined to construct a causal chain of circuit parameters, thereby identifying the core parameter interactions that affect circuit stability and performance. Integrating this information with the circuit parameter causal chain, a combined thermal-mechanical-electrical constraint approach is employed to optimize the circuit trajectory. First, a thermal-mechanical-electrical coupled multiphysics finite element model is established. The electric field distribution is solved using the Poisson equation, mechanical effects are analyzed using a nonlinear stress-strain model, and heat diffusion processes are calculated using the heat conduction equation. Within this coupled framework, reinforcement learning or Bayesian optimization methods are used to adaptively adjust the circuit optimization trajectory data to ensure that it meets design constraints under different physical field conditions.

[0119] It is particularly important that step S32 includes the following steps:

[0120] Perform subspace independent tensor division based on circuit multi-space decoupling data to obtain circuit trajectory space subvectors;

[0121] Perform temporal evolution according to the circuit track space subvectors and construct a circuit track hologram;

[0122] Performing phase interference fringe processing on the circuit track hologram and performing correlation hologram analysis to obtain circuit track hologram analysis data;

[0123] Parameter causal chain analysis is performed on the circuit trace hologram analysis data to obtain the circuit parameter causal chain.

[0124] In an embodiment of the present invention, independent tensor subspace partitioning is performed based on the multi-dimensional decoupled circuit data. The goal is to decompose the complex multi-dimensional data in the circuit into more independent and low-dimensional subspaces. Based on the mathematical theory of tensor decomposition, this independent tensor subspace partitioning technique can extract important low-dimensional information from the multi-dimensional decoupled circuit data, converting the original data into a more concise sub-vector form. These sub-vectors represent the different characteristics and changing trends of the circuit trajectory, providing an effective data foundation for subsequent analysis. Next, a circuit trajectory hologram is constructed by performing temporal evolution on the sub-vectors in the circuit trajectory space. Temporal evolution technology simulates the time-varying behavior of circuit systems based on time series analysis of dynamic data. This process maps the circuit's timing characteristics into a multi-dimensional space by constructing a hologram. Data points at each moment are accurately mapped into the hologram, forming a visual data structure that facilitates in-depth analysis. Subsequently, phase interference fringe processing is performed on the circuit trajectory hologram. This uses the principle of phase interference to analyze the phase changes and interference effects of the circuit under different conditions, generating a fringe-like interference pattern that can help reveal potential problems or performance bottlenecks in circuit design. Next, correlation hologram analysis technology is applied to further process the phase interference fringes to extract the underlying information and patterns, thereby generating circuit trace hologram analysis data. Correlation hologram analysis leverages graph theory and pattern recognition techniques to analyze spatial correlations within the image and identify the inherent connections between different data. Finally, parameter causal chain analysis is performed on the circuit trace hologram analysis data to reveal the causal relationships between various circuit parameters. This analysis typically relies on causal inference and graphical modeling techniques, constructing a causal network to determine how different circuit parameters influence each other, thereby optimizing circuit design and performance.

[0125] Preferably, step S33 includes the following steps:

[0126] Step S331: Obtain circuit space domain;

[0127] Step S332: Mapping the circuit space domain to a three-dimensional grid for discretization to obtain a circuit mapping three-dimensional space;

[0128] Step S333: defining the fiber bundle structure in the circuit mapping three-dimensional space and recording the states of the three fields of heat, force, and electricity to obtain circuit fiber bundle state data;

[0129] Step S334: performing thermal field phase constraint on the circuit fiber cluster state data to obtain circuit thermal field constraint data; performing force-electric nonlinear interaction constraint on the circuit fiber cluster state data to obtain circuit force-electric joint constraint data;

[0130] Step S335: performing constraint field fusion on the circuit thermal field constraint data and the circuit force-electricity combined constraint data to obtain the circuit thermal-force-electricity constraint data;

[0131] Step S336: performing causal trajectory fusion optimization based on the circuit thermal-mechanical-electrical constraint data and the circuit trajectory multi-physics field data to obtain circuit optimized trajectory data.

[0132] In an embodiment of the present invention, by obtaining the spatial domain information of the circuit, the spatial domain covers the geometric topological relationship of the circuit layout, the material distribution, and the initial state of the electric field, stress field, and temperature field. A three-dimensional mesh partitioning method (such as Delaunay triangulation or octree partitioning) is used to discretize the circuit spatial domain to ensure that the complex geometric structure can maintain analyticality during the calculation process and generate a three-dimensional space for circuit mapping. A fiber bundle structure is introduced to define the physical state of each grid cell in the circuit spatial domain. The structure uses the base space (Base Space) to represent the circuit geometric topology and uses fibers (Fiber) to record the physical states of electricity, force, heat, etc., forming circuit fiber bundle state data. Thermal field phase constraints are applied to the circuit fiber bundle state data. The dominant modes of the thermal field are extracted using Fourier transforms, and phase retrieval methods are used to correct for areas of sudden temperature gradient changes to ensure the continuity of heat flow. Then, the mechanical-electrical nonlinear interaction is constrained, and the stress-electrical field distribution is calculated using nonlinear finite element analysis (NFEA). The local mechanical-electrical coupling effect is described using nonlinear coupling equations (such as the Landau-Ginzburg equation), thereby obtaining the circuit mechanical-electrical joint constraint data. Based on a multi-field constraint fusion strategy, the circuit thermal field constraint data and the mechanical-electrical joint constraint data are uniformly solved through a multi-objective optimization method, and a constraint field fusion model is constructed to ensure the coordinated stability of the thermal, mechanical, and electrical components. Combining the multi-physics field data of circuit trajectories, a causal trajectory fusion method is adopted to analyze the impact of circuit signal changes on multi-physics field behaviors through temporal causal inference. A path optimization method based on graph neural network (GNN) is used to adjust the circuit trajectory optimization scheme to achieve optimal performance under thermal-mechanical-electrical coupling constraints.

[0133] Preferably, step S4 includes the following steps:

[0134] Step S41: Perform digital circuit tunneling detection on the circuit optimization trace data to obtain digital circuit cross-domain violation data;

[0135] Step S42: performing field intensity gradient analysis on the digital circuit cross-domain violation data to obtain digital circuit field intensity analysis data;

[0136] Step S43: performing abnormal hotspot detection on the digital circuit field strength analysis data and generating a digital integrated circuit optimization report.

[0137] In an embodiment of the present invention, digital circuit tunneling detection is performed on the circuit optimization trajectory data, and a quantum tunneling effect modeling method (such as WKB approximation or non-equilibrium Green's function method) is used to calculate the tunneling leakage path in the charge transfer process. Based on this modeling method, density functional theory (DFT) or drift-diffusion equation (Drift-DiffusionEquation) is used to calculate the local electric field enhancement area in the circuit trajectory to identify the cross-domain violation phenomenon, and finally obtain the digital circuit cross-domain violation data. In step S42, a field intensity gradient analysis is performed on the cross-domain violation data. First, the electric field distribution of the violation area is reconstructed using the finite difference method (FDM) or the finite element method (FEM). By calculating the electric field gradient Regions of high electric field variation are identified, and the Laplace transform is used to analyze potential electric field distortion. Furthermore, a spectral decomposition method based on the multi-scale wavelet transform is introduced to separate the field intensity variation characteristics of different frequency bands to improve the accuracy of cross-domain violation detection. Ultimately, digital circuit field intensity analysis data is obtained. Abnormal hotspot detection is performed on this digital circuit field intensity analysis data. Adaptive threshold segmentation is used to extract abnormally high field intensity regions, and a Markov random field (MRF) model is combined to probabilistically evaluate the spatial distribution of hotspot regions. Furthermore, deep learning models (such as CNN or Transformer) are used to identify hotspot patterns to improve detection accuracy, and causal inference is combined with temporal sequence analysis to analyze the potential causes of abnormal hotspots. Finally, an optimization report is generated based on the detection results, containing detailed information on the violation areas, optimization suggestions, and circuit adjustment plans to guide the execution of digital integrated circuit optimization tasks.

[0138] Preferably, step S43 includes the following steps:

[0139] Step S431: setting the field intensity gradient abnormality threshold;

[0140] Step S432: Filtering the digital circuit field strength analysis data using the field strength gradient abnormality threshold to obtain digital circuit field strength screening data;

[0141] Step S433: performing abnormal condition cluster analysis on the digital circuit field strength screening data, and generating a digital integrated circuit optimization report.

[0142] In an embodiment of the present invention, a field intensity gradient anomaly threshold is set to identify high electric field mutation areas in digital circuits. The setting of the threshold is based on historical circuit design data, experimental measurement data, and simulation analysis results. A statistical distribution method (such as normal distribution or Weibull distribution) can be used for probability modeling, and the degree of deviation between the mean μ and the standard deviation σ (such as μ±3σ) can be used to set the anomaly judgment range. In addition, an adaptive quantile analysis (Quantile-Based Adaptive Thresholding) method can be used to dynamically adjust the threshold to adapt to different process nodes and circuit types. In step S432, the field intensity analysis data of the digital circuit is screened using the set field intensity gradient anomaly threshold to extract abnormally high gradient change areas. Specifically, the electric field gradient is calculated based on the finite difference (Finite Difference) or finite element (Finite Element) method. Spatial locations that meet the threshold conditions are screened out in the grid structure, and a region growing algorithm is used for connectivity analysis to further eliminate isolated outliers and ensure the physical rationality of the screened areas. In addition, a Kalman filter or particle filter method based on spatiotemporal relationships is introduced to eliminate the interference of measurement noise on the screened data and obtain stable digital circuit field strength screening data. Abnormal condition clustering analysis is performed on the high-field strength areas screened to explore different abnormal patterns. First, K-means, DBSCAN or Gaussian Mixture Model (GMM) is used for cluster analysis, and high-dimensional feature dimensionality reduction methods (such as t-SNE or PCA) are combined to optimize the clustering effect. In addition, a self-supervised learning model is used to extract deep features of the abnormal patterns, and a topological association analysis method based on a graph neural network (GNN) is used to construct a causal relationship network between abnormal areas. Finally, an abnormal hotspot report is generated based on the cluster analysis results, including the distribution of abnormal areas, abnormal types and their influencing factors, and optimization suggestions are provided to guide the execution of digital integrated circuit optimization tasks.

[0143] It is particularly important that step S432 includes the following steps:

[0144] The digital circuit field strength analysis data is screened using the field strength gradient anomaly threshold to obtain the digital circuit field strength preliminary screening data;

[0145] Perform smoothing filtering and suppression processing on the digital circuit field strength preliminary screening data to obtain digital circuit field strength suppression data;

[0146] The spatial connectivity aggregation processing is performed on the digital circuit field strength suppression data to obtain the digital circuit field strength preliminary screening data.

[0147] In an embodiment of the present invention, digital circuit field strength analysis data is screened using a field strength gradient anomaly threshold. The core of this step is to set an anomaly threshold to identify and filter out field strength data that exceeds the normal range of variation. Setting the threshold effectively eliminates noise or abnormal data. This process typically employs statistical analysis techniques, such as the standard deviation method or percentile method, thereby retaining more accurate signal data. Next, smoothing filtering and suppression processing is performed on the initial screening digital circuit field strength data. This step aims to further remove high-frequency noise from the data and preserve important trends and signal characteristics. Smoothing filtering and suppression processing can be implemented using a variety of filters, such as low-pass filters, moving averages, or Gaussian filters. These smoothing operations aim to reduce short-term variations caused by signal fluctuations, thereby stabilizing the signal. Subsequently, spatial connectivity aggregation processing is performed on the digital circuit field strength suppression data to identify spatial correlations and structural features in the data. Spatial connectivity aggregation methods can cluster regions or nodes with similar attributes in the data, forming spatially consistent regions, which is very useful for analyzing connectivity issues in circuits. This method typically employs graph theory or clustering algorithms, such as K-means clustering, DBSCAN, or connectivity analysis, to extract spatial patterns and connections within the data. Ultimately, these processing steps yield preliminary screening data for digital circuit field strength, providing cleaner, more stable, and more efficient data input for subsequent analysis, optimization, and testing.

[0148] The present invention further provides a digital integrated circuit optimization system for executing the digital integrated circuit optimization method described above, the digital integrated circuit optimization system comprising:

[0149] The process parameter data acquisition and response grid construction module is used to obtain process parameter data and construct the parameter space response curve of the process parameter data; generate a process precision dense grid based on the parameter space response curve;

[0150] A 3D tensor construction module that fuses layout topology and timing data is used to extract the layout topology structure of the process precision dense grid; the process parameter data is converted into a time series spectrum to obtain circuit timing spectrum data; the process parameter data, circuit timing spectrum data and layout topology are used to construct a circuit 3D tensor, and the path tensor trajectory is detected to obtain circuit trajectory data;

[0151] The multi-physics data extraction and joint constraint optimization module is used to extract circuit trajectory multi-physics data based on circuit trajectory data; perform thermal-mechanical-electrical joint constraints on the circuit trajectory multi-physics data to obtain circuit optimized trajectory data;

[0152] The digital circuit anomaly detection and hotspot analysis module is used to perform digital circuit tunneling detection on circuit optimization trajectory data to obtain digital circuit cross-domain violation data; perform abnormal hotspot detection on digital circuit cross-domain violation data and generate a digital integrated circuit optimization report.

[0153] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0154] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A digital integrated circuit optimization method, characterized in that: The following steps are involved: Step S1: Acquire process parameter data and construct a parameter space response curve of the process parameter data; Generate process precision dense grid based on parameter space response curve; Step S2: extracting the layout topology of the process precision dense grid; Performing time series spectrum conversion on process parameter data to obtain circuit time series spectrum data; The process parameter data, circuit timing spectrum data and layout topology structure are used to construct a three-dimensional circuit tensor, and the path tensor trajectory is detected to obtain circuit trajectory data; Step S3: extracting circuit trajectory multi-physics field data based on the circuit trajectory data; performing thermal-mechanical-electrical joint constraints on the circuit trajectory multi-physics field data to obtain circuit optimized trajectory data; Step S4: Perform digital circuit tunneling detection on the circuit optimization trajectory data to obtain digital circuit cross-domain violation data; perform abnormal hotspot detection on the digital circuit cross-domain violation data, and generate a digital integrated circuit optimization report.

2. The digital integrated circuit optimization method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: Setting the measurement range of the high-precision source meter to 0.1V-1.5V, with a minimum change of 0.05V; Step S12: setting the measurement range of the electron microscope to 130nm-180nm and the EUV process range to 5nm-50nm; Step S13: Acquire historical simulation data; use a high-precision source meter and an electron microscope to collect process parameter data from the historical simulation data; Step S14: obtaining a sequential power consumption table; extracting sequential power consumption data from the sequential power consumption table; Step S15: constructing a parameter space response curve based on the timing power consumption data and the process parameter data, and generating a process precision dense grid of the parameter space response curve, wherein the process precision dense grid is 0.1σ.

3. The digital integrated circuit optimization method according to claim 1, characterized in that: The process precision dense grid construction described in step S1 includes: The collected process parameter data is used as the input axis; The time series power consumption data is used as the output axis; Forming a parameter space response curve based on the collected process parameter data and timing power consumption data; Analyze the sudden change region of the parameter space response curve where the curvature change is greater than 0.15 / nm and obtain the circuit second-order derivative matrix; A process precision dense grid is created based on the fact that the spacing between adjacent sampling points of the circuit second-order derivative matrix is ​​less than 3 nm, where the process precision dense grid is 0.1σ.

4. The digital integrated circuit optimization method according to claim 1, wherein: Obtaining the circuit trace data in step S2 includes: Constructing a circuit three-dimensional tensor from process parameter data, circuit timing spectrum data and process parameter data; Perform manifold isometric projection according to the circuit three-dimensional tensor to form a circuit manifold projection; Perform 8-layer deep autoencoder feature compression based on circuit manifold projection to obtain circuit feature compression data; The path tensor trajectory is detected according to the circuit feature compression data to obtain circuit trajectory data.

5. The digital integrated circuit optimization method according to claim 4, characterized in that: The construction of the circuit three-dimensional tensor includes: The process parameter data is converted into 128 feature vectors; The first dimension is constructed based on the process parameter data, where the sample size is set to 10k; The second dimension is constructed based on the process parameter data, where the feature is set to 512; Construct the third dimension based on the layout topology, where the dimension is set to 3; The first-dimensional circuit tensor, the second-dimensional circuit tensor, and the third-dimensional circuit tensor are aligned according to the [N samples × M features × K dimensions] structure to obtain the three-dimensional circuit tensor.

6. The digital integrated circuit optimization method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: performing subspace independent tensor division according to the circuit trace data, and performing matrix constraint decoupling to obtain circuit multi-space decoupling data; Step S32: performing correlation hologram analysis on the circuit multi-space decoupling data to obtain a circuit parameter causal chain; Step S33: Perform thermal-mechanical-electrical joint constraints on the circuit parameter causal chain to obtain circuit optimization trajectory data.

7. The digital integrated circuit optimization method according to claim 1, characterized in that: Step S33 includes the following steps: Step S331: Obtain circuit space domain; Step S332: Mapping the circuit space domain to a three-dimensional grid for discretization to obtain a circuit mapping three-dimensional space; Step S333: defining the fiber bundle structure in the circuit mapping three-dimensional space and recording the states of the three fields of heat, force, and electricity to obtain circuit fiber bundle state data; Step S334: performing thermal field phase constraint on the circuit fiber cluster state data to obtain circuit thermal field constraint data; performing force-electric nonlinear interaction constraint on the circuit fiber cluster state data to obtain circuit force-electric joint constraint data; Step S335: performing constraint field fusion on the circuit thermal field constraint data and the circuit force-electricity combined constraint data to obtain the circuit thermal-force-electricity constraint data; Step S336: performing causal trajectory fusion optimization based on the circuit thermal-mechanical-electrical constraint data and the circuit trajectory multi-physics field data to obtain circuit optimized trajectory data.

8. The digital integrated circuit optimization method according to claim 1, wherein: Step S4 includes the following steps: Step S41: Perform digital circuit tunneling detection on the circuit optimization trace data to obtain digital circuit cross-domain violation data; Step S42: performing field intensity gradient analysis on the digital circuit cross-domain violation data to obtain digital circuit field intensity analysis data; Step S43: performing abnormal hotspot detection on the digital circuit field strength analysis data and generating a digital integrated circuit optimization report.

9. The digital integrated circuit optimization method according to claim 1, wherein: Step S43 includes the following steps: Step S431: setting the field intensity gradient abnormality threshold; Step S432: Filtering the digital circuit field strength analysis data using the field strength gradient abnormality threshold to obtain digital circuit field strength screening data; Step S433: performing abnormal condition cluster analysis on the digital circuit field strength screening data, and generating a digital integrated circuit optimization report.

10. A digital integrated circuit optimization system, characterized in that: For executing the digital integrated circuit optimization method according to claim 1, the digital integrated circuit optimization system comprises: The process parameter data acquisition and response grid construction module is used to obtain process parameter data and construct the parameter space response curve of the process parameter data; generate a process precision dense grid based on the parameter space response curve; A 3D tensor construction module that fuses layout topology and timing data is used to extract the layout topology structure of the process precision dense grid; the process parameter data is converted into a time series spectrum to obtain circuit timing spectrum data; the process parameter data, circuit timing spectrum data and layout topology are used to construct a circuit 3D tensor, and the path tensor trajectory is detected to obtain circuit trajectory data; The multi-physics data extraction and joint constraint optimization module is used to extract circuit trajectory multi-physics data based on circuit trajectory data; perform thermal-mechanical-electrical joint constraints on the circuit trajectory multi-physics data to obtain circuit optimized trajectory data; The digital circuit anomaly detection and hotspot analysis module is used to perform digital circuit tunneling detection on circuit optimization trajectory data to obtain digital circuit cross-domain violation data; perform abnormal hotspot detection on digital circuit cross-domain violation data and generate a digital integrated circuit optimization report.

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