Sense amplifier based on flip point and current mirror compensation, reading circuit and chip

Abstract

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier based on flip point and current mirror compensation, a reading circuit and a chip. The invention designs a sensitive amplifier based on flip point and current mirror compensation. The sensitive amplifier comprises 11 NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M11 and two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2. Corresponding control logic is provided in cooperation with the provided sensitive amplifier, so that a pre-charging stage, an offset elimination stage, an offset compensation stage, a charge sharing and reference voltage amplification stage and an induction amplification stage are designed when the sensitive amplifier reads the DRAM storage unit. The sensitive amplifier provided by the invention has the advantages that the number of elements is small, the circuit area is not greatly increased, the high sensing yield is ensured, the offset voltage index is greatly reduced, and the reading speed is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of DRAM circuit design, and more specifically, to: 1. a sense amplifier based on flip point and current mirror compensation (abbreviated as SCCSA); 2. a read circuit constructed based on the SCCSA; and 3. a sense amplifier chip designed based on the SCCSA. Background Art

[0002] Dynamic random access memory (DRAM) is a core memory element with a simple structure, storing a single bit of data using a single transistor and a single capacitor. However, this design is not perfect. During operation, the transistors and capacitors can leak charge, causing data to be gradually lost. Therefore, periodic refresh operations are necessary to maintain data stability.

[0003] The sense amplifier plays a crucial role in DRAM read and write operations. It amplifies the weak charge signal in the memory cell and converts it into a logic level of "0" or "1." Sense amplifier performance parameters primarily include read speed, sensing yield, offset voltage, power consumption, component count, and circuit area.

[0004] Although DRAM sense amplifiers optimized for offset voltage have emerged, such as offset cancellation sense amplifiers (OCSAs), actual testing has revealed the following issues:

[0005] 1. OCSA circuit stability is average. When reading a "1," OSCA has a high sensing yield and a stable circuit; however, when reading a "0," OCSA has a very low sensing yield and is very unstable.

[0006] 2. The offset voltage level of OCSA is still high and has not reached the ideal level, and further improvement is still needed.

[0007] In addition, the present invention also needs to be optimized for read speed; at the same time, it is also hoped that in the process of improving the DRAM sense amplifier, the disorderly increase in the number of components can be avoided as much as possible to prevent the circuit layout from becoming complex and bloated, thereby ensuring that the area of ​​the overall circuit will not be excessively expanded due to design improvements, so as to meet the urgent needs of modern electronic devices for miniaturized, high-performance memory.

[0008] In summary, the research direction of the present invention is to effectively reduce the offset voltage of the DRAM sense amplifier and increase the read speed of the DRAM sense amplifier while minimizing the circuit area and ensuring a high sensing yield of the circuit. Summary of the Invention

[0009] Based on this, it is necessary to provide a sense amplifier, reading circuit, and chip based on flip point and current mirror compensation to address the problem that existing DRAM sense amplifiers fail to reduce offset voltage and increase reading speed while minimizing circuit area and ensuring high circuit sensing yield.

[0010] The present invention is achieved by adopting the following technical solutions:

[0011] In a first aspect, the present invention provides a sense amplifier based on a flip point and current mirror compensation, comprising: 11 NMOS transistors M1 - M11 and 2 PMOS transistors P1 - P2.

[0012] Among them, the source of P1 is connected to the control signal SAP2;

[0013] The source of P2 is connected to the control signal SAP1;

[0014] The source of M1 is connected to the control signal SAN2, and the drain is connected to the drain of P1;

[0015] The source of M2 is connected to the control signal SAN1, and the drain is connected to the drain of P2;

[0016] The source of M3 is connected to the drain of M1, the gate is connected to the control signal OC, and the drain is connected to the gate of M1;

[0017] The source of M4 is connected to the drain of M2, the gate is connected to OC, and the drain is connected to the gate of M2;

[0018] The source of M5 is connected to the drain of M1, the gate is connected to the control signal ISO1, and the drain is connected to the gate of P2;

[0019] The source of M6 is connected to the drain of M2, the gate is connected to the control signal ISO2, and the drain is connected to the gate of P1;

[0020] The source of M7 is connected to the gate of M1, the gate is connected to the control signal ISO3, and the drain is connected to the gate of P1;

[0021] The source of M8 is connected to the gate of M2, the gate is connected to the control signal ISO4, and the drain is connected to the gate of P2;

[0022] The source of M9 is connected to BL, the gate is connected to the control signal PRE, and the drain is connected to the control signal Vref;

[0023] The source of M10 is connected to BLB, the gate is connected to PRE, and the drain is connected to Vref;

[0024] The source of M11 is connected to BL, the gate is connected to PRE, and the drain is connected to BLB.

[0025] Among them, P1 and M1 constitute inverter one, and P2 and M2 constitute inverter two.

[0026] The implementation of the sense amplifier based on the flip point and current mirror compensation is in accordance with the method or process of an embodiment of the present disclosure.

[0027] In a second aspect, the present invention discloses a reading circuit, comprising: a first DRAM storage unit, a second DRAM storage unit, and a sensitive amplifier based on a flip point and current mirror compensation as disclosed in the first aspect.

[0028] DRAM storage unit 1 is used to store 0 or 1. DRAM storage unit 2 is used to store 0 or 1.

[0029] A sense amplifier based on a flip-point and current mirror compensation is used to read a DRAM storage cell one or a DRAM storage cell two.

[0030] The implementation of such a read circuit is in accordance with the method or process of an embodiment of the present disclosure.

[0031] In a third aspect, the present invention discloses a sense amplifier chip, which adopts the circuit layout of the sense amplifier based on the flip point and current mirror compensation disclosed in the first aspect.

[0032] The implementation of the sense amplifier chip is based on the method or process of the embodiment of the present disclosure.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. The present invention designs a sense amplifier based on flip-point and current mirror compensation, and uses corresponding control logic to implement the following stages when reading DRAM memory cells: a precharge phase, an offset cancellation phase, an offset compensation phase, a charge sharing and reference voltage amplification phase, and a sensing amplification phase. In the offset cancellation phase, the input and output of the inverter are connected, stabilizing the voltage across the bit line to the inverter's flip point, thereby reducing offset. The current mirror structure formed in the offset compensation phase equalizes the currents in the two branches, thereby compensating for the voltage difference between the two ends of the bit line. The coordination of the charge sharing and reference voltage amplification phase and the main sensing phase ensures that the bit line potential varies correctly and reaches its full swing, ensuring the SCCSA read amplification function.

[0035] 2. The number of sensitive amplifier components and the circuit area provided by the present invention do not increase much, which ensures a high sensing yield and achieves a significant reduction in offset voltage indicators and an increase in reading speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 This is a circuit diagram of the SCCSA disclosed in Example 1 of the present invention;

[0038] Figure 2 Based on Figure 1 Circuit diagram of the read circuit constructed by SCCSA;

[0039] Figure 3 for Figure 2 Timing operation diagram of the reading circuit;

[0040] Figure 4 Based on Figure 1 Pinout diagram of the sense amplifier chip designed by SCCSA;

[0041] Figure 5 is the offset voltage distribution diagram of SCCSA;

[0042] Figure 6 This is the offset voltage distribution diagram of OCSA;

[0043] Figure 7 This is the distribution diagram of the read time of SCCSA;

[0044] Figure 8 This is the distribution diagram of OCSA's read time. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0046] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0048] Example 1

[0049] First, see Figure 1 , which is a circuit structure diagram of a sense amplifier (ie, SCCSA) based on flip point and current mirror compensation provided in this embodiment 1.

[0050] The SCCSA circuit includes 11 NMOS transistors M1 to M11 and 2 PMOS transistors P1 to P2. In other words, the SCCSA circuit only requires 13 MOS transistors, which reduces the number of components and occupies a small circuit area.

[0051] like Figure 1 As shown, the connection relationship of each component is as follows:

[0052] The source of P1 is connected to the control signal SAP2;

[0053] The source of P2 is connected to the control signal SAP1;

[0054] The source of M1 is connected to the control signal SAN2, the gate is connected to the source of M7, and the drain is connected to the drain of P1;

[0055] The source of M2 is connected to the control signal SAN1, the gate is connected to the source of M8, and the drain is connected to the drain of P2;

[0056] The source of M3 is connected to the drain of M1, the gate is connected to the control signal OC, and the drain is connected to the gate of M1;

[0057] The source of M4 is connected to the drain of M2, the gate is connected to OC, and the drain is connected to the gate of M2;

[0058] The source of M5 is connected to the drain of M1, the gate is connected to the control signal ISO1, and the drain is connected to the gate of P2;

[0059] The source of M6 is connected to the drain of M2, the gate is connected to the control signal ISO2, and the drain is connected to the gate of P1;

[0060] The source of M7 is connected to the gate of M1, the gate is connected to the control signal ISO3, and the drain is connected to the gate of P1;

[0061] The source of M8 is connected to the gate of M2, the gate is connected to the control signal ISO4, and the drain is connected to the gate of P2;

[0062] The source of M9 is connected to BL, the gate is connected to PRE, and the drain is connected to the control signal Vref;

[0063] The source of M10 is connected to BLB, the gate is connected to PRE, and the drain is connected to the control signal Vref;

[0064] The source of M11 is connected to BL, the gate is connected to the control signal PRE, and the drain is connected to BLB.

[0065] It should be noted that P1 and M1 constitute inverter 1, and P2 and M2 constitute inverter 2.

[0066] Secondly, see Figure 2 Based on the above-mentioned SCCSA, a read circuit is constructed, namely, a circuit using the SCCSA. The read circuit includes: the SCCSA, a DRAM storage unit 1, and a DRAM storage unit 2.

[0067] DRAM storage cell 1 is used to store 0 or 1. DRAM storage cell 2 is used to store 0 or 1. SCCSA is used to read DRAM storage cell 1 or DRAM storage cell 2.

[0068] DRAM storage unit 1 and DRAM storage unit 2 may adopt a common 1T1C structure.

[0069] See Figure 2 DRAM storage cell 1 includes: an NMOS transistor NM1 and a capacitor Cc1. NM1's drain is connected to BL, and its gate is connected to word line WL1. Cc1's first end is connected to NM1's source, and its second end is connected to ground VSS. DRAM storage cell 2 includes: an NMOS transistor NM2 and a capacitor Cc2. NM2's drain is connected to BLB, and its gate is connected to word line WL2. Cc2's second end is connected to NM2's source, and its second end is connected to ground VSS.

[0070] It should be noted that WL1 and WL2 cannot be turned on at the same time to prevent damage to the data in the DRAM storage unit.

[0071] The above-mentioned disclosed reading circuit is used to perform data reading operations, and its operating timing includes: a pre-charge stage (PC), an offset cancellation stage (OC1), an offset compensation stage (OC2), a charge sharing and reference voltage amplification stage (CS), and a sensing amplification stage (MS).

[0072] The following is a principle description of each stage:

[0073] 1) In the pre-charge stage:

[0074] PRE, ISO1, ISO2, ISO3, and ISO4 are set to a high level (M5, M6, M7, M8, M9, M10, and M11 are turned on), OC is set to a low level (M3 and M4 are disconnected), SAP1, SAN1, SAP2, and SAN2 are set to VDD / 2 (inverter 1 and inverter 2 do not work, that is, P1, M1, P2, and M2 are disconnected), Vref is set to VDD / 2, and BL and BLB are precharged to VDD / 2 (Vref charges BL through M11, Vref charges BLB through M10, and BL and BLB are short-circuited through M9 to keep them at VDD / 2).

[0075] 2) During the offset elimination phase:

[0076] PRE, ISO1, and ISO2 are set to a low potential (M5, M6, M9, M10, and M11 are disconnected), OC, ISO3, and ISO4 remain high (M3, M4, M7, and M8 are on), SAP1 and SAP2 are set to a high level, and SAN1 and SAN2 are set to a low level (inverter 1 and inverter 2 are both operating, that is, P1, M1, P2, and M2 are on). The input and output of inverter 1 are connected, and the input and output of inverter 2 are connected, so that the voltage across the bit line can stabilize to the inverter's flip point, thereby reducing offset.

[0077] 3) In the offset compensation stage:

[0078] 301. If DRAM storage cell 1 is to be read subsequently (i.e., BL is the read bit line), then PRE, ISO2, and ISO4 are set to a low level (M6, M8, M9, M10, and M11 are disconnected), OC, ISO1, and ISO3 are set to a high level (M3, M4, M5, and M7 are turned on), SAP1 and SAP2 are set to a high level, and SAN1 and SAN2 are set to a low level (inverter 1 and inverter 2 are both working, i.e., P1, M1, P2, and M2 are turned on). The output voltage of inverter 1 formed by P1 and M1 is the gate voltage of P2, and the gate and drain of M2 are connected to form a diode structure, thus forming a current mirror structure in the circuit. In order to ensure that the currents in the left and right branches of the current mirror structure are equal, the voltage on BLB is dynamically adjusted to effectively compensate for the offset voltage;

[0079] 302. If DRAM storage cell 2 is to be read subsequently (i.e., BLB is the read bit line), PRE, ISO1, and ISO3 are set to a low level (M5, M7, M9, M10, and M11 are disconnected), OC, ISO2, and ISO4 are set to a high level (M3, M4, M6, and M8 are on), SAP1 and SAP2 are set to a high level, and SAN1 and SAN2 are set to a low level (inverter 1 and inverter 2 are both operating, i.e., P1, M1, P2, and M2 are on). The output voltage of inverter 2, formed by P2 and M2, is the gate voltage of P1. The gate and drain of N1 are connected to form a diode structure, thus forming a current mirror structure in the circuit. To ensure that the currents in the right and left branches of the current mirror structure are equal, the voltage on BL is dynamically adjusted to effectively compensate for the offset voltage.

[0080] 4) During the charge sharing phase and the reference voltage amplification phase:

[0081] 401. To read DRAM storage cell 1, WL1 is set high (NM1 is on), Cc1 and BL share charge (Cc1 is on with BL through NM1), PRE and OC are set low (M3, M4, M9, M10, and M11 are off), ISO1, ISO2, ISO3, and ISO4 are set high (M5, M6, M7, and M8 are on), SAN2 is set low, and SAP2 is set high (inverter 1 is on, i.e., P1 and M1 are on). SAN1 and SAP1 maintain VDD / 2 (inverter 2 is off, i.e., P2 and M2 are off), and BLB is reverse-boosted relative to the charge sharing polarity, increasing the voltage difference between the two end bit lines.

[0082] 402. To read DRAM storage cell 2, WL2 is set high (NM2 is on), Cc2 and BLB share charge (Cc2 is on with BLB via NM2). PRE and OC are set low (M3, M4, M9, M10, and M11 are off), ISO1, ISO2, ISO3, and ISO4 are set high (M5, M6, M7, and M8 are on), SAN1 is set low, and SAP1 is set high (inverter 2 is on, i.e., P2 and M2 are on). SAN2 and SAP2 maintain VDD / 2 (inverter 1 is off, i.e., P1 and M1 are off), and BL is reverse-boosted relative to the charge sharing polarity, increasing the voltage difference between the two end bit lines.

[0083] 5) In the induction amplification stage:

[0084] In general, in the sensing amplification stage, WL1 and WL2 remain in the same state as 4), PRE remains at a low level (M9, M10, and M11 are disconnected), OC remains at a low level (M3 and M4 are disconnected), ISO1, ISO2, ISO3, and ISO4 remain at a high level (M5, M6, M7, and M8 are turned on), SAN1 and SAN2 are set to a low level, and SAP1 and SAP2 are set to a high level (inverter 1 and inverter 2 are working, that is, P1, M1, P2, and M2 are turned on).

[0085] 501. If DRAM storage cell 1 is to be read and the DRAM storage cell 1 stores 1, then in the sensing and amplification stage, WL1 maintains a high level (NM1 is turned on), and the cross-coupled inverters 1 and 2 increase the voltage difference. Then, based on the reference voltage amplification stage, the BL voltage is quickly pulled to VDD and the BLB voltage is quickly reduced to 0. Then, the BL potential is read to obtain the storage data of DRAM storage cell 1.

[0086] 502. If DRAM storage cell 1 is to be read and the data stored in DRAM storage cell 1 is 0, then in the sensing and amplification stage, WL1 is kept at a high level (NM1 is turned on), and the cross-coupled inverters 1 and 2 increase the voltage difference. Then, based on the reference voltage amplification stage, the BL voltage is quickly reduced to 0 and the BLB voltage is quickly pulled to VDD. Then, the BL potential is read to obtain the storage data of DRAM storage cell 1.

[0087] 503. If DRAM storage unit 2 is to be read, and DRAM storage unit 2 stores 1, then in the sensing and amplification stage, WL2 maintains a high level (NM2 is turned on), and the cross-coupled inverters 1 and 2 increase the voltage difference. Then, based on the reference voltage amplification stage, the BLB voltage is quickly pulled to VDD and the BL voltage is quickly reduced to 0. Then, the storage data of DRAM storage unit 2 is obtained by reading the BLB potential.

[0088] 504. If DRAM storage cell 2 is to be read and DRAM storage cell 2 stores 0, then in the sensing and amplification stage, WL2 maintains a high level (NM2 is turned on), and the cross-coupled inverter 1 and inverter 2 increase the voltage difference. Then, based on the reference voltage amplification stage, the BLB voltage is quickly reduced to 0 and the BLB voltage is quickly pulled to VDD. Then, the storage data of DRAM storage cell 2 is obtained by reading the BLB potential.

[0089] In order to facilitate the understanding of the above stages, the timing change diagram of each signal at each stage is drawn by taking the reading of DRAM storage unit 1 as an example, as shown in the figure below: Figure 3 shown.

[0090] In addition, this embodiment 1 simultaneously discloses a sense amplifier chip, which adopts the circuit layout of the sense amplifier based on the flip point and current mirror compensation disclosed above. The mode of packaging into a chip makes it easier to promote and apply the above circuit.

[0091] like Figure 4 As shown, the sense amplifier chip has 13 pins:

[0092] Among them, pin 1 is used to connect BL; pin 2 is used to connect BLB; pin 3 is used to connect Vref; pin 4 is used to connect PRE; pin 5 is used to connect SAP1; pin 6 is used to connect SAP2; pin 7 is used to connect SAN1; pin 8 is used to connect SAN2; pin 9 is used to connect OC; pin 10 is used for ISO1; pin 11 is used for ISO2; pin 12 is used for ISO3; pin 13 is used for ISO4.

[0093] Example 2

[0094] This embodiment 2 is intended to verify the performance of the DRAM sense amplifier based on the flip point and current mirror compensation proposed in embodiment 1:

[0095] This embodiment 2 introduces a read circuit constructed based on OCSA (referred to as read circuit 2), and performs simulation comparison with the read circuit constructed based on SCCSA proposed in embodiment 1 (referred to as read circuit 1) (the simulation conditions of the two remain the same).

[0096] The OCSA is constructed with 12 MOS transistors (including 3 PMOS transistors and 9 NMOS transistors), while the SCCSA only includes 13 MOS transistors. The SCCSA has only one more component than the OCSA, effectively avoiding an excessive increase in component count and circuit area.

[0097] 1. Perform 500 Monte Carlo simulations at room temperature (27°C) to obtain the offset voltage distribution of the two readout circuits at different process angles. Figure 5 、 Figure 6 .

[0098] in, Figure 5 Shows the normal distribution curve of the offset voltage of the reading circuit 1, Figure 6 The offset voltage normal distribution curve for readout circuit 2 is shown. For both circuits, the standard deviation is used as the offset voltage. It can be seen that the offset voltage of the SCCSA (441μV) is much lower than that of the OCSA (9.305mV).

[0099] 2. Since the circuit is unstable when OCSA reads "0", the read time distribution when SCCSA and OCSA read "1" is investigated. The results are shown in Figure 7 、 Figure 8 .

[0100] Read time is defined as the time from the start of precharge to the time the voltage difference between the two bit lines reaches 80%*VDD. That is, the longer the read time, the slower the read speed.

[0101] in, Figure 7 Shows the normal distribution curve of the read time of the read circuit 1, Figure 8 The normal distribution curve of the read time for read circuit 2 is shown, with the average value of both being used as the read time. It can be seen that the read time of the SCCSA (9.402ns) is shorter than that of the OCSA (10.45ns). In other words, the read speed of the SCCSA is faster than that of the OCSA—this is because the OCSA adds a data latching phase after the compensation phase, resulting in a slower read speed.

[0102] 3. Monte Carlo simulations were performed 500 times at a voltage of 0.9 V and room temperature (27° C.) to investigate the sensing yield of the two readout circuits.

[0103] Simulation results show that the SCCSA accurately reads both "1" and "0," achieving a 100% sensing yield. However, the OCSA frequently makes errors when reading "0," resulting in an overall sensing yield of only 88%. This indicates that the SCCSA improves the sensing yield during circuit operation compared to the OCSA.

[0104] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A sense amplifier based on flip point and current mirror compensation, characterized in that: include: 11 NMOS transistors M1 to M11, 2 PMOS transistors P1 to P2; Among them, the source of P1 is connected to the control signal SAP2; The source of P2 is connected to the control signal SAP1; The source of M1 is connected to the control signal SAN2, and the drain is connected to the drain of P1; The source of M2 is connected to the control signal SAN1, and the drain is connected to the drain of P2; The source of M3 is connected to the drain of M1, the gate is connected to the control signal OC, and the drain is connected to the gate of M1; The source of M4 is connected to the drain of M2, the gate is connected to OC, and the drain is connected to the gate of M2; The source of M5 is connected to the drain of M1, the gate is connected to the control signal ISO1, and the drain is connected to the gate of P2; The source of M6 is connected to the drain of M2, the gate is connected to the control signal ISO2, and the drain is connected to the gate of P1; The source of M7 is connected to the gate of M1, the gate is connected to the control signal ISO3, and the drain is connected to the gate of P1; The source of M8 is connected to the gate of M2, the gate is connected to the control signal ISO4, and the drain is connected to the gate of P2; The source of M9 is connected to BL, the gate is connected to the control signal PRE, and the drain is connected to the control signal Vref; The source of M10 is connected to BLB, the gate is connected to PRE, and the drain is connected to Vref; The source of M11 is connected to BL, the gate is connected to PRE, and the drain is connected to BLB; Among them, P1 and M1 constitute inverter one, and P2 and M2 constitute inverter two.

2. A reading circuit, characterized in that: include: DRAM storage unit 1, which is used to store 0 or 1; DRAM storage unit 2, which is used to store 0 or 1; as well as The sense amplifier based on flip point and current mirror compensation as claimed in claim 1 is used to read DRAM storage cell 1 or DRAM storage cell 2.

3. The reading circuit according to claim 2, wherein: DRAM storage unit 1 includes: 1 NMOS transistor NM1, 1 capacitor Cc1; The drain of NM1 is connected to BL, and the gate is connected to word line WL1; A first end of Cc1 is connected to the source of NM1, and a second end thereof is connected to the ground VSS; DRAM storage unit 2 includes: 1 NMOS transistor NM2, 1 capacitor Cc2; The drain of NM2 is connected to BLB, and the gate is connected to word line WL2; A first end of Cc2 is connected to the source of NM2, and a second end thereof is connected to the ground VSS; Among them, WL1 and WL2 are not turned on at the same time.

4. The reading circuit according to claim 3, wherein: The working sequence of the reading circuit includes: a pre-charging stage, an offset elimination stage, an offset compensation stage, a charge sharing and reference voltage amplification stage, and a sensing amplification stage.

5. The reading circuit according to claim 4, wherein: In the precharge stage, M5, M6, M7, M8, M9, M10, and M11 are turned on, M3 and M4 are turned off, and inverter 1 and inverter 2 do not work.

6. The reading circuit according to claim 5, wherein: In the offset cancellation stage, M5, M6, M9, M10, and M11 are disconnected, M3, M4, M7, and M8 are turned on, and both inverter 1 and inverter 2 are working.

7. The reading circuit according to claim 6, wherein: During the offset compensation stage: To read DRAM storage unit 1, M6, M8, M9, M10, and M11 are disconnected, M3, M4, M5, and M7 are turned on, and inverter 1 and inverter 2 are both working; If DRAM storage unit 2 is to be read, M5, M7, M9, M10, and M11 are disconnected, M3, M4, M5, and M8 are turned on, and inverter 1 and inverter 2 are both working.

8. The reading circuit according to claim 7, wherein: In the charge sharing and reference voltage amplification stage: If you want to read DRAM storage unit 1, then NM1 is turned on, M3, M4, M9, M10, M11 are turned off, M5, M6, M7, M8 are turned on; inverter 1 works, and inverter 2 does not work; If DRAM storage unit 2 is to be read, NM2 is turned on, M3, M4, M9, M10, and M11 are turned off, and M5, M6, M7, and M8 are turned on; inverter 2 works, and inverter 1 does not work.

9. The reading circuit according to claim 7, wherein: In the induction amplification stage: To read DRAM storage unit 1, NM1 is turned on, M3, M4, M9, M10, and M11 are turned off, and M5, M6, M7, and M8 are turned on; inverter 1 and inverter 2 are both working; If DRAM storage unit 2 is to be read, NM2 is turned on, M3, M4, M9, M10, and M11 are turned off, and M5, M6, M7, and M8 are turned on; inverter 1 and inverter 2 are both working.

10. A sensitive amplifier chip, characterized in that: A circuit layout of a sense amplifier based on a flip point and current mirror compensation as claimed in claim 1 is adopted.

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