Low-temperature-drift multi-phase clock generation circuit capable of independently adjusting duty ratio

Abstract

The invention relates to a clock signal generation device, comprising an oscillation module configured to provide a periodic oscillation signal in response to an enable signal; the clock generation module is coupled to the oscillation module and is configured to acquire the oscillation signal and generate a plurality of periodic initial clock signals; and a clock output module coupled to the clock generation module and configured to generate a corresponding clock signal based on the initial clock signal. The invention also provides a corresponding integrated circuit.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit design, and specifically relates to a multi-phase clock generation circuit with low temperature drift and independently adjustable duty cycle. Background Art

[0002] Multiphase clocks are widely used in integrated circuits, for example, to control circuit switching and allocate sampling and integration time for sigma-delta modulators. Traditional multiphase clock generation circuits often use inverter delays. However, inverter delays vary with temperature, affecting accuracy, and they also suffer from a single duty cycle.

[0003] Therefore, there is an urgent need for a multi-phase clock generation circuit with low temperature drift and independently adjustable duty cycle. Summary of the Invention

[0004] In response to the technical problems existing in the prior art, the present application proposes a multi-phase clock generation device capable of adjusting temperature characteristics.

[0005] On one hand, the present application proposes a clock signal generating device, comprising: an oscillation module, configured to provide a periodic oscillation signal in response to an enable signal, wherein the oscillation module comprises: a resistance branch configured to receive a signal related to the enable signal, comprising a first variable resistor, which has a negative temperature coefficient; a second variable resistor, which has a positive temperature coefficient and is connected in series with the first variable resistor; a first variable capacitor, which is coupled to the first and second variable resistors, and under the influence of the enable signal, the first variable capacitor provides the oscillation signal; a clock generation module, coupled to the oscillation module, configured to obtain the oscillation signal and generate a plurality of periodic initial clock signals, wherein the clock generation module comprises: a first comparison module, which compares the oscillation signal based on the oscillation signal. signal and a first reference voltage to generate a first initial clock signal, wherein the first reference voltage has a first adjustable voltage range; a second comparison module, which generates a second initial clock signal based on the inverse signal of the oscillation signal and a second reference voltage, wherein the second reference voltage has a second adjustable voltage range; and an RS latch module, which receives and periodically latches the first and second initial clock signals to generate a third initial clock signal and a fourth initial clock signal that are inverse to each other; and a clock output module, coupled to the clock generation module, configured to generate a corresponding clock signal based on the initial clock signal; wherein the first variable capacitor is coupled to the plate at the output end of the resistance branch to output the oscillation signal under the control of a signal related to the enable signal.

[0006] In one embodiment, the oscillation module further includes: a differential unit, which includes a second variable capacitor connected in parallel with the first and second variable resistors, and is used to adjust the swing amplitude of the oscillation signal.

[0007] In one embodiment, the resistor is implemented by a resistor array, which includes a plurality of resistor adjustment units, wherein the resistance adjustment unit includes a first resistor branch, which includes a first resistor; a second resistor branch, which includes a second resistor and a branch switch, wherein the second resistor branch is connected in parallel with the first resistor branch.

[0008] In one embodiment, the first variable capacitor and / or the second variable capacitor include capacitance branches connected in parallel, wherein the capacitance branches include capacitors and capacitance transmission gates, and the capacitors are coupled to a low potential via the capacitance transmission gates.

[0009] In one embodiment, the first comparison module includes: a first switch configured to receive the first reference voltage, and a control end of the first switch is controlled by the third and fourth initial clock signals; a first comparator, which includes: a first input end configured to receive the oscillation signal; and a second input end coupled to the first switch and configured to obtain the first reference voltage through the first switch.

[0010] In one embodiment, the second comparison module includes: a second switch configured to receive the second reference voltage, and the control end of the second switch is controlled by the third and fourth initial clock signals; a second comparator, which includes: a third input end configured to receive an inverse signal of the oscillation signal; and a fourth input end coupled to the second switch and configured to obtain the second reference voltage through the second switch.

[0011] In one embodiment, the clock signal generating device includes: a first clock output unit for generating a first phase-non-overlapping clock based on the first initial clock signal; and a second clock output unit for generating a second phase-non-overlapping clock based on the second initial clock signal.

[0012] In one embodiment, the clock signal generating device further includes: a third clock output unit to generate a third phase-non-overlapping clock signal based on the third and fourth initial clock signals, wherein the third clock output unit is used to improve the driving capability of the third phase-non-overlapping clock signal.

[0013] The present application also discloses an integrated circuit, which includes any of the clock signal generating devices described above.

[0014] The technical solution of this application can generate three clocks with different phases, and the duty cycle of the clocks can be adjusted independently. At the same time, the three clock phases can be used to generate three pairs of non-overlapping clocks. In addition, the technical solution of this application has a zero temperature coefficient frequency, good temperature stability, and adjustable frequency and temperature characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1 1 is a diagram showing the architecture of a clock signal generating device according to an embodiment of the present application; Figure 2 is a schematic diagram of a clock generation circuit according to an embodiment of the present application; Figure 3 Schematic diagram of the structure of a resistor array according to an embodiment of the present application; Figure 4 Schematic diagram of the structure of a capacitor array according to an embodiment of the present application; Figure 5 Schematic diagram of the output waveform of the clock generation unit according to an embodiment of the present application; Figure 6 is a waveform diagram of a multi-phase clock according to an embodiment of the present application. DETAILED DESCRIPTION

[0016] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0017] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0018] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit communication between unconnected elements. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in communication between the two elements or at least the number of outputs provided, and is not intended to limit communication between the two elements to only the signals shown in the figure.

[0019] Figure 1 2 is a diagram illustrating the architecture of a clock signal generating device according to an embodiment of the present application.

[0020] like Figure 1 As shown, the clock signal generation apparatus includes an oscillation module 101, a clock generation module 102, and a clock output module 103. In response to an enable signal PD, oscillation module 101 provides a periodic oscillation signal clk0. Clock generation module 102, coupled to oscillation module 101, receives oscillation signal clk0 and generates multiple periodic initial clock signals (Q, Q', CK0, and CK1) based on the oscillation signal. Clock output module 103, coupled to clock generation module 102, generates corresponding clock signals based on the initial clock signals.

[0021] In one embodiment, the oscillation module 101 includes an adjustable resistor and an adjustable capacitor, wherein the adjustable resistor may include resistors having different polarity temperature characteristics to reduce the impact of temperature on the oscillation module 101. The adjustable capacitor and the adjustable resistor may form an RC oscillator. Therefore, under the influence of the enable signal PD, the capacitor can provide an oscillation signal.

[0022] Figure 2 FIG. 4 is a schematic diagram of a clock generation circuit according to an embodiment of the present application.

[0023] like Figure 2 As shown, the clock generation circuit includes an oscillation module 101 , a clock generation module 102 , a first clock output unit 103 , a second clock output unit 104 , a third clock output unit 105 and a latch feedback unit 106 .

[0024] The oscillation module 101 is used to generate a periodic oscillation signal clk0. The module includes resistors with positive and negative temperature coefficients, which can obtain better matching and temperature characteristics. Specifically, an RC oscillator is formed by series-connected resistors R_pos, R_neg and an adjustable capacitor C1, wherein the two resistors have positive temperature characteristics and negative temperature characteristics, respectively. Therefore, the response characteristics of the oscillator circuit to temperature can be adjusted by resistors R_pos and R_neg. The adjustable capacitor C1 is used to generate a periodic oscillation clock waveform, and the adjustable capacitor C7, R_pos, and R_neg constitute an RC differential unit, thereby enhancing the charge and discharge voltage amplitude of the circuit, increasing the output swing of the oscillator 101, and obtaining better driving capability. In one embodiment, capacitor C7 can also be used to shape the output waveform of the oscillator.

[0025] In this embodiment, the enable signal PD controls the on / off switching of the entire RC oscillator. Initially, the enable signal PD is high. At this point, the output signal en of inverter INV1011 is low. Consequently, transistor M1 is turned on, its drain voltage is pulled high, and the output of the positive plate of capacitor C1 is a "1," meaning the plate voltage is high. The capacitor voltage is fed back to buffer BUF1014 via inverter INV1012 and OR gate OR1015. The control terminal of buffer BUF1014 is high, and the entire circuit is inactive.

[0026] Discharge process: When the enable signal PD voltage is pulled low, the output signal en of the inverter INV1011 is high, the transistor M1 is turned off, and the output of BUF1014 instantly flips to a low level. Capacitor C1 discharges through resistors R_neg and R_pos. When capacitor C1 is fully discharged, the positive plate output of capacitor C1 is "0", that is, the voltage of this plate is low, and the initial clock signal clk0 is at a low level. Charging process: When the initial clock signal clk0 is at a low level, the output signal of the inverter INV1012 is high. At this time, the buffer BUF1014 charges the capacitor C1 through resistors R_pos and R_neg until the initial clock signal clk0 flips to a high level, thereby triggering the aforementioned discharge process.

[0027] Based on the above, when the enable signal PD triggers the oscillator to work, the oscillator 101 will generate a periodic oscillation signal clk0. Those skilled in the art will appreciate that the inverter INV1011 can also be composed of multiple inverters connected in series to adjust the delay caused by the inverter INV1011. Figure 5 As shown in FIG, since clk0 is an oscillation signal directly output by the capacitor and is not shaped by the inverter, clk0 is a non-square wave.

[0028] In one embodiment, the adjustable resistors R_neg and R_pos can be Figure 3 This is achieved with the resistor array shown.

[0029] like Figure 3 As shown, the exemplary resistor array includes eight resistors R1-R8, wherein resistors R1-R4 are connected in series and in parallel with resistors R5-R8, respectively. Branch switches S1-S4 are also connected in series on the branches of resistors R5-R8 to determine whether resistors R5-R8 are connected to the circuit. In other words, resistors R1, R5, and switch S1 constitute a resistance adjustment unit, and resistor R1 belongs to the first resistance branch, while resistor R5 and switch S1 belong to the second resistance branch. The equivalent resistance value range of each resistor unit is the parallel value of R1 and R5 or R1.

[0030] In actual applications, if the size of the resistor is to be adjusted, it can be selectively determined whether to close any one or more of the switches S1 to S4 as needed, thereby incorporating the corresponding resistor into the corresponding branch to reduce the resistance value of R_neg or R_pos, thereby adjusting the resistance value of R_neg and R_pos. It is understandable that the size of the resistors R1-R8 can be adjusted according to the actual application. For example, the resistance values ​​of the resistors R1-R4 can be equal or proportional, and can be N times that of the resistors R5-R8, where N is greater than or equal to 1. In one embodiment, the proportional relationship of the resistors R1-R4 is the same as the proportional relationship of the resistors R5-R8.

[0031] The control signals for switches S1-S4 are generated via registers, and the control strategy can be adjusted based on the actual application, so I won't elaborate on this here. The value of the R_neg (R_pos) resistor determines the oscillation frequency adjustment step size and frequency accuracy. Precisely controlling R_pos allows the target frequency to be found, while controlling the R_neg resistor allows the temperature coefficient of the frequency to be compensated.

[0032] For the adjustable capacitors C1 and C7 in the oscillator 101, Figure 4 This is achieved using the capacitor array shown.

[0033] like Figure 4As shown, the capacitor array includes capacitor branches connected in parallel, wherein each capacitor branch includes a capacitor and a capacitor transmission gate, and the capacitor is coupled to a low potential via the capacitor transmission gate. Specifically, the capacitor branch includes capacitors (Ca, Cb, and Cc), and each capacitor is coupled to the ground GND via a transmission gate (TGa, TGb, and TGc). Therefore, by controlling the on and off of each transmission gate, the size of the variable capacitors C1 and C7 can be adjusted. The configuration selection of capacitors C1 and C7 must be the same, and adjusting the number of capacitors C1 and C7 can adjust the size of the oscillation signal frequency.

[0034] Please continue to refer to Figure 2 The clock generation circuit 102 is configured to generate three clock signals with different phases and the same frequency.

[0035] Comparator COMP1 generates the first-phase clock signal CK0 by comparing the initial clock signal clk0 with the reference signal vbp1. Reference signal vbp1 is generated by an external reference voltage source, and its magnitude is unaffected by power supply voltage, process, and temperature. In this embodiment, the duty cycle of the clock signal is adjusted by setting the voltage of reference signal vbp1. For example, when the voltage of signal vbp1 is low, a narrow phase of clk0 is captured. vbp1 can be a voltage between the maximum and minimum voltages of clk0, thereby determining the magnitude of vbp1 based on the required duty cycle.

[0036] Comparator COMP2 generates a second-phase clock signal by comparing the inverted signal clk0_inv of the initial clock signal clk0 with a reference signal vbp2. vbp2 is generated by an external reference voltage source, and its voltage level is unaffected by power supply voltage, process technology, and temperature. Similar to reference signal vbp1, the voltage of vbp2 is between the maximum and minimum voltages of clk0_inv, and its value can be selected or adjusted based on duty cycle requirements. As will be appreciated, vbp1 and vbp2 each have their own adjustable range.

[0037] Figure 5 The output signals of comparators COMP1 and COMP2 are shown in FIG. Figure 5 It can be seen that vbp1 and vbp2 intercept different phases of clk0 and clk0_inv respectively, so that the outputs COMP1 and COMP2 of the comparator flip at different times, and two output waveforms CK0 and CK1 with different phases are obtained.

[0038] Please continue reading Figure 2. After the clock signals CK0 and CK1 generated by comparator COMP1 and comparator COMP2 are introduced into the SR trigger 106, and are fed back to the control terminals of switches S1 and S2 at the negative input terminals of the comparator respectively, signals Q and Q' with non-overlapping phases are obtained at the output terminal of the SR latch. Due to the effects of the two feedback loops Q to S2 and Q' to S1, the signals CK0, CK1, and Q have different phases but the same signal frequency. Since these three signals are all derived from clk0, they have the same temperature characteristics as clk0. In other words, the temperature characteristics of these signals can be adjusted by adjusting the resistors R_neg and R_pos.

[0039] The first clock output unit 103 receives the first-phase clock CK0 and delays it through adjustable capacitors C3 and C4 to generate phase-non-overlapping clocks CLK3 and CLK4. Similarly, the second clock output unit 104 receives the second-phase clock CK1 and delays it through adjustable capacitors C3 and C4 to generate phase-non-overlapping clocks CLK5 and CLK6.

[0040] Please also see Figure 2 and Figure 5 , the first clock output unit 103 is taken as an example for explanation.

[0041] The first phase clock CK0 charges the adjustable capacitor C3 through inverters INV1031 and 1032, and the voltage on the top plate of C3 and CK0 are output through AND gate AND1034 to form clock signal CLK3. Therefore, when the voltage on the top plate of adjustable capacitor C3 is at a low potential, clock signal CLK3 is 0, and vice versa. Similarly, the inverted signal of clock CK0 reaches AND gate AND1035, from which it can be seen that clock signals CLK3 and CLK4 are in opposite directions. For clock signal CLK3, the interval between two adjacent rising edges is the clock interval T CLK For the clock signal CLK4, the interval between two adjacent falling edges is the clock interval T CLK The values ​​of C3 and C4 can be adjusted independently to achieve different duty cycles. When the value of capacitor C3 decreases, its charge and discharge speeds increase, thus increasing the duty cycles of CLK3 and CLK4. When the value of capacitor C4 decreases, the duty cycle of CLK4 increases, but has little effect on the duty cycle of CLK3.

[0042] Similarly, by adjusting the values ​​of the capacitors C5 and C6 , the duty cycles of the clock signals CLK5 and CLK6 can be adjusted, which will not be described in detail here.

[0043] Figure 6The waveforms of CLK1 to CLK6 are shown. The phases of CLK1 and CLK2, CLK3 and CLK4, and CLK5 and CLK6 do not overlap. The frequencies of CLK1 to CLK6 are the same, but the duty cycles are different. It is understandable that the above clock duty cycles can be adjusted according to actual needs.

[0044] Through the above technical solution, a clock signal with low temperature characteristics can be achieved, and the duty cycle of the clock signal can be adjusted according to application requirements, which greatly improves the applicability of this technical solution.

[0045] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A clock signal generating device, characterized in that: include: an oscillation module configured to provide a periodic oscillation signal in response to an enable signal, wherein the oscillation module comprises: a resistance branch configured to receive a signal related to the enable signal, the resistance branch comprising a first variable resistor having a negative temperature coefficient; and a second variable resistor having a positive temperature coefficient and connected in series with the first variable resistor; a first variable capacitor coupled between the resistance branch and ground, configured to receive an output of the resistance branch; A clock generation module, coupled to the oscillation module, is configured to obtain the oscillation signal and generate a plurality of periodic initial clock signals, wherein the clock generation module includes: a first comparison module, configured to generate a first initial clock signal based on the oscillation signal and a first reference voltage, wherein the first reference voltage has a first adjustable voltage range; a second comparison module, which generates a second initial clock signal based on an inverted signal of the oscillation signal and a second reference voltage, wherein the second reference voltage has a second adjustable voltage range; and an RS latch module, which receives and periodically latches the first and second initial clock signals to generate a third initial clock signal and a fourth initial clock signal that are inverse to each other; and a clock output module, coupled to the clock generation module, configured to generate a corresponding clock signal based on the initial clock signal; The plate of the first variable capacitor coupled to the output end of the resistance branch outputs the oscillation signal under the control of a signal related to the enable signal.

2. The clock signal generating device according to claim 1, wherein: The oscillation module further includes: A second variable capacitor is connected in parallel with the first and second variable resistors and is used to adjust the amplitude of the oscillation signal.

3. The clock signal generating device according to claim 2, wherein: The resistor is implemented by a resistor array, and the resistor array includes a plurality of resistor adjustment units, wherein the resistor adjustment unit includes: A first resistance branch comprising a first resistor; The second resistance branch includes a second resistor and a branch switch, wherein the second resistance branch is connected in parallel with the first resistance branch.

4. The clock signal generating device according to claim 2, wherein: The first variable capacitor and / or the second variable capacitor include capacitance branches connected in parallel, wherein the capacitance branches include capacitors and capacitance transmission gates, and the capacitors are coupled to a low potential via the capacitance transmission gates.

5. The clock signal generating device according to claim 1, wherein: The first comparison module includes: a first switch configured to receive the first reference voltage, wherein a control terminal of the first switch is controlled by the third and fourth initial clock signals; A first comparator comprising: a first input terminal configured to receive the oscillation signal; The second input terminal is coupled to the first switch and configured to obtain the first reference voltage through the first switch.

6. The clock signal generating device according to claim 5, wherein: The second comparison module includes: a second switch configured to receive the second reference voltage, wherein a control terminal of the second switch is controlled by the third and fourth initial clock signals; A second comparator comprising: a third input terminal configured to receive a reverse signal of the oscillation signal; The fourth input terminal is coupled to the second switch and configured to obtain the second reference voltage through the second switch.

7. The clock signal generating device according to claim 1, wherein: Also includes: a first clock output unit for generating a first phase non-overlapping clock based on the first initial clock signal; A second clock output unit is configured to generate a second phase non-overlapping clock based on the second initial clock signal.

8. The clock signal generating device according to claim 1, wherein: Also includes: A third clock output unit is configured to generate a third phase-non-overlapping clock signal based on the third and fourth initial clock signals, wherein the third clock output unit is configured to improve a driving capability of the third phase-non-overlapping clock signal.

9. An integrated circuit, characterized in that: The device comprises the clock signal generating device according to any one of claims 1 to 8.

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