Randomly modulated clock spread spectrum device and switching power supply chip

Abstract

The invention discloses a random modulation clock spread spectrum device and a power chip, and the device comprises a frequency divider circuit which is used for receiving a first pulse signal outputted by an oscillator circuit in a t-1 modulation period; the M sequence generation circuit is used for generating a random digital sequence of a t-1 modulation period according to the first pulse signal; wherein the period of the random number sequence is 2n, and n is an integer greater than or equal to 4; the current bias circuit is used for generating a first bias current of a t-1 modulation period according to the random number sequence; and the oscillator circuit is used for generating a clock spread spectrum signal of a t modulation period according to the first bias current, and t is an integer greater than or equal to 2. The circuit can be widely applied to the technical field of electronic circuits.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a randomly modulated clock spread spectrum device and a switching power supply chip. Background Art

[0002] Currently, a common method to reduce EMI in switching power supply chips is to use periodic clock spread spectrum technology. This technology uses a periodic waveform as a modulation waveform to modulate the clock generation circuit, so that the fixed-frequency clock jitters within a certain range. The performance of the clock signal in the frequency domain changes from discrete values ​​and concentrated energy to continuous values ​​and average energy, thereby achieving the goal of reducing EMI related to the switching frequency in the circuit.

[0003] However, while clock spread spectrum technology, which uses a periodic waveform as the modulation waveform, can achieve the goal of reducing EMI related to switching frequencies in circuits, it also generates certain audible frequencies that can be heard by the human ear, significantly limiting the product's application scenarios. Therefore, technical issues still need to be addressed in related technologies. Summary of the Invention

[0004] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0005] To this end, one purpose of an embodiment of the present application is to provide a randomly modulated clock spread spectrum device and a switching power supply chip, which can reduce the generation of audible frequencies that can be heard by the human ear and improve the practicality of related products.

[0006] In order to achieve the above technical objectives, the technical solution adopted by the embodiment of the present application includes: a randomly modulated clock spread spectrum device, including: a frequency divider circuit for receiving a first pulse signal output by an oscillator circuit in a t-1 modulation period; an M sequence generating circuit for generating a random digital sequence of a t-1 modulation period according to the first pulse signal; wherein the random digital sequence is a number of periods of 2 n A random number sequence, n is an integer greater than or equal to 4; a current bias circuit, used to generate a first bias current of a t-1 modulation period according to the random number sequence; an oscillator circuit, used to generate a clock spread spectrum signal of a t modulation period according to the first bias current.

[0007] In addition, the randomly modulated clock spread spectrum device according to the above embodiment of the present invention may also have the following additional technical features:

[0008] Furthermore, in an embodiment of the present application, the M sequence generating circuit includes a sequence generating network and a feedback network;

[0009] The feedback network includes a logic processing module and nT D flip-flops;

[0010] The sequence generation network includes T D flip-flops; the sequence generation network is used to generate a random digital inverse sequence of a t-2 modulation period; the random digital inverse sequence is a digital sequence obtained by performing a logical NOT operation on the output signal of each D flip-flop in the T D flip-flops of the t-2 modulation period;

[0011] The nT D flip-flops are used to generate a first feedback signal set of a t-1 modulation period according to a pulse signal of a t-2 modulation period;

[0012] The logic processing module is configured to perform logic conversion processing on the first feedback signal set and the random digital reverse sequence to obtain a second feedback signal with a t-1 modulation period that is output to the sequence generation network;

[0013] The sequence generation network is further used to generate the random digital sequence based on the first pulse signal and the second feedback signal; wherein the random digital sequence is a digital sequence composed of the output signal of each D flip-flop in the T D flip-flops.

[0014] Furthermore, in an embodiment of the present application, the current bias circuit includes a decoder and a current converter;

[0015] The decoder is used to convert the random digital sequence into a target driving signal with a t-1 modulation period;

[0016] The current converter is used to convert the target driving signal into a first bias current of a t-1 modulation period.

[0017] Furthermore, in an embodiment of the present application, the current converter includes:

[0018] Current generation module, 2 T a resistance module and a resistance selection module; the current generating module is connected to the resistance selection module; the resistance selection module is used to select the current from the two according to the target drive signal T Any one of the resistance modules is determined to form a closed loop with the current generating module to generate the first bias current.

[0019] Furthermore, in the embodiment of the present application, the resistance values ​​of any two resistance modules among the T resistance modules are different.

[0020] Furthermore, in the embodiment of the present application, the decoder is used to convert T signals into 2 T bit binary number and output the 2 T The target drive signal corresponding to the binary number of the bit.

[0021] Furthermore, in an embodiment of the present application, the frequency divider circuit includes Y two-frequency dividers; any two adjacent two-frequency dividers among the Y two-frequency dividers are connected in series; wherein Y is a positive integer greater than or equal to 2.

[0022] Furthermore, in an embodiment of the present application, the oscillator circuit includes two current mirror modules, a gating module, an energy storage module, and an inverter module connected in parallel with each other;

[0023] The current mirror module is used to receive the first bias current and generate a charging current with a t modulation period;

[0024] The gating module is used to gating any one of the current mirror modules in the t modulation period and charging the energy storage module through the charging current;

[0025] The inverter module is used to generate a control signal according to the voltage of the energy storage module, so that the gating module enables another current mirror module in the t modulation period, charges the energy storage module through the charging current, and generates a clock spread spectrum signal of the t modulation period.

[0026] The feedback network includes a logic processing module and four D flip-flops; the sequence generation network includes four D flip-flops; the second feedback signal satisfies the following formula:

[0027]

[0028] Wherein, F is the second feedback signal, B1', B2', B3', B4' are the outputs of the Q' end of each D flip-flop in the random number inverse sequence, B5', B6', B7', B8' are the outputs of the Q' end of each D flip-flop in the first feedback signal set, and B5, B6, B8 are the outputs of the Q end of each D flip-flop in the first feedback signal set; B1'B2'B3'B4'B5'B6'B7'B8' in the formula represents an AND operation between B1', B2', B3', B4'B5', B6', B7', B8'; the symbol ⊕ represents an exclusive OR operation, and the symbol + represents an OR operation.

[0029] In addition, the present application also provides a switching power supply chip, comprising a randomly modulated clock spread spectrum device as described in any of the above items.

[0030] The advantages and benefits of this application will be partially given in the following description, and partially become apparent from the following description, or learned through practice of this application:

[0031] The present invention can generate a random digital sequence with a t-1 modulation period, each of which has a period of 2n, through an M-sequence generation circuit. This random digital sequence is then used in subsequent clock spread spectrum modulation, thereby reducing the risk of the circuit generating audible frequencies. Because the random digital sequence generated by the M-sequence generation circuit has pseudo-random characteristics, including balance and run-length characteristics, the period of the modulated signal is not fixed, thereby reducing the possibility of audible frequencies being generated by a randomly modulated clock spread spectrum device and improving the practicality of the device product. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A waveform diagram of the EMI problem of a switching power supply in the prior art;

[0033] Figure 2 This is a time domain diagram of the periodic modulation clock spread spectrum technology in the prior art;

[0034] Figure 3 Schematic diagram of a module of a randomly modulated clock spread spectrum device in a specific embodiment of the present invention;

[0035] Figure 4 Schematic diagram of the circuit structure of a randomly modulated clock spread spectrum device in a specific embodiment of the present invention;

[0036] Figure 5 Schematic diagram of a module of a randomly modulated clock spread spectrum device in another specific embodiment of the present invention. DETAILED DESCRIPTION

[0037] The embodiments of the present invention are described in detail below with reference to the accompanying drawings to illustrate the principles and processes of the randomly modulated clock spread spectrum device and the switching power supply chip in the embodiments of the present invention.

[0038] The following are necessary explanations of the nouns that appear in this application:

[0039] Currently, a common method to reduce EMI in switching power supply chips is to use periodic clock spread spectrum technology. This technology uses a periodic waveform as a modulation waveform to modulate the clock generation circuit, so that the fixed-frequency clock jitters within a certain range. The clock signal's performance in the frequency domain changes from discrete values ​​and concentrated energy to continuous values ​​and average energy, thereby reducing EMI problems related to switching frequency in the circuit.

[0040] Reference Figure 1 as well as Figure 2 , Figure 1 It is the spectrum diagram of EMI energy of switching power supply. Figure 1In the figure, the dashed line shows the noise distribution curve for a constant-frequency clock, while the solid line shows the noise distribution curve for a clock modulated using spread spectrum technology. The unmodulated clock's noise spectrum has a narrow energy distribution, concentrated energy, and an energy peak at fclk (the clock frequency). However, the frequency of a clock modulated using spread spectrum technology fluctuates, resulting in a wider noise spectrum and a more even energy distribution, with the energy peak decreasing from A to Ae. Figure 2 This is the timing diagram of the periodic modulated clock spread spectrum technology. The principle is to use a constant-period modulation waveform to modulate the clock generation circuit, so that the clock frequency changes periodically with the modulation waveform, and the performance in the frequency domain changes from discrete values ​​and concentrated energy to continuous values ​​and average energy, thereby achieving the goal of improving and optimizing the EMI problem of the switching power supply.

[0041] However, clock spread spectrum technology that uses a periodic waveform as the modulation waveform has the disadvantage of generating audible frequencies. Specifically, to ensure a small clock frequency jitter range while also requiring a significant reduction in EMI, a lower modulation frequency is required. When the modulation frequency drops below 20kHz, a sound audible to the human ear is generated, which greatly reduces the product's application scenarios. For example, a triangular modulation wave generating circuit suitable for a fixed-frequency Buck spread spectrum mode is disclosed in publication number CN114629344B: This patent uses a periodic wave of a triangular waveform to modulate the clock generation circuit. The patent method mentions that the modulation frequency needs to be around 10kHz, but this frequency is within the frequency range audible to the human ear, which greatly reduces the product's application scenarios. Therefore, there are still problems in the relevant technology that need to be solved.

[0042] In view of the above-mentioned defects of the prior art, Figure 3 , Figure 3 This is a schematic diagram of the structure of a randomly modulated clock spread spectrum device provided in an embodiment of the present application. Figure 3 In the embodiment, the randomly modulated clock spread spectrum device may include a frequency divider circuit 1, an M-sequence generating circuit 2, a current bias circuit 3 and an oscillator circuit 4. The frequency divider circuit 1 may be used to receive the first pulse signal output by the oscillator circuit 4 of the t-1 modulation period. Specifically, in the current modulation period, the frequency divider circuit 1 may receive the pulse signal of the previous period of the current modulation period. The M-sequence generating circuit 2 may be used to generate a random digital sequence of the t-1 modulation period based on the first pulse signal. Specifically, the M-sequence generating circuit 2 may generate a random digital sequence of the previous modulation period based on the first pulse signal of the previous modulation period. The random digital sequence has a period of 2 n , n can be an integer greater than or equal to 4, and the random number sequence has a period of 2 nThis means that the all-zero state is also the output state of the random digital sequence. The current bias circuit 3 can be used to generate a first bias current for the t-1 modulation cycle based on the random digital sequence. Specifically, the current bias circuit 3 can generate the first bias current for the previous modulation cycle based on the random digital sequence of the previous cycle. The oscillator circuit 4 can be used to generate a clock spread spectrum signal for the t modulation cycle based on the first bias current. Specifically, the oscillator circuit 4 can generate a clock spread spectrum signal for the current modulation cycle based on the first bias current of the previous cycle. The t modulation cycle and the t-1 modulation cycle can be two adjacent modulation cycles.

[0043] Furthermore, the M-sequence generation circuit includes a sequence generation network and a feedback network. The feedback network includes a logic processing module and nT D-type flip-flops. The sequence generation network includes T D-type flip-flops. The sequence generation network is used to generate a random digital inverse sequence of a t-2 modulation period. The random digital inverse sequence is a digital sequence obtained by performing a logical negation operation on the output signal of each of the T D-type flip-flops of the t-2 modulation period. The nT D-type flip-flops can generate a first feedback signal set of a t-1 modulation period based on the pulse signal of the t-2 modulation period. The logic processing module can perform a logical conversion process on the first feedback signal set and the random digital inverse sequence to obtain a second feedback signal output to the sequence generation network of the t-1 modulation period. The sequence generation network can generate a random digital sequence based on the first pulse signal and the second feedback signal. The random digital sequence is a digital sequence composed of the output signal of each of the T D-type flip-flops.

[0044] Specifically, refer to Figure 4 ,exist Figure 4 In the example, n is 8, T is 4, and the feedback network can include Figure 4 The sequence generation network includes four flip-flops numbered B5-B8, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a NAND gate NAND1, a first OR gate OR1, a first XOR gate XOR1, and a second XOR gate XOR2. The sequence generation network may include four flip-flops numbered B1-B4. Figure 4In the example, the D-terminal of D-type flip-flop B1 is connected to the output of the first OR gate OR1 in the feedback network. The D-terminals of flip-flops B2-B8 are all connected to the Q-terminal of the previous D-type flip-flop, forming a cascaded structure. The four Q-terminal outputs of flip-flops B1-B4, the three Q-terminal outputs of B5, B6, and B8, and the four Q'-terminal outputs of B5'-B8', totaling 11 outputs, serve as input signals for the logic operations of the feedback network. The clock signals for the eight D-type flip-flops B1-B8 all originate from the signal output of the frequency divider circuit. Specifically, when performing signal modulation in a modulation period of t, flip-flops B1-B4 in the sequence generation network can generate the inverse random digital sequence consisting of B1'-B4' for a modulation period of t-2. The four D-type flip-flops B5-B8 can generate the first feedback signal set for a modulation period of t-1 based on the pulse signal from the frequency divider during the modulation period of t-2. The first feedback signal set includes the three Q-terminal outputs of B5, B6, and B8, and the four Q'-terminal outputs of B5'-B8'. The logic processing module can perform logic conversion processing on the three Q-terminal outputs of B5, B6, and B8, the four Q'-terminal outputs of B5'-B8', and the random digital reverse sequence consisting of B1'-B4' during the t-1 modulation cycle to obtain the second feedback signal F output to the sequence generation network during the t-1 modulation cycle. The sequence generation network can generate the Q-terminal outputs of the four D-type flip-flops B1-B4 during the t-1 modulation cycle based on the first pulse signal of the t modulation cycle output by the frequency divider and the second feedback signal F of the t-1 modulation cycle.

[0045] Random number sequence generation logic: The OSC clock passes through a frequency divider to generate a clock signal CLK_di v. This clock signal is connected to the CLK pins of all D flip-flops in the M-sequence generation circuit module. When the CLK rising edge arrives, the D flip-flop data in the M-sequence generation circuit is shifted right once. The input of the leftmost D flip-flop, i.e., the first D flip-flop, is the output of the logic circuit. The input of the logic circuit is the Q terminal of some D flip-flops (random number inverse sequence). The output is 1-bit data, which is connected to the first D flip-flop.

[0046] The overall action can be summarized as follows: several D flip-flops shift data from left to right all the time, and the feedback network combines the data of these D flip-flops to produce a result, and feeds the data into the first D flip-flop, thereby realizing a pseudo-random sequence when there are multiple D flip-flops.

[0047] Furthermore, the current bias circuit includes a decoder and a current converter; the decoder can convert the random digital sequence into a target drive signal of a t-1 modulation period; and the current converter can convert the target drive signal into a first bias current of a t-1 modulation period.

[0048] Specifically, refer to Figure 4The input of the decoder is the Q output of the four D flip-flops B1-B4, and the output is 2 4 16-bit digital signal, that is, a 16-bit digital signal. Specifically, when the Q terminals of the four D flip-flops B1-B4 respectively output the four signals 1001 (binary representation of the decimal number 9), the output of the decoder is 0000000010000000, that is, the 9th port of the decoder is a high-level output. Similarly, when the Q terminals of the four D flip-flops B1-B4 respectively output the four signals 0111 (binary representation of the decimal number 7), the output of the decoder is 0000001000000000, that is, the 7th port of the decoder is a high-level output. The current converter can convert the output of the decoder into a current in the circuit loop and enable the current to be transmitted to the oscillator circuit. Specifically, each output terminal of the decoder can be connected to a resistor selection module. The resistor selection module can include a plurality of NMOS transistors with the same number of output terminals as the decoder. Each output terminal of the decoder can be connected to the gate of an NMOS tube, the source of each NMOS tube can be grounded, and the drain of each NMOS tube can be connected to a current generating module. Figure 3 In the example, the current generating module can be composed of an operational amplifier OP1, two field effect transistors connected in series, and a resistor Rb. Between each NMOS tube and the current generating module, there are also resistor modules with the same number as the output terminals of the decoder. The number of resistors in each resistor module can be different or the same, and the resistance value of each resistor module can be different. Figure 3 In the decoder, the resistor module corresponding to the first output terminal is R0, the resistor module corresponding to the second output terminal is R0+R1, the resistor module corresponding to the third output terminal is R0+R1+R2, and so on. The resistor module corresponding to the Cth output terminal is R0+R1+R2+....+RC, where 0≤C≤15.

[0049] Furthermore, the frequency divider circuit includes Y frequency dividers, any two adjacent frequency dividers among the Y frequency dividers are connected in series, and Y is a positive integer greater than or equal to 2.

[0050] Specifically, in Figure 4 In , there are 8 binary dividers, namely A1-A8. Among any two adjacent binary dividers between A1-A8, the output end of the binary divider of the previous level is the input end of the binary divider of the current level. Figure 4 In the embodiment, the output end of the frequency divider A1 is the clock end of the frequency divider A2, and the output end of the last frequency divider A8 serves as the output end of the frequency divider circuit and outputs the first pulse signal of the M sequence generating circuit.

[0051] It is understandable that the number of binary frequency dividers in the frequency divider circuit can be designed according to user needs, and the specific number is not limited here.

[0052] Furthermore, the oscillator circuit may include two current mirror modules connected in parallel, a gating module, an energy storage module, and an inverter module; the current mirror module may receive a first bias current and generate a charging current with a modulation period of t. The gating module may select any current mirror module during the modulation period of t and charge the energy storage module with the charging current. The inverter module may generate a control signal based on the voltage of the energy storage module to cause the gating module to select the other current mirror module during the modulation period of t, charge the energy storage module with the charging current, and generate a clock spread spectrum signal with a modulation period of t.

[0053] Specifically, in Figure 4 In the example, a current mirror module may include four field-effect transistors (FETs) T1, T2, T3, and T4. Another current mirror module may include four field-effect transistors (FETs) T5, T6, T7, and T8. The gate module may include two conductive transmission gates (G1 and G2). The energy storage module may include a capacitor (C1). The inverter module may include two inverters (D1 and D2) connected in series.

[0054] The oscillator circuit is described as follows:

[0055] The left side T1, T3, T5, T7 is the one that generates bias voltage for the right side T2, T4, G1, G2, T6, T8 branch. The gate terminal of T1 tube is connected to the PMOS gate terminal of the bias circuit, which is equivalent to copying the current of the bias circuit. Since the gate terminal and drain terminal of T3, T5, and T7 are connected, the VGS will be determined according to the current flowing through, thereby providing bias voltage.

[0056] The middle node of the right branch of T2, T4, G1, G2, T6, and T8 is connected to a capacitor to ground. G1 and G2 are transmission tubes. Note that the enable positions of G1 and G2 are different and are swapped (the left side of G1 is active low, and the left side of G2 is active high). Since the left side of G1 is connected to the left side of G2, and the right side of G1 is connected to the right side of G2, only one transmission tube is turned on at any time;

[0057] Two inverters are connected after the grounded capacitor to provide enable signals to G1 and G2 while adjusting the waveform; the output of inverter D2 is the clock output of the OSC oscillator;

[0058] The signal generation process of the oscillator circuit is as follows:

[0059] At any given moment in operation, the outputs of D1 and D2 are assumed to be either high, low, or both. Therefore, either only the upper current mirrors T2 and T4 are active, or only the lower current mirrors T6 and T8 are active. For example, when D1 outputs high and D2 outputs low (the voltage on the top plate of C1 is low), G1 is active and G2 is inactive. Therefore, the upper current mirrors T2 and T4 are active, charging the top plate of capacitor C1 until the voltage on C1's top plate is high enough to cause D1 to flip. Then, when D1 outputs low and D2 outputs high, G2 is active and G1 is inactive. The lower current mirrors T6 and T8 draw current from the top plate of C1, effectively discharging the charge, until the voltage on C1's top plate drops low enough to cause D1 to flip. This cycle repeats to generate the clock. The OSC oscillation frequency is primarily determined by the current mirror currents and the capacitance of C1. Therefore, if C1 remains constant, changing the bias current can change the clock frequency.

[0060] Further, in Figure 4 In [1], the feedback network includes a logic processing module and four D flip-flops B1-B4. The sequence generation network includes four D flip-flops. The second feedback signal satisfies the following formula:

[0061] F=B4⊕B5⊕B6⊕B8+B1′B2′B3′B4′B5′B6′B7′B8′

[0062] Where F is the second feedback signal, B1', B2', B3', and B4' are the Q' outputs of each D flip-flop corresponding to the reverse sequence of the random numbers, B5', B6', B7', and B8' are the Q' outputs of each D flip-flop in the first feedback signal set, and B5, B6, and B8 are the Q outputs of each D flip-flop in the first feedback signal set. In the formula, B1'B2'B3'B4'B5'B6'B7'B8' represents an AND operation between B1', B2', B3', B4'B5', B6', B7', and B8'. The symbol ⊕ represents an exclusive-or operation, and the symbol + represents an exclusive-or operation.

[0063] Specifically, the following Figure 5 Describe the implementation process of this application.

[0064] The current bias circuit (IBIAS) based on logic control in this embodiment has a 4-bit digital signal as input. After passing through a 4-16 decoder, it becomes a 16-bit digital sequence with only one bit being 1 and the rest being 0. The 16-bit digital sequence controls 16 NMOS tubes respectively. For each NMOS tube, it is turned on when the digital signal is 1 and turned off when the digital signal is 0. The on and off of the NMOS tube controls the actual number of series resistors. For example, when M8 is turned on, the resistors R8 to R16 are disconnected, and the resistors that actually work are Rb and R0 to R7, while the op amp clamping voltage remains unchanged, thereby achieving a change in the bias current. Therefore, this part can realize a bias circuit that generates 16 types of bias currents controlled by a 4-bit digital signal. The voltage divider resistors R1 to R16 in the example do not have to be equal and can be randomly set according to requirements to make the 16 levels of bias current unevenly distributed.

[0065] In a current-controlled oscillator (ICO) circuit, a current mirror copies the current from the bias circuit, using it as a pull-up current and a pull-down current. Each of these currents is connected to a transmission gate, with only one of the two gates in the on state at any given time. The current connected to the on-state transmission gate charges and discharges the capacitor, increasing its voltage as it charges and decreasing as it discharges. The capacitor voltage is then connected to a circuit consisting of two inverters connected in series, whose outputs serve as control signals for the two transmission gates. This creates an oscillator circuit capable of controlling its frequency using current.

[0066] The frequency divider can be realized by connecting 8 binary frequency dividers end to end. 8 The frequency divider can divide the pulse signal output by the current controlled oscillator. The low-speed pulse after frequency division is used as the clock signal of the M sequence generation circuit.

[0067] The 8-bit M sequence generating circuit is composed of an 8-bit shift register and a combinational logic circuit. The 8-bit shift register uses the low-speed pulse from the frequency divider as a clock to perform digital sequence shifting operations. The combinational logic circuit acts as a feedback circuit and takes the output signals of the 8 D flip-flops that make up the shift register as inputs. After logical operations, it is fed back to the first D flip-flop input of the 8-bit shift register, thus achieving a closed loop and generating a period of 2 8 The logic expression of the feedback circuit is formula (1). B1 to B4 are selected as the input signals of the current bias circuit based on logic control.

[0068] F=B4⊕B5⊕B6⊕B8+B1′B2′B3′B4′B5′B6′B7′B8′#(1)

[0069] The operational logic between the various modules can be summarized as follows: the logic-controlled bias circuit generates varying bias currents based on a 4-bit digital signal. The current-controlled oscillator replicates the bias circuit current to produce a series of pulsed square wave signals. The frequency divider divides this pulsed square wave signal to generate a low-speed pulsed square wave signal, which serves as the clock for the M-sequence generation circuit. The output of the first four D-type flip-flops in the M-sequence generation circuit serves as the input signal for the logic-controlled bias circuit, completing the logic loop of the entire circuit. This modulation method reduces the generation of audible frequencies while lowering the peak EMI of the switching power supply.

[0070] and Figure 1 Corresponding to the device, an embodiment of the present application further provides a switching power supply chip, including a randomly modulated clock spread spectrum device as described in any of the above items.

[0071] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present application. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the routine skills of an engineer. Therefore, a person skilled in the art can implement the present application as set forth in the claims using ordinary techniques without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the appended claims and their equivalents.

[0072] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0073] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0074] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A randomly modulated clock spread spectrum device, characterized in that: include: A frequency divider circuit is used to receive a first pulse signal output by the oscillator circuit in a t-1 modulation period; The M sequence generating circuit is used to generate a random digital sequence with a modulation period of t-1 according to the first pulse signal; wherein the period of the random digital sequence is 2 n , n is an integer greater than or equal to 4; a current bias circuit, configured to generate a first bias current of a t-1 modulation period according to the random digital sequence; An oscillator circuit is configured to generate a clock spread spectrum signal with a modulation period of t according to the first bias current, where t is an integer greater than or equal to 2.

2. The randomly modulated clock spread spectrum device according to claim 1, characterized in that: The M sequence generating circuit includes a sequence generating network and a feedback network; The feedback network includes a logic processing module and nT D flip-flops; The sequence generation network includes T D flip-flops; the sequence generation network is used to generate a random digital inverse sequence of a t-2 modulation period; the random digital inverse sequence is a digital sequence obtained by performing a logical NOT operation on the output signal of each D flip-flop in the T D flip-flops of the t-2 modulation period; The nT D flip-flops are used to generate a first feedback signal set of a t-1 modulation period according to a pulse signal of a t-2 modulation period; The logic processing module is configured to perform logic conversion processing on the first feedback signal set and the random digital reverse sequence to obtain a second feedback signal with a t-1 modulation period that is output to the sequence generation network; The sequence generation network is further used to generate the random digital sequence based on the first pulse signal and the second feedback signal; wherein the random digital sequence is a digital sequence composed of the output signal of each D flip-flop in the T D flip-flops.

3. The randomly modulated clock spread spectrum device according to claim 2, characterized in that: The current bias circuit includes a decoder and a current converter; The decoder is used to convert the random digital sequence into a target driving signal with a t-1 modulation period; The current converter is used to convert the target driving signal into a first bias current of a t-1 modulation period.

4. The randomly modulated clock spread spectrum device according to claim 3, characterized in that: The current converter comprises: Current generation module, 2 T a resistance module and a resistance selection module; the current generating module is connected to the resistance selection module; the resistance selection module is used to select the current from the two according to the target drive signal T Any one of the resistance modules is determined to form a closed loop with the current generating module to generate the first bias current.

5. The randomly modulated clock spread spectrum device according to claim 4, characterized in that: The resistance values ​​of any two resistance modules among the T resistance modules are different from each other.

6. The randomly modulated clock spread spectrum device according to claim 3, characterized in that: The decoder is used to convert T signals into 2 T bit binary number and output the 2 T The target drive signal corresponding to the binary number of the bit.

7. The randomly modulated clock spread spectrum device according to claim 1, characterized in that: The frequency divider circuit includes Y two-frequency dividers; any two adjacent two-frequency dividers among the Y two-frequency dividers are connected in series; wherein Y is a positive integer greater than or equal to 2.

8. The randomly modulated clock spread spectrum device according to claim 1, characterized in that: The oscillator circuit includes two current mirror modules connected in parallel, a gating module, an energy storage module and an inverter module; The current mirror module is used to receive the first bias current and generate a charging current with a t modulation period; The gating module is used to gating any one of the current mirror modules in the t modulation period and charging the energy storage module through the charging current; The inverter module is used to generate a control signal according to the voltage of the energy storage module, so that the gating module enables another current mirror module in the t modulation period, charges the energy storage module through the charging current, and generates a clock spread spectrum signal of the t modulation period.

9. The randomly modulated clock spread spectrum device according to claim 3, characterized in that: The feedback network includes a logic processing module and four D flip-flops; the sequence generation network includes four D flip-flops; the second feedback signal satisfies the following formula: Wherein, F is the second feedback signal, B1', B2', B3', B4' are the outputs of the Q' end of each D flip-flop corresponding to the random digital reverse sequence, B5', B6', B7', B8' are the outputs of the Q' end of each D flip-flop in the first feedback signal set, and B5, B6, B8 are the outputs of the Q end of each D flip-flop in the first feedback signal set; B1'B2'B3'B4'B5'B6'B7'B8' in the formula represents the AND operation between B1', B2', B3', B4'B5', B6', B7', B8'; the symbol The symbol + represents the exclusive OR operation, and the symbol + represents the OR operation.

10. A switching power supply chip, comprising a randomly modulated clock spread spectrum device according to any one of claims 1 to 9.

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