Ferroelectric memory device and method of manufacturing ferroelectric memory device

Abstract

The invention relates to a ferroelectric memory device and a manufacturing method of the ferroelectric memory device. The ferroelectric memory device includes: a dielectric layer including a plurality of ferroelectric regions alternately arranged with a plurality of non-ferroelectric regions in a first direction, the dielectric layer having a tubular structure; a channel layer extending in a first direction on an inner wall of the dielectric layer; and a gate stack structure including a plurality of conductive layers surrounding the plurality of ferroelectric regions of the dielectric layer, and wherein the plurality of conductive layers are spaced apart in the first direction.

Description

Technical Field

[0001] The present disclosure relates to semiconductor memory devices and methods of manufacturing the same, including but not limited to ferroelectric memory devices and methods of manufacturing the same. Background Art

[0002] Semiconductor memory devices are applicable to electronic devices in various fields such as automobiles, healthcare, and data centers, as well as small electronic devices. Therefore, there is an increasing demand for semiconductor memory devices.

[0003] Semiconductor memory devices include a plurality of memory cells for storing data. Three-dimensional memory devices have been proposed to increase the integration density of memory cells per unit area of ​​a substrate. A three-dimensional memory device includes, for example, memory cells stacked vertically above a substrate. Summary of the Invention

[0004] According to an embodiment, a ferroelectric memory device may include: a dielectric layer including a plurality of ferroelectric regions arranged alternately with a plurality of non-ferroelectric regions in a first direction, the dielectric layer having a tubular structure; a channel layer extending in the first direction on an inner wall of the dielectric layer; and a gate stack structure including a plurality of conductive layers surrounding the plurality of ferroelectric regions of the dielectric layer, wherein the plurality of conductive layers are spaced apart in the first direction.

[0005] According to an embodiment, a method for manufacturing a ferroelectric memory device may include the following steps: forming a stacked structure, the stacked structure including a plurality of first material layers arranged alternately with a plurality of second material layers in a stacking direction; forming a hole passing through the stacked structure by etching the plurality of first material layers and the plurality of second material layers; forming a ferroelectric layer in the hole, the ferroelectric layer having a tubular structure extending in the stacking direction; forming a channel layer extending in the stacking direction and covering the inner wall of the ferroelectric layer; forming a slit passing through the stacked structure by etching the plurality of first material layers and the plurality of second material layers; replacing the plurality of second material layers with the plurality of conductive layers through the slit; removing the plurality of first material layers through the slit so that openings are formed between continuous conductive layers in the plurality of conductive layers in the stacking direction; and injecting dopants into the regions of the ferroelectric layer exposed by the openings so that a plurality of non-ferroelectric regions are formed in the ferroelectric layer.

[0006] According to an embodiment, a ferroelectric memory device may include: a gate stack structure including a plurality of conductive layers spaced apart in a first direction; a dielectric layer disposed within the gate stack structure and including a plurality of ferroelectric regions forming memory cells arranged alternately with a plurality of non-ferroelectric regions in the first direction; and a channel layer disposed on an inner wall of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit diagram of a memory cell string of a ferroelectric memory device according to an embodiment of the present disclosure;

[0008] Figure 2 is a perspective view of a ferroelectric memory device according to an embodiment of the present disclosure;

[0009] Figure 3 is a polarization electric field hysteresis curve in the ferroelectric region according to an embodiment of the present disclosure;

[0010] Figure 4A and Figure 4B is a diagram illustrating a polarization state of a memory cell according to an embodiment of the present disclosure;

[0011] Figure 5A and Figure 5B is a cross-sectional view of a ferroelectric memory device according to an embodiment of the present disclosure;

[0012] Figures 6A to 6C is a cross-sectional view of a ferroelectric memory device according to an embodiment of the present disclosure;

[0013] 7A to 7E is a cross-sectional view showing a gate stack structure of a ferroelectric memory device formed using a process for forming a gate stack structure of a ferroelectric memory device according to an embodiment of the present disclosure;

[0014] Figure 8 shows a cross section of a non-ferroelectric region of a ferroelectric memory device formed using a process for forming a non-ferroelectric region of a ferroelectric memory device according to an embodiment of the present disclosure;

[0015] Figure 9 and Figure 10 is a cross-sectional view illustrating a non-ferroelectric region of a ferroelectric memory device formed using post-processing of the non-ferroelectric region according to an embodiment of the present disclosure;

[0016] Figure 11 is a cross-sectional view showing an interfacial oxide layer formed using a process according to an embodiment of the present disclosure; and

[0017] Figure 12 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Specific structural or functional descriptions of examples of implementations of the concepts disclosed in this specification are merely shown to describe examples of implementations according to the concepts, and examples of implementations according to the concepts may be implemented in various forms, but these descriptions are not limited to the examples of implementations described in this specification.

[0019] Terms such as "first" and "second" are used to distinguish between various elements and do not imply the size, order, priority, quantity, or importance of the elements. For example, in one example, a first element may be referred to as a second element, and in another example, a second element may be referred to as a first element. Terms such as "vertical," "horizontal," "top," "above," "up," "side," "up," "down," "higher," "column," "row," "inside," "outside," and other terms that suggest relative spatial relationships or orientations are used only for ease of description or reference to the drawings and are not intended to be limiting. Cross-hatching throughout the drawings illustrates corresponding or similar areas between the drawings, rather than indicating material associated with the areas.

[0020] With growing interest in next-generation memory devices, various technological advancements have been made, resulting in the use of ferroelectric layers in place of charge trapping layers in the data storage region of a memory cell associated with three-dimensional semiconductor memory devices. According to embodiments of the present disclosure, a ferroelectric memory device capable of improving operational reliability and a method for manufacturing the same are described.

[0021] Figure 1 is a circuit diagram of a memory cell string of a ferroelectric memory device according to an embodiment of the present disclosure.

[0022] Reference Figure 1 , the memory cell array of the ferroelectric memory device includes a plurality of memory cell strings. Each memory cell string includes a plurality of memory cells (first memory cell MC1 to nth memory cell MCn) connected in series between a corresponding bit line BL and a source layer SL, where n is a natural number of 2 or greater. According to an embodiment, among the plurality of memory cells MC1 to MCn, the first memory cell MC1 adjacent to the source layer SL is electrically coupled to the source layer SL, and the nth memory cell MCn is electrically coupled to the bit line BL. The present disclosure is not limited to this example. According to an embodiment, either or both of the bit line BL and the source layer SL are electrically coupled to the memory cell string via a select transistor.

[0023] Each of the plurality of memory cells MC1 to MCn is composed of a ferroelectric transistor using ferroelectricity as a data storage area. The memory cells MC1 to MCn have low-power and high-speed operation characteristics due to ferroelectric properties.

[0024] A plurality of memory cells MC1 to MCn are respectively coupled to a plurality of word lines WL1 to WLn. Each of the word lines WL1 to WLn serves as a gate electrode for a corresponding memory cell. Each of the word lines WL1 to WLn corresponds to one of a plurality of conductive layers disposed above a substrate (not shown). The plurality of memory cells MC1 to MCn are formed at intersections between the plurality of conductive layers and a channel layer passing through the plurality of conductive layers.

[0025] Figure 2 is a perspective view of a ferroelectric memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 2 The ferroelectric memory device includes a plurality of gate stack structures 21 , a plurality of dielectric layers 11 and a plurality of channel layers 13 .

[0027] The plurality of gate stack structures 21 are separated from each other in a first direction DR1 and extend in a second direction DR2. Each gate stack structure 21 includes a plurality of conductive layers 21A, 21B, and 21C that are spaced apart from each other and stacked on each other in a third direction DR3. The plurality of conductive layers 21A, 21B, and 21C are disposed over a substrate (not shown). The first direction DR1, the second direction DR2, and the third direction DR3 may correspond to the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0028] The plurality of conductive layers 21A, 21B, and 21C may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. The doped semiconductor material may include doped silicon, doped germanium, or the like. Each of the plurality of conductive layers 21A, 21B, and 21C may include a conductive metal nitride and a metal. The conductive metal nitride may extend over the upper and lower surfaces and sidewalls of the metal. Examples of metal nitrides include titanium nitride and tantalum nitride. Examples of metals include tungsten, titanium, tantalum, and molybdenum. Examples of metal-semiconductor compounds include tungsten silicide, cobalt silicide, and titanium silicide.

[0029] The sidewalls of the gate stack structures 21 are covered by an insulating layer 31. The insulating layer 31 is disposed between adjacent gate stack structures 21. The insulating layer 31 may include silicon oxide.

[0030] Each air gap 35 is formed or provided between adjacent or continuous conductive layers along the third direction DR3, for example, between conductive layers 21A and 21B or between conductive layers 21B and 21C. Insulating layer 31 shields air gap 35 from the outside of the ferroelectric memory device. Insulating layer 31 is adjacent to air gap 35. The dielectric constant of air gap 35 can be similar to or the same as the dielectric constant in a vacuum state. Compared to an example in which another dielectric, such as silicon oxide, is provided between adjacent or continuous conductive layers along the third direction DR3, parasitic capacitance between adjacent conductive layers along the third direction DR3 is reduced.

[0031] Multiple dielectric layers 11 are arranged in multiple rows and columns. The column dielectric layers 11 are arranged in a row in a first direction DR1. The row dielectric layers 11 are arranged in a row in a second direction DR2. Each gate stack 21 includes dielectric layers that form at least one row and extend in the second direction DR2. The rows controlled by each gate stack 21 are not limited to the example shown in the figure. According to an embodiment, each gate stack 21 surrounds the dielectric layers 11 that form at least two rows.

[0032] Each dielectric layer 11 has a tubular structure extending in the third direction DR3. The third direction DR3 may correspond to the longitudinal direction of the dielectric layer 11. The substrate of the dielectric layer 11 includes, for example, a material that exhibits ferroelectric properties when processed into a thin film of 10 nm or less. Depending on the embodiment, the dielectric layer 11 may include a hafnium oxide-based material or a hafnium oxide-based material doped with a dopant. The dopant may include one or more of zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr).

[0033] The dielectric layer 11 includes a plurality of ferroelectric regions 11A alternately arranged with a plurality of non-ferroelectric regions 11B. Each ferroelectric region 11A has a spontaneous polarization characteristic. Each non-ferroelectric region 11B is a region that undergoes depolarization when no electric field is applied. The non-ferroelectric regions 11B include at least one of an antiferroelectric region and a paraelectric region.

[0034] The plurality of channel layers 13 correspond to the plurality of dielectric layers 11. Each channel layer 13 extends along the inner wall of the corresponding dielectric layer 11. Figure 1 As shown, the channel layer 13 includes an end portion coupled to the source layer SL. Figure 1 As shown, the channel layer 13 extends in a third direction DR3 (e.g., a longitudinal direction) toward the bit line BL. The channel layer 13 may include a semiconductor material. Depending on the embodiment, the channel layer 13 may include silicon. The channel layer 13 may have a tubular structure. Depending on the embodiment, the central region of the channel layer 13 may be filled with a core insulating layer 15. The present disclosure is not limited to this example. The central region of the channel layer 13 may include an electrode.

[0035] The memory cell is formed at the intersection between the plurality of channel layers 13 and the plurality of conductive layers 21A, 21B, and 21C. The ferroelectric region 11A of the dielectric layer 11 serves as a data storage region of the memory cell.

[0036] Figure 3 is a polarization electric field hysteresis curve in the ferroelectric region according to an embodiment of the present disclosure.

[0037] Reference Figure 3When the external electric field applied to the ferroelectric region having a negative polarization state is a positive electric field greater than or equal to the first coercive electric field Ec, the polarization of the ferroelectric region is reversed. When the external electric field applied to the ferroelectric region increases from the first coercive electric field Ec to the first saturation electric field Ep or greater, and then the external electric field decreases to zero, the ferroelectric region has a first remanent polarization Pr. When the external electric field applied to the ferroelectric region having a positive polarization state is negative and its absolute value is greater than or equal to the absolute value of the second coercive electric field -Ec, the polarization of the ferroelectric region is reversed. When the absolute value of the negative external electric field applied to the ferroelectric region increases to a value greater than or equal to the absolute value of the second coercive electric field -Ec and then decreases to zero, the ferroelectric region has a second remanent polarization -Pr.

[0038] By utilizing these hysteresis characteristics of the ferroelectric region, logical data corresponding to the remnant polarization of the memory cell is stored. The logical data stored in the memory cell is read out by sensing current or voltage according to the remnant polarization state of the memory cell.

[0039] Figure 4A and Figure 4B is a diagram illustrating a polarization state of a memory cell according to an embodiment of the present disclosure.

[0040] Reference Figure 4A and Figure 4B , the memory cell MC is formed at the intersection between the channel layer 13 and the conductive layer 21G, and the on state or off state of the memory cell MC is determined based on the polarization direction in the ferroelectric region 11A. Figure 1 As shown, the channel layer 13 extends from the source layer SL toward the bit line BL and includes a channel region corresponding to the memory cell MC. Figure 2 As shown, the conductive layer 21G is one of the plurality of conductive layers 21A, 21B, and 21C of the gate stack structure 21 .

[0041] An external electric field is applied to the ferroelectric region 11A by the voltage applied to the conductive layer 21G and the voltage applied to the channel region of the channel layer 13. The voltage applied to the channel region of the channel layer 13 is from Figure 1 The bit line BL or Figure 1 The source layer SL shown is transferred.

[0042] Reference Figure 4A, a voltage higher than the voltage applied to the channel layer 13 is applied to the conductive layer 21G, so that an external electric field greater than or equal to the absolute value of the coercive electric field is applied to the ferroelectric region 11A. According to an embodiment, by applying 0V or a ground voltage GND to the channel layer 13 and applying a positive voltage to the conductive layer 21G, the external electric field applied to the ferroelectric region 11A is positive, and by controlling the voltage applied to the conductive layer 21G, an external electric field greater than or equal to the absolute value of the coercive electric field is applied to the ferroelectric region 11A. The radially outward polarization originates from the radially inward external electric field applied to the ferroelectric region 11A, wherein the radially outward polarization and the radially inward external electric field are relative to the center of the core insulating layer 15 in the channel layer 13. When the external electric field is eliminated or no longer applied, the ferroelectric region 11A has a remanent polarization in the radially outward direction. The state in which the ferroelectric region 11A has the remanent polarization in the radially outward direction is the on-state in which the logic data "0" is written. During the on-state, the energy band of channel layer 13 increases. As a result, when data stored in memory cell MC is read by controlling the voltage applied to conductive layer 21G and channel layer 13 so that an electric field smaller than the absolute value of the coercive electric field is formed in ferroelectric region 11A, current easily flows between ferroelectric region 11A and channel layer 13 due to the low potential barrier of channel layer 13. Therefore, the data stored in memory cell MC is read.

[0043] Reference Figure 4B , a voltage higher than the voltage applied to the conductive layer 21G is applied to the channel layer 13, so that an external electric field greater than the absolute value of the coercive electric field is applied to the ferroelectric region 11A. According to an embodiment, by applying 0V to the conductive layer 21G and applying a positive voltage to the channel layer 13, the external electric field applied to the ferroelectric region 11A is negative. By controlling the voltage applied to the channel layer 13, an external electric field with an absolute value greater than or equal to the absolute value of the coercive electric field is applied to the ferroelectric region 11A. The radially inward polarization originates from the radially outward external electric field applied to the ferroelectric region 11A, wherein the radially outward external electric field and the radially inward polarization are relative to the center of the core insulating layer 15 in the channel layer 13. When the external electric field is eliminated or no longer applied, the ferroelectric region 11A has a remanent polarization in the radially inward direction. The state in which the ferroelectric region 11A has a remanent polarization in the radially inward direction is the cut-off state for writing logical data "1". During the cut-off state, the energy band of the channel layer 13 increases. As a result, when data is read by controlling the voltage applied to the conductive layer 21G and the channel layer 13 so that an electric field smaller than the absolute value of the coercive electric field is formed in the ferroelectric region 11A, the current flowing between the ferroelectric region 11A and the channel layer 13 is suppressed. Therefore, the data stored in the memory cell MC is read out.

[0044] Figure 5A and Figure 5Bis a cross-sectional view of a ferroelectric memory device according to an embodiment of the present disclosure.

[0045] Figure 5A is a cross-sectional view of the ferroelectric memory device taken along a line extending in the first direction DR1 . Figure 5B is a cross-sectional view of the ferroelectric memory device taken along a line extending in the second direction DR2 .

[0046] Reference Figure 5A and Figure 5B Conductive layers 21A and 21B of gate stack structure 21 are alternately arranged with air gaps 35 in third direction DR3. Air gaps 35 are blocked by insulating layer 31 from the outside of the ferroelectric memory device and extend between dielectric layers 11 that are continuous or consecutive along second direction DR2.

[0047] Each dielectric layer 11 includes ferroelectric regions 11A alternately arranged with non-ferroelectric regions 11B1 in the third direction DR3. The ferroelectric regions 11A and the non-ferroelectric regions 11B1 are distinguished from each other based on a difference in dopant concentration in the hafnium-based material forming the dielectric layers 11. The non-ferroelectric regions 11B1 may include at least one of an antiferroelectric region and a paraelectric region.

[0048] The non-ferroelectric region 11B1 includes a dopant having a higher concentration than that of the ferroelectric region 11A and contacts the channel layer 13. According to an embodiment, the ferroelectric region 11A may include hafnium oxide (HfO2), and the non-ferroelectric region 11B may include silicon-doped hafnium oxide (HSO). According to another embodiment, each of the ferroelectric region 11A and the non-ferroelectric region 11B1 may include hafnium oxide doped with silicon. The silicon concentration, referred to as "Si / (Hf+Si)", is controlled to be higher in the non-ferroelectric region 11B1 than in the ferroelectric region 11A. The silicon concentration in the ferroelectric region 11A is controlled within a range that maintains the ferroelectricity of the ferroelectric region 11A and can operate as a memory layer. According to an embodiment, the silicon concentration in the ferroelectric region 11A may be 4% or more and less than 9%, and the silicon concentration in the non-ferroelectric region 11B1 may be 9% or more.

[0049] Figures 6A to 6C is a cross-sectional view of a ferroelectric memory device according to an embodiment of the present disclosure. Figures 6A to 6C is a cross-sectional view illustrating a ferroelectric memory device taken along a line extending in a first direction DR1 .

[0050] Reference Figure 6AThe dielectric layer 11 includes a ferroelectric region 11A and a non-ferroelectric region 11B2. The non-ferroelectric region 11B2 has a different crystal system or structure than the ferroelectric region 11A. The non-ferroelectric region 11B2 includes at least one of an antiferroelectric region and a paraelectric region. Depending on the embodiment, the ferroelectric region 11A may include an orthorhombic phase, the antiferroelectric region may include a tetragonal phase, and the paraelectric region may include a monoclinic phase.

[0051] Reference Figure 6B The dielectric layer 11 includes a ferroelectric region 11A and a non-ferroelectric region 11B3. The ferroelectric region 11A and the non-ferroelectric region 11B3 are distinguished from each other based on the difference in dopant concentration in the hafnium-based material forming the dielectric layer 11. The non-ferroelectric region 11B3 has a concave outer wall facing away from the channel layer 13.

[0052] Reference Figure 6C The dielectric layer 11 includes a ferroelectric region 11A and a non-ferroelectric region 11B1'. The interface oxide layer 30 is interposed between the non-ferroelectric region 11B1' and the channel layer 13'. Figure 5A and Figure 5B As depicted, the ferroelectric region 11A and the non-ferroelectric region 11B1' are distinguished from each other based on a difference in dopant concentration in the hafnium-based material forming the dielectric layer 11. The interface oxide layer 30 may include silicon dioxide SiO2.

[0053] Although not shown, the interface oxide layer 30 may be formed as Figure 6A As shown, it is inserted between the non-ferroelectric region 11B2 and the channel layer 13 or as shown Figure 6B It is shown interposed between the non-ferroelectric region 11B3 and the channel layer 13 .

[0054] Reference Figure 5A 、 Figure 6A 、 Figure 6B and Figure 6C Each of the channel layer 13 or 13' and the core insulating layer 15 includes a first region surrounded by the ferroelectric region 11A of the dielectric layer 11 and a second region surrounded by the non-ferroelectric region 11B, 11B2, 11B3, or 11B1'. The first region of the channel layer 13 or 13' contacts the ferroelectric region 11A of the dielectric layer 11.

[0055] Each of the conductive layers 21A and 21B of the gate stack structure 21 surrounds the ferroelectric region 11A of the corresponding dielectric layer 11. An air gap 35 is provided between the non-ferroelectric region 11B1, 11B2, 11B3, or 11B1' and the insulating layer 31.

[0056] The non-ferroelectric regions 11B1, 11B2, 11B3, or 11B1′ are interposed between the ferroelectric regions 11A that are continuous along the third direction DR3, so as to divide the ferroelectric region 11A into memory cell units. As a result, spontaneous polarization between the memory cells that are continuous along the third direction DR3 is reduced or prevented, thereby reducing the influence of disturbances caused by spontaneous polarization.

[0057] 7A to 7E is a cross-sectional view illustrating a gate stack structure of a ferroelectric memory device formed using a process for forming the gate stack structure of a ferroelectric memory device according to an embodiment of the present disclosure.

[0058] Reference Figure 7A , a stacked structure 110 is formed on a lower structure (not shown). The lower structure may include a substrate. The substrate may include a semiconductor material. The lower structure also includes a peripheral circuit, an interconnection connected to the peripheral circuit, an insulating structure covering the peripheral circuit and the interconnection, and a source layer disposed above the insulating structure. The peripheral circuit is disposed on the substrate and provides control operations for the memory cell array. The source layer corresponds to Figure 1 The source layer SL is shown.

[0059] The stacked structure 110 includes a plurality of first material layers 101 and a plurality of second material layers 103. Each of the first material layers 101 and the second material layers 103 may have a flat or thin plate shape, for example, extending in a first direction DR1 and a second direction DR2 in the XY plane. The first material layers 101 are alternately arranged with the second material layers 103 in a third direction DR3 orthogonal to the XY plane. The third direction DR3 may be the Z-axis direction and is referred to as the stacking direction.

[0060] The second material layer 103 has an etching selectivity with respect to the first material layer 101. According to an embodiment, the first material layer 101 may include an insulating material such as a silicon oxide layer, and the second material layer 103 may include a sacrificial insulating material such as a silicon nitride layer.

[0061] Reference Figure 7B , a plurality of holes 105 are formed by etching a plurality of first material layers 101 and a plurality of second material layers 103. The plurality of holes 105 are arranged in a plurality of rows and columns. Each hole 105 passes through the stacked structure 110. Although not shown, the holes 105 may be open to or expose the source layer of the lower structure.

[0062] A ferroelectric layer 111L is formed in the hole 105. The ferroelectric layer 111L includes a material whose polarization characteristics are affected by an applied electric field. According to an embodiment, the ferroelectric layer 111L may include a hafnium oxide-based material. The hafnium oxide-based material may be hafnium oxide (HfO2) or dopant-doped hafnium oxide. The ferroelectric layer 111L extends in the third direction DR3 along the inner walls of the plurality of first material layers 101 and the plurality of second material layers 103 exposed through the hole 105 and has a tubular structure. The ferroelectric layer 111L may include an orthorhombic phase.

[0063] A channel layer 113 is formed to cover the inner wall of the ferroelectric layer 111L. The channel layer 113 may include a semiconductor material. Depending on the embodiment, the channel layer 113 may include silicon. The channel layer 113 may have a tubular structure. A core insulating layer 115 is formed in the center region of the channel layer 113. Although not shown, a capping semiconductor pattern may be provided on the upper end of the core insulating layer 115.

[0064] Reference Figure 7C , by etching as Figure 7B The plurality of first material layers 101 and second material layers 103 are used to form the slits 117. The slits 117 pass through the Figure 7B The stacked structure 110 shown leaves the sidewalls of the plurality of second material layers 103 open.

[0065] The slit 117 selectively removes Figure 7B The plurality of second material layers 103 are shown. As a result, a plurality of horizontal spaces 119 are formed. The plurality of first material layers 101 are divided by slits 117 to form a mold structure MD.

[0066] Reference Figure 7D , in such Figure 7C A plurality of conductive layers 121A and 121B are provided in the plurality of horizontal spaces 119. The plurality of conductive layers 121A and 121B are spaced apart from each other in the first direction DR1 by the slits 117 and in the third direction DR3 by the mold structure MD.

[0067] Reference Figure 7E , selectively remove the Figure 7D The plurality of first material layers 101 are shown to remove Figure 7D The mold structure MD shown is shown. Figure 7D The mold structure MD shown is used to form openings 135 between the lower conductive layer 121A and the upper conductive layer 121B. The plurality of conductive layers 121A and 121B are alternately arranged with the plurality of openings 135 in the third direction DR3 to form the gate stack structure 121.

[0068] The region of the ferroelectric layer 111L is exposed through the opening 135. The ferroelectric layer 111L is formed relative to the region of the ferroelectric layer 111L. Figure 7DThe silicon oxide of the plurality of first material layers 101 shown has etching selectivity. Therefore, the ferroelectric layer 111L can serve as a support to prevent the gate stack structure 121 from collapsing during the etching process for selectively removing the plurality of first material layers 101.

[0069] Figure 8 A cross section of a non-ferroelectric region of a ferroelectric memory device formed using a process for forming the non-ferroelectric region of a ferroelectric memory device according to an embodiment of the present disclosure is shown.

[0070] Reference Figure 8 , by Figure 7D In the illustrated ferroelectric layer 111L, dopants 141 are implanted into certain regions to form a dielectric layer 111 including a non-ferroelectric region 111B1. Dopants 141 may include one or more of zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr). By controlling the doping concentration of dopants 141, the spontaneous polarization characteristics of the non-ferroelectric region 111B1 of the dielectric layer 111 may be lost or reduced.

[0071] During the process of doping the dopant 141, the dopant 141 is controlled so that a region of the ferroelectric layer between each of the plurality of conductive layers 131A and 121B and the channel layer 113 is not doped with the dopant 141. As a result, a region of the ferroelectric layer between each of the plurality of conductive layers 121A and 121B and the channel layer 113 remains as the ferroelectric region 111A of the dielectric layer 111. The ferroelectric region 111A is arranged alternately with the non-ferroelectric region 111B1 in the third direction DR3.

[0072] In execution of the combination Figure 8 After the process described above, an insulating layer may be formed in the slits 117 so that air gaps are formed in the respective openings 135. As a result, the above-described Figure 5A and Figure 5B A ferroelectric memory device is described.

[0073] Figure 9 and Figure 10 is a cross-sectional view illustrating a non-ferroelectric region of a ferroelectric memory device formed using post-processing of the non-ferroelectric region according to an embodiment of the present disclosure.

[0074] Reference Figure 9 , in the implementation of the combined Figure 8 After the described process, an oxygen O2 annealing process may be performed through the opening 135. The oxygen O2 annealing process is performed so that Figure 8The crystal system of the non-ferroelectric region 111B1 shown is changed. As a result, a non-ferroelectric region 111B2 having a crystal system or structure different from that of the non-ferroelectric region 111A is formed. The non-ferroelectric region 111B2 includes at least one of an antiferroelectric region and a paraelectric region. The ferroelectric region 111A may have an orthorhombic phase. The antiferroelectric region may have a tetragonal phase. The paraelectric region may have a monoclinic phase. Figure 9 After the process described above, an insulating layer may be formed in the slit 117. As a result, the Figure 6A A ferroelectric memory device is described.

[0075] Reference Figure 10 , in the implementation of the combined Figure 8 After the described process, the Figure 8 The non-ferroelectric region 111B1 shown is used to extend the opening 135. Due to the etching process, the sidewalls of the remaining non-ferroelectric region 111B3 may have a concave structure. Figure 10 After the process described above, an insulating layer may be formed in the slit 117. As a result, the Figure 6B The present disclosure is not limited to this example. According to another embodiment, in performing a combination Figure 7E After the described process, the Figure 7E The opening 135 is extended by the region of the ferroelectric layer 111L shown. Figure 8 As depicted, dopants are implanted through opening 135 .

[0076] Figure 11 is a cross-sectional view illustrating an interfacial oxide layer formed using a process according to an embodiment of the present disclosure.

[0077] Reference Figure 11 , in the implementation of the combined Figure 7E After the process described above, the region of the channel layer 113 is oxidized through the opening 135. During the oxidation process, oxygen penetrates the ferroelectric layer 111L through the opening 135 to oxidize the region of the channel layer 113. As a result, an interfacial oxide layer 130 is formed between the ferroelectric layer 111L and the channel layer 113. After forming the interfacial oxide layer 130, the process described in reference to FIG. Figure 8 As a result, the process described in reference Figure 6C The ferroelectric memory device described herein is not limited to this example. After forming the interface oxide layer 130, the following steps may be performed: Figure 9 The subsequent process described above may be performed as described above with reference to Figure 10 The subsequent process described.

[0078] Figure 12is a block diagram illustrating an electronic system 1000 according to an embodiment of the present disclosure.

[0079] Reference Figure 12 The electronic system 1000 may include a computing system, a medical device, a communication device, a wearable device, or a memory system. The electronic system 1000 includes a host 1100 and a storage device 1200 .

[0080] The host 1100 stores data in the storage device 1200 and reads the stored data from the storage device 1200 in response to a signal constructed according to the interface. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a PCI-Express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics interface (IDE), a FireWire interface, a universal flash storage (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0081] The memory device 1200 includes a memory controller 1210 and a semiconductor memory device 1220. According to an embodiment, the memory device 1200 may be a solid state drive (SSD), a universal serial bus (USB) memory, or the like.

[0082] The memory controller 1210 stores data in the semiconductor memory device 1220 and reads data stored in the semiconductor memory device 1220 in response to the control of the host 1100 .

[0083] The semiconductor memory device 1220 may include a single memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data in response to control of the memory controller 1210.

[0084] The semiconductor memory device 1220 is, for example, Figures 1 to 11 The ferroelectric memory device described herein includes a dielectric layer interposed between a channel layer and a conductive layer of a gate stack structure. The dielectric layer includes a ferroelectric region surrounding the conductive layer and a non-ferroelectric region separating the ferroelectric region.

[0085] According to the present disclosure, the operational reliability of a ferroelectric memory device may be improved by partitioning or separating a ferroelectric region using a non-ferroelectric region.

[0086] Although detailed embodiments of the present disclosure are disclosed in this disclosure, it will be understood by those skilled in the art that various modifications, additions, and substitutions related to these embodiments may be made without departing from the scope and technical concepts of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments. All changes within the meaning and equivalent range of the claims are intended to be included within their scope.

[0087] CROSS-REFERENCE TO RELATED APPLICATIONS

[0088] This application claims the benefit of Korean Patent Application No. 10-2024-0031437, filed on March 5, 2024, in the Korean Intellectual Property Office, the entire application of which is incorporated herein by reference.

Claims

1. A ferroelectric memory device, comprising: a dielectric layer comprising a plurality of ferroelectric regions arranged alternately with a plurality of non-ferroelectric regions in a first direction, the dielectric layer having a tubular structure; a channel layer extending in the first direction on an inner wall of the dielectric layer; as well as A gate stack structure includes a plurality of conductive layers surrounding the plurality of ferroelectric regions of the dielectric layer, wherein the plurality of conductive layers are spaced apart in the first direction.

2. The ferroelectric memory device according to claim 1, wherein The dielectric layer includes a hafnium oxide-based material.

3. The ferroelectric memory device according to claim 1, wherein The plurality of ferroelectric regions include hafnium oxide HfO2, and The plurality of non-ferroelectric regions include silicon-doped hafnium oxide (HSO).

4. The ferroelectric memory device according to claim 1, wherein The dielectric layer includes a hafnium oxide-based material doped with a dopant, and The dopant includes one or more of zirconium Zr, silicon Si, aluminum Al, gadolinium Gd, yttrium Y, lanthanum La, and strontium Sr.

5. The ferroelectric memory device according to claim 1, wherein Each of the ferroelectric region and the non-ferroelectric region of the dielectric layer comprises silicon-doped hafnium oxide (HSO), and A concentration of silicon in the plurality of non-ferroelectric regions is higher than a concentration of silicon in the plurality of ferroelectric regions.

6. The ferroelectric memory device according to claim 5, wherein In the plurality of ferroelectric regions, a concentration of the silicon is 4% or more and less than 9%, and in the plurality of non-ferroelectric regions, a concentration of the silicon is 9% or more. 7 . The ferroelectric memory device according to claim 5 , further comprising a silicon dioxide (SiO 2 ) layer interposed between each of the plurality of ferroelectric regions and the channel layer.

8. The ferroelectric memory device according to claim 1, wherein The plurality of non-ferroelectric regions have a different crystal system than the ferroelectric region.

9. The ferroelectric memory device according to claim 1, wherein Each of the plurality of non-ferroelectric regions includes an antiferroelectric region and a paraelectric region.

10. The ferroelectric memory device according to claim 1, wherein Each of the plurality of ferroelectric regions includes an orthorhombic phase, and Each of the non-ferroelectric regions includes at least one of a tetragonal phase and a monoclinic phase.

11. The ferroelectric memory device according to claim 1, wherein Each of the plurality of non-ferroelectric regions includes a concave outer wall facing in a direction away from the channel layer.

12. The ferroelectric memory device according to claim 1, further comprising: an insulating layer, the insulating layer covering a sidewall of the gate stack structure; as well as An air gap is formed between consecutive conductive layers of the plurality of conductive layers and adjacent to the insulating layer.

13. A ferroelectric memory device, comprising: a gate stack structure comprising a plurality of conductive layers spaced apart in a first direction; a dielectric layer disposed within the gate stack structure and comprising a plurality of ferroelectric regions forming memory cells and arranged alternately with a plurality of non-ferroelectric regions in the first direction; as well as A channel layer is provided on an inner wall of the dielectric layer.

14. A method of manufacturing a ferroelectric memory device, the method comprising the steps of: forming a stacked structure including a plurality of first material layers arranged alternately with a plurality of second material layers in a stacking direction; forming a hole through the stacked structure by etching the plurality of first material layers and the plurality of second material layers; forming a ferroelectric layer in the hole, the ferroelectric layer having a tubular structure extending in the stacking direction; forming a channel layer extending in the stacking direction and covering an inner wall of the ferroelectric layer; forming slits through the stacked structure by etching the plurality of first material layers and the plurality of second material layers; replacing the plurality of second material layers with a plurality of conductive layers through the slits; removing the plurality of first material layers through the slits so as to form openings between consecutive conductive layers in the plurality of conductive layers in the stacking direction; as well as Dopants are implanted into the regions of the ferroelectric layer exposed by the openings, such that a plurality of non-ferroelectric regions are formed in the ferroelectric layer.

15. The method according to claim 14, wherein A region of the ferroelectric layer between each of the conductive layers and the channel layer forms one of a plurality of ferroelectric regions, and the plurality of ferroelectric regions are alternately arranged with the plurality of non-ferroelectric regions in the stacking direction.

16. The method according to claim 14, further comprising the steps of: An interface oxide layer is formed between the region of the ferroelectric layer exposed by the opening and the channel layer.

17. The method according to claim 14, wherein: The non-ferroelectric region includes at least one of an antiferroelectric region and a paraelectric region.

18. The method according to claim 14, further comprising the step of changing a crystal system of the non-ferroelectric region after implanting the dopant.

19. The method according to claim 14, further comprising the steps of: The non-ferroelectric region is post-treated through the opening by oxygen annealing, so that the non-ferroelectric region includes at least one of a tetragonal phase and a monoclinic phase.

20. The method according to claim 14, further comprising the steps of: After implanting the dopant, the non-ferroelectric region is etched to extend the opening.

21. The method according to claim 14, further comprising the steps of: An insulating layer is formed in the slit to form an air gap in the opening.

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