Silicon carbide metal oxide semiconductor field effect transistor (SiCMOSFET) device with improved gate oxide layer reliability and preparation process

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a silicon carbide SiCMOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) device with improved gate oxide layer reliability, the silicon carbide SiCMOSFET device is composed of a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, a high-K medium is arranged between the grid electrode and the P well layer, and doped polycrystalline silicon is arranged on one side of the high-K medium and located between the source electrode and the N well layer. The high-K medium is one of hafnium oxide, aluminum oxide or zirconium dioxide. Through the double-layer stacked structure of the high-K dielectric and the SiOO gate oxide layer, the high dielectric constant of the high-K material is utilized to share the gate voltage, the electric field intensity of a SiOO interface is remarkably reduced, meanwhile, two orders of magnitude of gate leakage current are reduced, and gate oxide layer degradation caused by hot carrier injection is fundamentally inhibited.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability and a preparation process thereof. Background Art

[0002] The traditional SiO2 gate oxide layer has a low dielectric constant, which leads to concentrated electric field strength, causing significant gate leakage current and hot carrier injection effects; multiple high-temperature annealing processes aggravate lattice defects and reduce breakdown voltage consistency; the JFET effect and parasitic capacitance between cells lead to uneven electric field distribution during dynamic switching, accelerating the degradation and failure of the gate oxide layer, making it difficult to meet the stringent requirements for device life in new energy vehicles, rail transit and other fields.

[0003] An existing patent discloses a high-temperature stable power MOSFET device and its fabrication method (publication number CN116759461A). The power MOSFET device includes a silicon carbide substrate, an N-type silicon carbide drift layer, a floating P+ shield ring, an N-type epitaxial layer, a JFET region, a P-well region, a polycrystalline gate layer, a gate oxide layer, an N+ doped region, and a P+ shield region. This existing patent has the following problems: 1) Only the P+ shielding region and the floating P+ shielding ring are used to reduce the electric field stress of the gate oxide layer in the static blocking state, but the problem of uneven electric field distribution during dynamic switching is not solved, and the suppression of gate leakage current and hot carrier injection is limited.

[0004] 2) The source metal layer directly contacts the semiconductor, which can easily cause the gate oxide edge electric field distortion and increase the on-resistance fluctuation.

[0005] 3) The JFET effect and parasitic capacitance between cells lead to uneven electric field distribution during dynamic switching, accelerating the failure of the gate oxide layer. Summary of the Invention

[0006] The present invention provides a silicon carbide (SiC) MOSFET device and a preparation process with improved gate oxide layer reliability to solve existing technical problems, thereby solving the problem of uneven electric field distribution in MOS devices during dynamic switching, which accelerates gate oxide layer degradation and failure.

[0007] To solve the above technical problems, according to one aspect of the present invention, more specifically, a silicon carbide SiC MOSFET device with improved gate oxide layer reliability is provided. The silicon carbide SiC MOSFET device is composed of a plurality of mutually parallel MOS cells, wherein the MOS cell includes a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer, and a source. The semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P+ layer, a P well layer, and an N well layer. A high-K dielectric is provided between the gate and the P well layer, wherein doped polysilicon is provided on one side of the high-K dielectric and between the source and the N well layer.

[0008] Furthermore, the high-K dielectric is one of hafnium dioxide, aluminum oxide or zirconium dioxide.

[0009] Furthermore, the doped polysilicon is one of P-type polysilicon or low-concentration doped N-type polysilicon.

[0010] Furthermore, a polysilicon layer is provided below the inner portion of the gate in a single MOS cell; the polysilicon layer is one of P-type polysilicon or N-type polysilicon.

[0011] Furthermore, an inhibition P-layer is provided at the lower part of the gate, and the cross-sectional profile of the inhibition P-layer is trapezoidal; The top end of the suppression P-layer is in direct contact with the gate, and the bottom end of the suppression P-layer is in direct contact with the N diffusion layer.

[0012] Furthermore, a plurality of N-type guard rings that do not contact each other are formed inside the suppression P- layer by ion implantation, and the bottom ends of the N-type guard rings are in direct contact with the N diffusion layer.

[0013] Furthermore, an inner convex P-layer is provided on the surface of the semiconductor epitaxial layer and between two adjacent high-K dielectrics, and the cross-sectional profile of the inner convex P-layer is in a shape of thick top and thin bottom.

[0014] Furthermore, a plurality of N-type barrier rings that do not contact each other are provided inside the inner convex P-layer, and the tops of the N-type barrier rings are in direct contact with the gate oxide layer.

[0015] A process for preparing a silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability includes: S1. epitaxially growing a low-concentration N diffusion layer on the N substrate layer; S2, forming a P-well layer, an N-well layer, a P+ layer, and an inner convex P- layer in sequence through ion implantation and high temperature annealing; S3, implanting ions into the inner convex P-layer to form multiple N-type barrier rings; S4, thermally oxidizing and growing a gate oxide layer on the surface of the P-well layer; depositing a high-K dielectric between the gate and the P-well layer; S5. depositing doped polysilicon between the source and the N-well layer, wherein the doped polysilicon is P-type polysilicon or low-concentration N-type polysilicon; S6, etching the electrode contact window to expose the source, drain and gate regions; S7. Deposit a Ni, Ti or Al alloy layer and form a source electrode, a gate electrode and a drain electrode by photolithography.

[0016] The present invention provides a silicon carbide SiCMOSFET device with improved gate oxide layer reliability and a preparation process. Compared with the prior art, the present method achieves the following effects: 1. The present invention adopts a double-layer stack structure of high-K dielectric and SiO2 gate oxide layer, and utilizes the high dielectric constant of high-K material to share the gate voltage, significantly reducing the electric field strength at the SiO2 interface and reducing the gate leakage current by two orders of magnitude, thereby fundamentally suppressing the degradation of the gate oxide layer caused by hot carrier injection.

[0017] 2. The present invention constructs a distributed depletion region under the gate through the vertical integration design of the N-type guard ring and the barrier ring, actively absorbs the high-voltage spikes during the switching process, reduces the electric field non-uniformity of the gate oxide layer to <5%, and improves the impact resistance and life under high-frequency conditions.

[0018] 3. The present invention replaces the traditional source metal contact with doped polysilicon, and effectively reduces the source contact resistance through the carrier modulation effect of P-type / low-concentration N-type polysilicon, while eliminating the gate oxide edge electric field distortion, reducing the on-resistance fluctuation rate by 40%.

[0019] 4. The present invention simultaneously activates multiple injection layers through a single high-temperature annealing, simplifying the traditional four-step annealing to one step. The lattice defect density is effectively reduced, and the interface state density of the gate oxide layer is effectively optimized, and the breakdown voltage consistency is improved by >15%.

[0020] 5. The present invention controls the morphology of the trapezoidal suppression P-layer and the inner convex P-layer, and reconstructs the longitudinal / lateral electric field distribution through gradient doping and inverted cone structure, thereby effectively reducing the parasitic capacitance between cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of Example 1 of the present invention; Figure 2 This is a schematic diagram of Example 2 of the present invention; Figure 3 This is a schematic diagram of Example 3 of the present invention; Figure 4 This is a schematic diagram of Example 4 of the present invention; Figure 5 This is a schematic diagram of Example 5 of the present invention; Figure 6 This is a schematic diagram of Example 6 of the present invention.

[0022] In the figure: 1. Drain; 2. Gate; 3. Gate oxide layer; 4. Source; 5. N substrate layer; 6. N diffusion layer; 7. P+ layer; 8. P well layer; 9. N well layer; 10. Doped polysilicon; 11. High-K dielectric; 12. Polysilicon layer; 13. Suppressed P- layer; 14. N-type guard ring; 15. Inward convex P- layer; 16. N-type barrier ring. DETAILED DESCRIPTION

[0023] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] like Figure 1 、 6 As shown, the preparation process of the silicon carbide SiC MOSFET device with improved gate oxide layer reliability includes: Step 1: Epitaxially grow a low-concentration N diffusion layer 6 on the N substrate layer 5; Epitaxially grow a low-concentration N diffusion layer 6 on the N substrate layer 5 as a drift region. By precisely controlling the doping concentration and thickness, while ensuring the breakdown voltage, it provides a carrier transport foundation for the subsequent multilayer structure, laying the foundation for the device's high-voltage tolerance.

[0025] Step 2: Through ion implantation and high-temperature annealing, a P-well layer 8, an N-well layer 9, a P+ layer 7, and an inner convex P-layer 15 are formed in sequence; a single high-temperature annealing synchronously activates the ion implantation of the P-well layer 8, the N-well layer 9, the P+ layer 7, and the inner convex P-layer 15, and utilizes the coordinated optimization of annealing temperature and time to reduce the lattice damage caused by traditional multiple annealing, significantly improve the interface quality, and reduce the defect density of the gate oxide layer.

[0026] Step 3: Ions are injected into the inner convex P-layer 15 to form multiple N-type barrier rings 16; vertically distributed N-type barrier rings 16 are injected into the inverted cone-shaped inner convex P-layer 15, and their tops are closely attached to the gate oxide layer 3. By constructing a local depletion region, the vertical penetration of the drain electric field is blocked, thereby suppressing the hot carrier injection effect of the gate oxide layer from the source.

[0027] Step 4: Thermally oxidize and grow a gate oxide layer 3 on the surface of the P-well layer 8; deposit a high-K dielectric 11 between the gate 2 and the P-well layer 8; directly deposit the high-K dielectric 11 on the thermally grown SiO2 gate oxide layer 3, utilizing the dielectric constant advantage of the high-K material to reduce the equivalent oxide layer thickness. At the same time, the high-K layer shares the gate voltage and reduces the SiO2 interface electric field strength. The dual dielectric layers synergistically improve the gate insulation reliability.

[0028] Step 5: Deposit doped polysilicon 10 between the source 4 and the N-well layer 9, wherein the doped polysilicon 10 is P-type polysilicon or low-concentration N-type polysilicon; selectively deposit the doped polysilicon 10 between the source 4 and the N-well layer 9: If P-type polysilicon is used, the contact barrier can be reduced, while low-concentration N-type polysilicon balances the carrier concentration. Both optimize the ohmic contact resistance of the source region and avoid the gate oxide edge electric field distortion caused by traditional metal contacts.

[0029] Step 6: Etch the electrode contact windows to expose the source 4, drain 1 and gate 2 areas; simultaneously etch and expose the source / gate / drain contact windows, using the top protection of the inner convex P-layer 15 and the N-type barrier ring 16 to ensure etching accuracy without damaging the edge of the gate oxide layer and maintain interface integrity.

[0030] Step 7: Deposit a Ni, Ti, or Al alloy layer and photolithographically form the source, gate, and drain electrodes. Using a Ni / Ti / Al alloy layer and photolithographically forming the electrodes, the low-temperature alloying properties of metal and SiC are utilized to ensure ohmic contact quality while preventing thermal stress damage to the high-K dielectric 11 and gate oxide layer 3 stack during high-temperature processing.

[0031] Example 1 like Figure 1 As shown, a silicon carbide SiC MOSFET device with improved gate oxide layer reliability is composed of several mutually parallel MOS cells. The MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 2, a gate oxide layer 3, and a source 4. The semiconductor epitaxial layer includes an N substrate layer 5, an N diffusion layer 6, a P+ layer 7, a P well layer 8, and an N well layer 9. It is characterized in that a high-K dielectric 11 is provided between the gate 2 and the P well layer 8, wherein doped polysilicon 10 is provided on one side of the high-K dielectric 11 and between the source 4 and the N well layer 9. The doped polysilicon 10 does not hinder the ohmic contact between the source 4 and the N well layer 9.

[0032] High-K dielectric 11 is one of hafnium dioxide, aluminum oxide, or zirconium dioxide. Doped polysilicon 10 is one of P-type polysilicon or low-concentration doped N-type polysilicon. By introducing high-K dielectric 11 between gate 2 and P-well layer 8 and doped polysilicon 10 between source 4 and N-well layer 9, the high-K dielectric reduces gate leakage current and improves dielectric strength, while the doped polysilicon optimizes source contact resistance, synergistically enhancing gate oxide reliability while maintaining low on-resistance.

[0033] Example 2 like Figure 2As shown, a polysilicon layer 12 is provided underneath the gate 2 in a single MOS cell. This polysilicon layer 12 can be either P-type or N-type. Adding this polysilicon layer 12 below the gate 2 modulates the local electric field distribution, dissipating the electric field stress on the gate oxide layer 3, preventing gate oxide breakdown caused by electric field concentration and improving the long-term stability of the device.

[0034] Example 3 like Figure 3 As shown, a suppression P-layer 13 is provided below the gate 2. The cross-sectional profile of the suppression P-layer 13 is trapezoidal. The top of the suppression P-layer 13 is in direct contact with the gate 2, and the bottom of the suppression P-layer 13 is in direct contact with the N-diffusion layer 6. The trapezoidal suppression P-layer 13 connects the gate 2 and the N-diffusion layer 6. Its gradient doping structure optimizes the longitudinal electric field distribution, suppresses the increase in channel resistance caused by the JFET effect, and reduces the risk of gate oxide layer interface defects.

[0035] Example 4 like Figure 4 As shown, multiple non-contacting N-type guard rings 14 are formed inside the suppression P-layer 13 through ion implantation. The bottom ends of the N-type guard rings 14 are in direct contact with the N diffusion layer 6. Implanting the N-type guard rings 14 within the suppression P-layer 13 forms a local depletion region to absorb high-voltage stress, prevent electric field spikes from occurring under the gate, and significantly improve the gate oxide layer's shock resistance under high switching frequencies.

[0036] Example 5 like Figure 5 As shown, an inward-convex P-layer 15 is provided on the surface of the semiconductor epitaxial layer and between two adjacent high-k dielectrics 11. The cross-sectional profile of this inward-convex P-layer 15 is thick at the top and narrow at the bottom. The inward-convex P-layer 15 between adjacent high-k dielectrics 11, with its "wide at the top and narrow at the bottom" structure, reshapes the lateral electric field in the drift region, alleviates electric field crowding between cells, and reduces parasitic capacitance and hot carrier damage at the gate oxide edge.

[0037] Example 6 like Figure 6 As shown, multiple non-contacting N-type barrier rings 16 are disposed within the inner convex P-layer 15. The tops of the N-type barrier rings 16 are in direct contact with the gate oxide layer 3. The N-type barrier rings 16 in the inner convex P-layer 15 are perpendicular to the gate oxide layer 3, forming an electric field shielding fence that blocks the coupling path of the drain high voltage to the gate oxide layer, thereby fundamentally suppressing gate oxide degradation and failure.

[0038] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability, the silicon carbide (SiC) MOSFET device comprising a plurality of mutually parallel MOS cells, the MOS cells comprising a drain (1), a semiconductor epitaxial layer, a gate (2), a gate oxide layer (3), and a source (4), the semiconductor epitaxial layer comprising an N substrate layer (5), an N diffusion layer (6), a P+ layer (7), a P well layer (8), and an N well layer (9), characterized in that: A high-K dielectric (11) is provided between the gate (2) and the P-well layer (8), wherein doped polysilicon (10) is provided on one side of the high-K dielectric (11) and between the source (4) and the N-well layer (9).

2. The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability according to claim 1, wherein: The high-K medium (11) is one of hafnium dioxide, aluminum oxide or zirconium dioxide.

3. The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability according to claim 1, wherein: The doped polysilicon (10) is one of P-type polysilicon and low-concentration doped N-type polysilicon.

4. The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability according to claim 1, wherein: A polysilicon layer (12) is provided below the inner portion of the gate (2) in a single MOS cell; the polysilicon layer (12) is one of P-type polysilicon and N-type polysilicon.

5. The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability according to claim 1, wherein: An inhibition P-layer (13) is provided at the lower portion of the gate (2), and the cross-sectional profile of the inhibition P-layer (13) is trapezoidal; The top end of the suppression P-layer (13) is in direct contact with the gate (2), and the bottom end of the suppression P-layer (13) is in direct contact with the N diffusion layer (6).

6. The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability according to claim 5, characterized in that: A plurality of mutually non-contacting N-type protection rings (14) are formed inside the suppression P-layer (13) by ion implantation, and the bottom ends of the N-type protection rings (14) are in direct contact with the N diffusion layer (6).

7. The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability according to claim 1, wherein: An inward convex P-layer (15) is provided on the surface of the semiconductor epitaxial layer and between two adjacent high-K dielectrics (11). The cross-sectional profile of the inward convex P-layer (15) is in a shape of thick top and thin bottom.

8. The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability according to claim 7, characterized in that: A plurality of N-type barrier rings (16) that do not contact each other are provided inside the inner convex P-layer (15), and the top ends of the N-type barrier rings (16) are in direct contact with the gate oxide layer (3).

9. A process for preparing a silicon carbide SiC MOSFET device with improved gate oxide layer reliability, characterized in that: Applied to the silicon carbide SiC MOSFET device according to claim 8, the preparation process of the silicon carbide SiC MOSFET device with improved gate oxide layer reliability comprises: S1. epitaxially growing a low-concentration N diffusion layer (6) on the N substrate layer (5); S2, forming a P-well layer (8), an N-well layer (9), a P+ layer (7), and an inner convex P- layer (15) in sequence through ion implantation and high temperature annealing; S3, implanting ions into the inner convex P-layer (15) to form a plurality of N-type barrier rings (16); S4, thermally oxidizing and growing a gate oxide layer (3) on the surface of the P-well layer (8); depositing a high-K dielectric (11) between the gate (2) and the P-well layer (8); S5, depositing doped polysilicon (10) between the source (4) and the N-well layer (9), wherein the doped polysilicon (10) is P-type polysilicon or low-concentration N-type polysilicon; S6, etching the electrode contact window to expose the source (4), drain (1) and gate (2) regions; S7. Deposit a Ni, Ti or Al alloy layer and form a source electrode, a gate electrode and a drain electrode by photolithography.

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