Frequency-locked loop based on switched capacitor and microcontroller

Abstract

The invention provides a frequency-locked loop based on a switched capacitor and a microcontroller, and the frequency-locked loop comprises a first current module which provides a first current; the switched capacitor module is connected in series with the first current module and cooperates with the first current to provide a first voltage. The voltage module provides a second voltage; the chopping amplifier outputs an amplified signal based on the first voltage and the second voltage; the voltage-controlled oscillator outputs a square wave signal according to the amplified signal; the non-overlapping clock generation module generates a first clock signal and a second clock signal under the action of the square wave signal; the switched capacitor filter is connected in series between the chopping amplifier and the voltage-controlled oscillator; under the condition that the second voltage is smaller than the first voltage, the amplification signal output by the chopping amplifier is reduced, the switched capacitor filter filters ripples in the square wave signal under the action of the first clock signal and the second clock signal, and the voltage-controlled oscillator outputs the square wave signal with reduced frequency, so that the equivalent impedance of the switched capacitor module is increased; the first voltage is equal to the second voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic information technology, and in particular to a frequency-locked loop and a microcontroller based on a switched capacitor. Background Art

[0002] As integrated circuits continue to shrink in size, chip miniaturization is accelerating the progress of the Internet of Things. Oscillators are essential components of most circuits, and advances in semiconductor manufacturing technology have made on-chip clock integration possible.

[0003] Resistor-capacitor (RC) oscillators are compatible with complementary metal-oxide-semiconductor (CMOS) processes, eliminating the need for bulky off-chip components. The key concerns regarding the frequency stability of RC oscillators include temperature stability, voltage stability, and long-term stability.

[0004] A frequency-locked loop (FLL) oscillator is a negative-feedback RC oscillator. The feedback loop converts the output clock of a voltage-controlled oscillator (VCO) into a voltage signal. An amplifier amplifies the error between this voltage signal and a reference voltage and feeds it back to the VCO input, thus forming a closed-loop control loop to lock the frequency. This negative-feedback oscillator structure avoids the degradation of clock signal temperature and voltage stability caused by unstable reset pulse timing in traditional RC oscillators, mitigates the impact of comparator and loop delay drift on frequency, and suppresses clock jitter accumulation. However, offset voltage can affect the stability of the FLL's output frequency, and amplifier noise can also exacerbate jitter.

[0005] In related technologies, chopping technology can be added to eliminate offset voltage and the low-frequency noise of the amplifier to improve the accuracy of the output frequency. However, the ripple generated by the switched capacitor circuit during operation is amplified by the amplifier, and the output ripple caused by the amplifier's chopping switching requires load capacitance to suppress it. To achieve good suppression, the load capacitor usually needs to have a large capacitance value, resulting in the need for large-area capacitors in the circuit layout, which increases manufacturing costs. In addition, the main pole of the entire frequency-locked loop is at the output end of the amplifier. The large load capacitance pushes the main pole inward, reducing the loop bandwidth and extending the response time of the frequency-locked loop. Summary of the Invention

[0006] In view of the above technical problems, the present disclosure provides a frequency locked loop and a microcontroller based on a switched capacitor. The frequency locked loop based on the switched capacitor can effectively suppress the ripple at the output end of the amplifier while saving a large area of ​​load capacitance.

[0007] As one aspect of the present disclosure, a frequency locked loop based on a switched capacitor is provided, and the frequency locked loop based on the switched capacitor includes a first current module, a switched capacitor module, a voltage module, a chopper amplifier, a voltage controlled oscillator, a non-overlapping clock generation module, a frequency division component and a switched capacitor filter. The first current module is suitable for providing a first current, and the switched capacitor module is connected in series with the above-mentioned first current module, and is suitable for cooperating with the above-mentioned first current to provide the above-mentioned first voltage. The voltage module is suitable for providing a second voltage, and the chopper amplifier outputs an amplified signal based on the above-mentioned first voltage and the above-mentioned second voltage. The voltage controlled oscillator is suitable for outputting a square wave signal according to the above-mentioned amplified signal. The non-overlapping clock generation module is suitable for generating two non-overlapping first clock signals and second clock signals under the action of the above-mentioned square wave signal. The above-mentioned switched capacitor filter is connected in series between the above-mentioned chopper amplifier and the above-mentioned voltage controlled oscillator. In which, when the above-mentioned second voltage is less than the above-mentioned first voltage, the above-mentioned chopper amplifier is configured to reduce the above-mentioned amplified signal output, and the above-mentioned switched capacitor filter filters out the ripple in the above-mentioned square wave signal under the above-mentioned action of the above-mentioned first clock signal and the above-mentioned second clock signal. The above-mentioned voltage-controlled oscillator is configured to output the above-mentioned square wave signal with a reduced frequency according to the above-mentioned filtered amplified signal, so that the equivalent impedance of the above-mentioned switched capacitor module becomes larger, thereby making the above-mentioned first voltage equal to the above-mentioned second voltage.

[0008] According to an embodiment of the present disclosure, the switched capacitor filter includes a first switch, a first capacitor, a second switch, and a second capacitor. One end of the first switch is connected to the output end of the chopper amplifier, one end of the first capacitor is connected to the other end of the first switch, and the other end of the first capacitor is connected to the ground signal. The second switch is connected in series between the first switch and the voltage-controlled oscillator, one end of the second capacitor is connected to the other end of the second switch, and the other end of the second capacitor is connected to the ground signal. The first switch and the second switch are turned on or off in response to the first clock signal and the second clock signal, respectively.

[0009] According to an embodiment of the present disclosure, the frequency divider further includes a frequency dividing component adapted to provide, in response to the square wave signal, two non-overlapping third and fourth clock signals having lower frequencies than the square wave signal. The third and fourth clock signals serve as the chopping frequencies of the chopper amplifier.

[0010] According to an embodiment of the present disclosure, the frequency division component includes a clock generator, a frequency divider, and a non-overlapping clock generator. The clock generator generates a fifth clock signal in response to the square wave signal. The frequency divider is configured to divide the fifth clock signal into two non-overlapping clock signals, the third clock signal and the fourth clock signal, in response to the sixth clock signal.

[0011] According to an embodiment of the present disclosure, the frequency locked loop further includes a load capacitor, one end of which is connected to the output end of the chopper amplifier and the other end is connected to a ground signal, and is suitable for suppressing the output ripple of the chopper amplifier.

[0012] According to an embodiment of the present disclosure, the switched capacitor module includes a third capacitor, a third switch, a fourth switch, and a fourth capacitor. The third capacitor is connected in series with the first current module, the third switch is connected in series between the third capacitor and the first current module, the fourth switch is connected in parallel with the third capacitor, and the fourth capacitor is connected in parallel with the third capacitor and the third switch. The third switch and the fourth switch are respectively turned on or off under the action of the first clock signal and the second clock signal, generating an equivalent impedance related to the frequency of the first clock signal and the second clock signal, so that the switched capacitor circuit provides the first voltage to the chopper amplifier under the action of the first current.

[0013] According to an embodiment of the present disclosure, the voltage module includes a second current module and a resistor. The second current module matches the first current module and is adapted to provide a second current. The resistor is connected in series with the second current module to provide the second voltage to the chopper amplifier under the action of the second current.

[0014] According to an embodiment of the present disclosure, the voltage module further includes a cutoff module connected in parallel with the resistor, and the cutoff module includes a fifth switch and a sixth switch. The sixth switch is connected in series with the fifth switch. The fifth switch and the sixth switch are respectively opened or closed in response to the first clock signal and the second clock signal to cut off the tail current of the second current module.

[0015] According to an embodiment of the present disclosure, the frequency-locked loop further includes a fifth capacitor, the fifth capacitor matches the second capacitor, and the fifth capacitor is connected in parallel with the resistor.

[0016] As another aspect of an embodiment of the present disclosure, a microcontroller is provided, comprising any of the above-described frequency-locked loops, a first power supply, and a second power supply. The first power supply is adapted to provide a first supply voltage to the first current module, such that the first current module, under the action of the first supply voltage, cooperates with the switched capacitor module to provide the first voltage. The second power supply is adapted to provide a second supply voltage to the voltage module, such that the reference voltage module, under the action of the second voltage, provides the reference voltage.

[0017] According to the frequency-locked loop of the embodiment of the present disclosure, by adopting a switched capacitor filter, the first clock signal and the second clock signal, which are two clock signals generated by a non-overlapping clock generation module and have frequencies equal to the square wave signal and do not overlap with each other, are used as sampling clocks of the switched capacitor filter. This effectively suppresses the ripple at the output end of the amplifier and reduces the jitter of the output clock while saving a large area of ​​load capacitance, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A circuit diagram of a frequency locked loop according to an embodiment of the present disclosure is schematically shown;

[0019] Figure 2 The equivalent circuit diagram of the switched capacitor filter disclosed in the present invention is schematically shown;

[0020] Figure 3 Schematically shows a timing diagram of a switched capacitor filter according to an embodiment of the present disclosure;

[0021] Figure 4 A circuit diagram of a frequency locked loop according to another embodiment of the present disclosure is schematically shown.

[0022] Description of reference numerals:

[0023] 1-Variable voltage module;

[0024] 11- first current module;

[0025] 12- switched capacitor module;

[0026] 2- Voltage module;

[0027] 21- second current module;

[0028] 22-cut-off module;

[0029] 3-Chopper amplifier;

[0030] 4-Voltage Controlled Oscillator;

[0031] 5-frequency division components;

[0032] 6-Switched capacitor filter. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0034] During the implementation of the present disclosure, it was discovered that chopping technology is a method for eliminating static errors by periodically switching the gain or bias of an amplifier. Applying chopping technology to an amplifier can effectively suppress offset voltage and improve the accuracy of the output signal. However, every technology has its drawbacks. While chopping technology offers numerous advantages for amplifiers and oscillators, its use is also associated with some potential problems. The most obvious problem is the generation of ripple at the VCO control input. This ripple is caused by the interaction between the chopping signal and the VCO's voltage control characteristics. When this ripple occurs, it increases the VCO's output jitter, thereby affecting the performance of the entire system.

[0035] Typically, this problem can be solved by increasing the chopping frequency or increasing CL. However, the former may result in larger offset voltage drift and poorer accuracy at lower frequencies, while the latter involves a trade-off between capacitor area and jitter performance.

[0036] Figure 1 The circuit diagram of a frequency locked loop according to an embodiment of the present disclosure is schematically shown.

[0037] As one aspect of the embodiments of the present disclosure, a frequency locked loop is provided, such as Figure 1 As shown, the frequency locked loop includes a first current module 11, a switched capacitor module 12, a voltage module 2, a chopper amplifier 3, a voltage controlled oscillator (VCO) 4, a non-overlapping clock generation module NOC1, a frequency division component 5 and a switched capacitor filter 6. The first current module 11 is adapted to provide a first current I ref1 The switch capacitor module 12 is connected in series with the first current module 11 and is adapted to cooperate with the first current to provide a first voltage V + The voltage module 2 is adapted to provide a second voltage V _ , the chopper amplifier 3 is based on the first voltage V + and the second voltage V _ , outputting an amplified signal. The voltage-controlled oscillator 4 is adapted to output a square wave signal based on the amplified signal. The non-overlapping clock generation module NOC1 is adapted to generate two non-overlapping first and second clock signals CK1 and CK2 based on the square wave signal. A switched capacitor filter 6 is connected in series between the chopper amplifier 3 and the voltage-controlled oscillator 4.

[0038] In the case where the second voltage is less than the first voltage, the chopper amplifier 3 is configured to reduce the output amplified signal, the switched capacitor filter filters out the ripple in the square wave signal under the action of the first clock signal CK1 and the second clock signal CK2, and the voltage-controlled oscillator is configured to output a square wave signal with a reduced frequency according to the filtered amplified signal, so that the equivalent impedance of the switched capacitor module 12 becomes larger, thereby increasing the first voltage V + and the second voltage V -equal.

[0039] According to the frequency-locked loop of the embodiment of the present disclosure, by adopting a switched capacitor filter, the first clock signal CK1 and the second clock signal CK2, which are two non-overlapping clock signals with frequencies equal to square wave signals and generated by the non-overlapping clock generation module, are used as sampling clocks of the switched capacitor filter. This effectively suppresses the ripple at the output end of the amplifier and reduces the jitter of the output clock while saving a large area of ​​load capacitance, and has broad application prospects.

[0040] According to an embodiment of the present disclosure, the first current module 11 may be connected to the positive phase input terminal of the chopper amplifier 3 , and the voltage module 2 may be connected to the negative phase input terminal of the chopper amplifier 3 .

[0041] According to the frequency locked loop provided by the embodiment of the present disclosure, a combination of a chopper amplifier 3 and a voltage controlled oscillator 4 is used to realize the first voltage V + and the second voltage V - The comparison and square wave signal generation.

[0042] According to an embodiment of the present disclosure, the frequencies of the two non-overlapping first clock signals CK1 and the second clock signal CK2 generated by the non-overlapping clock generation module 5 can be the same as the frequency F of the square wave signal. out consistent.

[0043] According to an embodiment of the present disclosure, the variable voltage module 1 includes a first current module 11 and a switch capacitor module 12. The circuit structures of the variable voltage module 1 and the voltage module 2 are substantially matched.

[0044] According to an embodiment of the present disclosure, the frequency locked loop further includes a load capacitor C L . Load capacitance C L One end is connected to the output end of the chopper amplifier 3, and the other end is connected to the ground signal, which is suitable for suppressing the output ripple of the chopper amplifier.

[0045] According to an embodiment of the present disclosure, the switched capacitor filter 6 includes a first switch K1, a first capacitor C1, a second switch K2, and a second capacitor C2. One end of the first switch K1 is connected to the output end of the chopper amplifier 3, one end of the first capacitor C1 is connected to the other end of the first switch K1, and the other end of the first capacitor C1 is connected to the ground signal. The second switch K2 is connected in series between the first switch K1 and the voltage-controlled oscillator 3, one end of the second capacitor C2 is connected to the other end of the second switch K2, and the other end of the second capacitor C2 is connected to the ground signal. The first switch K1 and the second switch K2 are turned on or off in response to the first clock signal CK1 and the second clock signal CK2, respectively.

[0046] According to an embodiment of the present disclosure, in each chopping cycle of the switched capacitor filter 6 (the frequency of the first clock signal CK1 and the second clock signal CK2), the load capacitor C L The voltage on the switched capacitor is sampled to suppress ripple. The poles of the switched capacitor filter are determined by the frequency of the sampling signal (the first clock signal CK1 and the second clock signal CK2) and the ratio of the two filter capacitors, which can accurately suppress ripple.

[0047] Figure 2 The equivalent circuit diagram of the switched capacitor filter of the present disclosure is schematically shown.

[0048] like Figure 2 As shown, the equivalent circuit of the switched capacitor filter 6 is a first-order low-pass filter. The equivalent resistance R can be expressed as:

[0049]

[0050] Among them, f sc is the frequency of the switched capacitor, and C1 represents the capacitance of the first capacitor C1.

[0051] It can be seen that the transfer function H(s) of the switched capacitor filter 6 can be expressed as:

[0052]

[0053] Where s represents the complex independent variable in the complex frequency domain of Laplace transform, f sc is the frequency of the switched capacitor, C1 represents the capacitance of the first capacitor C1, and C2 represents the capacitance of the first capacitor C2.

[0054] It can be seen from formula (2) that the poles of the switched capacitor filter 6 are only related to the switching frequency and the values ​​of C1 and C2.

[0055] In some embodiments, the frequency f of the switched capacitor sc Can be equal to the frequency of the square wave signal.

[0056] Figure 3 The timing diagram of the switched capacitor filter according to the embodiment of the present disclosure is schematically shown.

[0057] like Figure 3 As shown, V CL Indicates the load capacitance C L Voltage, V C1 Represents the voltage of the first capacitor C1, V C2 Represents the voltage of the second capacitor C2. Figure 2 It can be seen that each chopping cycle has an impact on the load C L The voltage V CL Sampling can generate ripple-free V C2 .

[0058] According to an embodiment of the present disclosure, the frequency-locked loop further includes a frequency divider 5, which is adapted to provide, under the influence of a square wave signal, two non-overlapping third and fourth clock signals, foc1 and foc2, each having a lower frequency than the square wave signal. The third and fourth clock signals, foc1 and foc2, serve as the chopping frequencies for the chopper amplifier 3.

[0059] According to an embodiment of the present disclosure, the frequency division component 5 includes a clock generator (Clock Generator), a frequency divider Div, and a non-overlapping clock generator NOC2. The clock generator generates a fifth clock signal in response to a square wave signal. The frequency divider Div is adapted to divide the fifth clock signal to output a sixth clock signal having a frequency lower than that of the fifth clock signal. The non-overlapping clock generator NOC2 generates, in response to the sixth clock signal, two non-overlapping third clock signals foc1 and fourth clock signals foc2 having the same frequency as the sixth clock signal. The third clock signals foc1 and the fourth clock signals foc2 serve as the chopping frequencies of the chopper amplifier.

[0060] According to an embodiment of the present disclosure, by setting a frequency division component, a third clock signal foc1 and a fourth clock signal foc2 having a frequency lower than the square wave signal frequency are obtained, and the third clock signal foc1 and the fourth clock signal foc2 are used as the chopping frequency, thereby reducing the loss of the chopping amplifier gain.

[0061] According to an embodiment of the present disclosure, the switch capacitor module 12 includes a third capacitor C3, a third switch K3, a fourth switch K4, and a fourth capacitor C4. The third capacitor C3 is connected in series with the first current module 11, the third switch K3 is connected in series between the third capacitor C3 and the first current module 11, the fourth switch K4 is connected in parallel with the third capacitor C3, and the fourth capacitor C4 can be connected in parallel with the third capacitor C3 and the third switch K3. The third switch K3 and the fourth switch K4 are respectively turned on or off under the action of the first clock signal CK1 and the second clock signal CK2, generating an equivalent impedance related to the frequency of the first clock signal CK1 and the second clock signal CK2, so that the switch capacitor circuit 12 is in the first current I ref1 Under the action of the first voltage V + .

[0062] In an exemplary embodiment, the clock frequencies of the first clock signal CK1 and the second clock signal CK2 can be the same as the frequency F of the square wave signal output by the frequency locked loop. out The equivalent impedance R of the switch capacitor module 12 is the same as X for:

[0063]

[0064] Wherein, C3 represents the capacitance of the third capacitor C3, F out is the frequency of the square wave signal output by the frequency-locked loop.

[0065] Figure 4 A circuit diagram of a frequency locked loop according to another embodiment of the present disclosure is schematically shown.

[0066] According to the embodiments of the present disclosure, Figure 4 As shown, the first current module 11 includes a first differential amplifier, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The two ends of the first resistor R1 are respectively connected to the first output terminal and the first positive phase input terminal of the first differential amplifier, the two ends of the second resistor are respectively connected to the first output terminal and the first negative phase input terminal of the first differential amplifier, one end of the third resistor R3 is connected to the first negative phase input terminal, and the other end is connected to the ground signal. One end of the fourth resistor R4 is connected to the first power supply voltage Vin1, and the other end is connected to the first positive phase input terminal and outputs the first current. Among them, the ratio of the first resistor R1 to the second resistor R2 is equal to the ratio of the third resistor R3 to the fourth resistor R4, so that the first current I ref1 It changes linearly with the first power supply voltage Vin1.

[0067] According to the embodiments of the present disclosure, Figure 4 As shown, for an ideal amplifier, in the variable current module, the current I1 flowing through the resistor R2 is:

[0068]

[0069] The current I2 flowing through resistor R4 is:

[0070]

[0071] The current I3 flowing through resistor R1 is:

[0072]

[0073] Output current I of the variable current module C for:

[0074] I C =I2+I3 (7)

[0075] In formulas (4)-(7), e1 is the electromotive force at point e1, e2 is the electromotive force at point e2, R1 represents the resistance value of resistor R1, R2 represents the resistance value of resistor R2, R3 represents the resistance value of resistor R3, R4 represents the resistance value of resistor R4, V1 represents the first input voltage value of the first input terminal of the first current module, V in1V represents the voltage value of the first power supply voltage Vin1 input to the second input terminal of the first current module, and V3 represents the output voltage value of the output terminal of the amplifier.

[0076] Since the frequency of the square wave signal output by the frequency locked loop is F out In the locked state, the electromotive force at point e1 is equal to the electromotive force at point e2, that is, e1 = e2. Therefore, the voltage drop across resistor R2 is equal to the voltage drop across resistor R1. Therefore, we can get:

[0077]

[0078] According to formula (5), e2 can be expressed as:

[0079] e2=I1R3+V1 (9)

[0080] Therefore, we can get:

[0081]

[0082] like,

[0083]

[0084] Then the first current I ref1 and voltage difference (V in1 -V1). That is, the first current I ref1 The voltage difference between the second input terminal and the first input terminal of the first current module (V in1 -V1).

[0085] In the embodiment of the present disclosure, the first input terminal of the first current module 11 is connected to the ground signal, that is, V1=0, then the first current I ref1 is proportional to the first supply voltage Vin1. According to an embodiment of the present disclosure, Figure 1 and Figure 4 As shown, the voltage module 2 includes a second current module 21 and a resistor R5. The second current module 21 matches the first current module and is adapted to provide a second current I ref2 The resistor R5 is connected in series with the second current module 21 to ref2 Under the action of the second voltage V - .

[0086] According to an embodiment of the present disclosure, the circuit structures of the voltage module 2 and the variable voltage module 1 are matched, so that the frequency-locked loop circuit is as symmetrical as possible.

[0087] According to an embodiment of the present disclosure, the voltage module 2 further includes a cutoff module 22. The cutoff module 22 is connected in parallel with the resistor R5 and includes a fifth switch K5 and a sixth switch K6. The sixth switch K6 is connected in series with the fifth switch K5. The fifth switch K5 and the sixth switch K6 are opened or closed in response to the first clock signal CK1 and the second clock signal CK2, respectively, to cut off the tail current of the second current module 21.

[0088] According to the embodiment of the present disclosure, by providing the cut-off module 22 and the third capacitor C3 , in cooperation with the resistor R5 , and symmetrically matching the switch capacitor module 12 , the stability of the frequency-locked loop circuit is improved.

[0089] According to an embodiment of the present disclosure, the frequency locked loop further includes a fifth capacitor C5 , the fifth capacitor C5 matches the second capacitor C2 , and the fifth capacitor C5 is connected in parallel with the resistor R5 .

[0090] According to the embodiments of the present disclosure, Figure 4 As shown, the second current module 21 includes a second differential amplifier, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The two ends of the sixth resistor R6 are respectively connected to the output terminal and the positive phase input terminal of the second differential amplifier, the two ends of the seventh resistor R7 are respectively connected to the output terminal and the negative phase input terminal of the second differential amplifier, one end of the eighth resistor R8 is connected to the negative phase input terminal, and the other end is connected to the ground signal. One end of the ninth resistor R9 is connected to the external second voltage Vin2, and the other end is connected to the second positive phase input terminal and outputs the second current I ref2 .

[0091] According to an embodiment of the present disclosure, the reference current module 21 and the variable current module 11 adopt the same circuit structure to make the circuit structure of the frequency locked loop symmetrical.

[0092] According to an embodiment of the present disclosure, the second current I ref2 It can be expressed as:

[0093]

[0094] At this time, the voltage at the negative input of the amplifier, that is, the reference voltage V - for:

[0095] V - =I ref2 ×R5 (13)

[0096] Among them, V in represents the voltage value of the second voltage input to the reference voltage module, and R5 represents the resistance value of the resistor R5.

[0097] Then, the voltage at the non-inverting input of the amplifier, that is, the variable voltage V + for:

[0098]

[0099] Wherein, C3 represents the capacitance of the first capacitor C3, F out is the frequency of the square wave signal output by the frequency-locked loop, and Ic represents the current value of the variable current.

[0100] The frequency F of the square wave signal output by the frequency-locked loop out for:

[0101]

[0102] Wherein, C3 represents the capacitance of the first capacitor C3, R5 represents the resistance of the resistor R5, and I ref1 Represents the current value of the first current, I ref2 Indicates the current value of the second current.

[0103] From formula (15), we can see that at the second power supply voltage V in2 Unchanged, first current I ref1 When the frequency of the square wave signal output by the frequency locked loop changes, the frequency F out Synchronous changes. When the frequency-locked loop needs to reduce voltage and frequency, the frequency F out The first supply voltage V in1 Synchronous changes.

[0104] According to the frequency locked loop of the embodiment of the present disclosure, the first current module 11 is combined with the frequency lock, and the first supply voltage V is sensed by the first current module. in1 The change of the square wave signal output by the frequency locked loop is adjusted to adjust the frequency F out By setting the first current module 11, the ratio of the first resistor R1 to the second resistor R2 is set to be equal to the ratio of the third resistor R3 to the fourth resistor R4, so that the first current can follow the first supply voltage V in1 It changes linearly to achieve the first current I ref1 The precise control makes the frequency of the square wave signal output by the frequency-locked loop more flexible and adjustable.

[0105] The frequency-locked loop (FLL) of the disclosed embodiments overcomes the limitations of traditional frequency adjustment methods and achieves a wider range of frequency adjustment capabilities. By combining the high adjustability of the variable current module with the frequency locking mechanism of the FLL, it provides adaptability to a variety of operating frequencies, enabling the FLL to maintain stable performance in different application scenarios.

[0106] As another aspect of an embodiment of the present disclosure, a microcontroller is provided, comprising any of the aforementioned frequency-locked loops, a first power supply, and a second power supply. The first power supply is adapted to provide a first supply voltage to a first current module, such that the first current module, under the action of the first supply voltage, cooperates with a switched capacitor module to provide the first voltage. The second power supply is adapted to provide a second supply voltage to a second voltage module, such that a reference voltage module, under the action of the second voltage, provides a reference voltage.

[0107] According to the microcontroller of the embodiment of the present disclosure, by using the power supply of the microcontroller as the first supply voltage of the first current module, the frequency of the square wave signal output by the frequency-locked loop can change with the change of the power supply voltage of the microcontroller, thereby providing greater flexibility for the microcontroller to operate in various application scenarios and enabling the microcontroller to adapt to the requirements of different workloads and environmental conditions.

[0108] According to an embodiment of the present disclosure, the first power supply may also serve as a power supply for the second power supply.

[0109] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A frequency-locked loop based on switched capacitors, characterized in that: include: A first current module, adapted to provide a first current; a switched capacitor module, connected in series with the first current module, adapted to cooperate with the first current to provide the first voltage; a voltage module, adapted to provide a second voltage; a chopper amplifier, configured to output an amplified signal based on the first voltage and the second voltage; a voltage-controlled oscillator, adapted to output a square wave signal according to the amplified signal; a non-overlapping clock generation module adapted to generate two non-overlapping first clock signals and second clock signals under the action of the square wave signal; as well as a switched capacitor filter connected in series between the chopper amplifier and the voltage-controlled oscillator; In which, when the second voltage is less than the first voltage, the chopper amplifier is configured to reduce the output amplified signal, the switched capacitor filter filters out the ripple in the square wave signal under the action of the first clock signal and the second clock signal, and the voltage-controlled oscillator is configured to output the square wave signal with a reduced frequency according to the filtered amplified signal, so that the equivalent impedance of the switched capacitor module becomes larger, thereby making the first voltage equal to the second voltage.

2. The frequency-locked loop according to claim 1, wherein: The switched capacitor filter comprises: a first switch, one end of which is connected to the output end of the chopper amplifier; a first capacitor, one end of the first capacitor being connected to the other end of the first switch, and the other end of the first capacitor being connected to a ground signal; a second switch connected in series between the first switch and the voltage-controlled oscillator; a second capacitor, one end of the second capacitor being connected to the other end of the second switch, and the other end of the second capacitor being connected to a ground signal; The first switch and the second switch are turned on or off in response to the first clock signal and the second clock signal respectively.

3. The frequency locked loop according to claim 1, wherein: Also includes: A frequency dividing component adapted to provide, under the action of the square wave signal, a third clock signal and a fourth clock signal having two frequencies lower than the square wave signal and not overlapping with each other; The third clock signal and the fourth clock signal serve as chopping frequencies of the chopping amplifier.

4. The frequency locked loop according to claim 3, wherein: The frequency division component includes: a clock generator, responsive to the square wave signal, generating a fifth clock signal; a frequency divider, adapted to divide the frequency of the fifth clock signal and output a sixth clock signal; The non-overlapping clock generator generates two non-overlapping third clock signals and fourth clock signals in response to the sixth clock signal.

5. The frequency locked loop according to claim 1, wherein: Also includes: The load capacitor has one end connected to the output end of the chopper amplifier and the other end connected to the ground signal, and is suitable for suppressing the output ripple of the chopper amplifier.

6. The frequency locked loop according to claim 1, wherein: The switch capacitor module includes: a third capacitor connected in series with the first current module; a third switch connected in series between the third capacitor and the first current module; a fourth switch connected in parallel with the third capacitor; and a fourth capacitor connected in parallel with the third capacitor and the third switch; The third switch and the fourth switch are respectively turned on or off under the action of the first clock signal and the second clock signal, generating an equivalent impedance related to the frequency of the first clock signal and the second clock signal, so that the switched capacitor circuit provides the first voltage to the chopper amplifier under the action of the first current.

7. The frequency locked loop according to claim 1, wherein: The voltage module includes: a second current module, matched with the first current module, the second current module being adapted to provide a second current; and A resistor is connected in series with the second current module to provide the second voltage to the chopper amplifier under the action of the second current.

8. The frequency locked loop according to claim 7, wherein: The voltage module further includes a cut-off module connected in parallel with the resistor, the cut-off module including: a fifth switch; and a sixth switch connected in series with the fifth switch; The fifth switch and the sixth switch are respectively turned on or off under the action of the first clock signal and the second clock signal to cut off the tail current of the second current module.

9. The frequency locked loop according to claim 7, wherein: Also includes: A fifth capacitor is matched with the second capacitor, and the fifth capacitor is connected in parallel with the resistor.

10. A microcontroller, characterized in that: include: The frequency locked loop according to any one of claims 1 to 9; a first power supply, adapted to provide a first supply voltage to the first current module, so that the first current module cooperates with the switch capacitor module to provide the first voltage under the action of the first supply voltage, and The second power supply is adapted to provide a second supply voltage to the voltage module, so that the reference voltage module provides the reference voltage under the action of the second voltage.

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