A pn junction of a photovoltaic cell and a method of manufacturing the same, and a method of manufacturing a photovoltaic cell

Abstract

The application relates to the technical field of photovoltaic cells, and discloses a PN junction of a photovoltaic cell, a preparation method of the PN junction, and a preparation method of the photovoltaic cell. The preparation method of the PN junction comprises the following steps: forming a thickened first intrinsic amorphous silicon layer on the back surface of a silicon wafer; patterning and thinning the first intrinsic amorphous silicon layer of a P region to a normal thickness, so that the first intrinsic amorphous silicon layer of an N region and the first intrinsic amorphous silicon layer of the P region have a thickness difference; after boron doping, the thickness difference is used to control the boron doping concentration of the boron-doped polysilicon layer of the N region and the P region (the greater the thickness of the intrinsic amorphous silicon layer, the smaller the boron doping concentration); in this way, the doping concentration of the boron-doped polysilicon layer of the N region can be reduced to reduce the etching difficulty, and the boron-doped polysilicon layer of the P region can maintain a high doping concentration, so that the production capacity is improved, the problems of the boron-doped polysilicon layers of the N region and the P region caused by the height difference, such as the combination and electrode preparation defects, are avoided, the manufacturing cost is low, the combination caused by mutual doping is avoided, and the electrical performance of the cell is improved.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, specifically to a PN junction of a photovoltaic cell and its preparation method, and a method for preparing a photovoltaic cell. Background Technology

[0002] Back-contact (BC) solar cells are a novel type of photovoltaic device where both the PN junction and the metal electrode contacts are located on the back of the solar cell. BC cells have attracted considerable attention due to their structural design advantages, including the absence of grid lines or electrode obstructions on the front side, which effectively increases the light absorption area, shortens the carrier transport distance, reduces recombination losses, and improves the cell's high-temperature performance and long-term reliability. Currently, the mainstream technology for BC cells employs a dual-mask, dual-laser patterning and grooving process to fabricate the P-region and N-region (i.e., the PN junction) on the back surface. The specific process steps are as follows:

[0003] 1) Texturing is used to remove slicing damage and surface dirt from the original silicon wafer and to create a textured surface on the silicon wafer.

[0004] 2) A tunneling oxide layer and intrinsic Poly-Si (polycrystalline silicon) are sequentially formed on the back side of the silicon wafer using LPCVD (low-pressure chemical vapor deposition).

[0005] 3) Deposit silicon oxide or silicon nitride on the back of the intrinsic polysilicon as a first mask to prevent boron from diffusing into the N-region in subsequent steps.

[0006] 4) Laser patterning (also known as laser selective grooving) of the first mask, and then cleaning the grooved area of ​​the first mask by wet etching. The patterned grooved area of ​​the first mask is the P-region.

[0007] 5) Boron diffusion transforms the intrinsic polysilicon on the back side into P-type polysilicon (also known as boron-doped polysilicon), and forms BSG (borosilicate glass) on the back side of the P-type polysilicon.

[0008] 6) Then deposit silicon oxide or silicon nitride as a second mask on the back of the borosilicate glass to protect the P-type polysilicon from damage by wet etching and subsequent phosphorus diffusion.

[0009] 7) Laser patterning is used to create a second mask, and the grooved area of ​​the second mask, the first mask, and the boron diffusion-formed coating are cleaned by wet etching. The patterned grooved area of ​​the second mask is an N-region.

[0010] 8) Phosphorus diffusion transforms the N-type intrinsic polysilicon reserved on the back side into N-type polysilicon through phosphorus diffusion, and forms PSG (phosphosilicate glass) on the back side of the N-type polysilicon.

[0011] 9) Wet cleaning to remove the second mask, PSG, and BSG; after step 9, finger-shaped intersecting P and N regions are formed on the back side, thus obtaining the PN junction.

[0012] 10) Passivation films are first deposited on both the front and back sides of the silicon wafer after the PN junction is prepared, and then metallization treatment is performed to obtain the finished BC battery.

[0013] However, the complexity of this dual-mask, dual-laser patterning, grooving, and dual-etching process leads to longer production cycles and reduced capacity.

[0014] To simplify the process, existing technologies, such as a method for fabricating a TBC battery published in CN116845140A, do not use a mask after depositing the first polycrystalline silicon layer, and directly perform boron doping on the entire first polycrystalline silicon layer on the back side (i.e., both the P-region and N-region first polycrystalline silicon layers are boron doped). This, in turn, leads to the following problems:

[0015] If the doping concentration of the boron-doped polysilicon layer is ≥5×10 19 If the boron doping concentration (in centimeters cm⁻³) is high, there is a problem that the high boron doping concentration in the N-region cannot be etched away. However, if the doping concentration of the boron doped polysilicon layer is reduced, it will affect the formation and quality of the PN junction, resulting in a weakening of the built-in electric field and affecting the efficiency of carrier separation and collection; at the same time, it will also increase the recombination of minority carriers at the emitter.

[0016] Furthermore, CN118610280A discloses a back-contact solar cell that, while maintaining the same thickness of the N-type doped polycrystalline silicon layer, reduces the thickness of the P-type doped polycrystalline silicon layer. This aims to achieve a high doping concentration of boron-doped polycrystalline silicon in the P-region (i.e., a P-type doped polycrystalline silicon layer) while simultaneously reducing the etching difficulty of removing the high-doped P-type doped polycrystalline silicon layer in the N-region. However, the difficulty of wet etching away the P-type doped polycrystalline silicon layer depends not only on the thickness of the polycrystalline silicon layer but also, and perhaps more importantly, on its doping concentration. A thinner polycrystalline silicon layer makes it easier to obtain a high-doped P-type doped polycrystalline silicon layer. Therefore, reducing the thickness of the P-type doped polycrystalline silicon layer can lead to excessively high doping concentrations, making it difficult to remove by wet etching. Moreover, a thinner P-type doped polycrystalline silicon layer can also lead to insufficient carrier recombination, increasing interfacial recombination and reducing the open-circuit voltage (Voc) and fill factor (FF). Furthermore, the height difference between the P-type doped polysilicon layer in the P-region and the N-type doped polysilicon layer in the N-region can lead to uneven thickness of subsequent metal electrodes deposited in the P-region and N-region, which can easily cause poor local contact or breakage and increase the series resistance (Rsh). On the other hand, lattice stress or dangling bonds are also easily formed at the junction of the height difference between the P-region and N-region doped polysilicon layers, which can become recombination centers and increase recombination. Summary of the Invention

[0017] The purpose of this invention is to overcome the shortcomings of the prior art and provide a PN junction of a photovoltaic cell and its preparation method, as well as a method for preparing a photovoltaic cell.

[0018] Based on this, the present invention discloses a method for preparing a PN junction of a photovoltaic cell, comprising the following preparation steps:

[0019] Step 1: Form a thickened first intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0020] Step 2: Perform patterned thinning of the first intrinsic amorphous silicon layer to subtract the thickening amount of the first intrinsic amorphous silicon layer in the P region, so that a thickness difference is formed between the first intrinsic amorphous silicon layers in the P region and the N region.

[0021] Step 3: Boron doping, which transforms the first intrinsic amorphous silicon layer into a boron-doped polycrystalline silicon layer, and forms borosilicate glass on the back side of the boron-doped polycrystalline silicon layer. The thickness difference is used to make the doping concentration of the boron-doped polycrystalline silicon layer in the P region greater than that in the N region.

[0022] Step 4: Pattern the removal of borosilicate glass in the N-region while retaining borosilicate glass in the P-region; then perform wet etching to remove the boron-doped polysilicon layer in the N-region to expose the back side of the N-region silicon wafer, while the boron-doped polysilicon layer in the P-region is protected and retained by the borosilicate glass in the P-region.

[0023] Step 5, phosphorus doping, to sequentially form a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass on the back side of the silicon wafer after the treatment in step 4;

[0024] Step 6: Pattern the removal of the phosphorus-silicon glass in the P region to expose the phosphorus-doped polysilicon layer in the P region, while retaining the phosphorus-silicon glass in the N region; then perform wet etching to sequentially remove the phosphorus-doped polysilicon layer in the P region, the borosilicate glass in the P region, and the phosphorus-silicon glass in the N region to obtain the PN junction.

[0025] Preferably, step 1 further includes forming a first tunneling oxide layer between the back side of the silicon wafer and the first intrinsic amorphous silicon layer;

[0026] In step 1, the thickness of the first intrinsic amorphous silicon layer is 200–800 nm.

[0027] Preferably, in step 2, the first intrinsic amorphous silicon layer is thinned by laser patterning so that the thickness of the first intrinsic amorphous silicon layer in the P region is reduced to 100-500 nm.

[0028] Preferably, in step 3, the boron doping is performed by boron doping diffusion, and after boron doping diffusion, the doping concentration of the boron-doped polysilicon layer in the P-region is ≥5×10⁻⁶. 19 atoms cm -3. The thickness of the borosilicate glass in the P-region is 60–110 nm, while the doping concentration of the boron-doped polysilicon layer in the N-region is 2 × 10⁻⁶ nm. 19 ~3×10 19 atoms cm - 3. The thickness of the borosilicate glass in the N-region is 50–80 nm.

[0029] Preferably, in step 4, laser patterning is used to remove the borosilicate glass in the N region, and the wet etching is alkaline polishing.

[0030] Preferably, in step 5, before forming the phosphorus-doped polycrystalline silicon layer, a second tunneling oxide layer is first formed on the entire back side of the silicon wafer after step 4.

[0031] In step 5, the phosphorus doping also includes an annealing process in an oxygen atmosphere, during which boron is reactivated to increase the doping concentration of the boron-doped polysilicon layer in the P-region.

[0032] Preferably, in step 6, laser patterning is used to remove the phosphorus glass in the P-region. The wet etching is a low-temperature texturing process that first uses alkaline etching and then acid etching. The texturing temperature is 50-80°C, so that the front side of the silicon wafer is texturized to form a pyramid-shaped textured surface.

[0033] In the low-temperature texturing process, during the alkaline etching process, the phosphorus-doped polysilicon layer in the P region is removed to expose the borosilicate glass in the P region, while the phosphorus-doped polysilicon layer in the N region is protected and retained by the phosphorus-silicon glass in the N region; during the acid etching process, the borosilicate glass in the P region and the phosphorus-silicon glass in the N region are removed.

[0034] Preferably, before step 1, the process further includes polishing and cleaning the surface of the silicon wafer to remove mechanical damage and organic contamination; the silicon wafer is an N-type silicon wafer.

[0035] The present invention also discloses a PN junction for a photovoltaic cell, which is prepared by the PN junction preparation method for a photovoltaic cell described above in the present invention.

[0036] The photovoltaic cell is a BC cell, in which the boron-doped polycrystalline silicon layer in the P region is flush with the back of the phosphorus-doped polycrystalline silicon layer in the N region.

[0037] This invention also discloses a method for preparing a photovoltaic cell, comprising the following preparation steps:

[0038] Step 1: Using the PN junction preparation method for photovoltaic cells described above in this invention, a PN junction is formed on the back side of a silicon wafer;

[0039] Step 2: Form a front passivation antireflection layer and a back passivation antireflection layer on the front and back sides of the silicon wafer processed in Step 1, respectively; then perform metallization to form a first metal electrode of ohmic contact boron-doped polysilicon layer in the P region and a second metal electrode of ohmic contact phosphorus-doped polysilicon layer in the N region.

[0040] Compared with the prior art, the present invention has at least the following beneficial effects:

[0041] The method for preparing the PN junction of the photovoltaic cell of the present invention first forms a thickened first intrinsic amorphous silicon layer on the back of a silicon wafer, and then the first intrinsic amorphous silicon layer in the P region is thinned to a normal thickness in a patterned manner, so that a thickness difference is formed between the first intrinsic amorphous silicon layers in the N region and the P region. After boron doping, the boron doping concentration of the boron-doped polycrystalline silicon layer in the N region and the boron-doped polycrystalline silicon layer in the P region is controlled by this thickness difference (the thicker the intrinsic amorphous silicon layer, the smaller the boron doping concentration), so that the doping concentration of the boron-doped polycrystalline silicon layer in the P region is greater than that in the N region. Therefore, the present invention (1) can reduce the doping concentration of the boron-doped polycrystalline silicon layer in the N region to reduce the difficulty of wet etching, so that the boron-doped polycrystalline silicon layer in the N region can be removed cleanly; (2) can also maintain a high doping concentration of the boron-doped polycrystalline silicon layer in the P region, thereby avoiding the weakening of the built-in electric field caused by the reduction of the boron doping concentration, reducing the recombination of minority carriers at the emitter, and ensuring the quality of the PN junction and the carrier separation efficiency.

[0042] (3) Moreover, compared with the mainstream dual-mask dual-laser patterning and dual-etching process, the PN junction preparation method of the photovoltaic cell of the present invention omits the dual-mask step (specifically: the first mask is omitted, after the first intrinsic amorphous silicon layer of the P region is thinned to the normal thickness by patterning, boron doping is directly performed, and the thickness difference between the first intrinsic amorphous silicon layer of the N region and the P region is used to make the doping concentration of the boron-doped polycrystalline silicon layer in the P region greater than that in the N region, and in the subsequent phosphorus doping process, the borosilicate glass of the P region replaces the second mask); thus, the process can be simplified and the production capacity of BC cells can be improved.

[0043] (4) Compared with the existing technology CN118610280A, it also avoids a series of problems caused by the height difference between the phosphorus-doped polysilicon layer in the N region and the boron-doped polysilicon layer in the P region of the PN junction: such as the increased interfacial recombination due to the thinner P-type doped polysilicon layer in the P region, which reduces Voc and FF; such as the impact on the uniformity of the subsequent metal electrodes in the P and N regions, which leads to poor local contact or breakage, increasing Rsh; such as the easy formation of lattice stress or dangling bonds at the junction of the height difference between the doped polysilicon layers in the P and N regions, which becomes a recombination center and increases recombination, etc.

[0044] (5) Compared to purchasing lasers with better mask grooving effects, the PN junction fabrication method of this invention can significantly reduce production costs. Furthermore, compared to increasing the wet etching temperature and extending the wet etching time (to address the etching difficulty of the boron-doped polysilicon layer), the PN junction fabrication method of this invention can avoid excessive wet etching. During the wet etching process, it protects the thickness of the P-region borosilicate glass (BSG) from excessive thinning, which could lead to phosphorus doping into the boron-doped polysilicon layer in the P-region and boron doping into the phosphorus-doped polysilicon layer in the N-region due to the excessively thin P-region BSG during subsequent annealing processes. This avoids recombination caused by interdoping and helps improve the conversion efficiency of the BC cell. It also maintains the core performance characteristics of the BC cell: no electrode obstruction on the front side, high light absorption, and low recombination loss. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the preparation process of a photovoltaic cell preparation method according to the present invention.

[0046] Figure 2 This is a schematic diagram of the structure of a photovoltaic cell according to the present invention.

[0047] Figure 3 This is a laser microscope image showing the etching depth of the N-region boron-doped polysilicon layer after alkaline polishing in step S6 of Example 1.

[0048] Figure 4 This is a laser microscope image showing the etching depth of the N-region boron-doped polysilicon layer after alkaline polishing in step S5 of Comparative Example 1.

[0049] Explanation of reference numerals: 1. Front silicon nitride layer; 2. Front aluminum oxide layer; 3. Silicon wafer; 4. First tunneling oxide layer; 5. Boron-doped polycrystalline silicon layer; 6. Second tunneling oxide layer; 7. Phosphorus-doped polycrystalline silicon layer; 8. Back aluminum oxide layer; 9. Back silicon nitride layer; 10. First metal electrode; 11. Second metal electrode. Detailed Implementation

[0050] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Example 1

[0052] This embodiment describes a method for preparing a photovoltaic cell, see [link to relevant documentation]. Figure 1-2 The preparation steps include the following:

[0053] S1. Select an N-type monocrystalline silicon wafer 3 (N-Si) and use a tank-type alkaline polishing machine containing KOH solution to polish both sides of the silicon wafer 3 to remove mechanical damage and organic contamination.

[0054] S2. Using LPCVD (low-pressure chemical vapor deposition), a first tunneling oxide layer 4 (SiOx) and a first intrinsic amorphous silicon layer (i-Poly Si) are sequentially deposited on the back side of the silicon wafer 3 after the treatment in step S1.

[0055] In step S2, the thickness of the deposited first intrinsic amorphous silicon layer is increased to 400 nm.

[0056] In step S2, the thickness of the first tunneling oxide layer 4 is 1-5 nm (e.g., 2 nm) to prevent boron from diffusing into the silicon wafer 3 and causing recombination due to the PN junction being too deep after subsequent boron diffusion.

[0057] S3. Perform laser patterning thinning (i.e., laser selective thinning) on ​​the thickened first intrinsic amorphous silicon layer to reduce the first intrinsic amorphous silicon layer in the P region to 200nm (i.e., reduce to the normal thickness, which is the same as the thickness of the subsequent second intrinsic amorphous silicon layer), and the width of the thinned region (corresponding to the P region) is 500μm; thereby creating a thickness difference between the first intrinsic amorphous silicon layers in the P region and the N region, so that the boron doping concentration in the P region and the N region can be controlled by the thickness difference of the first intrinsic amorphous silicon layer.

[0058] In step S3, the process conditions for laser patterning thinning are as follows: a green picosecond laser is used, with a square laser spot size of 200μm × 200μm, a laser frequency of 500kHz, a laser output power of 30W, and a laser speed of 45000mm / min. -1 .

[0059] S4. Boron diffusion is performed on the patterned, thinned first intrinsic amorphous silicon layer using BCl3 as the dopant source. Doping is achieved through thermal diffusion, transforming the first intrinsic amorphous silicon layer into a boron-doped polycrystalline silicon layer 5 (i.e., a P-type polycrystalline silicon layer, P-PolySi). The average doping concentration of the boron-doped polycrystalline silicon layer 5 in the thinned region is 5.9 × 10⁻⁶. 19 The boron-doped polysilicon layer 5 in the thinned region has a thickness of 90–95 nm (e.g., 93 nm) and a BSG (borosilicate glass) layer on the back side. The average doping concentration of the boron-doped polysilicon layer 5 in the non-thinned region is ≤3 × 10⁻³. 19 atoms cm - 3 (It can be seen that the boron doping concentration of the boron-doped polysilicon layer 5 in the thinned region is greater than that in the non-thinned region), and a BSG with a thickness of 62-65 nm (e.g., 63 nm) is formed on the back side of the boron-doped polysilicon layer 5 in the non-thinned region (the BSG thickness in the P region is greater than that in the N region, which is beneficial for the BSG in the P region to play a better masking role during subsequent phosphorus doping to avoid cross-doping).

[0060] S5. Laser patterning is used to remove BSG from the N-region (corresponding to the non-thinning region), with a removal width of 500μm.

[0061] In step S5, the process conditions for laser patterning removal of BSG are as follows: a green picosecond laser is used, with a square laser spot size of 200μm × 200μm, a laser frequency of 500kHz, a laser output power of 56W, and a laser speed of 25000mm / min. -1 .

[0062] S6. The back side of the silicon wafer 3 after step S5 is subjected to alkaline polishing (a wet etching process). The alkaline solution used for alkaline polishing is a mixed solution of 1.5% NaOH solution and 0.37% polishing additive. The alkaline polishing time is 180s. Since the doping concentration of the boron-doped polysilicon layer 5 in the non-thinned region (N-region) is lower than that in the thinned region, the boron-doped polysilicon layer 5 in the N-region is easily removed by alkaline polishing etching, thereby forming a polished morphology and exposing the back side of the silicon wafer 3 in the N-region. However, due to the protection of BSG, the boron-doped polysilicon layer 5 in the P-region is not damaged during the alkaline polishing process in step S6 and is thus preserved.

[0063] S7. Using a POPAID device (plasma deposition and automation integration equipment), a second tunneling oxide layer 6 (SiOx) and a second intrinsic amorphous silicon layer (i-Poly Si) are sequentially deposited on the entire back side of the silicon wafer 3 after the treatment in step S6. The thickness of the second tunneling oxide layer 6 is 1-5 nm (e.g., 2 nm), and the deposition temperature is 550 °C. The thickness of the second polycrystalline silicon layer is 200 nm, and the deposition temperature is 550 °C. Then, after high-temperature oxygen atmosphere annealing, phosphorus source is doped into the second intrinsic amorphous silicon layer, so that the second intrinsic amorphous silicon layer is annealed to form a phosphorus-doped polycrystalline silicon layer 7 (i.e., N-type polycrystalline silicon layer, N-Poly Si). A 50 nm thick PSG (phosphosilicate glass) is formed on the back side of the phosphorus-doped polycrystalline silicon layer 7. At the same time, during the high-temperature oxygen atmosphere annealing process, the boron in the BSG and boron-doped polycrystalline silicon layer 5 will be reactivated to form effective doping, so as to increase the doping concentration of the boron-doped polycrystalline silicon layer 5.

[0064] In step S7, the second tunneling oxide layer 6, the phosphorus-doped polysilicon layer 7, and the PSG are formed not only on the back side of the exposed silicon wafer 3 in the N-region, but also on the back side of the BSG in the P-region. During the oxygen atmosphere annealing process, the BSG in the P-region acts as a mask to protect the boron-doped polysilicon layer 5 in the P-region, preventing recombination caused by phosphorus interdoping.

[0065] S8. The PSG in the P region is removed by laser patterning, with a removal width of 500μm.

[0066] In step S8, the process conditions for laser patterning removal of PSG in the P-region are as follows: a green picosecond laser is used, with a square laser spot size of 200μm×200μm, a laser frequency of 500kHz, a laser output power of 30W, and a laser speed of 25000mm / min. -1 .

[0067] S9. After step S8, a low-temperature texturing process is performed on the silicon wafer 3 using a tank-type machine to form a pyramid-shaped textured surface on the front side of the silicon wafer 3. The texturing temperature is set to 65°C. The specific process of the low-temperature texturing is as follows: first, the silicon wafer 3 is placed in an alkaline bath for etching, and then placed in an acid bath for etching. At the same time, during the alkaline bath etching process, after the PSG in the P-region on the back side of the silicon wafer 3 is removed by laser patterning, the phosphorus-doped polysilicon layer 7 in the P-region is exposed. Therefore, the phosphorus-doped polysilicon layer 7 and the second tunneling oxide layer 6 in the P-region can be removed by wet etching in the alkaline bath to expose the BSG in the P-region. The N-region on the back side of the silicon wafer 3 forms PSG during the oxygen atmosphere annealing process in step S7 (the annealing in the oxygen atmosphere in step S7 also helps to increase the thickness of the PSG in the N-region). This PSG can withstand the corrosion of low-temperature KOH alkaline solution. Therefore, due to the protection of the PSG, the phosphorus-doped polysilicon layer 7 in the N-region is not damaged and is preserved during the alkaline bath etching process. Then, during the acid bath etching process, the BSG in the P region and the PSG in the N region can be removed.

[0068] Therefore, after step S9, the P-region and N-region can be prepared, forming a PN junction (i.e., Figure 1 The n region shown + BSF and P area p + E).

[0069] S10. A double-sided ALD (Atomic Layer Deposition) passivation layer (such as an alumina layer) is deposited on the silicon wafer 3 after step S9, forming a front alumina layer 2 on the front side of the silicon wafer 3, and a back alumina layer 8 on the back side of the phosphorus-doped polysilicon layer 7 in the N-region and the boron-doped polysilicon layer 5 in the P-region. In step S10, the thickness of both the front alumina layer 2 and the back alumina layer 8 is 13–15 nm (e.g., 14 nm). This reduces the surface defect state density and improves carrier collection efficiency through both chemical passivation and field-effect passivation.

[0070] S11. A double-sided PECVD antireflection layer (such as a silicon nitride layer) is deposited on the silicon wafer 3 after step S10, so as to form a front silicon nitride layer 1 and a back silicon nitride layer 9 on the front side of the front aluminum oxide layer 2 and the back side of the back aluminum oxide layer 8, respectively. In step S11, the thickness of the front silicon nitride layer 1 and the back silicon nitride layer 9 is 75-85 nm (such as 80 nm).

[0071] S12. The P-region and N-region on the back side of the silicon wafer 3 after step S11 are metallized by screen printing and sintering to prepare the first metal electrode 10 of the ohmic contact boron-doped polycrystalline silicon layer 5 in the P-region and the second metal electrode 11 of the ohmic contact phosphorus-doped polycrystalline silicon layer 7 in the N-region, so as to achieve efficient collection and conduction of charge carriers.

[0072] After processing in step S12, the following can be obtained: Figure 2 The photovoltaic cell shown is a type of BC cell.

[0073] Comparative Example 1

[0074] The preparation method of this comparative example of a photovoltaic cell is specifically described in accordance with Example 1, except that:

[0075] Replace steps S2-S4 of Example 1 with steps S2-S3 of this comparative example (that is, this comparative example omits the laser patterning thinning of the first intrinsic amorphous silicon layer in the P-region in step S3 of Example 1; in step S2 of this comparative example, after directly depositing a 200nm thick first intrinsic amorphous silicon layer on the back side of the silicon wafer, step S3 of this comparative example directly performs boron diffusion on the first intrinsic amorphous silicon layer):

[0076] S2. Using PECVD, a first tunneling oxide layer (with the same thickness as the first tunneling oxide layer in Example 1) and a 200 nm thick first intrinsic amorphous silicon layer are sequentially deposited on the back side of the silicon wafer after the treatment in step S1.

[0077] S3. Boron diffusion is performed on the first intrinsic amorphous silicon layer using BCl3 as the dopant source. Doping is achieved through thermal diffusion, transforming the first intrinsic amorphous silicon layer into one with an average doping concentration of 5.9 × 10⁻⁶. 19 A boron-doped polysilicon layer (i.e., P-type polysilicon layer, P-Poly-Si) with atoms cm-3 is formed on the back side of the boron-doped polysilicon layer, and a BSG with a thickness of 62-65 nm (e.g., 63 nm) is formed.

[0078] Step S1 of this comparative example refers to step S1 of Example 1, and steps S4-S11 of this comparative example refer to steps S5-S12 of Example 1.

[0079] Performance testing

[0080] The performance of the BC batteries from Example 1 and Comparative Example 1 was tested, and the test results are shown in Table 1 below:

[0081] Table 1

[0082] Eta(%) Voc(mV) FF (%) <![CDATA[Jsc(mA / cm 2 ) <!-- 6 -->]]> Example 1 26.24 732.35 79.82 14.97 Comparative Example 1 18.67 619.84 72.56 13.88

[0083] Table 1 shows that Eta is the battery conversion efficiency, Voc is the open-circuit voltage, FF is the fill factor, and Jsc is the short-circuit current density.

[0084] Combining Table 1 and Figure 3-4 As can be seen, compared with Example 1, Comparative Example 1 directly deposits a 200nm thick first intrinsic amorphous silicon layer on the back side of the silicon wafer, omitting the laser patterning thinning step S3 of Example 1 to reduce the first intrinsic amorphous silicon layer in the P-region. Therefore, compared with Example 1, the boron-doped polycrystalline silicon layer in the N-region on the back side of the silicon wafer in Comparative Example 1 has a higher doping concentration, which makes it easier for etching residues and cleaning difficulties to occur during subsequent alkaline polishing (a wet etching process) (see...). Figure 3-4 After the alkaline polishing treatment in step S6, the etching depth of the boron-doped polysilicon layer in the N-region of Example 1 was significantly greater than that in Comparative Example 1. The residual boron-doped polysilicon layer in the N-region affected the built-in electric field of the PN junction, thus impacting the electrical performance of the BC battery. Therefore, the electrical performance data of the BC battery in Comparative Example 1, such as Eta, Voc, FF, and Jsc, were all inferior to those in Example 1.

[0085] Moreover, compared to the mainstream dual-mask, dual-laser patterning, grooving, and dual-etching process, the PN junction fabrication method for the BC cell in this embodiment omits the dual-mask step (specifically in this embodiment: the first mask is omitted, and after the laser patterning thinning of the first intrinsic amorphous silicon layer in the P region in step S3, the boron diffusion process in step S4 is directly performed to form a boron-doped polycrystalline silicon layer, and in the subsequent step S7, the BSG in the P region replaces the second mask). The process flow is also optimized by placing the texturing process of the silicon wafer in step S9 (instead of the mainstream dual-mask, dual-laser patterning, grooving, and dual-etching process: texturing is placed in step 1) to omit the wet cleaning step after phosphorus diffusion. In this way, the process can be simplified and the production capacity of the BC cell can be improved.

[0086] Furthermore, compared to the prior art CN116845140A, the BC battery of this embodiment combines the thickening of the first intrinsic amorphous silicon layer in step S2 with the laser patterning thinning of the first intrinsic amorphous silicon layer in the P region to a normal thickness in step S3. While maintaining a high boron doping concentration in the P-type polycrystalline silicon layer in the P region, it also makes the low boron doping concentration P-type polycrystalline silicon layer in the N region easier to be etched and removed by the alkaline polishing process in step S6. Therefore, it also overcomes the problems of etching residue and cleaning difficulties in the N region. In addition, it avoids the weakening of the built-in electric field caused by reducing the boron doping concentration, reduces the recombination of minority carriers at the emitter, and ensures the quality of the PN junction and the carrier separation efficiency.

[0087] Furthermore, compared with the prior art CN118610280A, the PN junction preparation method of the BC battery of the present invention also has the following advantages:

[0088] 1. This invention adds a first tunneling oxide layer to prevent boron from diffusing into the silicon wafer and causing recombination due to excessive PN junction depth after subsequent boron diffusion. Moreover, the tunneling oxide layer and the doped polycrystalline silicon layer together form a passivation contact structure (which acts as a passivator, reduces surface recombination, and allows for effective carrier transport), which can improve the passivation and contact performance of the BC battery.

[0089] 2. The difficulty of wet etching away P-type doped polysilicon layers is related not only to the thickness of the polysilicon layer but also, and perhaps more importantly, to its doping concentration. A thinner polysilicon layer makes it easier to achieve a high doping concentration of P-type doped polysilicon. Therefore, existing technology CN118610280A, by reducing the thickness of the P-type doped polysilicon layer while keeping the N-type doped polysilicon layer thickness unchanged, results in an excessively high doping concentration, making wet etching difficult. Furthermore, a thinner P-type doped polysilicon layer also increases the likelihood of incomplete carrier recombination, increasing interface recombination and reducing the open-circuit voltage (Voc) and fill factor (FF).

[0090] In this invention, the first intrinsic amorphous silicon layer is thickened in step S2, and then the first intrinsic amorphous silicon layer in the P region is thinned to a normal thickness by laser patterning in step S3. By using the thickness difference between the first intrinsic amorphous silicon layers in the N region and the P region, after boron diffusion in step S4, the boron doping concentration of the boron-doped polycrystalline silicon layer in the N region and the P region is controlled by the thickness difference (the greater the thickness of the first intrinsic amorphous silicon layer, the smaller the boron doping concentration of the resulting boron-doped polycrystalline silicon layer). This can reduce the boron doping concentration of the boron-doped polycrystalline silicon layer in the N region to reduce its etching difficulty, while maintaining a higher boron doping concentration in the boron-doped polycrystalline silicon layer in the P region.

[0091] 3. The BC battery prepared by this invention has a boron-doped polycrystalline silicon layer in the P region and a phosphorus-doped polycrystalline silicon layer in the N region with the back side flush and no height difference. Therefore, it can effectively overcome a series of problems caused by the height difference between the boron-doped polycrystalline silicon layer in the P region and the phosphorus-doped polycrystalline silicon layer in the N region in the prior art CN118610280A. It is more conducive to improving the quality of the subsequently prepared metal electrode and reducing recombination, which in turn is beneficial to improving the electrical performance of the BC battery.

[0092] Furthermore, compared to purchasing lasers with better mask grooving effects, the method of this invention can significantly reduce production costs. Moreover, compared to increasing the wet etching temperature and extending the wet etching time (to address the etching difficulty of boron-doped polysilicon layers), the method of this invention can protect the P-region BSG thickness from excessive thinning during wet etching, preventing phosphorus doping into the boron-doped polysilicon layer in the P-region and boron doping into the phosphorus-doped polysilicon layer in the N-region due to excessively thin P-region BSG during subsequent annealing processes. This avoids recombination caused by cross-doping and helps improve the conversion efficiency of BC cells.

[0093] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0094] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for preparing a PN junction in a photovoltaic cell, characterized in that, The preparation steps include the following: Step 1: Form a thickened first intrinsic amorphous silicon layer on the back side of the silicon wafer; Step 2: Perform patterned thinning of the first intrinsic amorphous silicon layer to subtract the thickening amount of the first intrinsic amorphous silicon layer in the P region, so that a thickness difference is formed between the first intrinsic amorphous silicon layers in the P region and the N region. Step 3: Boron doping, which transforms the first intrinsic amorphous silicon layer into a boron-doped polycrystalline silicon layer, and forms borosilicate glass on the back side of the boron-doped polycrystalline silicon layer. The thickness difference is used to make the doping concentration of the boron-doped polycrystalline silicon layer in the P region greater than that in the N region. Step 4: Pattern the removal of borosilicate glass in the N-region while retaining borosilicate glass in the P-region; then perform wet etching to remove the boron-doped polysilicon layer in the N-region to expose the back side of the N-region silicon wafer, while the boron-doped polysilicon layer in the P-region is protected and retained by the borosilicate glass in the P-region. Step 5, phosphorus doping, to sequentially form a phosphorus-doped polycrystalline silicon layer and a phosphorus-silicon glass on the back side of the silicon wafer after the treatment in step 4; Step 6: Pattern the removal of the phosphorus-silicon glass in the P region to expose the phosphorus-doped polysilicon layer in the P region, while retaining the phosphorus-silicon glass in the N region; then perform wet etching to sequentially remove the phosphorus-doped polysilicon layer in the P region, the borosilicate glass in the P region, and the phosphorus-silicon glass in the N region to obtain the PN junction.

2. The method for preparing a PN junction of a photovoltaic cell according to claim 1, characterized in that, Step 1 also includes forming a first tunneling oxide layer between the back side of the silicon wafer and the first intrinsic amorphous silicon layer; In step 1, the thickness of the first intrinsic amorphous silicon layer is 200–800 nm.

3. The method for preparing a PN junction of a photovoltaic cell according to claim 1, characterized in that, In step 2, the first intrinsic amorphous silicon layer is thinned by laser patterning to reduce the thickness of the first intrinsic amorphous silicon layer in the P region to 100-500 nm.

4. The method for preparing a PN junction of a photovoltaic cell according to claim 1, characterized in that, In step 3, the boron doping is performed by boron doping diffusion. After boron doping diffusion, the doping concentration of the boron-doped polysilicon layer in the P-region is ≥5×10⁻⁶. 19 atoms cm -3 The thickness of the borosilicate glass in the P-region is 60–110 nm, while the doping concentration of the boron-doped polysilicon layer in the N-region is 2 × 10⁻⁶. 19 ~3×10 19 atoms cm - 3. The thickness of the borosilicate glass in the N-region is 50–80 nm.

5. The method for preparing a PN junction of a photovoltaic cell according to claim 1, characterized in that, In step 4, laser patterning is used to remove the borosilicate glass in the N region, and the wet etching is alkaline polishing.

6. The method for preparing a PN junction of a photovoltaic cell according to claim 1, characterized in that, In step 5, before forming the phosphorus-doped polycrystalline silicon layer, a second tunneling oxide layer is first formed on the entire back side of the silicon wafer after step 4. In step 5, the phosphorus doping also includes an annealing process in an oxygen atmosphere, during which boron is reactivated to increase the doping concentration of the boron-doped polysilicon layer in the P-region.

7. The method for preparing a PN junction of a photovoltaic cell according to claim 1, characterized in that, In step 6, laser patterning is used to remove the phosphorus glass in the P-region. The wet etching is a low-temperature texturing process that first uses alkaline etching and then acid etching. The texturing temperature is 50-80°C, which forms a pyramid-shaped textured surface on the front side of the silicon wafer. In the low-temperature texturing process, during the alkaline etching process, the phosphorus-doped polysilicon layer in the P region is removed to expose the borosilicate glass in the P region, while the phosphorus-doped polysilicon layer in the N region is protected and retained by the phosphorus-silicon glass in the N region; during the acid etching process, the borosilicate glass in the P region and the phosphorus-silicon glass in the N region are removed.

8. The method for preparing a PN junction of a photovoltaic cell according to claim 1, characterized in that, Before step 1, the process includes polishing and cleaning the surface of the silicon wafer to remove mechanical damage and organic contamination; the silicon wafer is an N-type silicon wafer.

9. A PN junction for a photovoltaic cell, characterized in that, It is prepared by the PN junction preparation method of a photovoltaic cell according to any one of claims 1-8; The photovoltaic cell is a BC cell, in which the boron-doped polycrystalline silicon layer in the P region is flush with the back of the phosphorus-doped polycrystalline silicon layer in the N region.

10. A method for preparing a photovoltaic cell, characterized in that, The preparation steps include the following: Step 1: A PN junction is formed on the back side of a silicon wafer using the PN junction fabrication method of any one of claims 1-8. Step 2: Form a front passivation antireflection layer and a back passivation antireflection layer on the front and back sides of the silicon wafer processed in Step 1, respectively; then perform metallization to form a first metal electrode of ohmic contact boron-doped polysilicon layer in the P region and a second metal electrode of ohmic contact phosphorus-doped polysilicon layer in the N region.

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