Method and system for thermally aware electromigration evaluation and circuit design

Abstract

A method includes identifying a structure of interest in an IC design; assigning a heat affected region to a region of the IC design, the region containing at least a portion of the structure of interest; identifying a plurality of structures, all or part of which are located in the heat affected zone, and which correspond to IC device elements that are self-heated during operation of the IC device based on the IC design; modeling a corresponding plurality of operating temperatures for the plurality of structures, and identifying a highest temperature of the plurality of operating temperatures; identifying, among the plurality of structures, a structure having the highest temperature as a first adjacent structure; specifying a rating factor according to a distance between the structure of interest and the first adjacent structure; and modeling an operating temperature of the structure of interest according to the maximum temperature and the rating factor.

Description

Technical Field

[0001] The present disclosure relates to a method and system, and more particularly to a method and system for thermal-aware electromigration evaluation and circuit design. Background Art

[0002] Current passing through a conductive line causes electromigration (EM), which is the movement of atoms due to momentum transfer between electrons (the current flowing through the line) and atoms (the atoms that make up the line). In metal lines, electromigration can cause hillocks (accumulation of excess metal) and / or voids (depletion of the original metal) in the metal line over time, which can lead to shorts (hillocks) or opens (voids).

[0003] The mean time to failure (MTTF) of a conductive line due to electromigration is estimated by considering multiple operating factors, such as the size of the conductive line, the composition of the conductive line, the microstructure of the conductive line, the current density carried by the conductive line, the duty cycle of the current applied to the conductive line, and the operating temperature of the conductive line. Electromigration assessment, analysis, and signoff methods applied to a particular integrated circuit (IC) design attempt to consider at least some of these operating factors in order to provide an estimate of the lifetime of an IC device manufactured using the IC design to avoid premature failure of the IC device. Summary of the Invention

[0004] The present disclosure provides a method for evaluating thermal effects in an integrated circuit (IC) design, the method comprising: identifying a structure of interest in the IC design; assigning a heat-affected region to a region of the IC design such that the heat-affected region includes at least a portion of the structure of interest; identifying a plurality of structures that are entirely or partially within the heat-affected region and correspond to IC device components that self-heat during operation of the IC device based on the IC design; modeling a plurality of operating temperatures corresponding to the plurality of structures and identifying a highest temperature among the plurality of operating temperatures; identifying the structure having the highest temperature as a first adjacent structure among the plurality of structures; assigning a rating factor based on a distance between the structure of interest and the first adjacent structure; modeling an operating temperature for the structure of interest based on the highest temperature and the rating factor; evaluating temperature-dependent electromigration parameters of the structure of interest at the operating temperature of the structure of interest; and generating a revised IC design by revising the IC design, wherein generating the revised IC design includes revising current specifications of the structure of interest based on the evaluation of the temperature-dependent electromigration parameters.

[0005] The present disclosure provides a method for manufacturing an integrated circuit (IC) device, the method comprising: identifying a structure of interest in a first IC design; assigning a heat-affected region (HAZ) to a region of the first IC design such that the HZ includes at least a portion of the structure of interest; identifying a plurality of structures that are entirely or partially located within the HZ and correspond to IC device components that self-heat during operation of the IC device based on the first IC design; modeling a plurality of operating temperatures corresponding to the plurality of structures and identifying a highest temperature among the plurality of operating temperatures; identifying a structure having the highest temperature among the plurality of structures as a first adjacent structure; calculating a first temperature rise by multiplying the highest temperature by a temperature rise ratio, the temperature rise ratio being a number less than 1 and greater than 0; modeling a first operating temperature for the structure of interest; evaluating a temperature-dependent electromigration parameter of the structure of interest at a second operating temperature, the second operating temperature being at least the sum of the first operating temperature and the first temperature rise; revising a current specification of the structure of interest based on the evaluation of the temperature-dependent electromigration parameter; and generating a second IC design by revising the first IC design to include the revised current specification of the structure of interest.

[0006] The present disclosure provides a system for evaluating electromigration, comprising: at least one memory configured to store device layout design data and device layout thermal equations; at least one processor configured to: access the at least one memory and obtain the device layout design data and the device layout thermal equations; generate a device layout design based on the device layout design data; identify a structure of interest in the device layout design; assign a heat-affected region to a region of the device layout design such that the heat-affected region includes at least a portion of the structure of interest; identify a plurality of structures that are entirely or partially located within the heat-affected region and correspond to device elements that self-heat during operation of a device based on the device layout design; model a plurality of operating temperatures corresponding to the plurality of structures and identify a highest temperature among the plurality of operating temperatures; identify the structure having the highest temperature as a first adjacent structure among the plurality of structures; assign a ranking factor based on a distance between the structure of interest and the first adjacent structure; model the operating temperature of the structure of interest based on the highest temperature and the ranking factor; and generate a revised device layout design by revising the device layout design, wherein generating the revised device layout design includes revising a current specification of the structure of interest based on an evaluation of the temperature-dependent electromigration parameter. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figure 1 It is a schematic diagram of the electromigration process within a metal line;

[0009] Figure 2 is a schematic diagram of thermal coupling between components according to some embodiments;

[0010] Figure 3A and Figure 3B is a schematic diagram of thermal coupling between conductive lines according to some embodiments;

[0011] Figure 4 is a schematic diagram of an electromigration tool 400 useful in the operation of an electromigration signoff method according to some embodiments;

[0012] Figure 5 is a flow chart of a method 500 for calculating a temperature increase of a conductive line due to heating from one or more adjacent conductive lines, according to some embodiments;

[0013] Figure 6 is a flow chart of a method 600 for performing electromigration evaluation according to some embodiments;

[0014] Figure 7 is a schematic diagram of an electronic design automation system 700 useful in operation of an electromigration signoff method, according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides different embodiments or examples for realizing the provided subject matter. In order to simplify the present disclosure, specific examples of elements, materials, numerical values, steps, arrangements, etc. are described below. These are of course only examples and are not limiting. Other elements, materials, numerical values, steps, arrangements, etc. are also contemplated. For example, in the following description, a first feature formed on or above a second feature may include an embodiment in which the first and second features are directly in contact with each other, or may include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] IC devices, such as semiconductor devices, tend to increase in temperature during operation due to self-heating effects (SHE). These self-heating effects tend to limit the performance capabilities and operating life of the affected IC devices. For example, self-heating effects in IC devices, such as self-heating in active structures (e.g., transistors or active regions) or other resistive structures, tend to degrade device performance and reliability.

[0018] Therefore, some IC designs utilize conductive lines and interconnecting vias as heat sinks for temperature control. However, such heat dissipation techniques can increase the operating temperature of the conductive lines. Heat from active structures or other resistive structures, when coupled with the inherent IR heating (also known as ohmic or Joule heating) of the conductive lines, can increase the risk of accelerated electromigration-related failures in the conductive lines. Device designers have attempted to address the increased risk of electromigration in the conductive lines to some extent by modifying IC design and / or operating parameters, but such design compromises tend to reduce density, degrade performance, and / or increase the size of the resulting IC device.

[0019] IC devices based on fin field-effect transistors (FinFETs) tend to offer significant power, performance, and area advantages over semiconductor devices based on planar transistors. However, FinFET-based IC designs tend to exhibit greater local current density, which in turn leads to greater problems with electromigration failures in the conductive lines that form the interconnects for signal and power rails within FinFET-based IC devices.

[0020] In some cases, a FinFET-based semiconductor device includes a substrate including an active region (AR) and a guard ring, wherein a source and a drain are formed in the active region, a plurality of conductive line layers are separated by layers of interlayer dielectric (ILD) material, and vias are formed through the ILD material to establish electrical connections to and between the conductive line layers. Depending on the specific IC design, heat generated in the active region reaches the conductive lines adjacent to the active region, for example, by thermal conduction through an intermediate layer or by thermal conduction through connecting vias, conductive lines, etc.

[0021] The available heat dissipation paths in FinFET IC designs are limited by the fin structure. Consequently, there are areas and / or structures in the IC design where self-heating effects lead to increased operating temperatures, increasing the likelihood of accelerated electromigration degradation. In some IC designs, a 10°C temperature increase in a conductive line can increase electromigration degradation of the conductive line by 50%. For example, a 10°C temperature increase in a conductive line can reduce the conductive line specification from a 1 microampere (μA) specification to a 0.5 μA specification. Concerns regarding self-heating effects tend to increase with the reduction in structure size associated with more advanced process nodes and / or high-speed / high-performance IC designs.

[0022] Figure 1 Schematic diagram of the electromigration process within a conductive line.

[0023] Reference Figure 1 When current flows through a conductive line (such as a metal line), electromigration may occur, in which electrons transfer part of their momentum to atoms in the conductive line (such as metal atoms), thereby tending to cause the metal atoms to move in the direction of electron flow.

[0024] exist Figure 1 In FIG, a conductive line 100 includes a conductive line segment 102, which is composed of a plurality of atoms 104 (e.g., atoms of aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), platinum (Pt), cobalt (Co), nickel (Ni), etc.), or atoms of alloying elements such as nitrogen (N) and silicon (Si). Conductive line 102 is a conductive path for electrons 106 to move between a cathode and an anode. During operation of an IC device, electrons 106 repeatedly transfer momentum to atoms 104, which can gradually displace metal atoms 104 from their original positions, thereby increasing the non-uniformity of conductive line 102.

[0025] In those areas of the conductive line 100 where the movement of atoms 104 reduces the cross-sectional area of ​​the conductive line 100, the current density will increase, further exacerbating the self-heating effect and electromigration in the thinned areas. The conductive line 100 with such thinned areas may exhibit increased resistance and / or reduced performance, and the conductive line 100 may eventually degrade and result in voids or open circuits. Conversely, in those areas of the conductive line 100 where the movement of atoms 104 increases the cross-sectional area of ​​the conductive line 100, the thickened areas (e.g., loose) may stress the surrounding materials and ultimately compromise the structural integrity of the surrounding materials and / or form shorts with adjacent conductive lines or other conductors.

[0026] To help reduce or eliminate electromigration-induced failures, design rules associated with the manufacturing process include electromigration rules to limit the average current density through the conductive line 100 and to consider the temperature of the conductive line 100 during operation of the IC device, including the temperature contribution of self-heating in the conductive line 100. IC designs that pass applicable electromigration rules are approved for electromigration signoff and tape-out.

[0027] Additional self-heating effects can be modeled or estimated to increase the temperature of the transistor structure by a specific amount ΔT. At least a portion of the self-heating effect that generates ΔT will be transferred back to adjacent conductive lines, for example, through direct contact with the transistor, conduction through intervening materials (e.g., ILD materials or layers), etc. In some embodiments, in addition to the self-heating effects associated with the transistors and / or active regions, other high-resistance (Hi-R) structures (e.g., resistors) in the IC device can also generate additional heating of adjacent conductive lines.

[0028] Electromigration assessment methods that fail to recognize and compensate for increases in the operating temperature of the conductive line 100 risk underestimating the increased operating temperature of the conductive line 100. Underestimating the operating temperature of the conductive line 100 may produce overly optimistic electromigration assessment results, leading to an overestimation of the average lifespan of IC devices manufactured according to the design and / or causing premature field failures of affected IC devices.

[0029] To improve electromigration assessment, the electromigration assessment should identify and account for those portions of the IC design where self-heating effects are expected to increase the operating temperature of at least a portion of the conductive lines.

[0030] In some embodiments, electromigration assessment includes using equation-based device temperature calculations, estimating thermal coupling ranges and effects using a thermal model, generating estimated conductive line temperatures, and performing electromigration confirmation checks at the estimated conductive line temperatures to compensate for self-heating effects and improve the accuracy of the electromigration assessment.

[0031] Figure 2 is a schematic diagram of thermal coupling between components according to some embodiments.

[0032] exist Figure 2 In the embodiment, semiconductor structure 200 includes substrate 201 (eg, semiconductor substrate), transistor / AR structure 202, high resistance structure 204, conductive line 206 (conductive line of interest, CLi), and adjacent conductive line 210 (CLn), all of which are embedded in ILD structure 208.

[0033] exist Figure 2In the embodiment, the transistor / AR structure 202, the high resistance structure 204, the conductive line 206 of interest, the adjacent conductive line 210, and the ILD structure 208 are arranged on the first surface 201a of the substrate 201. In other embodiments, one or more of the transistor / AR structure 202, the high resistance structure 204, the conductive line 206, the adjacent conductive line 210, the ILD structure 208, etc. are arranged below the second surface 201b of the substrate 201. In other embodiments, one or more of the transistor / AR structure 202, the high resistance structure 204, the conductive line 206, the adjacent conductive line 210, the ILD structure 208, etc. are arranged both above the first surface 201a and below the second surface 201b of the substrate 201. In some embodiments, one or more of the transistor / AR structure 202, the high resistance structure 204, the conductive line 206, the adjacent conductive line 210, the ILD structure 208, etc. are arranged within the substrate 201.

[0034] Electromigration evaluation according to some embodiments includes considering the conductive line of interest CLi (at Figure 2 The thermal effects of the conductive line 206 in FIG. 2 are: (i) the heat of the transistor / AR structure 202, (ii) the heat of the high resistance structure 204 (e.g., a resistor or the like), (iii) the self-heating of the conductive line 206 itself, and (iv) the heat of the adjacent conductive line CLn (in FIG. Figure 2 In some embodiments, thermal effects considered during electromigration evaluation include bidirectional heat transfer effects between structures.

[0035] During operation of the IC device, the transistor / AR structure 202 and the high-resistance structure 204 can generate heat (through self-heating) and transfer it to the adjacent conductive line 206. Therefore, in some embodiments, the electromigration evaluation performed on the conductive line 206 takes into account the heat generated in the adjacent transistor / AR structure 202 and the high-resistance structure 204. As IC devices shrink to more advanced technology nodes, the cross-section of the conductive line 206 becomes smaller, thus also generating self-heating. Similarly, the adjacent conductive line CLn may also generate self-heating or otherwise increase in temperature.

[0036] Some advanced IC designs include one or more backside circuit structures (e.g., power structures such as super power rails, interconnect structures, etc. on the backside of the semiconductor substrate, which is opposite to the front side of the semiconductor substrate forming the active area), additional wafer substrates for mechanical support (e.g., carrier substrates incorporated into the final IC), one or more stacked dies, etc., which hinder the dissipation of heat and / or replace structures used as heat sinks in other IC designs, thereby increasing the number of potential heat sources while reducing the structures used to reduce the temperature of the device. In addition, the bonding layer used to connect the backside circuit structures, additional support substrates, stacked dies, etc. to the IC substrate can also hinder the flow of heat away from the IC device. In addition, some advanced IC designs also use thinner substrates, which are less effective as heat sinks compared to substrates that have not been thinned.

[0037] According to some embodiments, electromigration evaluation of a conductive line of interest CLi takes into account heat from transistors / active regions and high-resistance structures, self-heating of the conductive line itself, and heat from neighboring conductive lines CLn.

[0038] Figure 2 Thermal coupling 215 is schematically illustrated, where heat from the transistor / AR structure 202 can be transferred to the conductive line 206 through thermal coupling of the ILD structure 208 and / or other intermediate materials, and heat from the conductive line 206 can be transferred to the transistor / AR structure 202. Similarly, thermal coupling 217 represents heat transfer between the high resistance structure 204 and the conductive line 206, while thermal coupling 219 represents heat transfer between the conductive line 206 and the adjacent conductive line 210. Figure 2 In the embodiment, the high resistance structure 204 is located between the substrate 201 and the conductive line 206, but in other embodiments, the high resistance structure 204 is located in a layer above the conductive line 206, so that the conductive line 206 is located between the high resistance structure 204 and the substrate 201, and the thermal coupling 217 is evaluated above the conductive line 206.

[0039] Figure 2 For ease of explanation, thermal couplings 215 , 217 , 219 perpendicular to the substrate 201 (+Y and −Y directions) are schematically depicted, but in reality, thermal couplings 215 , 217 , 219 and heat transfer act in three dimensions starting from the heat source.

[0040] In some embodiments, the cumulative thermal effects of self-heating and heat transfer are used to calculate an estimated temperature of the conductive line 206 , which is used to perform electromigration evaluation on the conductive line 206 .

[0041] Figure 3A is a schematic diagram of thermal coupling between conductive lines according to some embodiments.

[0042] In some embodiments, the thermal model defines a heat affected zone (TAZ). The thermal model evaluates the features of interest (e.g., conductive wires) in the TAZ surrounding a heat source (e.g., a high temperature conductive wire). For example, Figure 3A In FIG. 1 , the TAZ surrounds the conductive lines, including conductive line 306 located in layer Lx, which is the conductive line of interest CLi. Within the TAZ, adjacent conductive line 310 located in layer Lx is considered a heat source. In some embodiments, adjacent conductive line 310 is identified or modeled as a structure within the TAZ that reaches the highest temperature during operation of the IC device.

[0043] exist Figure 3A In some embodiments, the size of the TAZ is determined and assigned to the TAZ using distance. In some embodiments, distance is used as one of two or more factors in assigning the size of the TAZ. For example, in some embodiments, the assigned TAZ size is based on lateral or longitudinal distance, based on differences in layers, etc. Figure 3A In some embodiments, the TAZ is circular in the XZ plane. In some embodiments, the TAZ is circular in the XY plane or other planes. In some embodiments, the TAZ is spherical. In some embodiments, the dimension of the TAZ along the X or Y axis is different from the dimension along the Z axis. In some embodiments, the dimensions of the TAZ along the X, Y, and Z axes are different. In some embodiments, for a 2 nm technology node, the TAZ is approximately 0.5 microns or less.

[0044] exist Figure 3A , semiconductor structure 300A includes transistor / AR / high resistance structure 302, conductive line 306, and adjacent conductive line 310. For clarity, only a single transistor / AR / high resistance structure 302 is shown, but it should be understood that in some embodiments, semiconductor structure 300A includes multiple transistors, active regions, and high resistance structures. For clarity, semiconductor structure 300A does not include an ILD (see FIG. Figure 2 ), but it should be understood that in some embodiments, ILD and / or other layers cover and / or surround the transistor / AR / high resistance structure 302, the conductive line 306 and the adjacent conductive line 310.

[0045] exist Figure 3AIn the embodiment, the thermal model is used to evaluate conductive lines in the TAZ surrounding an adjacent conductive line 310 that acts as a heat source. Conductive lines in the TAZ, such as conductive line 306, are evaluated for thermal impact from the heat source, namely, the thermal impact from adjacent conductive line 310 located above the first surface 301a of the substrate 301. In other embodiments, the thermal model is used to evaluate one or more transistors / ARs / high-resistance structures 302 surrounding the adjacent conductive line 310. One or more transistors / ARs / high-resistance structures 302 in the TAZ are evaluated for thermal impact from the heat source.

[0046] exist Figure 3A In some embodiments, the TAZ is located in the XZ plane above substrate 201. In some embodiments, the TAZ is defined in another plane, or in three-dimensional space as a sphere, cylinder, cube, cuboid, or similar shape. In some embodiments, the TAZ is defined below or around substrate 301. Figure 3A In the embodiment, the TAZ is circular in the XZ plane, centered on the adjacent conductive line 310 in layer Lx, and includes features in layers Lx+2 through Lx-2. In other embodiments, the TAZ has a larger diameter and / or is centered on features in a layer below layer Lx (e.g., layer Lx-1 or Lx-2, or a layer closer to the substrate 310 than layer Lx-2), and includes one or more transistors / AR / high resistance structures 302.

[0047] Figure 3A Schematically illustrates a thermal coupling 315 oriented in the XZ plane above the substrate 301 (e.g. Figure 3A ), for ease of illustration, thermal coupling and heat transfer act from the heat source in three dimensions and, in some embodiments, are evaluated in three dimensions.

[0048] exist Figure 3A , the TAZ includes the conductive line 306, the adjacent conductive line 310, and 19 other locations that could be conductive lines, for a total of 21 conductive line locations in the TAZ. In one example of an electromigration evaluation, the conductive line 306 is evaluated for a temperature increase due to heat generated by the adjacent conductive line 310. That is, the adjacent conductive line 310 is treated as a heat source, and the temperature increase of the conductive line 306 is evaluated, which is caused by heat transferred from the adjacent conductive line 310 to the conductive line 306. In some embodiments, each conductive line at any of the 20 locations in the TAZ surrounding the adjacent conductive line 310 is evaluated for the thermal effect of the heat from the adjacent conductive line 310. In other embodiments, the TAZ is larger and / or centered on a layer below layer Lx, and each conductive line and each transistor / AR / high resistance structure 302 in the TAZ is evaluated for the thermal effect from a heat source in the TAZ (e.g., at the center of the TAZ).

[0049] exist Figure 3A In FIG, each of the twenty conductive line positions is assigned a rating factor (RF) relative to the heat source (ie, relative to the adjacent conductive line 310), the rating factor corresponding to the impact of heat transferred by the adjacent conductive line 310 as a heat source on each position.

[0050] In some embodiments, the TAZ is divided into sub-regions, and each sub-region is assigned a rating factor. In some embodiments, the TAZ is divided into sub-regions based on distance. In some embodiments, the TAZ is divided into sub-regions based on distance from a heat source (e.g., adjacent conductive line 310) or based on distance from a temperature-affected structure (e.g., conductive line 306).

[0051] In some embodiments, the rating factor represents a temperature rise ratio relative to the heat source. In some embodiments, a lower rating factor represents a relatively greater heating impact (i.e., a relatively greater temperature rise ratio), while a higher rating factor represents a relatively lower heating impact (i.e., a relatively lower temperature rise ratio).

[0052] exist Figure 3A For example, there are four rating factors: RF1, RF2, RF3, and RF4. Figure 3A , conductive line 306 is assigned a rating factor RF3.

[0053] A conductive line in a TAZ (or a transistor / AR / high resistance structure 302 when contained by a TAZ) with an RF1 rating factor will tend to experience a greater temperature rise due to heat from an adjacent conductive line 310 (heat source) than a conductive line (or transistor / AR / high resistance structure 302) with an RF2 rating factor. A conductive line (or transistor / AR / high resistance structure 302) with an RF2 rating factor will tend to experience a greater temperature rise due to heat from an adjacent conductive line 310 than a conductive line (or transistor / AR / high resistance structure 302) with an RF3 rating factor. A conductive line (or transistor / AR / high resistance structure 302) with an RF3 rating factor will tend to experience a greater temperature rise due to heat from an adjacent conductive line 310 than a conductive line (or transistor / AR / high resistance structure 302) with an RF4 rating factor.

[0054] For example, in Figure 3A, assuming that adjacent conductive line 310 is a heat source and the temperature increase of conductive line 306 due to heat from adjacent conductive line 310 is being evaluated, and assuming that the temperature of adjacent conductive line 310 is normalized to 1, conductive line 306 experiences a temperature increase of 1×RF3 due to heat transfer from adjacent conductive line 310. More specifically, for an example where temperature is measured in degrees Celsius or degrees Celsius (°C) and RF3 represents a temperature rise ratio of 0.6, conductive line 306 experiences a temperature increase of 0.6°C for every 1.0°C temperature increase of adjacent conductive line 310. In this case, if adjacent conductive line 310 experiences a temperature increase of 10°C, conductive line 306 will experience a temperature increase of 6°C ((10°C×RF3)=(10°C×0.6)=6°C).

[0055] Conductive line 306 having a rating factor RF3 will exhibit a temperature rise due to heat from adjacent conductive line 310 that is greater than a conductive line having a rating factor RF4, and will exhibit a temperature rise due to heat from adjacent conductive line 310 that is less than a conductive line having rating factors RF1 or RF2.

[0056] exist Figure 3A , the TAZ including twenty-one conductive line locations is only an example. In some embodiments, the TAZ is larger or smaller and includes a greater or lesser number of possible structure locations. In another example, the TAZ includes front-end line features on substrate 310 such that transistors / AR / high resistance structures 302 are evaluated as in layer Lx-1, and ranking factors RF1 to RF4 are assigned to transistors / AR / high resistance structures 302. In another example, the TAZ includes front-end line features on substrate 310 such that transistors / AR / high resistance structures 302 are evaluated as in layer Lx-1, and ranking factors RF4 or higher are assigned to transistors / AR / high resistance structures 302 such that the nearest transistor / AR / high resistance structure 302 is assigned RF4, the next nearest transistor / AR / high resistance structure 302 is assigned RF5, the second nearest transistor / AR / high resistance structure 302 is assigned RF6, and so on. In another example, the high-resistance structure 302 is located in a back-end wiring layer above the adjacent conductive line 310, for example, in layer Lx+1 or Lx+2, such that the adjacent conductive line 310 is located between the high-resistance structure 302 and the substrate 301. The high-resistance structure 302 extends over a plurality of pitches to experience a temperature rise ratio of, for example, 0.9, and a high rating factor (for example, RF0 or RF1) is assigned to the high-resistance structure 302. Furthermore, the use of four rating factors RF1-RF4 within the TAZ is merely an example. In some embodiments, a greater or lesser number of rating factors may be assigned.

[0057] In some embodiments, the rating factor is based on the heat generated by the reference structure (in Figure 3A In some embodiments, the rating factor is assigned based on a combination of distance from a reference structure that generates heat and other factors, such as the thermal conductivity of the intervening structure or the like.

[0058] In some embodiments, each increase in the rating factor indicates a uniform reduction in the heating contribution from the heat-generating reference structure. In other embodiments, each increase in the rating factor indicates a reduction in the heating contribution from the heat-generating reference structure, but the reduction in heating contribution is not uniform.

[0059] exist Figure 3A In the present invention, it is assumed, by way of example only, that the rating factors are assigned in the XZ plane, i.e., in the X and Z directions. In some embodiments, the rating factors are assigned based on a two-dimensional analysis of the design of the semiconductor structure in planes other than the XZ plane. In some embodiments, the rating factors are assigned based on a three-dimensional analysis of the design of the semiconductor structure. In some embodiments, the rating factors are assigned based on an empirical evaluation of the IC design or a thermal model.

[0060] In some embodiments, the rating factors are assigned such that the same change in the rating factor, e.g., from RF1 to RF2, represents the same change in the effect of transferred heat from an adjacent heat source, regardless of the direction of heat transfer. In other embodiments, the rating factors have a directional component, and the assignment is such that the same change in the rating factor, e.g., from RF1 to RF2, represents the same change in the effect of heat transferred from an adjacent heat source in a lateral direction (X or Y axis) (e.g., in the same layer), but a different (e.g., greater or lesser) change in the effect of heat transferred from an adjacent heat source in a vertical direction (Z axis) (e.g., from another layer). For example, heat transfer in the vertical direction may be greater or less than heat transfer in the lateral direction. In other embodiments, the same change in the rating factor represents a greater or lesser change in the effect of heat transferred from an adjacent heat source in each of the three dimensions.

[0061] Figure 3B is a schematic diagram of thermal coupling between conductive lines according to some embodiments.

[0062] exist Figure 3B In FIG. 3 , semiconductor structure 300B includes conductive line 305 located between conductive line 306 and adjacent conductive line 310 . In addition, conductive line 307 is located on the other side of conductive line 306 relative to conductive line 305 , and conductive line 309 is located below conductive line 306 .

[0063] exist Figure 3BFor example, there are seven rating factors (rating factors RF1, RF2, RF3, RF4, RF5, RF6, and RF7). A lower rating factor indicates a relatively greater heating impact (i.e., a relatively higher temperature rise ratio), while a higher rating factor indicates a relatively lower heating impact (i.e., a relatively lower temperature rise ratio). A conductive line with an RF1 rating factor will tend to experience a greater temperature rise due to heat from an adjacent conductive line 310 (a heat source) than a conductive line with an RF2 rating factor. Similarly, a conductive line with an RF2 rating factor will tend to experience a greater temperature rise due to heat from an adjacent conductive line 310 than a conductive line with an RF3 rating factor, a conductive line with an RF3 rating factor will tend to experience a greater temperature rise due to heat from an adjacent conductive line 310 than a conductive line with an RF4 rating factor, and so on.

[0064] In some embodiments, rating factors RF1, RF2, RF3, RF4, RF5, RF6, and RF7 are assigned based on pitch. In some embodiments, the pitch is the contact poly pitch (CPP). In some embodiments, the CPP corresponds to the center-to-center distance between two immediately adjacent gate regions along the X-axis or Y-axis (two gate regions are considered immediately adjacent if there are no other gate regions between them). In some embodiments, the CPP is a fundamental unit of measurement having a specific value or range of values ​​for a corresponding semiconductor process technology node. The size and / or placement of many other structures (e.g., conductive lines) in a layout and / or IC device can be normalized relative to the CPP.

[0065] In some embodiments, the lateral size of the TAZ is allocated based on the number of CPPs. In some embodiments, the vertical size of the TAZ is allocated equal to the lateral size of the TAZ determined based on the number of CPPs. In some embodiments, the vertical size of the TAZ is based on the number of layers, while the lateral size of the TAZ is determined based on the number of CPPs.

[0066] In some embodiments, distance is used as one of two or more factors to assign the size of the TAZ. For example, in some embodiments, the size of the TAZ is assigned based on lateral or vertical distance, layer-based differences, or similar factors. In some embodiments, the TAZ is circular in the XZ plane or another plane. In some embodiments, the TAZ is spherical. In some embodiments, the size of the TAZ along the X-axis or Y-axis is different from the size along the Z-axis. In some embodiments, the size of the TAZ along the X-axis, Y-axis, and Z-axis are different.

[0067] In some embodiments, the rating factors RF1, RF2, RF3, RF4, RF5, RF6, and RF7 gradually increase in increments of 1 in the transverse direction (parallel to the X-axis or the Y-axis) (i.e., from RF1 to RF2, from RF2 to RF3, and so on) relative to the adjacent conductive line 310 that serves as a heat source, while within the same layer (e.g., within the first metal layer M0 above the metal to diffusion (MD), within the second metal layer M1 above the first metal layer M0, within the third metal layer M3 above the second metal layer M2, or the like).

[0068] In some embodiments, the rating factors RF1, RF2, RF3, RF4, RF5, RF6, and RF7 increase gradually by 1 every other CPP in the transverse direction (parallel to the X-axis or Y-axis) (i.e., from RF1 to RF2, from RF2 to RF3, and so on), relative to the adjacent conductive line 310 as a heat source, and within the same layer (i.e., RF1 is 1 CPP away from the adjacent conductive line 310, RF2 is 2 CPPs away from the adjacent conductive line 310, RF3 is 3 CPPs away from the adjacent conductive line 310, and so on), as shown in Table 1 below.

[0069] Table 1

[0070] RF1 1CPP RF2 2CPP RF3 3CPP RF4 4CPP RF5 5CPP RF6 6CPP RF7 7CPP

[0071] In some embodiments, increments in the rating factor represent progressively smaller heating impact ratios, as shown in Table 2 below.

[0072] Table 2

[0073] RF1 0.74 RF2 0.62 RF3 0.55 RF4 0.50 RF5 0.45 RF6 0.40 RF7 0.39

[0074] Taking Table 2 as an example, and assuming that the adjacent conductive line 310 experiences a temperature rise of 10°C, the positions of conductive lines 305, 306, and 307 are modeled as experiencing corresponding temperature rises of 7.4°C, 6.2°C, and 5.5°C due to heat transfer from the adjacent conductive line 310, as shown in Table 3 below.

[0075] Table 3

[0076] Conductive Thread 305 RF1 7.4℃ Conductive wire 306 RF2 6.2℃ Conductive Wire 307 RF3 5.5℃

[0077] In another example based on Table 2, and referring to Figure 3B, conductive lines located between locations with a particular rating factor are assigned an intermediate rating factor. For example, in some embodiments, conductive line 309 is farther from adjacent conductive line 310 than conductive line 306 but closer than conductive line 307, is assigned a rating factor between RF2 and RF3, and is modeled as experiencing a temperature rise between conductive line 306 and conductive line 307 (e.g., conductive line 309 is modeled as experiencing a temperature rise less than 6.2°C and greater than 5.5°C). In the preceding example, the intermediate rating factor is modeled solely based on distance. In other embodiments, the intermediate rating factor is modeled based on one or more of distance, layer differences, material differences, or similar factors. In some embodiments, conductive lines or other structures located between locations with a particular rating factor are assigned the same rating factor as the adjacent locations, e.g., conductive line 309 is assigned a rating factor of RF2 or a rating factor of RF3.

[0078] Some of the examples above describe the first rating factor RF1 as representing a temperature drop from a heat source, e.g., conductive line 305 is modeled as experiencing a lower temperature than adjacent conductive line 310. However, in some embodiments, the rating factors are assigned starting at 1, such that a first rating factor RF1 of 1, e.g., conductive line 305 is modeled as experiencing the same temperature as adjacent conductive line 310. In some embodiments, the rating factors range from a temperature rise ratio of 1.0 to 0.1. In other embodiments, a unity rating factor is assigned as RF0, and the rating factor RF1 is less than 1.

[0079] In some embodiments, the temperature rise of the conductive line of interest CLi due to heat transferred from the adjacent conductive line CLn as a heat source relative to the conductive line of interest CLi is calculated using the following Equation 1:

[0080] ΔT CLi(n) =T CL(n) ×RF[Equation 1]

[0081] ΔT CLi(n) : The temperature rise of the conductive line of interest (CLi) due to the heat transferred from the adjacent conductive line (CLn) as a heat source

[0082] T CL(n) : Temperature of the adjacent conductive line CL(n)

[0083] RF: Rating factor, the ratio of the temperature rise relative to the adjacent conductive line CL(n)

[0084] In one embodiment of Equation 1, for example, where the rating factor RF represents a temperature rise ratio of 0.6, the adjacent conductive line 310 (CLn) experiences a temperature rise of 10°C (T CL(n)= 10°C), the temperature rise of the conductive line 306 as the conductive line of interest (CLi) is calculated as ΔT CLi(n) =6℃(6℃=10℃×0.6).

[0085] Figure 4 is a schematic diagram of an electromigration tool 400 useful in operation according to an electromigration signoff method in some embodiments.

[0086] In some embodiments, reference Figure 4 The electromigration tool 400 includes a layout library 405 or a data storage device for storing design data corresponding to an IC layout.

[0087] Design data from the layout library 405 is used in a layout simulation operation 402 to generate a simulated design layout. The simulated design layout includes one or more heat-generating structures, such as transistors, active regions, high-resistance structures, conductive lines, etc. As described in detail below, the simulated design layout from the layout simulation operation 402 is used in conjunction with a device temperature equation 425, which in some embodiments is retrieved from a memory, to calculate the total temperature rise of the conductive line of interest CLi.

[0088] In some embodiments, the simulated design layout is used in operations subsequent to operation 402 to calculate the heat contribution from heat-generating structures in conjunction with a device temperature equation 425, which is a function of thermal resistance values, the number of transistor fins in a FinFET, power dissipation of the transistor or high-resistance structures, etc. In some embodiments, the relevant values ​​and / or parameters included in the device temperature equation 425 are provided by the foundry, incorporated into applicable design rules, extracted from the IC layout, etc. In some embodiments, the device temperature equation 425 is provided as part of a design tool, such as a Simulation Program for Integrated Circuit Emphasis (SPICE) model corresponding to a particular manufacturing process, provided by the foundry or the like.

[0089] In some embodiments, the electromigration tool 400 then performs operation 404 to calculate self-heating in one or more transistors, one or more active regions, and / or one or more high-resistance structures. In some embodiments, the thermal contribution of the active region is determined as a function of individual thermal contribution calculations for each transistor or other active structure in the active region. In some embodiments, the cumulative thermal contributions from multiple active regions are used in subsequent calculations to assess the magnitude of the thermal impact of the active region on the conductive line of interest CLi.

[0090] Next, the simulated design layout from layout simulation operation 402 is used in conjunction with device temperature equation 425 to calculate the simulated temperature increase of the conductive line of interest CLi due to self-heating in the conductive line of interest CLi (operation 406). In some embodiments, I rms is specified layer by layer. For example, instead of specifying a single I rms value, such as 5°C, but assign a higher I rms Values, such as up to 20°C, for example, layer M0 and layers immediately adjacent to M0 are assigned a higher I value than layers further away from layer M0. rms In some embodiments, I rms Also specified by layer material, layer materials with greater electromigration resistance are assigned higher I rms For example, instead of specifying a single I value regardless of the material in the layer, rms value, but by the one with higher activation energy (E a ) are assigned a higher I rms For example, cobalt, ruthenium or molybdenum layers are assigned a higher I value than copper or tungsten layers. rms Thus, in some embodiments, a greater electromigration margin is provided for the more robust layer in operation 406. In some embodiments, I rms is a function of metal width and ΔT.

[0091] Next, using thermal model 435, which in some embodiments is retrieved from memory, electromigration tool 400 calculates a simulated temperature increase of conductive line of interest CLi due to heating of one or more adjacent conductive lines CLn identified in the IC layout (operation 408). In some embodiments, thermal model 435 and Equation 1 (discussed above) are used to determine or simulate the temperature increase of conductive line of interest CLi due to heating of one or more adjacent conductive lines CLn.

[0092] In some embodiments, when performing operation 408, the electromigration tool 400 performs a temperature control operation when calculating the temperature increase of the conductive line of interest CLi due to heating of adjacent conductive lines CLn identified in the IC layout. Figure 5 The method 500 may be repeated one or more times (ie, in some embodiments, operation 408 includes one or more iterations of the method 500).

[0093] Figure 5 is a flow chart of a method 500 of calculating a temperature increase of a conductive line of interest CLi due to heating of one or more neighboring conductive lines CLn, according to some embodiments.

[0094] Method 500 includes operations 504, 506, 508, 510, and 512. In some embodiments, Figure 4 Operation 408 includes performing each of operations 504, 506, 508, 510, and 512 one or more times.

[0095] exist Figure 5 In the embodiment of the present invention, operation 504 includes calculating the temperature of each conductive line due to Joule heating of the conductive line itself. In some embodiments, this includes modeling or calculating the current-resistance (IR) temperature rise in each conductive line in the TAZ due to the resistance of the current passing through the conductive line during operation of the IC device.

[0096] Next, operation 506 includes determining the adjacent conductive line CLn (CL max In some embodiments, operation 506 includes defining or assigning a TAZ, importing a TAZ from the thermal model 435, or similar operations. In some embodiments, operation 506 includes positioning the TAZ so that the conductive line of interest CLi is centered in the TAZ along one or more X, Y, and Z axes.

[0097] In some embodiments, determining CL max This includes evaluating each conductive line within the TAZ that is adjacent to the conductive line of interest CLi. In some embodiments, determining CL max This includes evaluating each conductive line that extends to any extent within the TAZ. In some embodiments, determining CL max This includes evaluating each conductive line that is completely within the TAZ.

[0098] Next, operation 508 includes determining the adjacent conductive line CLn (CL max ) is the distance d between them.

[0099] Next, operation 510 includes assigning a rating factor corresponding to the distance d. In some embodiments, operation 510 includes assigning a rating factor corresponding to the distance d as described above. Figure 3A and 3B Relevant rating factors.

[0100] exist Figure 5 In some embodiments, operations 508 and 510 include determining a distance d and using the distance d to assign a rating factor. In some embodiments, distance is used as one of two or more factors to assign a rating factor. For example, in some embodiments, as described above with Figure 3A and 3B Relevant rating factors are assigned, for example, based on lateral or longitudinal distance, based on differences in layers or similar factors.

[0101] Next, operation 512 includes calculating the neighboring conductive line CLn (CL) having the maximum Joule heating temperature using the rating factor. maxIn some embodiments, operation 512 includes performing a calculation corresponding to Equation 1 to determine or simulate the temperature increase of the conductive line of interest CLi due to the adjacent conductive line CLn (CLn) having the maximum Joule heating temperature as a heat source. max ) caused by the transfer of heat.

[0102] In some embodiments, after operation 512, method 500 repeats one or more cycles of operations 504-512, for example, for another conductive line of interest CLi and / or another adjacent conductive line CLn. In some embodiments, method 500 is performed multiple times to calculate the temperature rise of multiple conductive lines of interest CLi. In some embodiments, electromigration tool 400 performs a Figure 4 Electromigration analysis 410.

[0103] In some embodiments, during electromigration analysis 410, thermal model 435 provides a plurality of coefficients, such as a, b, c, and d, that are specific to the materials and / or layers included in the IC design being analyzed and / or the specific manufacturing process that will be used to produce a device based on the IC design. In other embodiments, the coefficients and / or other relevant values ​​and / or parameters are provided by the foundry, incorporated into applicable design rules, or extracted from the IC layout.

[0104] In some embodiments, during electromigration analysis 410 , the total temperature of the conductive line of interest CLi is increased by ΔT sum is a function of, for example, the sum of the following temperature increase contributions: (i) heat transferred to the conductive line of interest CLi from self-heating of one or more transistors, one or more active regions, and / or one or more high-resistance structures (operation 404); (ii) self-heating in the conductive line of interest CLi (operation 406); and (iii) heat transferred to the conductive line of interest CLi from self-heating of one or more neighboring conductive lines CLn (operation 408). In some embodiments, the total temperature increase ΔT sum It is also a function of: (iv) the amount of heat transferred to the conductive line of interest CLi from one or more other structures (eg, other active structures such as bipolar junction transistors (BJTs), diodes, or similar structures).

[0105] In some embodiments, the total temperature increase ΔT of the conductive line of interest CLi sum Calculated according to Equation 2A below:

[0106] ΔT sum =f(a,b,ΔT AR ,ΔT Hi-R )+ΔT rms +ΔTCLi(n) [Equation 2A]

[0107] ΔT sum : The total temperature rise of the conductive line of interest CLi

[0108] a: Derating factor reflecting operation below maximum capacity

[0109] b: ΔT rms and ΔT AR Function [f(ΔT rms ,ΔT AR )]

[0110] (Thermal coefficients a and b are provided for each layer and / or material)

[0111] ΔT AR : Transistor / active area self-heating

[0112] ΔT Hi-R : High resistance structure self-heating

[0113] ΔT rms : Heating of the metal due to the current in the conductive line of interest CLi (i.e., heat from Irms)

[0114] ΔT CLi(n) : Temperature rise caused by heat transferred from the adjacent conductive line CLn as a heat source

[0115] In some embodiments, in Equation 2A, ΔT rms It is the self-heating of the conductive line CLi of interest in operation 406 .

[0116] In some embodiments, in Equation 2A, ΔT CLi(n) is the amount of heat transferred from the self-heating of one or more adjacent conductive lines CLn to the conductive line of interest CLi in operation 408. In some embodiments, ΔT is calculated using Equation 1 CLi(n) .

[0117] In some embodiments, the total temperature rise ΔT of the conductive line of interest CLi is calculated according to the following equation 2B: sum :

[0118] ΔT sum =f(a,b,ΔT AR ,ΔT Hi-R ,c,d)+ΔT rms +ΔT CLi(n) [Equation 2B]

[0119] c: Layer / material-related layer effects

[0120] d: Layer / material-dependent temperature distribution

[0121] (Provide thermal coefficients c and d for each layer and / or material)

[0122] In some embodiments, the total temperature rise ΔT of the conductive line of interest CLi is calculated according to the following equation 2C: sum :

[0123] ΔT Con =f(a,b,ΔT AR ,ΔT Hi-R ,c,d,ΔT other_structures )+ΔT rms +ΔT CLi(n) [Equation 2C]

[0124] ΔT other_structures : Self-heating from other structures

[0125] (Other structures include, for example, bipolar junction transistors thermally coupled to the conductive line of interest CLi

[0126] (BJT), diode, etc.)

[0127] In some embodiments, the total temperature rise ΔT of the conductive line of interest CLi sum The calculation of ΔT includes one or more factors representing the effects of heat dissipation structures. These heat dissipation structures include, for example, cooling structures surrounding and / or adjacent to the conductive line of interest CLi, cooling structures surrounding and / or adjacent to the transistor, active region, high resistance structure and / or adjacent to the conductive line CLn, other back-end structures, back-side structures, etc. In some embodiments, these factors are used to calculate the total temperature rise ΔT. sum , provides a more accurate simulation or expected operating temperature that takes into account the heating and cooling effects of structures in the IC device.

[0128] In some embodiments, operation 410 includes modifying the current specification of the conductive line of interest CLi and generating a modified IC design layout including the modified current specification. In some embodiments, one or more of operations 404-408 are repeatedly performed on the modified IC design layout. In some embodiments, after the electromigration analysis 410, the electromigration tool 400 then generates a tapeout profile 418 corresponding to the IC layout that passed the electromigration analysis, i.e., a signed-off IC layout.

[0129] Figure 6 is a flow chart of a method 600 of performing electromigration evaluation according to some embodiments.

[0130] In some embodiments, method 600 improves the accuracy of electromigration assessments associated with IC designs by accounting for degradation effects that may occur due to elevated temperatures caused by heat-generating structures (eg, performance limitations due to electromigration issues).

[0131] exist Figure 6 In operation 602, a structure of interest (Si) is identified. In some embodiments, the structure of interest Si is identified by performing a structural and / or operational review of the IC design layout being evaluated. In some embodiments, the structure of interest Si is a conductive line of interest CLi as described above. In other embodiments, the structure of interest Si is another structure, such as a front-end or back-end structure, such as a transistor, an active region, a high-resistance structure, etc., which is being evaluated for potential temperature increases that may degrade performance and / or lifetime.

[0132] In operation 604, adjacent structures are evaluated to identify heat-generating structures (HGS). In some embodiments, the HGS is a transistor, active region, or high-resistance structure that increases in temperature due to self-heating. In some embodiments, the HGS is an adjacent conductive line CLn that increases in temperature due to self-heating. In some embodiments, the HGS is other structures such as bipolar junction transistors (BJTs), diodes, and the like.

[0133] In some embodiments, if the conductive wire is located entirely or partially in the heat affected zone TAZ, for example as described above Figure 3A -B, the conductive line is considered to be adjacent and is therefore identified as a heat generating structure HGS in operation 604.

[0134] In some embodiments, if a neighboring structure other than a conductive line (e.g., a transistor, an active region, a high-resistance structure, etc.) is located entirely or partially within a heat-affected zone (TAZ), the structure is considered neighboring and, therefore, identified as a heat-generating structure (HGS) in operation 604. In other embodiments, one or more of these other structures are assigned a different thermal zone. For example, if a conductive line is located within the TAZ, it is assessed as a heat-generating structure (HGS), while in some embodiments, if a transistor is located within a thermal zone that differs in shape, size (2D or 3D), or size from the TAZ, it is assessed as a heat-generating structure (HGS).

[0135] In some embodiments, operation 604 includes a filtering operation to exclude such structures from consideration if their simulated or expected temperature is below a predetermined threshold.

[0136] At operation 606 , if fewer than all heat generating structures (HGS) have been identified, the method 600 branches from operation 606 to repeat operation 604 and identify another heat generating structure (HGS). If all heat generating structures (HGS) have been evaluated, the method 600 continues with operation 610 .

[0137] In operation 610, method 600 includes calculating the temperature of the structure of interest Si. In the case where the structure of interest Si is a conductive line of interest CLi, operation 610 also includes determining the temperature increase of the conductive line of interest CLi due to self-heating, for example, determining ΔT according to any one of Equations 2A-C rms In some embodiments, operation 610 includes calculating the total temperature rise ΔT of the conductive line of interest CLi according to any one of Equations 2A-C. sum In the case where the structure of interest Si is a structure other than a conductive line (eg, a front-end or back-end structure such as a transistor, an active region, a high resistance structure, etc.), in some embodiments, operation 610 includes one or more operations similar to operations 504-512.

[0138] In operation 612 , if fewer than all structures Si of interest have been evaluated, the method 600 branches from operation 612 to repeat operation 602 and evaluate another structure Si of interest. If all structures Si of interest have been evaluated, the method 600 continues with operation 614 .

[0139] In operation 614, the calculated temperature of the structure Si of interest is used to perform an electromigration assessment to determine whether the IC design layout being evaluated meets lifetime and / or performance goals for the specific IC design. In some embodiments, operation 614 includes modifying the current specification of the structure Si of interest and generating a modified IC design layout that includes the modified current specification. In some embodiments, one or more of operations 602-612 are repeated for the modified IC design layout.

[0140] In some embodiments, for the IC design layout that passes the electromigration evaluation in operation 614 , sign-off is completed, and a tape-out data file corresponding to the passed IC design layout is generated in operation 616 .

[0141] In some embodiments, a modified IC design layout is generated after the electromigration evaluation of operation 614. In some embodiments, one or more operations of method 600 are repeated on the modified IC design layout.

[0142] In some embodiments, in operation 618 , an IC device, such as a semiconductor device such as a memory or a processor, is manufactured using the tape-out data file according to the approved IC design layout or the modified IC design layout.

[0143] Considering self-heating effects during electromigration evaluation helps prevent an IC design layout from being described as more resistant to electromigration effects than the corresponding IC device actually achieves in operation. Embodiments help improve performance and prevent premature field failures of IC devices. By improving the accuracy of IC design layout analysis, embodiments increase confidence that IC devices manufactured according to a particular IC design layout will be optimized for performance and provide extended lifetimes.

[0144] By utilizing equation-based thermal evaluation, rather than slower, more time-consuming, and computationally demanding thermal models, the efficiency of electromigration signoff methods that consider the thermal effects of a specific IC design layout is improved. The efficiency of the signoff method in some embodiments is further enhanced by evaluating the thermal coupling between various components, including front-end-of-line (FEOL) and back-end-of-line (BEOL) structures.

[0145] In some embodiments, the detailed electromigration methods described above are applicable to any IC design layout and / or IC or semiconductor device fabrication process where self-heating effects are expected to be a factor. In some embodiments, the IC design layout corresponds to a fin field-effect transistor (FinFET)-based semiconductor device and / or other planar transistor-based or complex semiconductor device.

[0146] In some embodiments, performing electromigration evaluation with consideration of heat sinks utilizes an electronic design automation (EDA) tool (also known as an electronic computer-aided design (ECAD) tool) that identifies and evaluates structures in an IC design layout. In some embodiments, the EDA tool is configured to identify heat sources and / or heat sinks in the IC design layout from an IC design layout library 405. In some embodiments, the IC design layout library 405 utilizes the Open Artwork Systems Interchange Standard (OASIS) or another language for representing IC design layouts.

[0147] In some embodiments, the electromigration signoff method provides more accurate local temperature calculations within an IC design layout. In some embodiments, the electromigration signoff method provides more accurate thermally-aware electromigration assessment results during the design phase. In some embodiments, the electromigration signoff method reduces the risk of premature product failure and / or overdesign. In some embodiments, the electromigration signoff method uses equation-based device temperature calculations to reduce simulation run times. In some embodiments, the electromigration signoff method uses thermal model 435 to reduce electromigration simulation run times.

[0148] Figure 7 is a block diagram of an electronic design automation (EDA) system 700 according to some embodiments.

[0149] According to some embodiments, the electromigration evaluation method described herein may be implemented using, for example, an EDA system 700. According to some embodiments, the EDA system 700 implements or includes an electromigration tool 400 consistent with some embodiments.

[0150] In some embodiments, EDA system 700 is a general-purpose computer including a hardware processor 702 and a non-transitory computer-readable storage medium 704. Computer-readable storage medium 704 is encoded with (i.e., stores) computer program code (or instructions) 706, i.e., a set of executable instructions. Processor 702 executes computer program code 706 to represent an EDA tool that (at least partially) implements part or all of the methods described herein (hereinafter referred to as the processes and / or methods) according to some embodiments.

[0151] The processor 702 is electrically coupled to the computer-readable storage medium 704 via a cable 718. The processor 702 is also electrically coupled to the I / O interface 712 via the cable 718. The network interface 714 is also electrically connected to the processor 702 via the cable 718. The network interface 714 is connected to a network 716. The processor 702 and the computer-readable storage medium 704 are connected to external components via the network 716. The processor 702 is configured to execute computer program code 706 encoded in the computer-readable storage medium 704 to enable the EDA system 700 to perform part or all of the processes and / or methods described. In some embodiments, the processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0152] In some embodiments, computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). In some embodiments, computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disks, computer-readable storage medium 704 includes compact disc-read-only memory (CD-ROM), compact disc-read-write (CD-R / W) memory, and / or digital video disc (DVD) memory.

[0153] In some embodiments, the computer-readable storage medium 704 stores computer program code 706 configured to enable the EDA system 700 (where such execution represents (at least in part) an EDA tool) to perform some or all of the described processes and / or methods. In some embodiments, the computer-readable storage medium 704 also stores information that facilitates the execution of some or all of the described processes and / or methods. In some embodiments, the computer-readable storage medium 704 stores process data 708, which in some embodiments includes control algorithms, process variables and constants, target ranges, set points, and program code for enabling control of various processes based on statistical process control (SPC) and / or model predictive control (MPC).

[0154] In EDA system 700 , I / O interface 712 is coupled to external circuitry. In some embodiments, I / O interface 712 includes a keyboard, a numeric keypad, a mouse, a trackball, a touchpad, a touch screen, and / or cursor keys for communicating information and instructions to processor 702 .

[0155] A network interface 714 is coupled to the processor 702. The network interface 714 allows the EDA system 700 to communicate with a network 716, to which one or more other computer systems are connected. In some embodiments, the network interface 714 includes one or more wireless network interfaces, such as Bluetooth, WIFI, WIMAX, GPRS, WCDMA, etc., and / or one or more wired network interfaces, such as Ethernet, USB, IEEE-1364, etc. In some embodiments, some or all of the processes and / or methods described are implemented in two or more EDA systems 700.

[0156] The EDA system 700 is configured to receive information via an I / O interface 712. The information received via the I / O interface 712 includes one or more instructions, data, design rules, process performance history, target ranges, set points, and / or other parameters for processing by the processor 702. This information is transmitted to the processor 702 via a cable 718. The EDA system 700 is configured to receive information related to a user interface (UI) via the I / O interface 712. This information is stored in the computer-readable storage medium 704 as the user interface (UI) 710.

[0157] In some embodiments, part or all of the processes and / or methods are implemented as standalone software applications for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 700.

[0158] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include external / removable and / or internal / built-in storage or memory units, for example, one or more optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards, etc.).

[0159] As described herein, one or more embodiments provide systems and methods for improving electromigration signoff methodologies associated with IC design analysis by considering self-heating effects and thermal coupling between heat-generating structures (e.g., self-heating transistors, active regions, high-resistance structures, conductive lines, etc.) and temperature-affected structures (e.g., transistors, active regions, high-resistance structures, conductive lines, etc.) to provide more accurate estimates of the performance and lifetime of semiconductor devices manufactured based on such IC designs.

[0160] The following U.S. patents and U.S. patent application publications are hereby incorporated by reference in their entirety: U.S. Patent No. 10,867,109, U.S. Patent No. 11,288,437, U.S. Patent No. 11,687,698, U.S. Patent Application Publication 2023 / 0334220 Al, U.S. Patent No. 11,107,714, U.S. Patent No. 11,658,049, U.S. Patent Application Publication 2023 / 0290658 Al, U.S. Patent No. 11,256,847, and U.S. Patent Application Publication 2022 / 0147692 Al.

[0161] According to some embodiments, a method for evaluating thermal effects in an integrated circuit (IC) design includes identifying a structure of interest in the IC design; assigning a heat-affected region to a region of the IC design such that the heat-affected region includes at least a portion of the structure of interest; identifying a plurality of structures that are entirely or partially within the heat-affected region and correspond to IC device elements that self-heat during operation of the IC device based on the IC design; modeling a plurality of operating temperatures corresponding to the plurality of structures and identifying a highest temperature among the plurality of operating temperatures; identifying, among the plurality of structures, a structure having the highest temperature as a first adjacent structure; assigning a ranking factor based on a distance between the structure of interest and the first adjacent structure; and modeling the operating temperature of the structure of interest based on the highest temperature and the ranking factor.

[0162] In some embodiments, the structure of interest is a first conductive line, and the first adjacent structure is a second conductive line.

[0163] In some embodiments, modeling the multiple operating temperatures corresponding to the multiple structures includes: modeling the temperature rise of the multiple structures during operation of the IC device, and modeling the operating temperature of the structure of interest based on the maximum temperature and the rating factor includes: multiplying the temperature rise of the first adjacent structure by a number less than 1 and greater than 0.

[0164] In some embodiments, the method further includes dividing the heat-affected zone into a plurality of sub-regions, each sub-region representing a different distance from the structure of interest, and assigning a corresponding plurality of rating factors to the plurality of sub-regions.

[0165] In some embodiments, assigning the rating factor based on the distance between the structure of interest and the first neighboring structure comprises: selecting the rating factor from the plurality of rating factors.

[0166] In some embodiments, the multiple rating factors include a first rating factor, a second rating factor, and a third rating factor, wherein the first rating factor corresponds to the shortest distance from the structure of interest among the first to third rating factors, the first rating factor corresponds to a first number less than 1 and greater than 0, the second rating factor corresponds to a second number less than 1 and greater than 0, the third rating factor corresponds to a third number less than 1 and greater than 0, the first number is greater than the second number, and the second number is greater than the third number.

[0167] In some embodiments, the difference between the first number and the second number is greater than the difference between the second number and the third number.

[0168] In some embodiments, each sub-region corresponds to a distance between contacting polysilicon.

[0169] In some embodiments, the method further includes modeling an operating temperature of the structure of interest based on a maximum temperature in the revised IC design and a rating factor.

[0170] In some embodiments, the method further includes generating a tapeout archive based on the revised IC design.

[0171] In some embodiments, the method further includes manufacturing an IC device based on the revised IC design.

[0172] According to some embodiments, a method for manufacturing an integrated circuit (IC) device includes identifying a structure of interest in a first IC design; assigning a heat-affected region to a region of the first IC design such that the heat-affected region includes at least a portion of the structure of interest; identifying a plurality of structures that are entirely or partially within the heat-affected region and correspond to IC device elements that self-heat during operation of the IC device based on the first IC design; modeling a plurality of operating temperatures corresponding to the plurality of structures and identifying a highest temperature among the plurality of operating temperatures; identifying, among the plurality of structures, a structure having a highest temperature as a first adjacent structure; calculating a first temperature rise by multiplying the highest temperature by a temperature rise ratio, the temperature rise ratio being a number less than 1 and greater than 0; modeling the first operating temperature of the structure of interest; and evaluating a temperature-dependent electromigration parameter of the structure of interest at a second operating temperature, the second operating temperature being at least the sum of the first operating temperature and the first temperature rise.

[0173] In some embodiments, the method further includes modeling a second temperature rise for at least one transistor, active region, or high-resistance device during operation of the IC device, wherein the second operating temperature is at least the sum of the first operating temperature, the first temperature rise, and the second temperature rise.

[0174] In some embodiments, the temperature rise ratio decreases as the distance between the structure of interest and the first adjacent structure increases.

[0175] In some embodiments, the heat-affected zone has a center located at the structure of interest, and the temperature rise ratio has a minimum value at a location in the heat-affected zone farthest from the center.

[0176] In some embodiments, the method further includes modeling an operating temperature of the structure of interest based on a maximum temperature in the second IC design and a rating factor.

[0177] In some embodiments, the method further includes manufacturing the IC device according to the second IC design.

[0178] According to some embodiments, a system for evaluating electromigration includes at least one memory configured to store device layout design data and a device layout thermal equation; at least one processor configured to: access the at least one memory and obtain the device layout design data and the device layout thermal equation; generate a device layout design from the device layout design data; identify a structure of interest in the device layout design; assign a heat-affected region to an area of ​​the device layout design so that the heat-affected region includes at least a portion of the structure of interest; identify multiple structures that are entirely or partially located within the heat-affected region and correspond to device elements that self-heat during operation of a device based on the device layout design; model multiple operating temperatures corresponding to the multiple structures and identify the highest temperature among the multiple operating temperatures; identify the structure with the highest temperature as a first adjacent structure among the multiple structures; assign a rating factor based on the distance between the structure of interest and the first adjacent structure; and model the operating temperature of the structure of interest based on the highest temperature and the rating factor.

[0179] In some embodiments, the at least one processor is further configured to evaluate a temperature-dependent electromigration parameter of the structure of interest at the operating temperature of the structure of interest.

[0180] In some embodiments, the at least one processor is further configured to model an operating temperature of the structure of interest based on a maximum temperature and a rating factor in the revised device layout design.

[0181] The foregoing summarizes the features of multiple embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. It will be appreciated by those skilled in the art that they can easily use the present disclosure as a basis to design or modify other processes and structures to achieve the same purpose and / or obtain the same advantages of the embodiments introduced herein. It will also be appreciated by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for evaluating thermal effects in integrated circuit design, the method comprising: identifying a structure of interest in the integrated circuit design; assigning a heat-affected region to a region of the integrated circuit design such that the heat-affected region encompasses at least a portion of the structure of interest; identifying a plurality of structures located entirely or partially within the heat-affected zone and corresponding to integrated circuit device components that self-heat during operation of an integrated circuit device based on the integrated circuit design; modeling a corresponding plurality of operating temperatures for the plurality of structures and identifying a highest temperature among the plurality of operating temperatures; identifying, among the plurality of structures, a structure having the highest temperature as a first adjacent structure; assigning a ranking factor based on a distance between the structure of interest and the first neighboring structure; modeling an operating temperature for the structure of interest based on the maximum temperature and the rating factor; evaluating a temperature-dependent electromigration parameter of the structure of interest at the operating temperature of the structure of interest; as well as A revised integrated circuit design is generated by revising the integrated circuit design, wherein generating the revised integrated circuit design includes revising a current specification of the structure of interest based on the evaluation of the temperature-dependent electromigration parameter.

2. The method according to claim 1, wherein: Modeling the plurality of operating temperatures corresponding to the plurality of structures comprises: modeling a temperature rise of the plurality of structures during operation of the integrated circuit device, and Modeling the operating temperature of the structure of interest based on the maximum temperature and the rating factor includes: The temperature rise of the first adjacent structure is multiplied by a number that is less than 1 and greater than 0.

3. The method according to claim 1, further comprising: dividing the heat affected zone into a plurality of sub-regions, each sub-region representing a different distance from the structure of interest, and A corresponding plurality of rating factors are assigned to the plurality of sub-regions.

4. The method according to claim 3, wherein: The plurality of rating factors include a first rating factor, a second rating factor, and a third rating factor, the first rating factor corresponding to the shortest distance from the structure of interest among the first to third rating factors, The first rating factor corresponds to a first number that is less than 1 and greater than 0, the second rating factor corresponds to a second number that is less than 1 and greater than 0, The third rating factor corresponds to a third number that is less than 1 and greater than 0, The first number is greater than the second number, and The second number is greater than the third number.

5. The method according to claim 4, wherein: A difference between the first number and the second number is greater than a difference between the second number and the third number. The method according to claim 3 , wherein each sub-region corresponds to a distance between two contacting polysilicon layers.

7. A method of manufacturing an integrated circuit device, the method comprising: identifying a structure of interest in a first integrated circuit design; assigning a heat-affected region to a region of the first integrated circuit design such that the heat-affected region includes at least a portion of the structure of interest; identifying a plurality of structures located entirely or partially within the heat-affected region and corresponding to components of an integrated circuit device that self-heat during operation of an integrated circuit device based on the first integrated circuit design; modeling a plurality of operating temperatures corresponding to the plurality of structures and identifying a highest temperature among the plurality of operating temperatures; identifying a structure having the highest temperature among the plurality of structures as a first adjacent structure; calculating a first temperature rise by multiplying the maximum temperature by a temperature rise ratio, wherein the temperature rise ratio is a number less than 1 and greater than 0; modeling a first operating temperature for the structure of interest; evaluating a temperature-dependent electromigration parameter of the structure of interest at a second operating temperature, the second operating temperature being at least a sum of the first operating temperature and the first temperature rise; revising a current specification for the structure of interest based on the evaluation of the temperature-dependent electromigration parameter; as well as A second integrated circuit design is generated by revising the first integrated circuit design to include the revised current specification of the structure of interest.

8. The method according to claim 7, further comprising: modeling a second temperature rise for at least one transistor, active region, or high-resistance device during operation of the integrated circuit device, The second operating temperature is at least the sum of the first operating temperature, the first temperature rise, and the second temperature rise.

9. The method according to claim 7, wherein: The heat affected zone has a center located at the structure of interest, and The temperature rise ratio has a minimum value at a position farthest from the center in the heat-affected zone.

10. A system for evaluating electromigration, comprising: at least one memory configured to store device layout design data and device layout thermal equations; At least one processor is configured to: accessing the at least one memory and obtaining the device layout design data and the device layout thermal equation; generating a device layout design according to the device layout design data; identifying structures of interest in the device layout design; assigning a heat-affected region to an area of ​​the device layout design such that the heat-affected region includes at least a portion of the structure of interest; identifying a plurality of structures located in whole or in part within the heat-affected zone and corresponding to device elements that self-heat during operation of the device based on the device layout design; modeling a plurality of operating temperatures corresponding to the plurality of structures and identifying a highest temperature among the plurality of operating temperatures; identifying, among the plurality of structures, a structure having the highest temperature as a first adjacent structure; assigning a ranking factor based on a distance between the structure of interest and the first neighboring structure; modeling an operating temperature of the structure of interest based on the maximum temperature and the rating factor; as well as A revised device layout design is generated by revising the device layout design, wherein generating the revised device layout design includes revising a current specification of the structure of interest based on the evaluation of the temperature-dependent electromigration parameter.

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