Pseudo-random sequence generation system based on four-dimensional hyper-chaotic system

Abstract

The invention relates to the field of information security and random number generation, and discloses a pseudo-random sequence generation system based on a four-dimensional hyperchaotic system, and the system comprises a chaotic signal generation module which is used for generating a chaotic state track composed of four state variables; the numerical solution module is used for carrying out multi-step numerical integral iteration on the state variable; the signal optimization module is used for performing cross recombination, disturbance arrangement and nonlinear quantization on the state variables; the control management module is used for controlling initialization, operation time sequence and state synchronization of each module; and the output interface module is used for outputting the pseudorandom sequence. According to the method, a four-dimensional hyper-chaotic system and a double positive Lyapunov index structure are adopted as a core dynamics basis, the technical effect of improving the unpredictability of the pseudo-random sequence and the trajectory complexity is achieved, and the potential safety hazards that the dynamic behavior is single, the dependence on initial conditions is too weak and the like are effectively overcome.

Description

Technical Field

[0001] The present invention relates to the fields of information security and random number generation, and in particular to a pseudo-random sequence generation system based on a four-dimensional hyperchaotic system. Background Art

[0002] In modern information systems, pseudo-random sequence generation has become the underlying support for multiple critical scenarios, including secure communications, encrypted transmission, identity authentication, and IoT protection. Whether it's key expansion in symmetric cryptography or synchronization control of frequency-hopping signals, the random quality of the sequence directly determines the system's ability to withstand attacks. Especially in high-speed communications and lightweight deployment environments, there is an urgent need for a pseudo-random sequence generation mechanism that combines high randomness with rapid generation.

[0003] Several technical solutions are currently gaining widespread application in pseudo-random number generation. For example, the linear feedback shift register (LFSR) offers advantages such as high generation speed and simple implementation, making it suitable for low-power scenarios. Some improved algorithms also employ classical three-dimensional chaotic systems in conjunction with numerical integration methods, which can simulate nonlinear system behavior to a certain extent, resulting in a preliminary level of unpredictability in the output sequence. Other research attempts to embed high-precision floating-point Runge-Kutta solvers into embedded devices, pursuing both numerical accuracy and system dynamic fidelity.

[0004] However, existing technologies still have many unavoidable limitations. Three-dimensional chaotic systems are often easily restored by mathematical modeling due to their simple dynamic structures and single trajectory evolution patterns. However, once the initial state of the sequence is leaked, the overall security will collapse. Other floating-point algorithms, while highly accurate, are computationally intensive to implement in hardware, making them unsuitable for deployment on resource-constrained platforms. At the output level, many designs rely solely on basic modular operations or truncation, making output patterns susceptible to detection, especially in NIST tests where occasional failures are common. Some algorithms also attempt to perturb and permute state variables, but these lack deep cross-cutting designs, resulting in high data redundancy and low perturbation efficiency. Therefore, those skilled in the art have proposed a pseudo-random sequence generation system based on a four-dimensional hyperchaotic system to address these issues. Summary of the Invention

[0005] In response to the shortcomings of the existing technology, the present invention provides a pseudo-random sequence generation system based on a four-dimensional hyperchaotic system, which solves the core problems of the existing pseudo-random number generation technology in terms of randomness intensity, system security and hardware deployment adaptability.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a pseudo-random sequence generation system based on a four-dimensional hyperchaotic system, comprising: A chaotic signal generation module is used to generate a chaotic state trajectory consisting of four state variables; A numerical solution module, used for performing multi-step numerical integration iteration on the state variables; A signal optimization module, configured to perform cross-recombination, perturbation arrangement, and nonlinear quantization on the state variables; Control management module, used to control the initialization, operation sequence and status synchronization of each module; The output interface module is used to output a pseudo-random sequence.

[0007] Preferably, the chaotic signal generating module includes: Initial value setting unit, used to set the four-dimensional state variables ; Parameter setting unit, used to set the control parameters of the chaotic system 、 、 ; The state evolution unit is used to implement the following state variable relationship: The derivative of the first state variable is the product of the third state variable and the second state variable minus a constant The product of and the fourth state variable; The derivative of the second state variable is the fourth state variable minus a constant The product of the first state variable; The derivative of the third state variable is the product of the first state variable and the second state variable minus a constant The product of the third state variable; The derivative of the fourth state variable is the inverse of the product of the first state variable and the second state variable.

[0008] Preferably, the numerical solution module includes: A step size setting unit is used to set the discretization step size; A fourth-order Runge-Kutta unit is used to perform four intermediate calculations based on the current state variable values ​​and update the state values; The variable cache unit is used to store the state variable value of each iteration for subsequent calls.

[0009] Preferably, the signal optimization module includes: A multi-dimensional perturbation arrangement unit is used to implement cross-dimensional cross-rearrangement of four-dimensional state variables; A bit width mapping unit is used to convert continuous real state values ​​into fixed-point format; The nonlinear transformation unit is used to perform modular operation, truncation operation and offset coding processing on the mapping result.

[0010] Preferably, the control management module includes: A timing control unit is used to coordinate the operation sequence of the chaotic signal generation module and the numerical solution module; State synchronization unit, used to maintain data consistency in each stage of the system; The initialization and reset unit is used for system power-on initialization and abnormal status clearing.

[0011] Preferably, the output interface module includes: A data formatting unit, used for converting a pseudo-random sequence into a fixed-length bit stream; Output channel selection unit, used to select parallel or serial output mode; Cache scheduling unit, used to match external read rates and manage data buffering.

[0012] Preferably, the initial value setting unit supports a random perturbation mechanism to make the initial value unpredictable; The parameter setting unit defines 、 、 are fixed real numbers, namely 1, 8, and 1; The state evolution unit is implemented in FPGA logic and can be updated at the clock edge.

[0013] Preferably, the perturbation arrangement unit performs an index transformation operation on the state variable to generate a cyclic index sequence; The bit width mapping unit extracts the decimal part of the state variable, expands it by a multiple, and then truncates it to form an 8-bit integer; The nonlinear transformation unit maps integer values ​​to the interval [1, 256] through a double-layer modular operation.

[0014] Preferably, the pseudo-random sequence generation system passes the NIST SP800-22 test and supports standard verification of indicators such as randomness, frequency, run length, block frequency, and linear complexity; The sequence output rate is not less than 100MB / s; The system has anti-interference and fault-tolerant mechanisms.

[0015] Preferably, the system is deployed on an FPGA platform, supporting the parallel output of multiple random bit streams; the system structure adopts a modular layered design, and each module has an independent callable logic interface; the overall resource scheduling strategy of the system adopts a combination of static configuration and dynamic tuning The present invention provides a pseudo-random sequence generation system based on a four-dimensional hyperchaotic system. It has the following beneficial effects: 1. The present invention adopts a four-dimensional hyperchaotic system and a double-positive Lyapunov exponent structure as its core dynamics, achieving the technical effect of improving the unpredictability and trajectory complexity of pseudo-random sequences. Compared with the existing common three-dimensional chaotic system with only a single positive exponent and limited chaotic performance, it effectively overcomes the safety risks of its single dynamic behavior and weak dependence on initial conditions.

[0016] 2. By introducing a modular structure and asynchronous FIFO cache under the FPGA architecture, the present invention realizes multi-channel parallel pseudo-random output and a sequence rate exceeding 100MB / s. Traditional CPU simulation generators based on floating-point solutions have difficulty in balancing rate and randomness and are severely limited by timing control and resource conflicts. This technical solution avoids such performance bottlenecks.

[0017] 3. The present invention uses a combination of signal perturbation rearrangement and double-layer nonlinear mapping to quantize chaotic trajectories and cleverly constructs a high-entropy pseudo-random integer stream. Compared with the existing sequence construction mechanism that only uses modular operations or truncation, it significantly enhances the statistical independence of the final output and avoids the occurrence of low-bit repetitions or fixed patterns in the sequence.

[0018] 4. The present invention combines the fourth-order Runge-Kutta method and the dynamic step-size control strategy. While ensuring the chaotic accuracy of the system, the present invention significantly reduces the computational complexity of each iteration. Existing hyperchaotic systems often suffer from distorted dynamic characteristics due to floating-point precision degradation in hardware. This solution effectively resolves the contradiction between computational redundancy and precision degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the system architecture of the present invention; Figure 2 This is a schematic diagram of the chaotic signal generating module architecture of the present invention; Figure 3 This is a schematic diagram of the numerical solution module architecture of the present invention; Figure 4 This is a schematic diagram of the signal optimization module architecture of the present invention; Figure 5 This is a schematic diagram of the control and management module architecture of the present invention; Figure 6 This is a schematic diagram of the output interface module architecture of the present invention. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the present specification. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0021] Please see the attached Figure 1 -Attached Figure 6 , an embodiment of the present invention provides a pseudo-random sequence generation system based on a four-dimensional hyperchaotic system, comprising: A chaotic signal generation module is used to generate a chaotic state trajectory consisting of four state variables; Specifically, in the four-dimensional hyperchaotic pseudo-random sequence generation system involved in the present invention, the logical relationships between the functional modules are meticulously divided to ensure the modular design and functional controllability of the entire system structure. Typically, the generation of pseudo-random sequences relies on the complex dynamic characteristics of high-dimensional chaotic systems. Especially when implemented on hardware platforms such as FPGAs, it is necessary to efficiently discretize the continuous dynamic evolution of chaotic equations using a modular structure. To this end, the present invention separately encapsulates the chaotic signal generation process into a chaotic signal generation module, which serves as the data source and entropy source for the entire system and plays a decisive role in the randomness of the sequence.

[0022] This module is the initial execution point in the system, and its output directly influences the subsequent pseudo-random sequence construction and signal optimization process. Therefore, this module requires a simple structure, clear logic, and stable computation to meet the requirements of high performance and low resource consumption. In its implementation, the module consists of three subunits: an initial value setting unit, a parameter setting unit, and a state evolution unit. This module is described in detail below.

[0023] In this embodiment, the chaotic signal generation module is used to generate a chaotic state trajectory composed of four state variables as source data for generating a pseudo-random sequence.

[0024] In one possible implementation, the module includes three parts: an initial value setting unit, a parameter setting unit, and a state evolution unit: In the initial value setting unit, the system supports setting initial values ​​based on a mechanism of external random perturbations to ensure that the sensitivity of chaotic trajectories to initial conditions is fully reflected.

[0025] Specifically, the initial state variables can be set as: ; As an option, a 10 -14 Small perturbations at the same level increase the unpredictability of pseudo-randomness.

[0026] In the parameter setting unit, in order to ensure the fixed-point stability and chaotic performance of the system in hardware implementation, the chaotic system control parameters are set as follows: , , ; Typically, these parameters are mapped to 42-bit fixed-point numbers to facilitate efficient discrete processing in the FPGA. This setting ensures that the system always operates in a hyperchaotic state, with good structural symmetry and controllable system response.

[0027] The state evolution unit is the core of the entire module, which updates the state based on a four-dimensional chaotic dynamics system in the form of continuous differential equations. The state variables are , , , , the corresponding differential relationship is defined as follows: ; ; ; ; in: , , , are four state variables, all of which are time function; , , is a fixed control parameter, and its specific value is as mentioned above; is the system running time variable, in seconds (s); , , , represents the derivative of each state variable.

[0028] The above differential relationship represents the dynamic process of the system state evolving over time. In the discrete implementation, the state evolution unit does not directly solve the continuous differential, but instead updates the state variables at each clock edge using small steps and long iterations.

[0029] In one possible digital implementation, the state evolution unit, based on internal fixed-point multipliers and adders, works with state machine control logic to update state variables once per clock cycle. The results of the state variable iterations are written to a register array in real time and provided to the next-level numerical solution module.

[0030] As a design optimization method, the state evolution unit can embed redundant check logic to detect numerical overflow or exponential divergence anomalies. This mechanism is based on boundary comparison and sign bit detection algorithm. If it is detected that the state variable exceeds the specified safety interval at a certain moment (such as ), will trigger the reset mechanism or enter state latch.

[0031] In one specific hardware architecture, the state evolution unit is tied to the FPGA's on-chip phase-locked loop (PLL) clock resource, with each state update triggered by the rising edge of the PLL. This mechanism synchronizes the evolution rhythm with the system's master clock, ensuring strict timing consistency during state variable updates and preventing data races.

[0032] To further support the system's hyperchaotic properties, mathematical simulations were performed. Using the MATLAB platform, the Lyapunov spectrum was calculated using the QR decomposition method. The steps are as follows: First, an initial state point is selected and a unit orthogonal perturbation matrix is ​​added to describe the propagation of small perturbations in the system's four principal directions. Next, the fourth-order Runge-Kutta method is used to numerically integrate the system's initial state trajectory and simultaneously solve the corresponding perturbation propagation equation, which is constructed from the system's Jacobian matrix (i.e., partial derivative matrix). This Jacobian characterizes the system's sensitivity to perturbations in its current state and is continuously updated as the system's trajectory progresses. At fixed simulation time intervals, the system performs a QR decomposition on the perturbation matrix, splitting it into an orthogonal matrix and an upper triangular matrix. The diagonal elements of the resulting upper triangular matrix are used to measure the local amplification or contraction ratio of the perturbation. By taking the logarithm of these diagonal elements and averaging them over the entire simulation time, the Lyapunov exponent values ​​in the four directions are obtained. The resulting four Lyapunov exponent values ​​are: , , , ; The two positive values ​​in the above results indicate that the system's state diverges exponentially in both directions and exhibits attractor characteristics, forming an embedded fractal structure within the four-dimensional phase space. This complex structure makes its trajectory irreversible and unpredictable.

[0033] From a systems engineering perspective, the four state variables output by this module are directly fed into the numerical solver for Runge-Kutta iteration. Prior to the iteration, the system does not output any pseudo-random sequences to prevent the guidance sequence from leaking its structure. This design fully guarantees the quality of the initial entropy source for pseudo-random sequence generation.

[0034] As an extension, the chaotic signal generation module can also be used in heterogeneous platform deployments, such as embedding ARM processor collaborative control in a SoC architecture or building a continuous-time version in an analog circuit platform (such as Multisim), while maintaining the same differential relationship.

[0035] A numerical solution module, used for performing multi-step numerical integration iteration on the state variables; Specifically, in the pseudo-random sequence generation system based on a four-dimensional hyperchaotic system provided by the present invention, after the chaotic signal generation module completes the establishment of the initial state variables, the resulting four-dimensional state trajectory must be input into the numerical solution module for iterative updating. The numerical solution module is responsible for discretizing the system state equation and promoting the continuous evolution of the state variables in phase space through precise numerical methods. Its iterative output not only serves as the core support for the continuous generation of chaotic signals, but also directly affects the timing integrity and randomness quality of subsequent signal perturbation and optimization links.

[0036] Generally, continuous-time chaotic systems are difficult to implement directly on digital circuit platforms. Therefore, the differential equations must be converted into executable numerical form through discrete iterations. To ensure numerical accuracy and system stability, the fourth-order Runge-Kutta (RK4) method is used to solve the state equation. This method offers high approximate accuracy and computational stability, making it suitable for solving the evolution of multivariable, strongly coupled systems. It has particular advantages in the four-dimensional hyperchaotic system of the present invention.

[0037] In this embodiment, the numerical solution module includes a step size setting unit, a fourth-order Runge-Kutta unit, and a variable buffer unit. Each submodule is interconnected by a data channel and has independent control logic.

[0038] In a possible implementation, the step size setting unit is used to set the discrete step size of the system numerical iteration. The step size is recorded as , is a positive real number. In the present invention, the step value is generally set to: ; This value is empirically selected to ensure a certain level of integration accuracy while ensuring stable system operation. Alternatively, a dynamic step size can be configured, adjusting based on system operating status or external commands. For example, if the master control system determines that the rate of change of the state variable is too rapid, the step size can be automatically reduced to suppress error diffusion.

[0039] Specifically, the fourth-order Runge-Kutta element is used for the four state variables , , , Synchronously perform an iterative update. The following uses the state variable For example, the RK4 iterative calculation steps are as follows: ; ; ; ; ; in: , , , is the state variable value at the current iteration moment; is the step length; , , , is the estimated value of the intermediate slope; function Indicates the variables in the original system The derivative function of , that is: .

[0040] The remaining three variables , , The RK4 update method follows the same structure, with each variable being calculated using its own derivative expression. To facilitate calculations, the system separates the slope calculation and variable update into two pipeline stages, allowing the calculation of the four variables to be completed in parallel.

[0041] As a structural optimization, the fourth-order Runge-Kutta cell utilizes hard-coded multiplication-addition logic on the FPGA platform, combining fixed-point multipliers and adders to enable rapid evaluation of intermediate results. Calculation results retain 18-bit fixed-point precision, and fixed-point truncation blocks constrain the error range to prevent error accumulation. Each complete RK4 iteration completes within eight master clock cycles, achieving tens of millions of state updates per second at a 100MHz clock frequency.

[0042] In some embodiments, to avoid numerical divergence or the influence of initial states, the present invention implements a pre-iteration mechanism. This mechanism prevents the output of the first several iterations after system initialization. For example, the number of pre-iterations can be set to 1000, and variable results are released for subsequent module calls only after the system state enters a stable attractor range.

[0043] The variable cache unit is used to save the updated state variable values ​​after each round of iteration. The unit is internally configured with multiple register groups, which are used to store variables , and supports a dual-end read / write interface. One end is directly connected to the RK4 computation logic, while the other end is open to the signal optimization module. The cache uses a circular storage structure, which can store the values ​​of the last N rounds of state variables, which can be used to construct delay sequences or cross-rearrangement operations.

[0044] In one specific architecture, the variable cache unit supports cross-clock domain access and asynchronous value retrieval based on system scheduling, making it suitable for multi-threaded parallel architecture deployment. Furthermore, the unit integrates a status flag to indicate whether the variable contains a valid result, preventing premature reading of values ​​that have not yet been updated.

[0045] From the perspective of expanding applications, the versatility of the numerical solution module also enables iterative applications for other chaotic systems. For example, by replacing the state function expression or increasing the coupling dimension, higher-dimensional chaotic models or dual-system coupling structures can be constructed based on this module, showing excellent scalability.

[0046] A signal optimization module, configured to perform cross-recombination, perturbation arrangement, and nonlinear quantization on the state variables; Specifically, in the proposed pseudo-random sequence generation system based on a four-dimensional hyperchaotic system, a numerical solution module performs discrete iterations of chaotic state variables, resulting in a continuously updated four-dimensional variable trajectory. To further enhance the unpredictability and complexity of the generated pseudo-random sequence, it is necessary to perturb and restructure these continuous real-valued state variables to avoid numerical correlations or recognizable patterns present in the original chaotic trajectory. To this end, a signal optimization module is provided, specifically designed to convert the discretely solved state variable sequence into a pseudo-random sequence with complex structure and excellent statistical properties in the discrete integer domain.

[0047] While the state variables output by chaotic systems typically possess certain chaotic properties, they lack continuity and numerical smoothness, making them difficult to directly use as a high-intensity random number source for security applications. To address this issue, the present invention incorporates multi-layer perturbation rearrangement, bit width compression, and nonlinear mapping mechanisms into the signal optimization module. By multidimensionally processing the variable structure and values, the nonlinear characteristics of the output sequence are effectively enhanced.

[0048] In this embodiment, the signal optimization module includes a multi-dimensional perturbation arrangement unit, a bit width mapping unit and a nonlinear transformation unit, and the units are sequentially connected in a pipeline manner to achieve a step-by-step construction of a pseudo-random output.

[0049] In one possible implementation, the multi-dimensional perturbation arrangement unit is used to perturb the four-dimensional state variables from the numerical solution module. , , , Perform dimension rearrangement and sequence perturbation. This rearrangement operation uses a cyclic indexing strategy to implement cross-variable mixing and time-series crossover for each round of state variables. Specifically, the following perturbation sequence is constructed: ; Among them: Among them: , , , Represents the set of rearranged sequences constructed in each round of perturbation.

[0050] The above sequence combines variables using a preset rearrangement rule and updates the index position in each iteration, thereby destroying the original association of the variables. In the implementation process, the order of each group of variables is generated based on the following loop index formula: ; in: is the current iteration number; Number the current variable group; is the perturbation sequence period; Represents the modulo operation.

[0051] As an option, the perturbation rearrangement structure can be embedded with an exponential variable-step perturbation mechanism, that is, the rearrangement mode is automatically changed after a certain number of steps M to increase the degree of dynamic perturbation.

[0052] In the present invention, the bit width mapping unit is used to map the rearranged state variables from the continuous real number space to the integer space with a finite bit width. Specifically, first extract the decimal part of the variable value , and then perform amplification, truncation and rounding operations. The mapping process is as follows: ; in: Represents a sequence of rearranged variables (such as The item); Indicates its decimal part; is the magnification; Indicates a floor operation.

[0053] The above operation retains the real number precision to 10 -14 level, effectively amplifying the perturbation information and improving the random granularity. It is an unsigned integer with a width of up to 64 bits.

[0054] Specifically, the nonlinear transformation unit is used to perform multi-layer perturbation operations on the mapping results, further compressing the bit width and constructing a pseudo-random output. In one possible implementation, a combination of two-layer modular operations, weighted coding, and truncation operations is used for processing. The mapping formula is as follows: ; in: The final output is a pseudo-random integer; the inner and outer double-layer modular operation effectively removes the high-order pattern features; Operation ensures that the output range is within Within the interval, avoid the risk of sequence duplication caused by outputting zero values.

[0055] In some embodiments, in order to enhance the nonlinear perturbation effect, the nonlinear transformation unit may also introduce a variable modulus factor or an XOR scrambling mechanism, combined with a preset dynamic constant to Perform disturbance processing, the formula can be expressed as: ; in: is the preset scrambling code value; is the disturbance factor; Represents a bitwise exclusive OR operation.

[0056] This processing method is extremely sensitive to adjacent values, and even small initial changes can cause global changes in the results, reflecting the high uncertainty and chaotic characteristics of the system output.

[0057] To support internal timing consistency and resource reuse, the signal optimization module utilizes a synchronized triggering scheme. Each completed numerical solution iteration triggers the signal optimization process, outputting a set of 8-bit pseudo-random integers. Multiple outputs can be concatenated through a cache structure to form high-width random bit streams, such as 32-bit and 64-bit ones.

[0058] From a system architecture perspective, the signal optimization module not only supports the four-dimensional chaotic source described in this paper but also adapts to the outputs of various nonlinear systems, demonstrating excellent versatility and engineering reusability. In actual deployment, the perturbation structure, bit width, and modular operation can be customized based on application requirements.

[0059] Control management module, used to control the initialization, operation sequence and status synchronization of each module; Specifically, after the signal optimization module completes the perturbation and quantization of the chaotic state variables, a unified scheduling mechanism is introduced to manage and control each submodule to ensure the coordinated operation, data synchronization, and functional stability of the entire system. Therefore, a control management module is provided in the pseudo-random sequence generation system based on a four-dimensional hyperchaotic system constructed by the present invention. This module is used to perform unified scheduling of each subunit of the system, including initialization procedures, runtime coordination, and state synchronization maintenance, thereby achieving stable communication and functional coupling between modules, ensuring the controllability and reliability of the entire system.

[0060] Typically, chaotic sequence generation systems contain multiple high-frequency computational units, each with strong logical dependencies. Without centralized scheduling and control, these can easily lead to operational races, data inconsistencies, or state drift, compromising system output quality. To address this, the present invention incorporates a control management module to coordinate the sequential logic relationships between the chaotic signal generation module, numerical solution module, and signal optimization module, while ensuring the stable transmission of various intermediate variables.

[0061] In this embodiment, the control management module includes a timing control unit, a state synchronization unit, and an initialization and reset unit. This module exists as the master control in the entire system and is typically deployed on the main control unit or scheduling core. It establishes command and feedback channels with each functional module through signal lines.

[0062] Specifically, the timing control unit is used to coordinate the operation sequence between the chaotic signal generation module and the numerical solution module. In one possible implementation, a state machine structure is used to divide the system operation phases, and the following timing process is defined: state Waiting for the start signal; state Perform initial chaotic excitation; state Start the numerical solution module and iteratively calculate the chaotic trajectory; state Start the signal optimization module to perform variable perturbation and mapping; state Output a pseudo-random sequence and determine whether to continue iterating.

[0063] The above states are switched through the following sequential logic formula: ; in: Indicates the current state; Trigger signal for current event; is the state transfer function, defined by the control logic.

[0064] In some embodiments, the state switching mechanism adopts a clock edge triggering strategy and combines external interrupt events for fine scheduling, thereby taking into account both response speed and system load balancing.

[0065] The state synchronization unit is used to maintain data consistency in the system at all stages of operation, preventing variable mismatches or confusion caused by concurrent access. In one possible implementation, the unit introduces a double-buffering mechanism to separate variable writes and reads, namely: The current calculation cycle uses buffer A for data reading and writing; The next cycle switches to buffer B; Cache swapping is performed after each cycle to maintain data continuity.

[0066] To ensure synchronization accuracy, the state synchronization unit uses a trigger flag with a mutex mechanism to achieve data isolation and consistent updates between threads or modules, which can be specifically expressed as: ; As an option, a CRC check or hash summary mechanism can be introduced into the state synchronization unit to perform consistency detection on cross-module variables. Introduce the quick verification formula: ; in: Representing variables No. bytes; It is a 16-bit check code; Variable length.

[0067] In high-concurrency system scenarios, this verification method can effectively detect data drift and improve synchronization robustness.

[0068] The initialization and reset unit is used to load the initial configuration after the system is powered on, and to restore the system to a safe operating state when an abnormal state occurs. This unit performs the initialization process when the system is first powered on, including: Load the initial chaos parameters; Set the initial operating status of each module; Clear cache registers and intermediate variables; Set the interrupt response table and exception handling priority.

[0069] In a specific implementation, the abnormality detection logic is set on the control path and the output path. When the output value is found to be abnormal continuously, the calculation is interrupted, or the data synchronization fails, the reset process is immediately triggered. The reset process is divided into soft reset and hard reset: Soft reset retains non-critical state variables and only re-executes initialization operations; A hard reset cycles power to all modules to ensure the system restarts from a stable initial state.

[0070] To avoid performance loss caused by frequent resets, the reset threshold can be set using the following dynamic adjustment formula: ; in: Indicates the current reset threshold; is the initial setting value; is the regulating factor; The cumulative number of historical anomalies.

[0071] The above mechanism ensures that the control module has good fault tolerance and dynamic adaptability.

[0072] The output interface module is used to output a pseudo-random sequence.

[0073] Specifically, after the control and management module completes unified scheduling of system states and runtime management, the resulting pseudo-random number sequence must be stably and efficiently output to external devices or upper-layer application systems. To this end, the present invention incorporates an output interface module, which serves as a data transmission bridge between the system and the external environment. This module is used to format, select output modes, and adjust the rate of the pseudo-random sequence optimized by the previous stage, thereby ensuring that the pseudo-random bit stream can be quickly and correctly received and used by the upper-layer system.

[0074] Typically, the direct output of chaotic pseudo-random numbers often causes difficulties for the receiving end due to inconsistent data formats and timing mismatches, and can even affect communication stability. Especially for high-frequency or high-speed interfaces, output buffer management and data channel configuration are particularly critical. Based on these considerations, the present invention integrates a data formatting unit, an output channel selection unit, and a buffer scheduling unit into the output interface module, thereby improving output controllability and system adaptability.

[0075] In this embodiment, the first functional subunit of the output interface module is a data formatting unit, which is used to convert the integer pseudo-random sequence generated by the previous module into a standard fixed-length bit stream format for subsequent transmission and decoding.

[0076] Specifically, the output of the previous nonlinear transformation module is set to an 8-bit integer , then the integer is first converted into a binary codeword in a fixed format: ; in: Indicates the Group pseudo-random bit stream; Indicates the decimal to binary format conversion operation.

[0077] To ensure the consistency of codeword length, the system adopts a zero-padding mechanism, namely: ; in: Indicates that Padded to 8-bit binary format with constant bit width.

[0078] In some embodiments, the endianness of the output bit stream can be configured according to the external interface protocol, such as big-endian mode (MSB-first) or little-endian mode (LSB-first), to enhance the protocol compatibility of the system.

[0079] As an option, if the upper layer system requires a wider bit block, several Sequential splicing is performed to form a 32-bit, 64-bit or longer fixed-length code block: ; in: Represents a bitwise concatenation operation; Represents a 32-bit output block.

[0080] The output channel selection unit is used to select the output mode according to the system configuration, including parallel output and serial output. In one possible implementation, the system sets the output mode by configuring the control word, as follows: ; In serial mode, a single bit is output per cycle, triggered by the clock edge: , ; in: Indicates the current bit position; Indicates the current clock cycle.

[0081] In parallel output mode, a complete code word is directly output each cycle , improve the output rate and is suitable for high-speed communication interfaces.

[0082] In some embodiments, to support dynamic channel switching, the output channel selection unit integrates status monitoring logic. When serial channel congestion or interface abnormality is detected, it automatically switches to parallel output mode to achieve adaptive control.

[0083] The cache scheduling unit is used to coordinate the matching relationship between the output rate and the upper layer reading rate to prevent data blocking or loss. In this embodiment, a FIFO buffer mechanism is used to achieve data temporary storage, and the buffer depth can be dynamically adjusted: ; in: Indicates the frequency of data generation within the system; Indicates external reading frequency; is the minimum cache block length; is the ceiling function.

[0084] Specifically, the cache scheduling unit maintains two pointers: write pointer With read pointer .when When there is no external reading, the system determines that the cache is full and suspends writing; when When the write rate is higher than the read rate, the throttling mechanism is activated to reduce the write frequency.

[0085] In some embodiments, the cache scheduling unit also integrates a rate prediction module, which analyzes the external reading speed change trend through a sliding window to allocate resources in advance and improve data throughput stability.

[0086] In addition, in some embodiments, to verify the statistical performance of the pseudo-random sequence generated by the system, the system performs a complete randomness test based on the NIST SP800-22 standard test framework.

[0087] Specifically, the tests cover 15 indicators, including single-bit frequency testing, runs, intra-block frequency testing, approximate entropy testing, and linear complexity testing. After testing the system output sequence with a sampling volume exceeding 1Gb, the p-values ​​for each test fell within an acceptable confidence interval (typically 0.01–0.99), meeting the requirements for statistical randomness, and the pass rate exceeded the NIST recommended standard of 95%.

[0088] In terms of system output performance, after resource optimization, the sustained output rate of pseudo-random sequences reaches or exceeds 100MB / s, making it suitable for applications such as high-speed encryption and decryption, key expansion, and real-time simulation. Furthermore, to enhance system stability and practicality, multi-level fault tolerance and interference detection mechanisms have been introduced into the control and management module. For example, abnormal interrupt response logic has been incorporated into the timing control and state synchronization unit to quickly identify sudden data drift, clock anomalies, and buffer overflows, and initiate soft resets or state recovery.

[0089] This fault-tolerance mechanism significantly enhances the system's stability under adverse operating conditions such as electromagnetic interference and timing drift, ensuring consistent pseudo-random output. In some embodiments, the pseudo-random sequence generation system is deployed on an FPGA-based platform to improve processing efficiency and support flexible expansion.

[0090] Specifically, the system adopts a completely modular design structure, including a chaotic excitation module, a numerical solution module, a signal optimization module, a control management module and an output interface module. Each module is encapsulated with a standard interface definition, supports independent calling and reuse, and facilitates rapid integration and application reconstruction.

[0091] In actual deployment, by utilizing the parallel resource characteristics of the FPGA chip, the system can support the synchronous and parallel generation of multiple pseudo-random bit streams. Each sequence has an independent initial value input and an independent output channel, meeting the high-speed randomness requirements of multiple channels.

[0092] As a possible implementation, system resource scheduling employs a hybrid strategy of "static configuration + dynamic tuning": basic hardware resources are statically allocated by the synthesis tool, while some frequencies, channels, and cache depths are dynamically adjusted during operation based on external load, cache status, and other parameters. This scheduling strategy not only improves FPGA resource utilization but also enhances the system's adaptability and operational flexibility to diverse operating scenarios.

[0093] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A pseudo-random sequence generation system based on a four-dimensional hyperchaotic system, characterized in that: include: A chaotic signal generation module is used to generate a chaotic state trajectory consisting of four state variables; A numerical solution module, used for performing multi-step numerical integration iteration on the state variables; A signal optimization module, configured to perform cross-recombination, perturbation arrangement, and nonlinear quantization on the state variables; Control management module, used to control the initialization, operation sequence and status synchronization of each module; The output interface module is used to output a pseudo-random sequence.

2. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 1, characterized in that: The chaotic signal generating module comprises: Initial value setting unit, used to set the four-dimensional state variables ; Parameter setting unit, used to set the control parameters of the chaotic system 、 、 ; The state evolution unit is used to implement the following state variable relationship: The derivative of the first state variable is the product of the third state variable and the second state variable minus a constant The product of and the fourth state variable; The derivative of the second state variable is the fourth state variable minus a constant The product of the first state variable; The derivative of the third state variable is the product of the first state variable and the second state variable minus a constant The product of the third state variable; The derivative of the fourth state variable is the inverse of the product of the first state variable and the second state variable.

3. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 1, characterized in that: The numerical solution module includes: A step size setting unit is used to set the discretization step size; A fourth-order Runge-Kutta unit is used to perform four intermediate calculations based on the current state variable values ​​and update the state values; The variable cache unit is used to store the state variable value of each iteration for subsequent calls.

4. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 1, characterized in that: The signal optimization module includes: A multi-dimensional perturbation arrangement unit is used to implement cross-dimensional cross-rearrangement of four-dimensional state variables; A bit width mapping unit is used to convert continuous real state values ​​into fixed-point format; The nonlinear transformation unit is used to perform modular operation, truncation operation and offset coding processing on the mapping result.

5. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 1, characterized in that: The control management module includes: A timing control unit is used to coordinate the operation sequence of the chaotic signal generation module and the numerical solution module; State synchronization unit, used to maintain data consistency in each stage of the system; The initialization and reset unit is used for system power-on initialization and abnormal status clearing.

6. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 1, characterized in that: The output interface module includes: A data formatting unit, used for converting a pseudo-random sequence into a fixed-length bit stream; Output channel selection unit, used to select parallel or serial output mode; Cache scheduling unit, used to match external read rates and manage data buffering.

7. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 2, characterized in that: The initial value setting unit supports a random perturbation mechanism to make the initial value unpredictable; The parameter setting unit defines 、 、 are fixed real numbers, namely 1, 8, and 1; The state evolution unit is implemented in FPGA logic and can be updated at the clock edge.

8. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 4, characterized in that: The disturbance arrangement unit performs an index transformation operation on the state variable to generate a cyclic index sequence; The bit width mapping unit extracts the decimal part of the state variable, expands it by a multiple, and then truncates it to form an 8-bit integer; The nonlinear transformation unit maps integer values ​​to the interval [1, 256] through a double-layer modular operation.

9. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to claim 1, characterized in that: The pseudo-random sequence generation system has passed the NIST SP800-22 test and supports standard verification of indicators such as randomness, frequency, run length, block frequency, and linear complexity; The sequence output rate is not less than 100MB / s; The system has anti-interference and fault-tolerant mechanisms.

10. The pseudo-random sequence generation system based on a four-dimensional hyperchaotic system according to any one of claims 1 to 9, characterized in that: The system is deployed on an FPGA platform and supports parallel output of multiple random bit streams. The system structure adopts a modular layered design, and each module has an independent and callable logic interface. The overall resource scheduling strategy of the system adopts a combination of static configuration and dynamic tuning.

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