Light emitting diode for improving electric leakage and preparation method thereof

Abstract

The invention provides a light emitting diode for improving electric leakage and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The preparation method of the light-emitting diode comprises the following steps: forming an epitaxial structure on a patterned substrate; the surface, away from the patterned substrate, of the epitaxial structure is bonded to a conductive substrate, and the patterned substrate is removed; the surface, away from the conductive substrate, of the epitaxial structure is etched, a first groove is formed, etching gas comprises chlorine and boron trichloride, the upper power of etching equipment in at least part of stages in the etching process is smaller than or equal to 500 W, and the lower power of the etching equipment in at least part of stages in the etching process is smaller than or equal to 300 W. According to the embodiment of the invention, the problem of over-etching of the epitaxial layer can be improved, and electric leakage caused by short circuit of the film layer after over-etching can be avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved leakage current and a preparation method thereof. Background Art

[0002] Light-emitting diodes (LEDs) are common products. LEDs are typically manufactured by fabricating various film layers on a substrate, performing patterning, and then cutting them into individual LED cores.

[0003] In the related art, during the fabrication process of light-emitting diodes, epitaxial layers are typically grown on a patterned substrate. The surface of the patterned substrate typically features micron-scale patterns (e.g., bumps with a period of 2μm to 4μm and a height of 1μm to 2.5μm). These patterns effectively reduce the dislocation density of the epitaxial material grown on the patterned substrate, thereby improving the quality of the epitaxial layer.

[0004] However, after epitaxial growth is complete, the epitaxial layer is peeled off from the patterned substrate, leaving multiple, spaced pits on the surface of the epitaxial layer opposite the patterned substrate. This creates an uneven surface. Consequently, when etching grooves into the epitaxial layer, the pit-containing areas etch faster than areas without them, making overetching more likely. This can lead to short circuits in the film and electrical leakage. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode with improved leakage current and a method for manufacturing the same, which can improve the problem of over-etching of the epitaxial layer and avoid leakage caused by short-circuiting of the film layer after over-etching. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode, the method comprising: forming an epitaxial structure on a patterned substrate; bonding a surface of the epitaxial structure away from the patterned substrate to a conductive substrate, and removing the patterned substrate; etching the surface of the epitaxial structure away from the conductive substrate to form a first groove, the etching gas comprising chlorine and boron trichloride, and the upper power of the etching equipment during at least some stages of the etching process being less than or equal to 500 W, and the lower power being less than or equal to 300 W.

[0007] In one implementation of the present disclosure, etching the surface of the epitaxial structure away from the conductive substrate includes: sequentially performing a rapid etching stage and a slow etching stage on the surface of the epitaxial structure away from the conductive substrate, the etching power of the rapid etching stage is higher than the etching power of the slow etching stage, and the flow rate of the etching gas in the rapid etching stage is higher than the flow rate of the etching gas in the slow etching stage.

[0008] In one implementation of the present disclosure, the upper power of the rapid etching stage is greater than or equal to 700W, and the lower power of the rapid etching stage is greater than or equal to 500W; the upper power of the slow etching stage is less than or equal to 500W, and the lower power of the slow etching stage is less than or equal to 300W.

[0009] In another implementation of the present disclosure, the flow rate of chlorine gas in the rapid etching stage is greater than or equal to 120 sccm, and the flow rate of boron trichloride in the rapid etching stage is greater than or equal to 20 sccm; the flow rate of chlorine gas in the slow etching stage is less than or equal to 80 sccm, and the flow rate of boron trichloride in the slow etching stage is less than or equal to 10 sccm.

[0010] In another implementation of the present disclosure, the ratio of the etching depth in the rapid etching stage to the groove depth of the first groove is 1 / 3 to 2 / 3.

[0011] On the other hand, an embodiment of the present disclosure provides a light-emitting diode, which is prepared using the light-emitting diode preparation method as described above. The light-emitting diode includes: a conductive substrate and an epitaxial structure, and the epitaxial structure is located on the conductive substrate.

[0012] In another implementation of the present disclosure, the epitaxial structure includes: an epitaxial layer, a transparent conductive layer, a passivation layer, a reflector layer and an insulating layer, the transparent conductive layer and the passivation layer are both located on a surface of the epitaxial layer, and the passivation layer covers the transparent conductive layer, the passivation layer has a through hole exposing the transparent conductive layer, the reflector layer is located on the surface of the passivation layer and is connected to the transparent conductive layer through the through hole, the insulating layer is located on the surface of the passivation layer and covers the reflector layer, the insulating layer has a second groove exposing the epitaxial layer, the conductive substrate is located on the surface of the insulating layer away from the epitaxial layer, and is connected to the epitaxial layer through the second groove; the first groove is located on the surface of the epitaxial layer away from the conductive substrate, and the first groove exposes the passivation layer.

[0013] In another implementation of the present disclosure, the thickness of the passivation layer in the first groove is smaller than the thickness of the passivation layer outside the first groove.

[0014] In another implementation of the present disclosure, the thickness of the passivation layer in the first groove is greater than or equal to 2000 angstroms.

[0015] In another implementation of the present disclosure, the bottom of the first groove has a groove or a protrusion.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The method for fabricating a light-emitting diode provided in the embodiments of the present disclosure employs etching gases including chlorine and boron trichloride when etching the surface of an epitaxial structure. Adding boron trichloride to the chlorine slows the etching rate, thereby preventing the epitaxial structure from being etched too quickly and causing over-etching. Furthermore, boron trichloride reduces lateral erosion and inhibits etching of non-target areas, enabling the stable formation of grooves that meet dimensional requirements. Furthermore, the upper power of the etching equipment is controlled to be less than or equal to 500W and the lower power to be less than or equal to 300W during at least some stages of the etching process. This significantly reduces the etching power of the etching equipment, effectively lowering the etching rate and preventing rapid etching of other film layers of the epitaxial structure, which could form leakage paths. This improves the problem of leakage in light-emitting diodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 This is a structural diagram of a light emitting diode provided by the related art;

[0020] Figure 2 This is a flow chart of a method for preparing a light-emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 3 This is a diagram showing the preparation state of a light-emitting diode provided by an embodiment of the present disclosure;

[0022] Figure 4 This is a diagram showing a preparation state of a first groove provided by an embodiment of the present disclosure;

[0023] Figure 5 is a diagram showing another preparation state of a first groove provided by an embodiment of the present disclosure;

[0024] Figure 6 This is a diagram of the preparation state of a light-emitting diode provided in an embodiment of the present disclosure.

[0025] The descriptions of the marks in the figure are as follows:

[0026] 20. epitaxial structure; 21. first groove; 22. second groove;

[0027] 30. Conductive substrate; 31. Bonding metal layer;

[0028] 40. epitaxial layer; 41. first semiconductor layer; 42. multi-quantum well layer; 43. second semiconductor layer;

[0029] 50. Transparent conductive layer;

[0030] 60. Passivation layer;

[0031] 70. reflector layer; 71. metal reflective layer; 72. metal protective layer;

[0032] 80. Insulation layer;

[0033] 90. Electrode. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0035] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] Figure 1 This is a schematic diagram of the structure of a light emitting diode provided by the related technology. Figure 1As shown, since the epitaxial layer 40 of the light emitting diode is formed by epitaxial growth on the patterned substrate, after the patterned substrate is removed, a plurality of spaced pits will be formed on the surface of the epitaxial layer 40 opposite to the patterned substrate, resulting in an uneven surface of the epitaxial layer 40.

[0037] like Figure 1 As shown, when etching grooves on the epitaxial layer 40, the etching speed in the area where the pits are located is faster than the etching speed in the area without pits, which makes the area where the pits are located prone to over-etching and etches out the reflector layer 70 in the epitaxial structure 20, which easily leads to short circuit between the reflector layer and other film layers, resulting in leakage problems.

[0038] To this end, an embodiment of the present disclosure provides a method for preparing a light emitting diode. Figure 2 This is a flow chart of a method for preparing a light-emitting diode provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises:

[0039] Step S11: forming an epitaxial structure 20 on a patterned substrate.

[0040] Step S12: bonding the surface of the epitaxial structure 20 away from the patterned substrate to the conductive substrate 30, and removing the patterned substrate.

[0041] Step S13 : etching the surface of the epitaxial structure 20 away from the conductive substrate 30 to form a first groove 21 .

[0042] The etching gas includes chlorine and boron trichloride, and the upper power of the etching equipment in at least part of the etching process is less than or equal to 500W, and the lower power is less than or equal to 300W.

[0043] The method for fabricating a light-emitting diode provided in the embodiments of the present disclosure employs etching gases including chlorine and boron trichloride when etching the surface of the epitaxial structure 20. Adding boron trichloride to the chlorine slows the etching rate, thereby preventing over-etching of the epitaxial structure 20 due to excessive etching. Furthermore, boron trichloride reduces lateral erosion and inhibits etching of non-target areas, enabling the stable formation of grooves that meet dimensional requirements. Furthermore, the upper power of the etching equipment is controlled to be less than or equal to 500W and the lower power to be less than or equal to 300W during at least some stages of the etching process. This significantly reduces the etching power of the etching equipment, effectively lowering the etching rate and preventing rapid etching of other film layers of the epitaxial structure 20, which could form leakage paths. This improves the problem of leakage in the light-emitting diode.

[0044] Figure 3 FIG. 1 is a diagram showing the preparation state of a light emitting diode provided by an embodiment of the present disclosure. Figure 3As shown, the epitaxial structure 20 includes: an epitaxial layer 40, a transparent conductive layer 50, a passivation layer 60, a reflector layer 70 and an insulating layer 80. The transparent conductive layer 50 and the passivation layer 60 are both located on a surface of the epitaxial layer 40, and the passivation layer 60 covers the transparent conductive layer 50. The passivation layer 60 has a through hole exposing the transparent conductive layer 50. The reflector layer 70 is located on the surface of the passivation layer 60 and is connected to the transparent conductive layer 50 through the through hole. The insulating layer 80 is located on the surface of the passivation layer 60 and covers the reflector layer 70. The insulating layer 80 has a second groove 22 exposing the epitaxial layer 40. The conductive substrate 30 is located on the surface of the insulating layer 80 away from the epitaxial layer 40 and is connected to the epitaxial layer 40 through the second groove 22.

[0045] like Figure 3 As shown, the first groove 21 formed by etching in the embodiment of the present disclosure is located on the surface of the epitaxial layer 40 away from the conductive substrate 30, and the first groove 21 exposes the passivation layer 60. That is, the first groove 21 does not completely etch through the passivation layer 60, nor does it expose the reflector layer 70. Therefore, this preparation method can avoid the rapid etching of other film layers of the epitaxial structure 20 and the formation of leakage channels, thereby improving the problem of easy leakage of light-emitting diodes.

[0046] The preparation of the epitaxial structure 20 in step S11 may include the following steps:

[0047] In the first step, an epitaxial layer 40 is grown on a patterned substrate, including a second semiconductor layer 43 , a multi-quantum well layer 42 and a first semiconductor layer 41 stacked in sequence.

[0048] For example, the patterned substrate can be a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire is a relatively hard material with relatively stable chemical properties, which enables the LED to have good luminous effects and stability.

[0049] The sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0050] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0051] For example, the first semiconductor layer 41 may be a p-type layer, and the second semiconductor layer 43 may be an n-type layer.

[0052] Optionally, the n-type layer is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0053] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 Torr to 300 Torr.

[0054] Optionally, the multi-quantum well layer 42 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 42 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0055] When growing the multi-quantum well layer 42, the MOCVD chamber pressure is controlled at 200 Torr. When growing the InGaN quantum well layer, the chamber temperature is 760° C. to 780° C. When growing the GaN quantum barrier layer, the chamber temperature is 860° C. to 890° C.

[0056] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 42 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0057] Optionally, the thickness of the multi-quantum well layer 42 may be 150 nm to 200 nm.

[0058] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0059] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0060] In the second step, the epitaxial layer 40 is etched to form a second groove 22 on the surface of the first semiconductor layer 41 to expose the second semiconductor layer 43 .

[0061] In the third step, a transparent conductive layer 50 is formed on the surface of the first semiconductor layer 41 .

[0062] The transparent conductive layer 50 is located outside the second groove 22 .

[0063] Exemplarily, the transparent conductive layer 50 is an indium tin oxide layer or an indium zinc oxide layer.

[0064] Exemplarily, the thickness of the transparent conductive layer 50 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 50 is 200 angstroms.

[0065] In the fourth step, a passivation layer 60 is formed on the surface of the epitaxial layer 40 .

[0066] For example, Figure 3 As shown, the passivation layer 60 covers the transparent conductive layer 50 , and the passivation layer 60 has a through hole exposing the transparent conductive layer 50 .

[0067] Exemplarily, the passivation layer 60 includes at least one of a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an aluminum nitride layer.

[0068] For example, the passivation layer 60 may be a silicon oxide layer.

[0069] Optionally, the thickness of the passivation layer 60 is 6000 angstroms to 12000 angstroms. Exemplarily, the thickness of the passivation layer 60 is 10000 angstroms.

[0070] Optionally, the passivation layer 60 may be prepared by chemical vapor deposition (CVD), which allows the passivation layer 60 to be grown quickly.

[0071] Exemplarily, the growth rate of the passivation layer 60 may be 2 angstroms / s to 4 angstroms / s.

[0072] In the fifth step, a reflective mirror layer 70 is formed on the surface of the passivation layer 60 .

[0073] like Figure 3 As shown, the reflector layer 70 includes a metal reflective layer 71 and a metal protective layer 72 .

[0074] When preparing the reflector layer 70, a metal reflective layer 71 is first formed on the surface of the current blocking layer, and the metal reflective layer 71 is connected to the transparent conductive layer 50 through a through hole. Then, a metal protective layer 72 is formed on the surface of the passivation layer 60, so that the metal protective layer 72 covers the metal reflective layer 71.

[0075] In the sixth step, an insulating layer 80 is formed on the passivation layer 60 and in the second groove 22 .

[0076] The specific process of preparing the insulating layer 80 may include: rapidly growing the insulating layer 80 using a CVD process.

[0077] Exemplarily, the insulating layer 80 may be a silicon oxide layer.

[0078] Optionally, the thickness of the insulating layer 80 is 6000 angstroms to 12000 angstroms. Exemplarily, the thickness of the insulating layer 80 is 10000 angstroms.

[0079] In the seventh step, the insulating layer 80 is etched to form a through hole exposing the bottom of the second groove 22 , and a bonding metal layer 31 is formed in the through hole so that the bonding metal layer 31 is electrically connected to the second semiconductor layer 43 .

[0080] Illustratively, the bonding metal layer 31 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0081] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0082] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0083] Step S12 may include: bonding the side of the epitaxial structure 20 having the insulating layer 80 to the conductive substrate 30 , and removing the patterned substrate.

[0084] Specifically, the method may include forming a bonding metal layer 31 on the conductive substrate 30 , bonding the bonding metal layer 31 of the conductive substrate 30 to the bonding metal layer 31 on the epitaxial layer 40 , and removing the patterned substrate by laser lift-off to expose the second semiconductor layer 43 .

[0085] Exemplarily, the conductive substrate 30 may be a silicon substrate.

[0086] Step S13 may include the following two implementations:

[0087] In a first implementation, during all stages of the etching process, the upper power of the etching equipment is less than or equal to 500W, and the lower power is less than or equal to 300W.

[0088] Figure 4 FIG. 2 is a diagram showing a preparation state of a first groove 21 provided by the present disclosure. Figure 4 As shown, during all stages of the etching process, the upper power of the etching equipment is controlled to be less than or equal to 500 W, and the lower power is controlled to be less than or equal to 300 W. This can minimize the etching rate, thereby preventing rapid etching from penetrating the passivation layer 60 of the epitaxial structure 20 and forming a leakage path, thereby improving the problem of easy leakage of the light-emitting diode.

[0089] like Figure 4 As shown, the entire etching process adopts a slow etching method with low etching power, which can retain a thicker passivation layer 60. The thickness of the passivation layer 60 in the first groove 21 is smaller than the thickness of the passivation layer 60 outside the first groove 21.

[0090] For example, Figure 4As shown, the thickness of the passivation layer 60 in the first groove 21 is 2000 angstroms, and the thickness of the passivation layer 60 below the epitaxial layer 40 is 6000 angstroms.

[0091] For example, Figure 4 As shown, the angle between the groove wall and the groove bottom of the first groove 21 is 44°±5°.

[0092] In this way, the groove wall of the first groove 21 is tilted, and the angle between the groove wall and the groove bottom is controlled within the above range. In other words, the side wall of the epitaxial layer 40 is tilted, which can break the critical angle limit of total internal reflection and allow more photons to escape from the light-emitting diode device through scattering or reflection from the side wall.

[0093] For example, Figure 4 As shown, the bottom of the first groove 21 has a groove and a protrusion, while the surface of the passivation layer 60 outside the first groove 21 is flat. That is, the surface flatness of the passivation layer 60 outside the first groove 21 is higher than the surface flatness of the passivation layer 60 inside the first groove 21.

[0094] Since the first groove 21 is used to form the electrode 90 , making the surface of the passivation layer 60 in the first groove 21 rougher is beneficial to improving the connection reliability between the electrode 90 and the groove bottom of the first groove 21 and preventing the electrode 90 from being easily loosened.

[0095] In the second implementation, in some stages of the etching process, the upper power of the etching equipment is controlled to be less than or equal to 500W, and the lower power is controlled to be less than or equal to 300W.

[0096] Optionally, the specific process of etching the epitaxial structure 20 may include: sequentially performing a fast etching phase and a slow etching phase on the surface of the epitaxial structure 20 away from the conductive substrate 30 .

[0097] The etching power in the fast etching stage is higher than that in the slow etching stage, and the flow rate of the etching gas in the fast etching stage is higher than that in the slow etching stage.

[0098] Optionally, the upper power in the rapid etching stage is greater than or equal to 700W, and the lower power in the rapid etching stage is greater than or equal to 500W.

[0099] Illustratively, in the rapid etching stage, the upper power is 700W and the lower power is 500W.

[0100] Optionally, the upper power in the slow etching stage is less than or equal to 500W, and the lower power in the slow etching stage is less than or equal to 300W.

[0101] Illustratively, in the slow etching stage, the upper power is 500W and the lower power is 300W.

[0102] In the embodiment of the present disclosure, in the rapid etching stage, the upper power and the lower power of the etching equipment are relatively high, so that most of the epitaxial materials can be quickly etched away, thereby saving etching time and improving production capacity; in the slow etching stage, the upper power and the lower power of the etching equipment are greatly reduced, thereby achieving the purpose of greatly reducing the etching rate, thereby avoiding rapid etching of other film layers of the epitaxial structure 20 to form a leakage channel, and improving the problem of easy leakage of the light-emitting diode.

[0103] Optionally, the flow rate of chlorine gas in the rapid etching stage is greater than or equal to 120 sccm, and the flow rate of boron trichloride in the rapid etching stage is greater than or equal to 20 sccm.

[0104] Illustratively, the flow rate of chlorine gas in the rapid etching stage is 120 sccm, and the flow rate of boron trichloride in the rapid etching stage is 20 sccm.

[0105] Optionally, the flow rate of chlorine gas in the slow etching stage is less than or equal to 80 sccm, and the flow rate of boron trichloride in the slow etching stage is less than or equal to 10 sccm.

[0106] Illustratively, the flow rate of chlorine gas in the slow etching stage is 80 sccm, and the flow rate of boron trichloride in the slow etching stage is 10 sccm.

[0107] In the disclosed embodiment, during the rapid etching phase, a chlorine gas flow rate exceeding 120 sccm increases the density of Cl radicals in the plasma, accelerating chemical reactions with the epitaxial material and generating volatile products, thereby increasing the etching rate. A boron trichloride flow rate exceeding 20 sccm allows the boron trichloride to decompose more B and Cl radicals within the reaction chamber, preferentially reacting with oxides within the reaction chamber or on the surface of the material, rapidly removing the passivation layer 60 and ensuring that the chlorine gas directly contacts and etches the target material.

[0108] During the slow etching stage, the flow rates of chlorine and boron trifluoride are greatly reduced, thereby significantly reducing the etching rate of the epitaxial material, preventing rapid etching from penetrating the passivation layer 60 and forming a leakage path, thereby improving the problem of easy leakage of the light-emitting diode.

[0109] Figure 5 FIG. 2 is another preparation state diagram of the first groove 21 provided by the present disclosure. Figure 5 As shown, the etching process includes a fast etching stage and a slow etching stage. The angle between the groove wall and the groove bottom formed in the fast etching stage is 73°±5°, and the angle between the groove wall and the groove bottom formed in the slow etching stage is 43°±5°.

[0110] This allows the inclination angle of the groove wall of the first groove 21 to change, so that when the electrode is subsequently prepared in the first groove 21, the electrode can be deposited more smoothly on the groove wall of the first groove 21, and the contact area between the electrode and the groove wall of the first groove 21 is increased, thereby improving the connection reliability between the electrode and the first groove 21.

[0111] like Figure 4 、 5 As shown, since the etching speed in the partial etching stage in the second implementation is faster, the depth of the formed first groove 21 is greater than the depth of the first groove 21 in the first implementation. That is, the thickness of the passivation layer 60 in the first groove 21 in the second implementation is less than the thickness and depth of the passivation layer 60 in the first groove 21 in the first implementation.

[0112] For example, Figure 5 As shown, the thickness of the passivation layer 60 in the first groove 21 is 1500 angstroms, while the thickness of the passivation layer 60 below the epitaxial layer 40 is 6000 angstroms.

[0113] For example, Figure 5 As shown, the bottom of the first groove 21 has a groove and a protrusion, while the surface of the passivation layer 60 outside the first groove 21 is flat. That is, the surface flatness of the passivation layer 60 outside the first groove 21 is higher than the surface flatness of the passivation layer 60 inside the first groove 21.

[0114] Since the first groove 21 is a groove for forming an electrode, making the surface of the passivation layer 60 in the first groove 21 rougher is beneficial to improving the connection reliability between the electrode and the groove bottom of the first groove 21 and preventing the electrode from being easily loosened.

[0115] Optionally, the ratio of the etching depth in the rapid etching stage to the groove depth of the first groove 21 is 1 / 3 to 2 / 3, that is, the rapid etching stage first rapidly etches 1 / 3 to 2 / 3 of the first groove 21, and the remaining epitaxial material is etched in the slow etching stage. In this way, most of the epitaxial material can be etched away quickly, saving etching time and improving production capacity.

[0116] like Figure 6 As shown, after step S13, the preparation method may further include: wet etching the passivation layer 60 in the first groove 21 so that the passivation layer 60 exposes the via hole of the reflector layer 70; then, forming an electrode 90 in the first groove 21, and connecting the electrode 90 to the reflector layer 70 through the via hole, thereby achieving the purpose of connecting the electrode 90 to the first semiconductor layer 41.

[0117] An embodiment of the present disclosure provides a light emitting diode, which is manufactured using the light emitting diode manufacturing method as described above.

[0118] like Figure 3 As shown, the light emitting diode includes a conductive substrate 30 and an epitaxial structure 20 , wherein the epitaxial structure 20 is located on the conductive substrate 30 .

[0119] Alternatively, as Figure 3 As shown, the epitaxial structure 20 includes: an epitaxial layer 40, a transparent conductive layer 50, a passivation layer 60, a reflector layer 70 and an insulating layer 80. The transparent conductive layer 50 and the passivation layer 60 are both located on a surface of the epitaxial layer 40, and the passivation layer 60 covers the transparent conductive layer 50. The passivation layer 60 has a through hole exposing the transparent conductive layer 50. The reflector layer 70 is located on the surface of the passivation layer 60 and is connected to the transparent conductive layer 50 through the through hole. The insulating layer 80 is located on the surface of the passivation layer 60 and covers the reflector layer 70. The insulating layer 80 has a second groove 22 exposing the epitaxial layer 40. The conductive substrate 30 is located on the surface of the insulating layer 80 away from the epitaxial layer 40 and is connected to the epitaxial layer 40 through the second groove 22.

[0120] like Figure 3 As shown, the first groove 21 is located on the surface of the epitaxial layer 40 away from the conductive substrate 30, and the first groove 21 exposes the passivation layer 60. That is, the first groove 21 does not completely penetrate the passivation layer 60 and does not expose the reflector layer 70. Therefore, the light-emitting diode can avoid other film layers connecting with the reflector layer 70 and forming a leakage path, thereby improving the problem of the light-emitting diode being prone to leakage.

[0121] Alternatively, as Figure 4 As shown, the thickness of the passivation layer 60 in the first groove 21 is less than the thickness of the passivation layer 60 outside the first groove 21. That is, part of the passivation layer 60 is also etched. Using the passivation layer 60 as an etching buffer layer can effectively avoid over-etching the reflector layer 70.

[0122] Optionally, the thickness of the passivation layer 60 in the first groove 21 is greater than or equal to 2000 angstroms.

[0123] For example, Figure 4 As shown, the thickness of the passivation layer 60 in the first groove 21 is 2000 angstroms, and the thickness of the passivation layer 60 below the epitaxial layer 40 is 6000 angstroms.

[0124] For example, Figure 4 As shown, the angle between the groove wall and the groove bottom of the first groove 21 is 44°±5°.

[0125] In this way, the groove wall of the first groove 21 is tilted, and the angle between the groove wall and the groove bottom is controlled within the above range. In other words, the side wall of the epitaxial layer 40 is tilted, which can break the critical angle limit of total internal reflection and allow more photons to escape from the light-emitting diode device through scattering or reflection from the side wall.

[0126] For example, Figure 4As shown, the bottom of the first groove 21 has a groove and a protrusion, while the surface of the passivation layer 60 outside the first groove 21 is flat. That is, the surface flatness of the passivation layer 60 outside the first groove 21 is higher than the surface flatness of the passivation layer 60 inside the first groove 21.

[0127] Since the first groove 21 is a groove for forming an electrode, making the surface of the passivation layer 60 in the first groove 21 rougher is beneficial to improving the connection reliability between the electrode and the groove bottom of the first groove 21 and preventing the electrode from being easily loosened.

[0128] Optionally, the epitaxial layer 40 includes a first semiconductor layer 41 , a multi-quantum well layer 42 , and a second semiconductor layer 43 stacked in sequence.

[0129] Optionally, one of the first semiconductor layer 41 and the second semiconductor layer 43 is an n-type layer, and the other of the first semiconductor layer 41 and the second semiconductor layer 43 is a p-type layer.

[0130] Exemplarily, the first semiconductor layer 41 is a p-type layer, and the second semiconductor layer 43 is an n-type layer.

[0131] Optionally, the n-type layer is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0132] Optionally, the multi-quantum well layer 42 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 42 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0133] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 42 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0134] Optionally, the thickness of the multi-quantum well layer 42 may be 150 nm to 200 nm.

[0135] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0136] Optionally, the transparent conductive layer 50 may be an indium tin oxide (ITO) layer, which has good transmittance and low resistivity.

[0137] Alternatively, the transparent conductive layer 50 may be an indium zinc oxide (IZO) layer. The IZO layer has good transmittance and low resistivity.

[0138] Among them, using an ITO layer or an IZO layer as the transparent conductive layer 50 can allow more light to be transmitted from the transparent conductive layer 50, thereby ensuring the light extraction effect; at the same time, due to the low resistivity, the metal reflective layer 71 is stacked on the transparent conductive layer 50, so that carriers can be more efficiently conducted from the metal reflective layer 71 to the epitaxial layer 40, thereby improving the injection efficiency.

[0139] For example, the thickness of the transparent conductive layer 50 may be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 50 is 1500 angstroms.

[0140] In the embodiment of the present disclosure, the reflector layer 70 is provided to reflect the light emitted from the epitaxial layer 40 , allowing more light to be emitted from the light-emitting surface of the epitaxial layer 40 , thereby improving the luminous intensity of the light-emitting diode.

[0141] At the same time, the metal reflective layer 71 is covered with a metal protective layer 72 to prevent the metal in the metal reflective layer 71 from migrating upward.

[0142] Optionally, the metal reflective layer 71 includes Ag layers stacked sequentially.

[0143] Since Ag has a good reflective effect, providing an Ag layer in the metal reflective layer 71 can enhance the reflection of light by the metal reflective layer 71 and improve the brightness of light emitted from the light emitting surface of the light emitting diode.

[0144] Optionally, the metal protection layer 72 includes a Ni layer or a TiW layer.

[0145] The Ni layer has good corrosion and wear resistance, while the TiW layer acts as an adhesion layer that can be successfully deposited on other thin films without peeling or cracking. The alternating stack of Ni and TiW layers acts as a barrier layer to protect the silver mirror.

[0146] Illustratively, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0147] Illustratively, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0148] Illustratively, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0149] Alternatively, as Figure 3 As shown, the light emitting diode further includes a bonding metal layer 31 , the second groove 22 is located on the surface of the insulating layer 80 and exposes the second semiconductor layer 43 , the bonding metal layer 31 is located on the side where the first semiconductor layer 41 is located and is connected to the second semiconductor layer 43 through the second groove 22 .

[0150] Illustratively, the bonding metal layer 31 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0151] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0152] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0153] Alternatively, the conductive substrate 30 may be a silicon substrate.

[0154] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: forming an epitaxial structure (20) on a patterned substrate; Bonding the surface of the epitaxial structure (20) away from the patterned substrate to a conductive substrate (30), and removing the patterned substrate; The surface of the epitaxial structure (20) away from the conductive substrate (30) is etched to form a first groove (21), the etching gas includes chlorine and boron trichloride, and the upper power of the etching equipment in at least part of the etching process is less than or equal to 500W, and the lower power is less than or equal to 300W.

2. The preparation method according to claim 1, characterized in that Etching a surface of the epitaxial structure (20) away from the conductive substrate (30) comprises: A rapid etching phase and a slow etching phase are sequentially performed on the surface of the epitaxial structure (20) away from the conductive substrate (30), wherein the etching power in the rapid etching phase is higher than the etching power in the slow etching phase, and the flow rate of the etching gas in the rapid etching phase is higher than the flow rate of the etching gas in the slow etching phase.

3. The preparation method according to claim 2, characterized in that The upper power of the rapid etching stage is greater than or equal to 700W, and the lower power of the rapid etching stage is greater than or equal to 500W; The upper power in the slow etching stage is less than or equal to 500W, and the lower power in the slow etching stage is less than or equal to 300W.

4. The preparation method according to claim 2, characterized in that The flow rate of chlorine gas in the rapid etching stage is greater than or equal to 120 sccm, and the flow rate of boron trichloride in the rapid etching stage is greater than or equal to 20 sccm; The flow rate of chlorine gas in the slow etching stage is less than or equal to 80 sccm, and the flow rate of boron trichloride in the slow etching stage is less than or equal to 10 sccm.

5. The preparation method according to claim 2, characterized in that The ratio of the etching depth in the rapid etching stage to the groove depth of the first groove (21) is 1 / 3 to 2 / 3.

6. A light emitting diode, characterized in that: The light-emitting diode is prepared by the method for preparing a light-emitting diode according to any one of claims 1 to 5, and comprises: a conductive substrate (30) and an epitaxial structure (20), wherein the epitaxial structure (20) is located on the conductive substrate (30).

7. The light emitting diode according to claim 6, characterized in that The epitaxial structure (20) comprises: an epitaxial layer (40), a transparent conductive layer (50), a passivation layer (60), a reflector layer (70) and an insulating layer (80), wherein the transparent conductive layer (50) and the passivation layer (60) are both located on a surface of the epitaxial layer (40), and the passivation layer (60) covers the transparent conductive layer (50), the passivation layer (60) has a through hole exposing the transparent conductive layer (50), and the reflector layer (70) is located on the passivation layer. The conductive substrate (30) is located on the surface of the passivation layer (60) and is connected to the transparent conductive layer (50) through the through hole, the insulating layer (80) is located on the surface of the passivation layer (60) and covers the reflector layer (70), the insulating layer (80) has a second groove (22) exposing the epitaxial layer (40), and the conductive substrate (30) is located on the surface of the insulating layer (80) away from the epitaxial layer (40) and is connected to the epitaxial layer (40) through the second groove (22); The first groove (21) is located on a surface of the epitaxial layer (40) away from the conductive substrate (30), and the first groove (21) exposes the passivation layer (60).

8. The light emitting diode according to claim 7, characterized in that The thickness of the passivation layer (60) within the first groove (21) is smaller than the thickness of the passivation layer (60) outside the first groove (21).

9. The light emitting diode according to claim 8, characterized in that The thickness of the passivation layer (60) in the first groove (21) is greater than or equal to 2000 angstroms.

10. The light emitting diode according to any one of claims 6 to 9, characterized in that: The bottom of the first groove (21) has a groove or a protrusion.

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