Wafer structure, packaging module and thermal test chip

Abstract

The invention discloses a wafer structure, a packaging module and a thermal testing chip, and relates to the technical field of chip thermal testing, and the wafer structure comprises a plurality of wafers arranged at intervals and cutting channels connecting two adjacent wafers. Each wafer comprises a surface wiring layer, a temperature measuring unit and a heating unit, the temperature measuring unit and the heating unit are stacked below the surface wiring layer, the surface wiring layer is provided with a temperature measuring pin and a heating pin which are independent from each other, and the temperature measuring unit is electrically connected with the temperature measuring pin through a temperature measuring metal via hole. The heating unit is electrically connected with the heating pins through the heating metal via holes; the heating pins in the plurality of wafers are arranged independently from each other, and the temperature measuring pins in the plurality of wafers are arranged independently from each other. According to the technical scheme, the universality of the hot test chip is improved, and the development cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of thermal testing of chips, and in particular to a wafer structure, a packaging module, and a thermal testing chip. Background Art

[0002] With the rapid advancement of semiconductor technology, chip integration continues to increase, leading to increased power consumption. To ensure chip reliability and stability in high-temperature operating environments, thermal testing has become an integral part of the chip design process. Thermal test chips are widely used to simulate the operating conditions of real chips, facilitating research and optimizing thermal design. However, these chips are typically designed specifically for electronic chips of specific sizes and types. For real chips of different sizes or with different thermal characteristics, the corresponding thermal test chips must be independently developed, fabricated, and packaged, resulting in high costs. Summary of the Invention

[0003] The main purpose of this application is to provide a wafer structure, a packaging module and a thermal test chip, aiming to improve the versatility of the thermal test chip and reduce development costs.

[0004] To achieve the above-mentioned purpose, an embodiment of the present application proposes a wafer structure, which includes a plurality of wafers arranged at intervals and a cutting path connecting two adjacent wafers, each of the wafers including a surface wiring layer and a temperature measuring unit and a heating unit stacked below the surface wiring layer, the surface wiring layer being provided with temperature measuring pins and heating pins independent of each other, the temperature measuring unit being electrically connected to the temperature measuring pins through temperature measuring metal vias, and the heating unit being electrically connected to the heating pins through heating metal vias; the heating pins in the plurality of wafers are arranged independently of each other, and the temperature measuring pins in the plurality of wafers are arranged independently of each other.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application proposes a packaging module, which includes a packaging substrate and a grain unit arranged on the packaging substrate. The grain unit is cut from the wafer structure described above, and a plurality of independent welding units are spaced apart on the surface of the packaging substrate. The arrangement of the plurality of welding units is the same as that of the plurality of chips and corresponds one to one.

[0006] To achieve the above objectives, an embodiment of the present application provides a thermal testing chip, which includes the packaging module described above.

[0007] The technical solution of the present application, by arranging multiple independent chips on the wafer structure and utilizing cutting paths, can cut the entire wafer structure into grain units composed of multiple chips arranged in an arbitrary array, thereby supporting the packaging and processing of thermal test chips of various sizes and reducing the development cost of thermal test chips. Moreover, the heating unit of each chip can be independently controlled to achieve independent adjustment of the heat output of each heating unit. Compared with the method of merging and controlling the heating units, the technical solution of the present application can simulate the heat generation of a real chip and achieve an uneven heating effect, thereby improving the test effect of the thermal test chip. In addition, the heating unit and the temperature measuring unit are stacked, and there is no need to hollow out the heating unit, which effectively improves the heating area coverage of the heating unit and better simulates the heating conditions of a real chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0009] Figure 1 This is a schematic structural diagram of an embodiment of the wafer structure of the present application;

[0010] Figure 2 Schematic diagram of the cross-sectional structure of a single wafer in the wafer structure embodiment of the present application;

[0011] Figure 3 This is a schematic diagram of a top view of a single wafer in the wafer structure embodiment of the present application;

[0012] Figure 4 This is a schematic structural diagram of an embodiment of the packaging module of the present application;

[0013] Figure 5 This is a partial structural diagram of an embodiment of the packaging module of the present application, wherein the die unit is hidden;

[0014] Figure 6 This is a side view schematic diagram of an embodiment of the packaging module of the present application;

[0015] Figure 7 A schematic diagram of a packaging state of an embodiment of the packaging module of the present application;

[0016] Figure 8 A cross-sectional view of an embodiment of a packaging module of the present application;

[0017] Figure 9 This is a cross-sectional view of another embodiment of the packaging module of the present application.

[0018] Description of Figure Numbers:

[0019] 100. Wafer structure; 110. Chip; 111. Surface wiring layer; 112. Temperature measurement unit; 113. Heating unit; 114. Temperature measurement pin; 115. Heating pin; 116. Temperature measurement metal via; 117. Heating metal via; 118. Insulation layer; 1191. Heating connection trace; 1192. Temperature measurement connection trace; 120. Substrate; 130. Cutting road; 200. Packaging module; 210. Packaging substrate; 211. Welding unit; 212. Solder ball; 220. Die unit; 230. Transfer board; 240. Heat dissipation cover; 250. Thermal interface material layer; 260. Bottom filling material layer.

[0020] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0022] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0023] In addition, in the embodiments of the present application, descriptions such as "first" and "second" are only for descriptive purposes and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0024] In the embodiments of the present application, unless otherwise specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean a fixed connection, a detachable connection, or an integral connection; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal connection between two elements or the interaction between two elements, unless otherwise specified. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0025] In addition, the technical solutions between the various embodiments of the present application can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the embodiments of the present application.

[0026] To dissipate heat for high-performance, high-power chips, a better cooling solution is needed. Metal heating blocks, thin-film heaters, and thermal test chips are typically used to replace actual chips to calibrate and verify the feasibility of the cooling solution. For actual chips of varying sizes or with varying thermal characteristics, corresponding thermal test chips must be independently developed, fabricated, and packaged, resulting in high development costs.

[0027] Moreover, traditional metal heating blocks or thin-film heating sheets can only produce uniform power consumption, while the internal heating of real chips is uneven. Therefore, metal heating blocks and thin-film heating sheets cannot effectively represent the junction temperature performance of real chips when used to verify heat dissipation modules or heat dissipation solutions. This is especially true when the internal hot spots of large-size packaged chips are more prominent, which can easily lead to large deviations.

[0028] In addition, in existing thermal test chips, the coverage area of ​​the heating unit is relatively low, resulting in uneven heating.

[0029] In view of this, the embodiments of the present application provide a wafer structure, a packaging module, and a thermal test chip. By arranging multiple independent chips on the wafer structure and utilizing cutting paths, the entire wafer structure can be cut into grain units formed by arbitrarily arrayed multiple chips, thereby supporting the packaging and processing of thermal test chips of various sizes and reducing the development cost of thermal test chips. Moreover, the heating unit of each chip can be independently controlled to achieve independent adjustment of the heat output of each heating unit. Compared with the method of merging and controlling the heating units, the technical solution of the present application can simulate the heat generation of a real chip and achieve an uneven heating effect, thereby improving the test effect of the thermal test chip. In addition, the heating unit and the temperature measuring unit are stacked, and there is no need to hollow out the heating unit, which effectively improves the heating area coverage of the heating unit and better simulates the heating conditions of a real chip.

[0030] In order to better understand the above technical solution, the above technical solution is described in detail below with reference to the accompanying drawings.

[0031] like Figures 1 to 3 As shown, an embodiment of the present application proposes a wafer structure, wherein the wafer structure 100 includes a plurality of chips 110 arranged at intervals and a cutting path 130 connecting two adjacent chips 110, each chip 110 includes a surface wiring layer 111 and a temperature measuring unit 112 and a heating unit 113 stacked below the surface wiring layer 111, the surface wiring layer 111 is provided with temperature measuring pins 114 and heating pins 115 independent of each other, the temperature measuring unit 112 is electrically connected to the temperature measuring pin 114 through a temperature measuring metal via 116, and the heating unit 113 is electrically connected to the heating pin 115 through a heating metal via 117; the heating pins 115 in the plurality of chips 110 are independently arranged from each other, and the temperature measuring pins 114 in the plurality of chips 110 are independently arranged from each other.

[0032] Specifically, the wafer structure 100 includes a plurality of wafers 110, with the wafers 110 being spaced apart. The wafers 110 may be arranged in an array, such as 2 rows of 2 columns, 8 rows of 8 columns, or 10 rows of 10 columns. Of course, the wafers 110 may also be arranged irregularly. In this embodiment, the specific arrangement rules of the wafers 110 are not limited.

[0033] Multiple chips 110 are connected together by cutting lanes 130, that is, two adjacent chips 110 are connected by cutting lanes 130, and no devices or traces are set in the cutting lanes 130 area. By cutting the wafer structure 100 on the cutting lanes 130, the wafer structure 100 can be cut into the required size or shape, thereby meeting the requirements of real chips of different specifications or forms during thermal testing. That is, the wafer structure 100 formed by multiple spaced-apart chips 110 can support the packaging and processing of thermal test chips of various sizes, thereby reducing the development cost of thermal test chips. It can be understood that in this embodiment, the wafer structure 100 is designed as multiple modular chips 110, and the same chip 110 structure can be cut into heat source modules of various sizes. After the heat source modules and substrates are packaged, thermal test chips can be formed. That is, the design of the same set of wafer structures 100 can meet the processing and manufacturing of thermal test chips of various heat source module sizes, thereby effectively reducing development costs. Optionally, the cutting lanes 130 can be cutting grooves or cutting marks set between two adjacent chips 110, which are not limited here. In this embodiment, a plurality of independent chips 110 form the entire wafer structure 100 , and the plurality of chips 110 are cut from the wafer structure 100 according to required sizes to form die units 220 .

[0034] Each chip 110 includes a surface wiring layer 111, and a temperature measuring unit 112 and a heating unit 113 are provided below the surface wiring layer 111. It is understood that the heating unit 113 can generate heat, thereby simulating the heating condition of a real chip; the temperature can be measured by using the set temperature measuring unit 112, which is equivalent to the temperature of each position of the real chip. In this embodiment, the heating unit 113 and the temperature measuring unit 112 are stacked and arranged below the surface wiring layer 111. It is understood that the heating unit 113 and the temperature measuring unit 112 are arranged on different metal layers and can be electrically isolated by the insulating layer 118. There is no need to hollow out the heating unit 113 to arrange the temperature measuring unit 112, so that the heating unit 113 can cover the entire structure, thereby improving the heating area coverage of the heating unit 113, thereby improving the uniformity of the heat generation, and better simulating the heating condition of the real chip when working. Optionally, the temperature measuring unit 112 can be arranged in the middle, edge or corner of the entire structure, which is not limited here. Specifically, the heating unit 113 is arranged on the side of the temperature measuring unit 112 facing the surface wiring layer 111, or the temperature measuring unit 112 is arranged on the side of the heating unit 113 facing the surface wiring layer 111. In actual application, it can be selected according to the specific situation and is not limited here.

[0035] The surface wiring layer 111 is further provided with a temperature measurement pin 114 and a heating pin 115. The temperature measurement pin 114 is electrically connected to the temperature measurement unit 112 via a temperature measurement metal via 116, and the heating pin 115 is electrically connected to the heating unit 113 via a heating metal via 117, thereby providing power to the heating unit 113 and outputting a signal from the temperature measurement unit 112. In this embodiment, the heating pins 115 in the multiple chips 110 are independently provided, and the temperature measurement pins 114 in the multiple chips 110 are also independently provided. That is, the heating pin 115 in one chip 110 is independent of the heating pins 115 in other chips 110, and the temperature measurement pin 114 in one chip 110 is independent of the temperature measurement pins 114 in other chips 110. In this way, in actual use, the heating amount of each heating unit 113 can be independently controlled, and the temperature of each temperature measurement unit 112 can be collected. By utilizing the independent control feature of each chip 110, the power consumption of any chip 110 can be controlled by adjusting the output of the power supply, so as to simulate the non-uniform heating effect inside the real chip, and obtain the internal junction temperature of the chip 110 through the temperature measuring unit 112 during the test. In addition, each chip 110 inside the heat source module (i.e., the grain unit 220 mentioned below) formed after the wafer structure 100 is cut has an independent temperature measurement function, which can provide a large number of temperature measurement points for the heat source module, and can provide more intensive temperature monitoring inside the heat source module, providing more effective temperature data for thermal test research, thereby improving the accuracy of the thermal test effect. Optionally, the heating pin 115 and the temperature measuring pin 114 can be a Cu column plus a SnAg alloy cap, or a SnAg solder ball.

[0036] The wafer structure 100 proposed in this embodiment can be applied to both 2D flip chips and 2.5D flip chips. For 2.5D flip chips, a signal transfer medium, namely a transfer plate, needs to be added between the substrate and the heat source, which will not be described in detail.

[0037] In the technical solution adopted in this embodiment, by arranging multiple independent chips 110 on the wafer structure 100, the entire wafer structure 100 can be cut into chip 110 units arranged in any array using the cutting path 130, thereby supporting the processing of thermal test chips of various sizes and reducing the development cost of thermal test chips. Moreover, the heating unit 113 of each chip 110 can be independently controlled to achieve independent adjustment of the heat amount of each heating unit 113. Compared with the method of merging and controlling the heating units 113, the technical solution of the present application can simulate the heat generation of a real chip, achieve an uneven heating effect, and thus improve the test effect of the thermal test chip. In addition, the heating unit 113 and the temperature measuring unit 112 are stacked, and there is no need to hollow out the heating unit 113, which effectively improves the heating area coverage of the heating unit 113 and better simulates the heating conditions of a real chip.

[0038] In an embodiment of the present application, the temperature measuring unit 112 is a temperature measuring metal trace, and the heating unit 113 is a heating metal trace. The temperature measuring metal trace and the heating metal trace are spaced apart. Designing the heating unit 113 and the temperature measuring unit 112 by metal traces can save processing costs for the chip 110 structure. The heating metal trace and the temperature measuring metal trace can be made of any one of platinum, copper, nickel, titanium, and aluminum. The heating metal trace is connected to the heating pin 115 through the heating metal via 117, and the temperature measuring metal trace is electrically connected to the temperature measuring pin 114 through the temperature measuring metal via 116.

[0039] In one embodiment, the heating metal traces are evenly arranged inside the chip 110. Optionally, two heating metal traces are provided, and the two heating metal traces are arranged in parallel, and the ends of the two heating metal traces are electrically connected to the metal vias. Of course, one or more heating metal traces can also be provided, or they can be arranged in a circuitous manner to cover the entire chip 110, which helps to distribute heat more evenly on the traces, reduce local hot spots, and increase the coverage of the heating area. Moreover, the size of the envelope surface of the heating metal trace is adapted to the size of the surface wiring layer 111, so that the entire chip 110 can be covered, heating is more uniform, and the heating effect is better.

[0040] In another embodiment, the temperature measuring metal traces can be arranged in the central area of ​​the chip 110, or can be arranged at the corners, the center of the edge, etc. of the entire chip 110, and can be evenly distributed in the temperature measuring area. It can be understood that the projection of the temperature measuring metal traces is located at the center or the center of the corners or the edge of the surface wiring layer 111, and the arrangement is more flexible and convenient. Optionally, the line width of the temperature measuring metal traces can be smaller to increase the resistance of the temperature measuring metal traces. Specifically, the resistance values ​​of all the temperature measuring metal traces are collected by a data acquisition device, and the relationship curve between the resistance value and temperature of the temperature measuring metal traces is used to convert the junction temperature.

[0041] In the examples of this application, refer to Figure 2 The wafer structure 100 also includes a multi-layer insulating layer 118 stacked below the surface wiring layer 111, wherein one insulating layer 118 is provided with a temperature measuring metal trace, wherein another insulating layer 118 is provided with a heating metal trace, and at least one insulating layer 118 is provided between the temperature measuring metal trace and the heating metal trace. It can be understood that by providing the insulating layer 118 between the temperature measuring metal trace and the heating metal trace, the temperature measuring metal trace and the heating metal trace can be electrically isolated to avoid interference with each other. Optionally, the insulating layer 118 can be provided with one layer, or two or more layers, which is not limited here. Specifically, the insulating layer 118 can be made of insulating materials such as SiO2, SiN, SiCN, SiCOH, etc.

[0042] In the examples of this application, refer to Figure 2 and Figure 3 The surface wiring layer 111 is provided with independent heating connection traces 1191 and temperature measurement connection traces 1192. The heating pin 115, the heating connection trace 1191, the heating metal via 117, and the heating metal trace are electrically connected and conducted in sequence. The temperature measurement pin 114, the temperature measurement connection trace 1192, the temperature measurement metal via 116, and the temperature measurement metal trace are electrically connected and conducted in sequence. In this embodiment, the heating pin 115, the heating connection trace 1191, the heating metal via 117, and the heating metal trace are electrically connected and conducted in sequence to form a complete heating circuit for transmitting current to the heating metal trace, thereby realizing the heating function. At the same time, the temperature measurement pin 114, the temperature measurement connection trace 1192, the temperature measurement metal via 116, and the temperature measurement metal trace are electrically connected and conducted in sequence to form a complete temperature measurement circuit for outputting the resistance signal on the temperature measurement metal trace, thereby realizing the temperature measurement function.

[0043] In the embodiment of the present application, four heating pins 115 and four temperature measurement pins 114 are provided on the same chip 110. It is understood that the two ends of the heating metal trace are connected to two heating pins 115, and the two ends of the temperature measurement metal trace are connected to two temperature measurement pins 114. The four interconnected heating pins 115 and temperature measurement pins 114 support the Kelvin resistance measurement method, achieving accurate resistance measurement and heating power consumption monitoring.

[0044] In the embodiment of the present application, the temperature-measuring metal traces on each chip 110 are arranged in a circuitous manner. The resistance of the temperature-measuring metal traces changes with temperature, and by measuring the resistance change, the temperature change can be calculated. Therefore, it is very important to increase the sensitivity of the temperature-measuring metal traces to temperature changes. To this end, in this embodiment, the temperature-measuring metal traces on each chip 110 are arranged in a circuitous manner, which can increase the total length of the temperature-measuring metal traces within a limited space. The longer wires can increase the sensitivity to temperature changes, thereby improving the accuracy of the thermal test results.

[0045] In the examples of this application, refer to Figure 2, the chip 110 also includes a substrate 120, and the chips 110 are arranged in rows in a first direction and arranged in columns on the substrate 120 along an orthogonal second direction. The substrate 120 is provided to provide physical support for the circuit on the chip 110. Optionally, the substrate 120 is a silicon wafer and does not contain other electrical components. Of course, in other embodiments, the substrate 120 may also contain active or passive components, which is not limited here. The chips 110 are arranged into several rows along the first direction, and at the same time, the chips 110 are arranged into several columns along a second direction perpendicular to the first direction. In this way, a plurality of chips 110 are arranged on the substrate 120 and neatly arranged in the form of a grid to form a dense array, which can then be cut according to the required size of the heat source module. In one embodiment, the material of the substrate 120 can be Si, SiC, diamond and the like.

[0046] The present application also provides a packaging module 200, referring to Figures 4 to 9The packaging module 200 includes a packaging substrate 210 and a grain unit 220 provided on the packaging substrate 210, and the grain unit 220 is formed by cutting the above wafer structure 100. In other words, the heat source module formed after the wafer structure 100 is cut constitutes the grain unit 220. A plurality of independent welding units 211 are provided on the surface of the packaging substrate 210 at intervals, and the arrangement of the plurality of welding units 211 is the same as that of the plurality of chips 110 and corresponds one to one. Specifically, the specific structure of the wafer structure 100 refers to the above embodiment. Since the packaging module 200 adopts all the technical solutions of the above embodiment, it has at least all the beneficial effects brought about by the technical solutions of the above embodiment, which will not be described one by one here. It can be understood that the packaging substrate 210 in this embodiment is also modularly configured, that is, a plurality of independent welding units 211 are arrayed on the packaging substrate 210, and the arrangement of the plurality of welding units 211 is the same as the arrangement of the plurality of chips 110 on the wafer structure 100. In this way, when the wafer structure 100 is cut into heat source modules of different sizes, one packaging substrate 210 can be assembled with a plurality of heat source modules (i.e., die units 220) of different sizes. In other words, through the modular welding units 211 provided on the packaging substrate 210, it is possible to support the packaging of heat source modules of various sizes, and it is possible to electrically connect a plurality of heating pins 115 and a plurality of temperature measuring pins 114 to the corresponding welding units 211. The same set of packaging design can support the processing of thermal test chips of various sizes, thereby reducing the development cost of the thermal test chip. In the embodiment of the present application, each welding unit 211 includes a heating pad and a temperature measuring pad provided independently of each other, the heating pad and the heating pin 115 are electrically connected to each other, and the temperature measuring pad and the temperature measuring pin 114 are electrically connected to each other. Optionally, the heating pad and the heating pin 115, and the temperature measuring pad and the temperature measuring pin 114 are interconnected by reflow soldering; the packaging module 200 also includes a solder ball 212 provided on the bottom surface of the packaging substrate 210, and there are multiple solder balls 212. Some of the multiple solder balls 212 form heating solder balls, and another part of the multiple solder balls 212 form temperature measuring solder balls. The interior of the packaging substrate 210 is provided with a first trace and a second trace that are independent of each other. The heating solder ball is electrically connected to the heating pad via the first trace, and the temperature measuring solder ball is electrically connected to the temperature measuring pad via the second trace. In this way, by adjusting the output of the power supply, the heat generated by each heating unit can be independently controlled to achieve power consumption control of any chip 110, and the temperature of each temperature measuring unit 112 can be independently collected, thereby improving the flexibility of thermal testing.

[0047] Reference Figure 4 The size of the heat source module is the same as the array size of all welding units 211 on the packaging substrate 210. The welding units 211 on the packaging substrate 210 are all located below the heat source module, and all the pads are interconnected with the corresponding pins.

[0048] Reference Figure 7 The size of the heat source module is smaller than the array size of all welding units 211 on the packaging substrate 210. Some pads on the packaging substrate 210 are exposed and have no corresponding pins for interconnection.

[0049] In the examples of this application, refer to Figure 9 The packaging module 200 also includes a transfer board 230, and the grain unit 220 is interconnected with the packaging substrate 210 through the transfer board 230. In this way, a 2.5D flip chip can be realized. Optionally, the transfer board 230 can be any one of a silicon-based transfer board, an organic stacked transfer layer, and a glass transfer board, with multiple independent transfer traces inside. One surface of the transfer board 230 is provided with multiple independent transfer pads, and the other surface of the transfer board 230 is provided with transfer pins. The transfer pads and the transfer pins are respectively interconnected with the corresponding transfer traces, the heating pins 115 and the temperature measuring pins 114 are respectively interconnected with the corresponding transfer pads, and the heating pads and the temperature measuring pads are respectively interconnected with the corresponding transfer pins, so as to achieve electrical conduction between the heating circuit and the temperature measuring circuit.

[0050] In the examples of this application, refer to Figure 8 and Figure 9 The packaging module 200 also includes a heat dissipation cover 240, which is mounted on the packaging substrate 210 and cooperates with the packaging substrate 210 to form a mounting cavity, in which the die unit 220 is mounted. In this way, the heat dissipation cover 240 can effectively conduct heat emitted from the entire module, thereby reducing the operating temperature and improving the reliability and stability of the device. Furthermore, the heat dissipation cover 240 can also protect the die unit 220 from damage caused by the external environment. Optionally, the heat dissipation cover 240 and the packaging substrate 210 are bonded and fixed.

[0051] In the examples of this application, refer to Figure 8 and Figure 9 The packaging module 200 further includes a thermal interface material layer 250, which is filled between the heat dissipation cover 240 and the chip 110. The thermal interface material layer 250 can reduce the contact thermal resistance between the die unit 220 and the heat dissipation cover 240 and the chip-to-case thermal resistance. Optionally, the thermal interface material layer 250 can be made of an organic silicon thermal interface material, a carbon-based thermal interface material, or a metal thermal interface material.

[0052] In the examples of this application, refer to Figure 8 and Figure 9The packaging module 200 further includes an underfill material layer 260, which is placed between the heating pins 115 and the temperature measuring pins 114. The underfill material layer 260 fills the gap between the heating pins 115 and the temperature measuring pins 114. Furthermore, after curing, the underfill material layer 260 enhances the soldering strength between the heating pins 115 and the temperature measuring pins 114. When used in a 2.5D flip chip, an underfill material layer 260 may also be provided between the transfer pins of the transfer board 230 to improve the soldering strength of the transfer pins.

[0053] An embodiment of the present application also proposes a thermal test chip, which includes the packaging module 200 as described above. Specifically, the specific structure of the packaging module 200 refers to the above embodiment. Since the thermal test chip adopts all the technical solutions of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment, which will not be repeated here.

[0054] The above description is merely an exemplary embodiment of the present application and does not limit the patent scope of the embodiments of the present application. Any equivalent structural transformations made using the description and drawings of the embodiments of the present application under the technical concept of the embodiments of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the embodiments of the present application.

Claims

1. A wafer structure, characterized in that: The wafer structure includes a plurality of wafers arranged at intervals and a dicing path connecting two adjacent wafers, each wafer including a surface wiring layer and a temperature measuring unit and a heating unit stacked below the surface wiring layer, the surface wiring layer being provided with temperature measuring pins and heating pins independent of each other, the temperature measuring unit being electrically connected to the temperature measuring pins via temperature measuring metal vias, and the heating unit being electrically connected to the heating pins via heating metal vias; The heating pins in the plurality of chips are independently arranged, and the temperature measuring pins in the plurality of chips are independently arranged.

2. The wafer structure according to claim 1, wherein: The temperature measuring unit is a temperature measuring metal wire, the heating unit is a heating metal wire, and the temperature measuring metal wire and the heating metal wire are spaced apart.

3. The wafer structure according to claim 2, wherein: The wafer structure also includes multiple insulating layers stacked below the surface wiring layer, one of the insulating layers is provided with the temperature measuring metal trace, another of the insulating layers is provided with the heating metal trace, and at least one insulating layer is provided between the temperature measuring metal trace and the heating metal trace.

4. The wafer structure according to claim 2, wherein: In the same chip, four heating pins and four temperature measuring pins are provided.

5. The wafer structure according to claim 2, wherein: The heating metal traces are evenly arranged and the size of the envelope surface of the heating metal traces matches the size of the surface wiring layer; And / or, the projection of the temperature measuring metal trace is located at the center, corner, or center of the edge of the surface wiring layer.

6. The wafer structure according to claim 1, wherein: The wafer further includes a substrate on which the wafers are arranged in rows in a first direction and in columns along an orthogonal second direction.

7. A packaging module, characterized in that: The packaging module includes a packaging substrate and a grain unit arranged on the packaging substrate. The grain unit is cut from the wafer structure according to any one of claims 1 to 6. A plurality of independent welding units are spaced apart on the surface of the packaging substrate. The plurality of welding units are arranged in the same manner as the plurality of chips and correspond one to one.

8. The packaging module according to claim 7, wherein: Each of the welding units includes a heating pad and a temperature measuring pad that are independently arranged from each other, the heating pad and the heating pin are electrically connected to each other, and the temperature measuring pad and the temperature measuring pin are electrically connected to each other; the packaging module also includes a heating solder ball and a temperature measuring solder ball that are independent of each other and are arranged on the bottom surface of the packaging substrate, and the interior of the packaging substrate is provided with a first routing and a second routing that are independent of each other, the heating solder ball is electrically connected to the heating pad via the first routing, and the temperature measuring solder ball is electrically connected to the temperature measuring pad via the second routing.

9. The packaging module according to claim 8, wherein: The packaging module further includes a transfer board, and the die unit is interconnected with the packaging substrate via the transfer board.

10. The packaging module according to claim 8 or 9, characterized in that: The packaging module further includes a heat dissipation cover, which is disposed on the packaging substrate and cooperates with the packaging substrate to form a mounting cavity, and the die unit is disposed in the mounting cavity.

11. The packaging module according to claim 10, wherein: The packaging module further includes a thermal interface material layer filled between the heat dissipation cover and the chip.

12. The packaging module according to claim 10, wherein: The packaging module further includes an underfill material layer, and the underfill material layer is filled between the heating pins and the temperature measuring pins.

13. A thermal test chip, characterized in that: The thermal test chip comprises the package module according to any one of claims 7 to 12.

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