Coverage rate analysis method for chip verification and related device

Abstract

The invention relates to the technical field of chips, and provides a coverage rate analysis method for chip verification and a related device. The method is applied to hardware simulation equipment in which simulation codes are stored, the simulation codes comprise RTL codes used for simulating a chip and target codes used for simulating a recorder, and the chip comprises a controller and a memory; the method comprises the steps that in the process that a controller conducts chip verification through a preset test case, a recorder monitors a plurality of preset key signals; when the recorder monitors that any key signal is triggered, a test result corresponding to the key signal is stored in a storage area of the recorder; wherein the storage area and the memory have a mapping relationship; and the controller accesses the memory according to the mapping relation to obtain a test result set of the test cases in the storage area and performs coverage rate analysis. Therefore, the coverage rate information is obtained in real time in the chip verification process, and the efficiency and accuracy of coverage rate analysis are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a coverage analysis method and related devices for chip verification. Background Art

[0002] Coverage analysis is a crucial tool in chip design and verification, used to assess the extent to which test cases cover the chip's code and functionality. When using hardware emulation devices like EMUs (Emulators) to simulate chips, all test cases must be executed before test results can be obtained for coverage analysis.

[0003] However, in real-world applications, there are scenarios with specialized coverage requirements. For example, in some cases, users may need to obtain test results and perform coverage analysis immediately after executing a test case before continuing to the next test case. This requirement is crucial for gradually optimizing test strategies and monitoring chip functional coverage in real time. Therefore, existing coverage analysis methods cannot meet these flexible coverage analysis requirements. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a coverage analysis method and related apparatus for chip verification.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, the present invention provides a coverage analysis method for chip verification, which is applied to a hardware simulation device, wherein the hardware simulation device stores simulation code, the simulation code including RTL code for simulating a chip and target code for simulating a recorder, and the chip includes a controller and a memory. The method includes:

[0007] When the controller verifies the chip using a preset test case, the recorder monitors a plurality of preset key signals;

[0008] When the recorder detects that any key signal is triggered, the test result corresponding to the key signal is stored in the storage area of ​​the recorder; wherein the storage area has a mapping relationship with the memory;

[0009] The controller accesses the memory according to the mapping relationship, obtains the test result set of the test case in the storage area and performs coverage analysis.

[0010] In an optional embodiment, the target code is generated by a smart device in the following manner:

[0011] Perform chip verification based on the RTL code through a pre-existing software simulation platform to obtain a reference coverage report;

[0012] Using a pre-existing analysis tool, based on the reference coverage report, determine a plurality of code segments to be processed and their code segment types associated with the coverage;

[0013] Using a pre-existing analysis tool, based on each code segment to be processed and its code segment type, each key signal associated with the coverage is obtained to obtain a plurality of key signals;

[0014] The target code is generated according to the multiple key signals using a pre-existing generation tool.

[0015] In an optional implementation, determining, based on the reference coverage report, a plurality of code segments to be processed and their code segment types associated with the coverage includes:

[0016] Analyzing the information structure of the reference coverage report to obtain coverage information of multiple modules in the reference coverage report;

[0017] A plurality of code segments to be processed and associated with the coverage and their code segment types are determined from the coverage information of the plurality of modules.

[0018] In an optional embodiment, each code segment type has at least one code segment format;

[0019] Based on each code segment to be processed and its code segment type, each key signal associated with the coverage is obtained, and multiple key signals are obtained, including:

[0020] For each code segment to be processed, obtaining at least one candidate code segment format according to the code segment type of the code segment to be processed;

[0021] Selecting a target code segment format that matches the code segment to be processed from all candidate code segment formats;

[0022] According to the target code segment format, key signals are obtained from the code segment to be processed, and key signals in each code segment to be processed are obtained to obtain multiple key signals; wherein the key signals represent execution conditions of the code segment to be processed.

[0023] In an optional embodiment, generating the target code according to the multiple key signals includes:

[0024] Creating corresponding storage areas according to the multiple key signals, and establishing a mapping relationship between the storage space of each key signal in the storage area and the memory;

[0025] Based on the multiple key signals, the storage areas and the mapping relationships, corresponding synthesizable codes are generated to obtain the target code; wherein the synthesizable code refers to a code that represents the structure and behavioral logic of a device through a hardware description language.

[0026] In an optional embodiment, the simulation code is generated by a smart device in the following manner:

[0027] The RTL code and the target code are compiled to obtain the simulation code.

[0028] In a second aspect, the present invention provides a computer program product, comprising a computer program. When the computer program is executed by a processor, the computer program implements the coverage analysis method for chip verification described in any one of the aforementioned embodiments.

[0029] In a third aspect, the present invention provides an electronic device comprising a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the chip verification coverage analysis method described in any one of the aforementioned embodiments is implemented.

[0030] In a fourth aspect, the present invention provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the coverage analysis method for chip verification described in any one of the aforementioned embodiments is implemented.

[0031] In a fifth aspect, the present invention provides a system comprising a hardware simulation device and an intelligent device.

[0032] The chip verification coverage analysis method and related device provided by the embodiment of the present invention are applied to a hardware simulation device storing simulation code, the simulation code including RTL code for simulating the chip and target code for simulating the recorder, and the chip including a controller and a memory; the method includes: when the controller uses a preset test case to verify the chip, the recorder monitors a plurality of preset key signals; when the recorder detects that any key signal is triggered, the test result corresponding to the key signal is stored in the storage area of ​​the recorder; wherein the storage area has a mapping relationship with the memory; the controller accesses the memory according to the mapping relationship, obtains the test result set of the test case in the storage area and performs coverage analysis. Thus, it is possible to obtain coverage information in real time during the chip verification process, improve the efficiency and accuracy of coverage analysis, and provide technical support for dynamically adjusting the test strategy.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 A schematic diagram of a system provided by an embodiment of the present invention is shown;

[0036] Figure 2 A block diagram of an electronic device provided by an embodiment of the present invention is shown;

[0037] Figure 3 A schematic diagram showing a flow chart of a coverage analysis method for chip verification provided by an embodiment of the present invention is shown;

[0038] Figure 4 A schematic diagram of a process for generating target code according to an embodiment of the present invention is shown;

[0039] Figure 5 A schematic diagram of a process for generating simulation codes provided by an embodiment of the present invention is shown.

[0040] Icon: 100 - electronic device; 110 - processor; 120 - memory; 130 - communication module. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0043] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0044] See also Figure 1 , is a schematic diagram of a system provided by an embodiment of the present invention. The system includes a hardware emulation device and an intelligent device in communication with each other. The intelligent device generates emulation code and transmits it to the hardware emulation device. The hardware emulation device simulates a chip and recorder based on the emulation code and executes the chip verification coverage analysis method provided by an embodiment of the present invention.

[0045] A hardware emulation device can be understood as a device that simulates system and device functionality through hardware. For example, a hardware emulation device can be a Cadence Palladium emulator. Smart devices can include personal computers, ultra-mobile personal computers, tablets, netbooks, and other devices.

[0046] See also Figure 2 , is a block diagram of an electronic device provided by an embodiment of the present invention. The structure of the electronic device 100 can be used to implement Figure 1 The electronic device 100 includes a processor 110, a memory 120, and a communication module 130. Each component is electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines.

[0047] The processor 110 is used to read / write data or programs stored in the memory 120 and execute corresponding functions. It can be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc.; it can also be a DSP digital signal processor, an ASIC application-specific integrated circuit, an FPGA off-the-shelf programmable gate array or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0048] The memory 120 is used to store programs or data, and can be RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0049] The communication module 130 is used to communicate signaling or data with other devices.

[0050] It is understandable that Figure 2 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may also include Figure 2 More or fewer components than shown, or with Figure 2 Different configurations shown. Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0051] The following will use the hardware simulation device as the execution subject to introduce the various steps in the chip verification coverage analysis method provided by the embodiment of the present invention, as well as the corresponding technical effects. Figure 3 , is a flow chart of the coverage analysis method for chip verification provided by an embodiment of the present invention.

[0052] In step S202 , the controller uses a preset test case to verify the chip, and the recorder monitors a plurality of preset key signals.

[0053] In step S204 , when the recorder detects that any key signal is triggered, the recorder stores the test result corresponding to the key signal in a storage area of ​​the recorder; wherein the storage area has a mapping relationship with the memory.

[0054] Step S206: The controller accesses the memory according to the mapping relationship, obtains the test result set of the test case in the storage area, and performs coverage analysis.

[0055] It is understood that the hardware emulation device in the embodiments of the present invention stores emulation code. This emulation code consists of two parts: one is the RTL (Register Transfer Level Code) code used to emulate the chip, and the other is the target code used to emulate the recorder. The chip also includes a controller and memory, which work together with the recorder to implement coverage analysis.

[0056] In this embodiment, the controller verifies the chip by running pre-set test cases. During this process, the recorder monitors multiple pre-set key signals. These key signals are closely related to the functional characteristics of the chip, and their trigger status directly reflects whether the test case covers the specific code or function.

[0057] When the recorder detects any key signal being triggered, it will store the test results corresponding to that key signal in the recorder's storage area. It should be noted that the storage area is a region dedicated to recording coverage-related information, which can provide data support for subsequent coverage analysis.

[0058] Furthermore, to enable the controller to access the test result sets in the storage area, a mapping relationship is established between the storage area and the chip's memory. Based on this mapping relationship, the controller can access the memory to obtain the test result set for the test case in the storage area and perform coverage analysis based on this test result set. This ensures that after executing a test case, the test result information and coverage analysis can be obtained in a timely manner.

[0059] It can be understood that in the embodiment of the present invention, during the process of the controller using test cases to verify the chip, a recorder is used to monitor key signals. When the key signals are detected to be triggered, the test results are saved to the storage area. After executing the test cases, the controller can access the memory to obtain the test result set and perform coverage analysis based on the mapping relationship between the storage area and the memory. This enables real-time acquisition of coverage information during the chip verification process, improves the efficiency and accuracy of coverage analysis, and provides technical support for dynamically adjusting test strategies.

[0060] Optionally, based on the above target code, the embodiment of the present invention uses the smart device as the execution subject and provides an implementation method for generating the target code through the smart device. Figure 4 .

[0061] Step S302 : performing chip verification based on the RTL code through a pre-stored software simulation platform to obtain a reference coverage report.

[0062] Step S304 : using a pre-stored analysis tool and based on the reference coverage report, determining a plurality of code segments to be processed and their code segment types that are associated with the coverage.

[0063] Step S306 : using a pre-stored analysis tool, based on each code segment to be processed and its code segment type, obtaining each key signal associated with the coverage rate, and obtaining a plurality of key signals.

[0064] Step S308: Generate target code based on multiple key signals using a pre-stored generation tool.

[0065] It is understandable that the smart device is pre-stored with a software simulation platform such as EDA (Electronic Design Automation), as well as analysis tools such as Html Parser and generation tools such as Coverage Module Generator.

[0066] In this embodiment, a software simulation platform can be used to first verify the chip based on the RTL code to obtain a reference coverage report. For example, a software simulation platform such as EDA can be used to simulate the chip based on the RTL code, and test cases can be used to perform functional verification of the chip to obtain a functional verification report, that is, a reference coverage report. This reference coverage report can provide detailed information about the RTL code coverage, laying the foundation for subsequent key signal extraction.

[0067] Since the reference coverage report is in HTML (Hypertext Markup Language) format, an analysis tool such as HTML Parser can be used to parse it to identify multiple pending code segments associated with coverage and their code segment types. A pending code segment can be understood as a code segment in the RTL code that affects the coverage result, and a code segment type can be understood as a type classified according to the structural characteristics of the code segment.

[0068] Next, using an analysis tool such as HTML Parser, based on each code segment to be processed and its code segment type, key signals are obtained from each code segment to be processed, thereby obtaining multiple key signals. Finally, using a generation tool such as Coverage Module Generator, target code for simulating a recorder is generated based on the multiple key signals.

[0069] This embodiment of the present invention uses a software simulation platform to obtain a reference coverage report. Analysis tools are then used to parse the report, identify the code segments to be processed and their types, extract key signals, and then use generation tools to generate target code based on these key signals. This ensures that the target code accurately reflects coverage-related characteristics, improving the efficiency of coverage analysis.

[0070] Optionally, for step S304, an embodiment of the present invention provides a possible implementation method.

[0071] Step S304 - 1 : Analyze the information structure of the reference coverage report to obtain coverage information of multiple modules in the reference coverage report.

[0072] Step S304 - 2 : determining, from the coverage information of the multiple modules, multiple code segments to be processed and their code segment types associated with the coverage.

[0073] In this embodiment, an analysis tool such as HTML Parser can be used to analyze the information structure of a reference coverage report to obtain coverage information for multiple modules. The coverage information for a module includes the module name, instantiation path, coverage result, and its corresponding code segment. Subsequently, for each module's coverage information, at least one code segment to be processed associated with the coverage is obtained and its code segment type is determined, thereby obtaining multiple code segments to be processed and their code segment types.

[0074] It can be understood that the embodiment of the present invention processes the coverage information of each module in a similar manner. For the sake of simplicity, the coverage information of a module is used as an example for explanation. For example, the coverage information of a module is as follows:

[0075]

[0076]

[0077] In the above module coverage information example, m_module is the module name, top.m_inst is the instantiation path, and branch result1, branch result2, and branch result3 are all coverage results. Branch result1 corresponds to code segment 1, namely, assign sig1=sig2?sig3:sig4. Branch result2 corresponds to code segment 2, namely, if (!sig5) a=b; else if (sig6) a=c; else=d. Branch result3 corresponds to code segment 3, namely, case ((sig7, sig8))0:xxx1:xxx2:xxxdefault:xxxendcase.

[0078] You can pre-set a variety of coverage-related code segment types. For example, code segment types can include branch type, condition type, and finite state machine type. Among them, the branch type indicates that the code segment is used to describe different paths of data flow or control flow. The condition type indicates that the code segment is used to describe the conditions for performing a certain operation or entering a certain state. The finite state machine type indicates that the code segment is used to describe the logic of state transition. In addition, you can also set corresponding keywords for each code segment type. For example, the keyword for the branch type is Branch, the keyword for the condition type is Condition, and the keyword for the finite state machine type is FSM or Finite State Machine.

[0079] Then, the keyword of each code segment type can be matched with the coverage information of the module. If there is a coverage result that matches the keyword, the code segment corresponding to the coverage result is used as the code segment to be processed associated with the coverage, and the code segment type corresponding to the keyword is used as the code segment type of the code segment to be processed.

[0080] For example, in the coverage information example of the above module, the coverage results branch result1, branch result2 and branch result3 all match the branch type keyword, namely Branch, then the code segments corresponding to branch result1, branch result2 and branch result3, namely code segment 1, code segment 2 and code segment 3 are all used as code segments to be processed, and the code segment types of these three code segments to be processed are all branch types.

[0081] It can be understood that the embodiments of the present invention parse the information structure of the reference coverage report to extract coverage information for multiple modules. Based on this coverage information, the code segments to be processed and their types are further determined. This ensures that the selection of the code segments to be processed has a clear basis and accurately reflects the code characteristics that have a direct impact on the coverage results.

[0082] Optionally, for step S306, an embodiment of the present invention provides a possible implementation method.

[0083] Step S306 - 1 : For each code segment to be processed, obtain at least one candidate code segment format according to the code segment type of the code segment to be processed.

[0084] Step S306 - 2 : Select a target code segment format that matches the code segment to be processed from all candidate code segment formats.

[0085] Step S306-3, according to the target code segment format, obtain key signals from the code segment to be processed, obtain key signals in each code segment to be processed, and obtain multiple key signals; wherein the key signals represent the execution conditions of the code segment to be processed.

[0086] It is understood that each code segment type has at least one code segment format. For example, a branch type code segment has three code segment formats: tri-state conditional, if-else (if...else), and multi-branch (case). For ease of understanding, the following description will continue with the example of code segments 1 to 3 being the code segments to be processed.

[0087] For example, for the code segment to be processed, Code Segment 1, given that Code Segment 1 is a branch type, three candidate code segment formats are obtained: tri-state conditional, if-else (if...else), and multi-branch (case). Then, from these three candidate code segment formats, the candidate code segment format that matches Code Segment 1 is selected, resulting in the target code segment format, the tri-state conditional. Based on the tri-state conditional code segment format, information representing its execution condition is obtained from Code Segment 1, resulting in the key signal, sig2.

[0088] For the code segment to be processed, Code Segment 2, since its code segment type is a branch type, three candidate code segment formats are obtained: tri-state conditional, if-else, and multi-branch (case). Then, from these three candidate code segment formats, the candidate code segment format that matches Code Segment 2 is selected, resulting in the target code segment format, if-else. Based on the if-else code segment format, information representing its execution condition is obtained from Code Segment 2, resulting in the key signals, sig5 and sig6.

[0089] For the code segment to be processed, code segment 3, since its code segment type is a branch type, three candidate code segment formats are obtained: tri-state conditional, if-else (if...else), and multi-branch (case). Then, from these three candidate code segment formats, the candidate code segment format that matches code segment 3 is selected, resulting in the target code segment format, multi-branch (case). Based on the multi-branch (case) code segment format, information representing its execution condition is obtained from code segment 3, resulting in the key signals sig7 and sig8.

[0090] It can be understood that this embodiment of the present invention determines candidate code segment formats based on the code segment type to be processed, selects a target code segment format through a matching operation, and extracts key signals based on the target code segment format. This matching and extraction mechanism enables efficient acquisition of coverage-related key signals, laying a solid foundation for generating target code.

[0091] Optionally, for step S308, an embodiment of the present invention provides a possible implementation method.

[0092] Step S308 - 1 : creating corresponding storage areas according to a plurality of key signals, and establishing a mapping relationship between the storage space of each key signal in the storage area and the memory.

[0093] Step S308-2, based on multiple key signals, storage areas and mapping relationships, generate corresponding synthesizable code to obtain target code; wherein the synthesizable code refers to the code that represents the structure and behavior logic of the device through the hardware description language.

[0094] In this embodiment, based on the multiple key signals obtained, a generation tool, such as Coverage Module Generator, can be used to create a storage area of ​​corresponding size. Specifically, the generation tool creates a storage area with a size that matches the number of key signals, with each key signal having a corresponding storage space within the storage area. Furthermore, to facilitate timely access to test results by the controller, a mapping relationship is established between the storage space corresponding to each key signal and the memory.

[0095] Subsequently, a generation tool such as Coverage Module Generator is used to generate corresponding synthesizable code based on multiple key signals, storage areas, and mapping relationships to obtain the target code. The target code can be understood as a code that is generated by a generation tool using a hardware description language to represent the structure and behavioral logic of the recorder. The structure of the recorder includes a storage area that has a mapping relationship with the memory, and each storage space in the storage area has a corresponding key signal. Moreover, the behavioral logic of the recorder is to monitor multiple key signals when the controller uses a test case to verify the chip, and when a key signal is detected to be triggered, the test result corresponding to the key signal is stored in the corresponding storage space in the storage area.

[0096] It can be understood that the embodiments of the present invention create storage areas based on multiple key signals and establish a mapping relationship between the storage areas and memory to generate synthesizable code to obtain target code. This ensures that the target code not only accurately reflects the state changes of key signals but also runs efficiently in a hardware simulation environment to support real-time coverage analysis.

[0097] Optionally, based on the target code obtained above, the embodiment of the present invention also provides an implementation method for generating simulation code through a smart device, see Figure 5 After the above step S308, the process further includes step S310, compiling the RTL code and the target code to obtain simulation code.

[0098] In this embodiment, the RTL code and target code are compiled to produce complete simulation code adapted for the hardware simulation device. The two components of the simulation code each play a different role: the RTL code describes the basic logic structure and behavioral characteristics of the chip, while the target code supplements the monitoring and recording functions required for real-time coverage analysis.

[0099] It can be understood that the embodiment of the present invention integrates the RTL code and the target code into a complete simulation code through a compilation operation. In addition, during the compilation process, the target code is embedded into the RTL code to ensure that the two can work together. In this way, the final simulation code not only retains the RTL code's ability to describe the chip logic, but also integrates the coverage monitoring and recording functions provided by the target code. This achieves the functional expansion of the simulation code and can simultaneously meet the needs of chip verification and coverage analysis.

[0100] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the coverage analysis method for chip verification disclosed in the embodiment of the present invention.

[0101] An embodiment of the present invention further provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the chip verification coverage analysis method disclosed in the embodiment of the present invention is implemented.

[0102] An embodiment of the present invention further provides a storage medium storing a computer program. When the computer program is executed by a processor, the coverage analysis method for chip verification disclosed in the embodiment of the present invention is implemented.

[0103] An embodiment of the present invention further provides a system, including the hardware simulation device and the intelligent device provided by the embodiment of the present invention.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a portion of code, and the module, program segment or a portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0105] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0106] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0107] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip verification coverage analysis method, characterized in that: Applied to a hardware emulation device, the hardware emulation device stores emulation code, the emulation code includes RTL code for emulating a chip and target code for emulating a recorder, the chip includes a controller and a memory, and the method includes: When the controller verifies the chip using a preset test case, the recorder monitors a plurality of preset key signals; When the recorder detects that any key signal is triggered, the test result corresponding to the key signal is stored in the storage area of ​​the recorder; wherein the storage area has a mapping relationship with the memory; The controller accesses the memory according to the mapping relationship, obtains the test result set of the test case in the storage area and performs coverage analysis.

2. The chip verification coverage analysis method according to claim 1, characterized in that: The target code is generated by the smart device in the following manner: Perform chip verification based on the RTL code through a pre-existing software simulation platform to obtain a reference coverage report; Using a pre-stored analysis tool, based on the reference coverage report, determine a plurality of code segments to be processed and their code segment types associated with the coverage; Using a pre-existing analysis tool, based on each code segment to be processed and its code segment type, each key signal associated with the coverage is obtained to obtain a plurality of key signals; The target code is generated according to the multiple key signals using a pre-existing generation tool.

3. The chip verification coverage analysis method according to claim 2, characterized in that: Determine, based on the reference coverage report, a plurality of code segments to be processed and associated with the coverage and their code segment types, including: Analyzing the information structure of the reference coverage report to obtain coverage information of multiple modules in the reference coverage report; A plurality of code segments to be processed and associated with the coverage and their code segment types are determined from the coverage information of the plurality of modules.

4. The chip verification coverage analysis method according to claim 2, characterized in that: Each code segment type has at least one code segment format; Based on each code segment to be processed and its code segment type, each key signal associated with the coverage is obtained, and multiple key signals are obtained, including: For each code segment to be processed, obtaining at least one candidate code segment format according to the code segment type of the code segment to be processed; Selecting a target code segment format that matches the code segment to be processed from all candidate code segment formats; According to the target code segment format, key signals are obtained from the code segment to be processed, and key signals in each code segment to be processed are obtained to obtain multiple key signals; wherein the key signals represent execution conditions of the code segment to be processed.

5. The chip verification coverage analysis method according to claim 2, characterized in that: Generating the target code according to the multiple key signals includes: Creating corresponding storage areas according to the multiple key signals, and establishing a mapping relationship between the storage space of each key signal in the storage area and the memory; Based on the multiple key signals, the storage areas and the mapping relationships, corresponding synthesizable codes are generated to obtain the target code; wherein the synthesizable code refers to a code that represents the structure and behavioral logic of a device through a hardware description language.

6. The chip verification coverage analysis method according to claim 2, characterized in that: The simulation code is generated by the smart device in the following manner: The RTL code and the target code are compiled to obtain the simulation code.

7. A computer program product, characterized in that The computer program product includes a computer program, and when the computer program is executed by a processor, the coverage analysis method for chip verification according to any one of claims 1 to 6 is implemented.

8. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the coverage analysis method for chip verification according to any one of claims 1 to 6 is implemented.

9. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the coverage analysis method for chip verification according to any one of claims 1 to 6.

10. A system, characterized in that: Including hardware emulation devices and smart devices.

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