Oscillator circuit for PWM controller

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to an oscillator circuit for a PWM controller. Background Art

[0002] Oscillator circuits are key electronic circuits that generate periodic electrical signals (such as sine waves, square waves, or pulse waves) and are widely used in communications, consumer electronics, industrial control, and instrumentation. In communications systems, oscillators generate carrier signals to ensure the stability of wireless transmission. In consumer electronics (such as smartphones and IoT devices), they provide a reference frequency for clock circuits, ensuring the synchronous operation of processors and sensors. In industrial control, oscillators drive PWM controllers to regulate motor speed and power conversion efficiency. In precision instruments (such as medical equipment and test instruments), high-frequency, low-noise oscillators are central to achieving high-precision measurements.

[0003] The current PWM controller oscillator industry is undergoing a technological transition. While traditional RC charging and discharging and ring oscillator architectures remain mainstream, they face new challenges in high frequency, low power consumption, and strong anti-interference. International giants maintain their lead through digital DCO and intelligent spread spectrum technology, while domestic manufacturers are accelerating import substitution in the mid- and low-end markets. With the high-frequency trend brought about by the popularization of GaN / SiC power devices and the stringent high-reliability requirements of automotive electronics and industrial power supplies, the industry urgently needs to break through key technical bottlenecks such as high-precision temperature compensation, ultra-low static power consumption (<10μA), and adaptive EMI suppression while maintaining cost advantages. This will drive the evolution of oscillator architecture towards a mixed-signal "analog core + digital calibration + intelligent control" to meet the differentiated needs of emerging markets such as 5G power supplies and new energy vehicles.

[0004] In existing technology, the oscillator circuit of a PWM controller typically uses an RC charge-discharge or ring oscillator design. Its core function is to generate a stable frequency signal to set the PWM switching period. The following is a brief description of two mainstream technical solutions: ① The first technical solution uses an RC charge-discharge oscillator. The charge and discharge processes of resistor R and capacitor C generate a triangular or sawtooth wave, which, in conjunction with a comparator, generates the clock signal required for PWM. For example, the key components of a typical circuit include a timing resistor RT and capacitor CT, which determine the frequency, and a comparator that compares the triangular wave with a reference voltage to output a square-wave clock. During the charging phase, a current source charges the capacitor through the resistor, causing the voltage to rise linearly. During the discharging phase, when the capacitor voltage reaches an upper threshold, an internal switch, such as a MOS transistor, turns on, rapidly discharging the capacitor to a lower threshold, and the cycle repeats. Advantages of this circuit include a simple structure, low cost, and flexible frequency adjustment via the RC value. Disadvantages include poor frequency stability due to temperature and component accuracy, and significant nonlinear charge and discharge errors at high frequencies. Another technical solution uses a ring oscillator; an odd number of inverter stages (such as three or five) form a feedback loop, generating a square wave through gate-delayed self-oscillation. Key components of a typical circuit include a CMOS inverter chain as the basic oscillation unit and a frequency modulation control circuit, such as a varactor diode or current source. Each inverter stage introduces a delay td, resulting in a total period T = 2 × n × td (n is the number of stages). The frequency can be adjusted by controlling the delay VCD voltage, forming a voltage-controlled oscillator (VCO). Advantages of this circuit: Suitable for integrated circuit (IC) design, no external RC required; excellent high-frequency performance (up to MHz); Disadvantages: Frequency is significantly affected by process variations and power supply noise; Area / power consumption is high for low-frequency applications.

[0005] In summary, the PWM controller in the prior art has the following main defects: (1) Weak anti-interference ability: Both traditional solutions are susceptible to external noise (such as power supply ripple and coupling interference). High-frequency EMI (such as di / dt noise of the switching power supply) may be coupled to the RC loop through parasitic capacitance, causing the charge and discharge waveforms to be distorted and destroying the linearity of the PWM duty cycle.

[0006] (2) Slow dynamic regulation response: When adjusting the frequency in real time (such as variable frequency control), the charging and discharging inertia of the RC circuit or the phase-locking delay of the ring oscillator will cause a response lag.

[0007] (3) Poor frequency stability: The values ​​of resistors and capacitors in traditional structures change with temperature (such as the capacitance-temperature characteristics of ceramic capacitors and the TCR of resistors), resulting in oscillation frequency drift.

[0008] (4) Poor frequency adjustability: When the traditional structure oscillator is adjusted over a wide range, the frequency change rate is inconsistent, requiring table lookup or digital compensation, which increases costs.

[0009] (5) High power consumption: Dynamic power consumption is linearly related to frequency. The overall power consumption rises sharply in high-frequency applications. The switching loss is significant. The short-circuit current and gate drive loss during the MOS tube switching process increase with increasing frequency. Summary of the Invention

[0010] The present invention aims to provide an oscillator circuit and a charge pump circuit for a PWM controller. The present invention dynamically adjusts the PWM frequency to match the switching frequency with the load demand, reduces the number of invalid switches, and greatly reduces power consumption. By using constant current charging and discharging instead of resistors, di / dt noise is reduced and frequency stability is improved. The present invention implements a spread spectrum function through frequency jittering or intermittent modulation to slightly modulate the oscillator frequency and disperse EMI energy over a wider frequency band, thereby reducing peak noise.

[0011] To solve the above technical problems, the present invention provides an oscillator circuit for a PWM controller, comprising: An oscillator module includes a feedback loop and a current detection circuit; the input end of the feedback loop inputs the inverted signal X41_YN output by the output end of the current detection circuit; the output end of the feedback loop outputs a signal N4_G to the input end of the current detection circuit, compares the signal with the voltage signal VH and the voltage signal VL, and outputs a signal X42_YN, which is then inverted and output as the signal X41_YN; The hiccup module, according to the level of the input PWM logic control signal X840_SNN, the data selector selects and outputs its input signal to control the on and off of the transmission gate, and establishes the charging and discharging process, providing a delayed start function for the oscillator module; The frequency jittering module outputs a current source Iref0 of different magnitudes by combining and selecting the current source I'ref and the current sources I1 to I4, and then outputs four current sources Iref1 to Iref4 of different magnitudes through a current mirror array, thereby providing charge and discharge currents for the oscillator module and the hiccup module. When the PWM logic control signal X840_SNN is low, the data selector MUX selects the output signal X1225_Y as signal R720_MINUS, and the operating mode enters hiccup mode. The discharge process in hiccup mode is the same as that in normal operating mode. When the voltage VN4_G drops below the voltage VL, the current source Iref1 does not immediately start charging the capacitor C1. Instead, it waits until the capacitor C2 is charged to a voltage VN1_G greater than the voltage VP45_S. When the comparator COM3 outputs a high level and the R-terminal input of the RS trigger RS2 is low, the current source Iref1 begins to charge the capacitor C1.

[0012] Preferably, the feedback loop includes: an inverter INV1, a PMOS transistor P1, an NMOS transistor N1 and a capacitor C1; the input end of the inverter INV1 inputs a signal X42_YN, the output end of the inverter INV1 outputs a signal X41_YN to the gates of the PMOS transistor P1 and the NMOS transistor N1, the PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and the grounded capacitor C1, and outputs a signal N4_G as an output end, the source of the PMOS transistor P1 is connected to a current source Iref1 connected to a power supply X2_D, and the source of the NMOS transistor N1 is connected to a grounded current source Iref2.

[0013] Preferably, the current detection circuit includes: comparators COM1~COM2, inverters INV2~INV6 and RS triggers RS1~RS2; the non-inverting input terminals of the comparators COM1~COM2 input signal N4_G, the inverting input terminals of the comparators COM1~COM2 input voltage signal VH and voltage signal VL respectively, the output terminal of the comparator COM1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the S terminal of the RS trigger RS1, the output terminal of the comparator COM2 is connected in series with inverters INV3~INV4 in sequence, the output terminal of the inverter INV4 is connected to the D terminal of the RS trigger RS1, an inverter INV5 is connected in series between the Q terminal of the RS trigger RS1 and the S terminal of the RS trigger RS2, the Q terminal of the RS trigger RS2 is connected to the input terminal of the inverter INV6, and the output terminal of the inverter INV6 outputs the signal X42_YN.

[0014] Preferably, the hiccup module includes: a data selector MUX, a PMOS tube P2, a transmission gate, a capacitor C2, a comparator COM3 and an inverter INV7; the control end of the data selector MUX is connected to the PWM logic control signal X840_SNN, the two input ends of the data selector MUX are respectively connected to the signal R734_MINUS and the signal P872_G, the output end of the data selector MUX is connected to the gate of the PMOS tube P2, and the source of the PMOS tube P2 is connected to the current source I connected to the power supply X2_D ref4 and the input end of the transmission gate, the drain of the PMOS tube P2 is grounded, the two control ends of the transmission gate are respectively connected to the signal X41_YN and the signal, the output end of the transmission gate is connected to the current source Iref3 connected to the power supply X2_D, the grounded capacitor C2 and the non-inverting input end of the comparator COM3, the inverting input end of the comparator COM3 is connected to the signal P45_S, the output end of the comparator COM3 is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is connected to the R end of the RS trigger RS2.

[0015] Preferably, the transmission gate is composed of a parallel complementary PMOS transistor and NMOS transistor pair.

[0016] Preferably, the frequency jittering module includes: switching tubes D1~D4; the gates of the switching tubes D1~D4 are sequentially connected to the control signals X1_Q~X4_Q, the drains of the switching tubes D1~D4 are sequentially connected to the current sources I1~I4 connected to the power supply X2_D, and the sources of the switching tubes D1~D4 are connected to the current source I'ref connected to the power supply X2_D and the grounded current source Iref0.

[0017] Preferably, the ratio of the current sources I1 to I4 is I1:I2:I3:I4=8:4:2:1.

[0018] Preferably, it further comprises a charge-discharge constant current source circuit, wherein the charge-discharge constant current source circuit generates a current source I'ref by mirroring the current mirror.

[0019] Preferably, the charge and discharge constant current source circuit includes: PMOS transistors P3-P4, NMOS transistors N2-N3, an operational amplifier OP, a temperature compensation resistor r, and a resistor RI; the source of the PMOS transistor P3 is connected to the power supply X2_D, the gate and drain of the PMOS transistor P3 are connected to the source of the PMOS transistor P4, the gate and drain of the PMOS transistor P4 are connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N2 is connected to the output end of the operational amplifier OP and the gate of the NMOS transistor N3, the source of the NMOS transistor N2 is connected to the source of the NMOS transistor N3, one end of the temperature compensation resistor r, and the inverting input end of the operational amplifier OP, the non-inverting input end of the operational amplifier OP is connected to the reference voltage Vref, the other end of the temperature compensation resistor r is connected to the grounded resistor RI, and the drain of the NMOS transistor N3 is connected to the current source Iref connected to the power supply X2_D.

[0020] Preferably, the gate and drain of the PMOS transistor P4 generate a current source Iref5, the ratio of the current source Iref5 to the current source Iref is Iref5:Iref=1:14.85, and the resistor RI=56KΩ.

[0021] Compared with the prior art, the present invention has the following beneficial effects: The present invention significantly reduces power consumption through dynamic frequency regulation, reduces invalid switches by real-time matching of load demand, and improves energy efficiency, making it particularly suitable for battery-powered scenarios. It optimizes the use of constant current sources to replace traditional resistors, suppresses noise and enhances frequency stability, and solves temperature drift and process deviation problems. It implements intelligent spread spectrum function through frequency jittering or intermittent modulation. The intelligent spread spectrum function disperses EMI energy while maintaining PWM accuracy, reduces filtering costs, and easily passes EMI certification. Therefore, the present invention breaks through the existing technical bottlenecks in low power consumption, high stability and anti-interference through the synergistic effect of these three innovations, and is suitable for high-end scenarios such as consumer electronics and automotive power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The present invention provides a block diagram of an oscillator circuit for a PWM controller.

[0023] Figure 2 It is a circuit diagram of the oscillator module provided by the present invention.

[0024] Figure 3 It is a circuit diagram of the hiccup module provided by the present invention.

[0025] Figure 4 This is a circuit diagram of the frequency jittering module provided by the present invention.

[0026] Figure 5 It is a circuit diagram of the charge and discharge constant current source circuit provided by the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0028] like Figures 1 to 5 As shown, an embodiment of the present invention specifically provides an oscillator circuit for a PWM controller, including: An oscillator module includes a feedback loop and a current detection circuit; the input end of the feedback loop inputs the inverted signal X41_YN output by the output end of the current detection circuit, and the output end of the feedback loop outputs a signal N4_G (a triangular wave signal, which is also output to an external slope compensation) to the input end of the current detection circuit. After comparing the signal with the voltage signal VH and the voltage signal VL, the signal X42_YN (a rectangular wave signal, which is also output to an external frequency divider) is output, and the signal X41_YN is output after being inverted. The hiccup module, according to the level of the input PWM logic control signal X840_SNN, the data selector selects and outputs its input signal to control the on and off of the transmission gate, and establishes the charging and discharging process, providing a delayed start function for the oscillator module; The frequency jittering module outputs a current source Iref0 of different sizes by combining and selecting the current source I'ref and the current sources I1~I4, and outputs four current sources Iref1~Iref4 of different sizes through a current mirror array to provide charging and discharging current for the oscillator module and the hiccup module.

[0029] As a further explanation of an embodiment of the present invention, the feedback loop includes: an inverter INV1, a PMOS transistor P1, an NMOS transistor N1 and a capacitor C1; the input end of the inverter INV1 inputs a signal X42_YN, the output end of the inverter INV1 outputs a signal X41_YN to the gates of the PMOS transistor P1 and the NMOS transistor N1, the PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and the grounded capacitor C1, and outputs a signal N4_G as an output end, the source of the PMOS transistor P1 is connected to a current source Iref1 connected to a power supply X2_D, and the source of the NMOS transistor N1 is connected to a grounded current source Iref2.

[0030] As a further explanation of an embodiment of the present invention, the current detection circuit includes: comparators COM1~COM2, inverters INV2~INV6 and RS triggers RS1~RS2; the non-inverting input terminals of the comparators COM1~COM2 input signal N4_G, the inverting input terminals of the comparators COM1~COM2 respectively input voltage signals VH and VL, the output terminal of the comparator COM1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the S terminal of the RS trigger RS1, the output terminal of the comparator COM2 is connected in series with inverters INV3~INV4 in sequence, the output terminal of the inverter INV4 is connected to the D terminal of the RS trigger RS1, an inverter INV5 is connected in series between the Q terminal of the RS trigger RS1 and the S terminal of the RS trigger RS2, the Q terminal of the RS trigger RS2 is connected to the input terminal of the inverter INV6, and the output terminal of the inverter INV6 outputs the signal X42_YN.

[0031] As a further elaboration of an embodiment of the present invention, the hiccup module includes: a data selector MUX, a PMOS tube P2, a transmission gate, a capacitor C2, a comparator COM3 and an inverter INV7; the control end of the data selector MUX is connected to the PWM logic control signal X840_SNN, the two input ends of the data selector MUX are respectively connected to the signal R734_MINUS and the signal P872_G, the output end of the data selector MUX is connected to the gate of the PMOS tube P2, and the source of the PMOS tube P2 is connected to the power supply X2_ D's current source Iref4 and the input end of the transmission gate, the drain of the PMOS tube P2 is grounded, the two control ends of the transmission gate are respectively connected to the signal X41_YN and the signal, the output end of the transmission gate is connected to the current source Iref3 connected to the power supply X2_D, the grounded capacitor C2 and the non-inverting input end of the comparator COM3, the inverting input end of the comparator COM3 is connected to the signal P45_S, the output end of the comparator COM3 is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is connected to the R end of the RS trigger RS2.

[0032] As a further explanation of an embodiment of the present invention, the transmission gate is composed of a parallel complementary PMOS transistor and NMOS transistor pair, and the capacitors C1~C2 are all MOS capacitors; the ratio of the current sources I1~I4 is I1:I2:I3:I4=8:4:2:1.

[0033] As a further explanation of an embodiment of the present invention, the frequency jittering module includes: switching tubes D1 to D4; the gates of the switching tubes D1 to D4 are sequentially connected to control signals X1_Q to X4_Q, the drains of the switching tubes D1 to D4 are sequentially connected to current sources I1 to I4 connected to power supply X2_D, and the sources of the switching tubes D1 to D4 are connected to current source I'ref connected to power supply X2_D and grounded current source Iref0.

[0034] As a further explanation of the embodiment of the present invention, a charge-discharge constant current source circuit is also included. The charge-discharge constant current source circuit generates a current source I'ref by mirroring the current mirror.

[0035] The charge and discharge constant current source circuit includes: PMOS transistors P3-P4, NMOS transistors N2-N3, an operational amplifier OP, a temperature compensation resistor r, and a resistor RI; the source of the PMOS transistor P3 is connected to the power supply X2_D, the gate and drain of the PMOS transistor P3 are connected to the source of the PMOS transistor P4, the gate and drain of the PMOS transistor P4 are connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N2 is connected to the output end of the operational amplifier OP and the gate of the NMOS transistor N3, the source of the NMOS transistor N2 is connected to the source end of the NMOS transistor N3, one end of the temperature compensation resistor r, and the inverting input end of the operational amplifier OP, the non-inverting input end of the operational amplifier OP is connected to the reference voltage Vref, the other end of the temperature compensation resistor r is connected to the grounded resistor RI, and the drain of the NMOS transistor N3 is connected to the current source Iref connected to the power supply X2_D.

[0036] The gate and drain of the PMOS transistor P4 generate a current source Iref5 , the ratio of the current source Iref5 to the current source Iref is Iref5:Iref=1:14.85, and the resistor RI=56KΩ.

[0037] It also includes the following working principles: In the above-mentioned charge and discharge constant current source circuit, an external LDO circuit generates a current source Iref, where Iref = Vref / (RI+r). The current source Iref is copied by a current mirror to obtain a current source I'ref. Then, the current source I'ref is combined with the frequency jittering module to generate a current source Iref0. The current source Iref0 then passes through a current mirror to generate a charge and discharge current.

[0038] The oscillator circuit of the present invention includes the following two operating modes: Normal operating mode: PWM logic control signal X840_SNN is high, data selector MUX selects output signal X1225_Y as signal P872_G. If signal X41_YN is high, transmission gate is closed, current source Iref3 charges capacitor C2, and when signal X41_YN is low, transmission gate is opened, capacitor C2 is discharged until voltage across capacitor C2 is equal to voltage VP44_S. At this time, regardless of whether transmission gate is open or not, voltage VN1_G and voltage VP44_S are always greater than voltage VP45_S. Then the output of comparator COM3 is always high, that is, R input of RS trigger RS2 is always low. At this time, the output of RS trigger RS2 depends only on its S input. When the circuit is just powered on, the voltage VN4_G is at a low level, and the current source Iref1 starts to charge the capacitor C1. When the voltage VN4_G is less than the voltage VL, the output of the RS trigger RS1 is at a low level, and the S-terminal input of the RS trigger RS2 is at a high level. At this time, the RS trigger RS2 outputs a low level.

[0039] When the voltage VL<VN4_G<VH, the RS trigger RS1 outputs a low level, then the S-terminal input of the RS trigger RS2 is a high level, and at this time the RS trigger RS2 outputs a low level, and this state will be maintained until the voltage VN4_G=VH; when the voltage VN4_G>VH, the RS trigger RS1 outputs a high level, then the S-terminal input of the RS trigger RS2 is a low level, and at this time the RS trigger RS2 outputs a high level; and this cycle repeats.

[0040] Hiccup mode: The primary power loss in a switching power supply controller at light or no load comes from switching losses, which are proportional to the PWM frequency. To meet green mode requirements, the chip achieves this by reducing the switching frequency or intermittently switching on and off.

[0041] In this state, the PWM logic control signal X840_SNN is low, and the data selector MUX selects the output signal X1225_Y as signal R720_MINUS. The discharge process in hiccup mode is the same as in normal operation. However, when voltage VN4_G drops below voltage VL, current source Iref1 does not immediately begin charging capacitor C1. Instead, it waits until capacitor C2 is charged to voltage VN1_G > VP45_S, comparator COM3 outputs a high level, and the R input of RS flip-flop RS2 is low. Only then does current source Iref1 begin charging capacitor C1.

[0042] To better achieve EMI characteristics, a frequency dithering function is set inside the chip to make the actual PWM frequency dither within the set value range. The four control signals X1_Q to X4_Q from the external divider control the shutdown of the switches D1 to D4, thereby periodically changing the charge and discharge current.

[0043] In summary, the present invention designs an oscillator module composed of a feedback loop and a current detection circuit to detect the load current / voltage in real time and dynamically adjust the PWM frequency, and cooperates with the frequency jitter module and the hiccup module to reduce electromagnetic interference EMI and improve system efficiency; by adopting a high-precision (Iref5: Iref=1:14.85) temperature-compensated current mirror charge and discharge constant current source circuit, it has the function of supporting a wide range of current regulation such as 1μA~1mA and a temperature drift accuracy within ±1%.

[0044] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An oscillator circuit for a PWM controller, characterized in that: include: An oscillator module includes a feedback loop and a current detection circuit; the input end of the feedback loop inputs the inverted signal X41_YN output by the output end of the current detection circuit; the output end of the feedback loop outputs a signal N4_G to the input end of the current detection circuit, compares the signal with the voltage signal VH and the voltage signal VL, and outputs a signal X42_YN, which is then inverted and output as the signal X41_YN; The hiccup module, according to the level of the input PWM logic control signal X840_SNN, the data selector selects and outputs its input signal to control the on and off of the transmission gate, and establishes the charging and discharging process, providing a delayed start function for the oscillator module; The frequency jittering module outputs a current source Iref0 of different magnitudes by combining and selecting the current source I'ref and the current sources I1 to I4, and then outputs four current sources Iref1 to Iref4 of different magnitudes through a current mirror array, thereby providing charge and discharge currents for the oscillator module and the hiccup module. When the PWM logic control signal X840_SNN is low, the data selector MUX selects the output signal X1225_Y as signal R720_MINUS, and the operating mode enters hiccup mode. The discharge process in hiccup mode is the same as that in normal operating mode. When the voltage VN4_G drops below the voltage VL, the current source Iref1 does not immediately start charging the capacitor C1. Instead, it waits until the capacitor C2 is charged to a voltage VN1_G greater than the voltage VP45_S. When the comparator COM3 outputs a high level and the R-terminal input of the RS trigger RS2 is low, the current source Iref1 begins to charge the capacitor C1.

2. An oscillator circuit for a PWM controller according to claim 1, characterized in that: The feedback loop includes: an inverter INV1, a PMOS transistor P1, an NMOS transistor N1 and a capacitor C1; the input end of the inverter INV1 inputs a signal X42_YN, and the output end of the inverter INV1 outputs a signal X41_YN to the gates of the PMOS transistor P1 and the NMOS transistor N1. The PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and the grounded capacitor C1, and outputs a signal N4_G as an output end. The source of the PMOS transistor P1 is connected to a current source Iref1 connected to a power supply X2_D, and the source of the NMOS transistor N1 is connected to a grounded current source Iref2.

3. The oscillator circuit for a PWM controller according to claim 1, wherein: The current detection circuit includes: comparators COM1~COM2, inverters INV2~INV6 and RS triggers RS1~RS2; the non-inverting input terminals of the comparators COM1~COM2 are input with signal N4_G, the inverting input terminals of the comparators COM1~COM2 are respectively input with voltage signals VH and VL, the output terminal of the comparator COM1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the S terminal of the RS trigger RS1, the output terminal of the comparator COM2 is sequentially connected in series with inverters INV3~INV4, the output terminal of the inverter INV4 is connected to the D terminal of the RS trigger RS1, an inverter INV5 is connected in series between the Q terminal of the RS trigger RS1 and the S terminal of the RS trigger RS2, the Q terminal of the RS trigger RS2 is connected to the input terminal of the inverter INV6, and the output terminal of the inverter INV6 outputs the signal X42_YN.

4. An oscillator circuit for a PWM controller according to claim 3, characterized in that: The hiccup module includes: a data selector MUX, a PMOS tube P2, a transmission gate, a capacitor C2, a comparator COM3 and an inverter INV7; the control end of the data selector MUX is connected to the PWM logic control signal X840_SNN, the two input ends of the data selector MUX are respectively connected to the signal R734_MINUS and the signal P872_G, the output end of the data selector MUX is connected to the gate of the PMOS tube P2, the source of the PMOS tube P2 is connected to the current source Iref4 connected to the power supply X2_D and the input end of the transmission gate, the drain of the PMOS tube P2 is grounded, and the two control ends of the transmission gate are respectively connected to the signal X41_YN and the signal The output end of the transmission gate is connected to the current source Iref3 connected to the power supply X2_D, the grounded capacitor C2 and the non-inverting input end of the comparator COM3, the inverting input end of the comparator COM3 is connected to the signal P45_S, the output end of the comparator COM3 is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is connected to the R end of the RS trigger RS2.

5. An oscillator circuit for a PWM controller according to claim 4, characterized in that: The transmission gate is composed of a parallel complementary PMOS transistor and NMOS transistor pair.

6. The oscillator circuit for a PWM controller according to claim 1, wherein: The frequency jittering module includes: switching tubes D1 to D4; the gates of the switching tubes D1 to D4 are sequentially connected to control signals X1_Q to X4_Q, the drains of the switching tubes D1 to D4 are sequentially connected to current sources I1 to I4 connected to power supply X2_D, and the sources of the switching tubes D1 to D4 are connected to current source I'ref connected to power supply X2_D and grounded current source Iref0.

7. An oscillator circuit for a PWM controller according to claim 6, characterized in that: The ratio relationship of the current sources I1 to I4 is I1:I2:I3:I4=8:4:2:

1.

8. The oscillator circuit for a PWM controller according to claim 1, wherein: It also includes a charge and discharge constant current source circuit, which generates a current source I'ref through current mirror replication.

9. The oscillator circuit for a PWM controller according to claim 8, wherein: The charge and discharge constant current source circuit includes: PMOS transistors P3-P4, NMOS transistors N2-N3, an operational amplifier OP, a temperature compensation resistor r, and a resistor RI; the source of the PMOS transistor P3 is connected to the power supply X2_D, the gate and drain of the PMOS transistor P3 are connected to the source of the PMOS transistor P4, the gate and drain of the PMOS transistor P4 are connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N2 is connected to the output end of the operational amplifier OP and the gate of the NMOS transistor N3, the source of the NMOS transistor N2 is connected to the source end of the NMOS transistor N3, one end of the temperature compensation resistor r, and the inverting input end of the operational amplifier OP, the non-inverting input end of the operational amplifier OP is connected to the reference voltage Vref, the other end of the temperature compensation resistor r is connected to the grounded resistor RI, and the drain of the NMOS transistor N3 is connected to the current source Iref connected to the power supply X2_D.

10. The oscillator circuit for a PWM controller according to claim 9, wherein: The gate and drain of the PMOS transistor P4 generate a current source Iref5 , the ratio of the current source Iref5 to the current source Iref is Iref5:Iref=1:14.85, and the resistor RI=56KΩ.

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