Quantum processing device and method

Abstract

The invention provides a quantum processing apparatus, the apparatus comprising at least one array of bilinear quantum dots, each array configured to accommodate a plurality of spin qubits. The apparatus further includes a controller configured to control coherent transmission of one or more of the plurality of qubits within each array to implement a quantum error correction code (QECC), where the QECC encodes a set state of the spin qubits of the respective array as corresponding first level (L1) logical qubits.

Description

[0001] This application claims priority to Australian Provisional Patent Application No. 2022904005 filed on December 23, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a quantum processing device and a method for operating a quantum processing device to achieve fault-tolerant computing through quantum error correction that is scalable and achievable in current quantum technology. Background Art

[0003] Realizing a large-scale quantum computer capable of executing groundbreaking algorithms remains a daunting task because its building blocks, qubits, are susceptible to errors caused by effects such as decoherence and noise. Quantum error correction is used in quantum computing to protect quantum information from errors and is considered essential for achieving fault-tolerant quantum computing.

[0004] Quantum error correction operates by representing the quantum information associated with a high-quality logical qubit as an entangled state of multiple physical qubits. Thus, the state of a physical qubit can be encoded in the state of a logical qubit. If the logical qubit is encoded according to a quantum error correction code (QECC), the state of the logical qubit can be protected from errors in one or more of the physical qubits.

[0005] Similar to classical error correction, although QECC does not always correctly decode logical qubits, its use reduces the impact of noise, thereby improving the practicality of quantum processing devices. The large number of high-fidelity qubits required for error correction has long been beyond experimental capabilities. As we enter the era of quantum computing, characterized by the ability to control noisy qubits, the implementation of quantum error correction is becoming practical. Therefore, there is a need for error correction techniques that utilize a small number of qubits and also consider the constraints of realistic and manufacturable architectures.

[0006] Any discussion of documents, acts, materials, devices, articles of manufacture or the like included in this specification is solely for the purpose of providing a context for the present invention and is not to be taken as an admission that any or all of these matters formed part of the prior art base or were common general knowledge in the field relevant to the present invention as they existed before the priority date of each claim of this application.

[0007] Throughout this specification, the word "comprise" or variations such as "comprises" or "comprising" will be understood to imply the inclusion of a stated element, integer or step or group of elements, integers or steps, but not the exclusion of any other element, integer or step or group of elements, integers or steps. Summary of the Invention

[0008] A quantum processing device is provided, comprising: at least one bilinear quantum dot array, each array being configured to accommodate a plurality of spin qubits; and a controller configured to control coherent transmission of one or more qubits from the plurality of qubits within each array to implement a quantum error correction code (QECC), wherein the QECC encodes the collective state of the spin qubits of the corresponding array into corresponding first-level (L1) logical qubits.

[0009] In some embodiments, each bilinear array comprises: a first row of N quantum dots, wherein the first row of N quantum dots is configured to accommodate up to N spin qubits; and a second row of N quantum dots, wherein the second row of N quantum dots is configured to enable entanglement operations to be performed between corresponding qubits through the coherent transmission.

[0010] In some embodiments, the spin qubits are accommodated in the first row of the array according to an arrangement selected to facilitate the coherent transmission of the one or more spin qubits in the plurality of spin qubits to perform error correction according to the QECC.

[0011] In some embodiments, the apparatus is configured to perform a cycle of error correction on the L1 logical qubits of any one of the at least one bilinear arrays by: (i) initializing one or more ancillary qubits of the QECC in the array according to the arrangement; (ii) executing one or more two-qubit entanglement gates, each gate entangling one or more pairs of spin qubits of the QECC; and (iii) measuring the ancillary qubits.

[0012] In some embodiments, the entangled qubits of the QECC include a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

[0013] In some embodiments, the apparatus is configured to entangle two spin qubits in the array by coherently transmitting a selected spin qubit of a spin qubit pair from the first row of the array through the second row of the array; aligning the selected spin qubit with the other spin qubit; performing a two-qubit gate; and then coherently transmitting at least the selected spin qubit back to the first row of the array.

[0014] In some embodiments, the apparatus is configured to entangle two spin qubits in the array by causing a direct local interaction between the qubits if the qubits to be entangled are already located in adjacent spots.

[0015] In some embodiments, the one or more two-qubit entanglement gates are scheduled according to the QECC and the geometry of the bilinear array.

[0016] In some embodiments, the arrangement of the qubits in the first row of the array is determined to minimize a depth of the syndrome extraction circuit.

[0017] In some embodiments, each bilinear array is composed of silicon metal oxide semiconductor (SiMOS) quantum dots.

[0018] In some embodiments, the QECC is a surface code.

[0019] Also provided is a method for implementing quantum error correction on a quantum processing device, the method comprising: (i) arranging a plurality of spin qubits in a bilinear quantum dot array of the quantum processing device according to a quantum error correction code (QECC), wherein a collective state of a subset of the spin qubits forms a first level (L1) logical qubit protected by the QECC; (ii) determining a sequence of one or more entanglement operations for respective pairs of the plurality of spin qubits; and (iii) executing a syndrome extraction circuit to determine a syndrome of the QECC for performing an error correction cycle by performing the sequence of entanglement operations, wherein performing the sequence of entanglement operations involves coherently transmitting one or more spin qubits from the plurality of spin qubits within the array.

[0020] In some embodiments, the arrangement of the plurality of spin qubits in the first row is selected to facilitate the coherent transmission of the one or more spin qubits in the plurality of spin qubits to perform error correction according to the QECC.

[0021] In some embodiments, executing the syndrome extraction circuit comprises: (i) initializing one or more auxiliary qubits of the QECC in the array according to the arrangement; (ii) performing the determined sequence of entanglement operations, each entanglement operation entangling a pair of spin qubits of the QECC; and (iii) measuring the auxiliary qubits.

[0022] In some embodiments, each entangled qubit pair comprises a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

[0023] In some embodiments, entangling a spin qubit pair of the QECC comprises: coherently transmitting a selected spin qubit of the spin qubit pair from the first row of the array through the second row of the array; aligning the selected spin qubit with the other spin qubit of the pair; performing a two-qubit gate; and then coherently transmitting at least the selected spin qubit back to the first row of the array.

[0024] In some embodiments, entangling a pair of spin qubits comprises causing a direct local interaction between the qubits without coherently transmitting either of the qubits if the qubits to be entangled are already located in adjacent spots.

[0025] In some embodiments, the sequence of disentanglement operations of the syndrome extraction circuit is determined based on the geometry of the QECC and the bilinear array.

[0026] In some embodiments, the arrangement of the qubits in the first row of the array is determined to minimize a depth of the syndrome extraction circuit.

[0027] In some embodiments, the method for implementing quantum error correction on a quantum processing device further comprises: (iv) decoding the syndrome to obtain an output recovery operator; and (v) applying the recovery operator to the QECC of the array.

[0028] In some embodiments, steps (iv) and (v) are performed by a classical processing device in response to transferring the syndrome from the quantum processing device to the classical processing device.

[0029] In some embodiments, the device comprises a plurality of bilinear quantum dot arrays, and wherein the controller is further configured to: selectively couple a first L1 logical qubit of a first bilinear array with a second L1 logical qubit of a second bilinear array via a coherent coupling mechanism, wherein the coupling occurs by transferring information encoded by the first L1 qubit to the second L1 qubit based on a long-range interaction; and perform one or more fault-tolerant quantum processing operations on the L1 logical qubits of the plurality of bilinear arrays.

[0030] In some embodiments, the coherent coupling mechanism includes a quantum transport structure configured to connect the plurality of bilinear arrays to enable the controller to selectively couple the first L1 logical qubit with the second L1 logical qubit by coherently transferring one or more spin qubits between the first bilinear array and a second bilinear array connected to the first array.

[0031] In some embodiments, the quantum transport structure comprises one or more quantum dot shuttle arrays, each of which is disposed between a pair of connected bilinear arrays.

[0032] In some embodiments, the controller is further configured to couple the first L1 logical qubit and the second L1 logical qubit by creating an entanglement operation between one or more of the spin qubits in each array of the pair by: transferring the spin qubits from one array in the pair to the other array in the pair; and performing one or more entanglement operations between the transferred spin qubits.

[0033] In some embodiments, the controller is further configured to perform a fault-tolerant CNOT gate between a control array in the plurality of bilinear arrays and a target array in the plurality of bilinear arrays by: coherently transferring the spin qubits from the control array to the target array through the quantum transport structure; performing a nearest-neighbor CNOT gate between pairs of one or more of the data qubits of the QECC; coherently transferring the spin qubits from the target array back to the control array; and performing an error correction cycle on each of the control array and the target array.

[0034] In some embodiments, the controller is further configured to apply a second-level QECC to encode a collective state of the set of L1 logical qubits into corresponding second-level (L2) logical qubits.

[0035] In some embodiments, the distance of the second-level QECC can be arbitrarily scaled as the number M of the bilinear arrays of the device is greater than 1.

[0036] Also provided is a quantum processing device comprising: a plurality of bilinear quantum dot arrays, each array being configured to accommodate a plurality of spin qubits of up to N spin qubits; a controller configured to: control coherent transmission of one or more qubits of the plurality of qubits within each array to implement a first-level QECC, thereby encoding the collective state of the spin qubits of the array into corresponding first-level (L1) logical qubits; and selectively couple one or more L1 logical qubit pairs of the plurality of bilinear arrays through a coherent coupling mechanism to implement a second-level QECC. , thereby encoding the collective state of a set of M>1 of the L1 logical qubits into corresponding second-level (L2) logical qubits, wherein for each pair, the coupling is performed by transferring information encoded by the first L1 qubit in the pair to the second L1 qubit in the pair based on long-range interaction, so that the first-level QECC reduces the error rate of the spin qubit to the lower error rate of the L1 logical qubit, and the second-level QECC further reduces the lower error rate of the L1 logical qubit to the further lower error rate of the L2 logical qubit.

[0037] In some embodiments, the coherent coupling mechanism comprises a quantum transport structure configured to connect the plurality of bilinear arrays to enable the controller to selectively couple the one or more L1 logic qubit pairs by, for each pair, coherently transferring one or more spin qubits between a first array in the pair and a second array in the pair connected to the first array.

[0038] In some embodiments, the controller is further configured to perform a set of fault-tolerant quantum processing operations using one or more L2 logical qubits of the device.

[0039] Also provided is a method for performing a fault-tolerant quantum processing operation, the method being performed by the quantum processing apparatus described herein, the method comprising: determining at least two connected bilinear arrays to perform a quantum processing operation; selecting one or more pairs of the determined connected bilinear arrays, and for each selected pair comprising a first array and a second array: (i) coherently transferring at least a subset of the spin qubits from the first array to the second array; (ii) performing a separate entanglement operation between the spin qubits within the second array; (iii) reversing the coherent transferring of step (i); and (iv) performing an error correction cycle on each of the first array and the second array, wherein the error correction cycle is implemented by any one of the methods described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Some embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0041] Figure 1A is a schematic diagram of a quantum processor according to some embodiments;

[0042] Figure 1B yes Figure 1A Schematic diagram of the bilinear quantum dot array of the first quantum processor in [1].

[0043] Figure 1C is a schematic diagram of a portion of a quantum processor having a plurality of bilinear arrays coupled via a coherent coupling mechanism according to some embodiments;

[0044] Figure 1D yes Figure 1C An illustration of an exemplary layout of a quantum processor;

[0045] Figure 1E It is used to control Figure 1C Illustration of how the quantum bits of a bilinear array of quantum processors are controlled;

[0046] Figure 1F is Figure 1C Illustration of how qubits are coherently transferred between a pair of bilinear arrays of a quantum processor;

[0047] Figure 2A is a cross-sectional view of a schematic circuit diagram of a qubit device for realizing spin qubit shuttling;

[0048] Figure 2B is the stability diagram for charge transfer for spin qubit shuttling;

[0049] Figure 3A is a flow chart of a method for implementing quantum error correction on a quantum processing device according to some embodiments;

[0050] Figure 3B is a flow chart of a method for implementing a syndrome extraction circuit according to some embodiments;

[0051] Figure 4A is Figure 1A -Schematic diagram of the implementation of Surface-17 code on a bilinear array of D processors;

[0052] Figure 4B is Figure 1A -Schematic diagram of the stabilizer of the Surface-17 code implemented on a dual linear array of D processors;

[0053] Figure 5 is a circuit diagram of a syndrome extraction circuit for Surface-17 code according to some embodiments;

[0054] Figure 6 is a schematic diagram of a multi-round quantum error correction cycle of the Surface-17 code according to some embodiments;

[0055] Figure 7A is a flow chart of a simulation model for evaluating quantum error correction performance in a 2×N quantum dot array according to some embodiments;

[0056] Figure 7B This is a circuit identity diagram showing a CNOT gate implemented by combining a CZ gate and two Hadamard gates.

[0057] Figure 7C is a circuit diagram illustrating Pauli error propagation in a CNOT gate according to an example gate configuration;

[0058] Figure 8 Is the basis of display Figure 7A A plot of the logical failure rate of a quantum error correction code for L1 logical qubits in a 2×N module with a shuttling error model.

[0059] Figure 9A and 9B This shows the logic used to initialize the corresponding state of the Surface-17 code. L AND Logic |+> L Circuit diagram of fault-tolerant logic coding circuit;

[0060] Figure 10A and 10B is a circuit diagram of a logical CNOT gate between two L1 qubits of coupled 2×N modules at the logical level and the physical level, respectively, according to some embodiments;

[0061] Figure 11is a flow chart of a method for coupling (entangling) two logical qubits encoded in two independent 2×N arrays, according to some embodiments;

[0062] Figure 12 is based on Figure 11 Schematic diagram of the coherent transmission of the underlying spin qubits during formation of a CNOT gate on an L1 logical qubit pair of the illustrated method; and

[0063] Figure 13 is to evaluate the logical |Φ in the lateral-based two-qubit gate + >Graph of prepared failure rates. DETAILED DESCRIPTION

[0064] Previous approaches to designing quantum processing architectures and corresponding devices typically utilize lattice-based structures to create and manipulate qubits. Quantum error correction can be achieved by forming logical qubits using QECC on portions of the lattice, such as square regions of predetermined size. Practical implementations of fault-tolerant quantum computing architectures benefit from processing qubits (i.e., qubits on which quantum operations are performed) with error rates down to ~10 -15 (See Delfosse[1]).

[0065] Reducing the error rate requires using codes with a larger number of qubits (i.e., increasing the code distance). However, as the distance between a given qubit and the edge of the structure increases, the difficulty of implementing quantum error correction increases (often nonlinearly). Practical limits on logical qubit error rates typically stem from the cost and layout difficulty of interconnects in conventional architectures. Therefore, designing a conventional lattice-based architecture that is suitable for high-distance QECC (required to achieve sufficiently low logical qubit error rates) and can be practically implemented using currently available manufacturing technologies is challenging.

[0066] Furthermore, the architecture suitable for implementing a practical fault-tolerant quantum computing architecture will depend on the physical platform of the device. In previous work, qubits based on neutral atoms have been transported across spatial structures (see Bluvstein [2]). However, neutral atom qubits differ significantly from qubits formed in other platforms, such as qubits that exploit the spin of charge carriers (i.e., electrons or holes) in a solid-state host (referred to as "spin qubits"). Therefore, the movement operations performed on the qubits of the respective platforms are fundamentally different. For example, neutral atoms are captured and moved using optical tweezers with lasers, while spin qubit transport relies on electric field control. Laser-based tweezers control of neutral atoms may experience scalability difficulties associated with resolution and optical aberrations. In contrast, gate-based electrically controlled spin qubits have strong scalability that is practically achievable based on the manufacturing capabilities of the metal oxide semiconductor (MOS) device industry.

[0067] In other approaches, error correction is performed on a 2D qubit lattice in a one-dimensional structure in which electrons are moved to symmetric points of an array of nanomagnets, for example for performing qubit operations based on exchange interactions (see Mohiyaddin [3]). It would be desirable to devise techniques that ameliorate these or one or more other disadvantages of the prior art or at least provide effective alternatives.

[0068] Overview

[0069] Disclosed herein are apparatus and methods for fault-tolerant quantum processing, in which high-quality logical qubits are encoded by applying quantum error correction to bilinear quantum dot arrays. In one aspect, the proposed architecture is based on a qubit module comprising a bilinear array configured to accommodate a plurality of physical spin qubits. A controller is configured to control the coherent transmission (referred to as "shuttling") of one or more spin qubits within each array. The quantum information stored in the spin qubits in the array collectively forms a first-level (L1) logical qubit, and the shuttling of qubits enables the implementation of QECC, such as surface codes, to protect the L1 logical qubits in the event of errors in the spin qubits.

[0070] The advantage of the proposed architecture is that it enables logical qubits of a quantum processing device to be formed by arranging physical qubits in a linear structure. The architecture provides scalability, that is, it is possible to perform calculations using a physical qubit arrangement that is easier to control and can actually achieve fan-out than a denser arrangement in a conventional surface code architecture (for example, an arrangement using square lattice qubits). In addition, the proposed architecture is naturally suitable for silicon-based spin qubits, which are realized by electrons in corresponding silicon metal oxide semiconductor (SiMOS) quantum dots. In this way, the design and manufacture of quantum devices can be realized using the realistic processes of modern transistor foundries.

[0071] In some embodiments, the bilinear array is organized into two rows of N quantum dots each (referred to as a "2xN array"), where the 2xN array is configured to accommodate up to N qubits. For example, this disclosure describes a 2xN array composed of SiMOS quantum dots, where the qubits are the respective spins of the electrons accommodated in the dots.

[0072] In a 2×N array, the corresponding arrangement of spin qubits is selectively configured to facilitate qubit (i.e., electron) shuttling for implementing QECC operations of L1 logical qubits. The spin qubits are accommodated in the first row of the array according to the arrangement, thereby enabling initialization, quantum computation, and readout of the QECC qubits. The second row of the array enables entanglement operations to be performed between arbitrary spin qubits through shuttling (also referred to as the "shuttle row" of the array).

[0073] In the present disclosure, L1 logical qubits are encoded by a QECC in the form of a low-distance ("small") surface code, such as Surface-17. The arrangement of the qubits in the first row of the 2×N array minimizes the depth of the corresponding syndrome extraction circuit of the code (which is scheduled for the array). Optimization techniques are applied to determine an arrangement that facilitates the shuttling of one or more spin qubits among a plurality of spin qubits in the array (e.g., by minimizing the errors associated with the shuttling). For example, one or more numerical tools based on simulated annealing and the Metropolisal algorithm can be applied to determine the arrangement. Simulation results show that a complete cycle of the Surface-17 code can be scheduled to the 2×N array using a total of 8 steps (circuit depth of 8), which is only 2 rounds more than the optimal depth of 6 when the qubits are arranged in a square lattice.

[0074] In another aspect, the proposed architecture includes multiple bilinear arrays. A controller is configured to control the shuttling of multiple qubits within each array (i.e., implement QECC encoding L1 logical qubits) and selectively couple corresponding pairs of first L1 logical qubits of a first bilinear array with second L1 logical qubits of a second bilinear array. L1 logical qubit coupling can also be achieved through other coupling mechanisms based on transferring information encoded by the first L1 qubit to the second L1 qubit via long-range interactions. Thus, second-level (L2) logical qubits can be constructed by controlling and coupling L1 logical qubits.

[0075] An exemplary coupling mechanism includes a quantum transport structure that connects the arrays such that coupling of L1 logical qubits is induced by coherent transmission of one or more spin qubits between a plurality of corresponding interconnected arrays. In one example, each array in the architecture is connected to at least one other array via an independent quantum dot shuttle array. In this way, the underlying spin qubits can be shuttled between interconnected 2×N array pairs. In other examples, the coupling mechanism can include quantum transport arrays having alternative physical configurations, such as patches or buses formed of quantum dots, and / or one or more other coupling devices (e.g., superconducting couplers).

[0076] The controller performs fault-tolerant quantum processing operations on a collection of L1 logical qubits in a plurality of bilinear arrays. The ability to perform a universal set of arbitrary quantum operations on L1 logical qubits enables these logical qubits to be used as underlying qubits, further enabling the application of error correction methods.

[0077] In one embodiment, a first QECC is applied to each 2×N array, thereby reducing the error rate of the spin qubits (e.g., ˜10 -4 ) to a lower error rate corresponding to the L1 logical qubit. For example, evaluation of logical CNOT gates shows that the error rate of achieving L1 logical qubits is ~10 -5 Then, a second QECC is applied to encode the collective state of the L1 logical qubit set into corresponding L2 logical qubits. The L2 logical qubits have an error rate that is further reduced relative to the lower error rate of the L1 logical qubits (e.g., close to the expected value of 10 -15 ).

[0078] For example, by selecting a set of L1 logical qubits M > 1, the distance of the second-level encoding can be extended to achieve arbitrarily well-protected (L2 logical) qubits. Thus, forming L2 logical qubits according to the proposed architecture provides a solution to the lack of scalability of a single 2×N array for achieving improved quantum error correction. By increasing the number of L1 qubits M, the total number of qubits used for error correction can be increased while maintaining a fixed size N of the underlying bilinear array.

[0079] At least in this way, the proposed architecture advantageously facilitates the implementation of fault-tolerant quantum processing by enabling a scalable, practical, and universal error correction method across two levels of logical qubits.

[0080] quantum processor

[0081] Figure 1A A quantum processor 100 is shown, comprising at least one bilinear array, such as a plurality of arrays 102a and 102b. Qubits 101 (solid) are spin qubits implemented within corresponding quantum dots 103 (solid and hollow circles) of arrays 102a and 102b. The qubits of processor 100 are digital qubits, meaning each qubit represents information in digital form, such as electron or nuclear spin, or superconducting qubits using a Josephson junction. The digital qubits in each array 102a and 102b can have a specific functional role, such as a data qubit or an auxiliary qubit for the QECC implemented by processor 100.

[0082] Quantum processor 100 also includes a controller 110 configured to control the coherent transmission (referred to as "shuttling") of one or more of the qubits contained within each of arrays 102a, 102b. Controller 110 controls the shuttling to implement a QECC on at least one of arrays 102a, 102b, encoding the collective state of the spin qubits in the corresponding array into corresponding first-level (L1) logical qubits. In this sense, controller 110 applies a first error correction method, namely, forming a QECC on each of arrays 102a, 102b and generating L1 qubits. In some embodiments, the QECC is a surface code that reduces the error rate of the physical spin qubits to the relatively low error rate of each L1 logical qubit in the corresponding array 102a, 102b.

[0083] Each array 102a, 102b is configured to accommodate multiple qubits within a corresponding quantum dot 103. That is, at any given moment, each quantum dot 103 may or may not accommodate a qubit. The array's "accommodation" of each qubit refers to the localization of the physical qubit (e.g., electron) at a location (or "address") within the array. For example, qubit 101 may be implemented as the spin state of an electron accommodated by quantum dot 103.

[0084] Figure 1B Demonstrates the implementation of Figure 1A 1 . An exemplary bilinear array 102 of arrays 102a, 102b in an exemplary processor 100 in FIG. In other examples, the processor 100 can be configured with a single array or with any arbitrary positive real number of arrays. The arrays 102 are configured into two rows, each with N quantum dots, collectively referred to as "2×N" arrays. Each individual 2×N array 102 is configured with a first (bottom) row 105 for accommodating up to N spin qubits 101, and a second (top) row 107 for enabling the shuttling of spin qubits 101 within the array 102. That is, in such embodiments, the shuttling of spin qubits occurs between the first and second rows of the bilinear array 102. In other embodiments, the shuttling row can be implemented as the first (bottom) row, with the qubits accommodated in the second (top) row. In the illustration, the quantum dots 103 accommodating spin qubits 103b are depicted as shaded rounded squares, while the empty quantum dots 103a are depicted as unfilled rounded squares.

[0085] In the depicted embodiment, the 2×N array 102 comprises a collection of SiMOS quantum dots. In one embodiment, the electron spin in each SiMOS quantum dot is confined at the interface between the silicon and SiO2 in the quantum dot. SiMOS quantum dots offer advantages for quantum computing, including long coherence times, the ability to be controlled to perform quantum logic operations, and scalability. As discussed below, SiMOS quantum dots also enable long-range qubit interactions through qubit shuttling.

[0086] Figure 1A and 1B The geometry of the 2×N array 102 is shown in a two-dimensional abstract form (i.e., a simple double row). It will be apparent that in an actual implementation of the processor 100, the array is manufactured according to a three-dimensional layout and a specific fan-out. For example, in one embodiment, the gates may be densely packed along a one-dimensional channel array supporting electrostatic quantum dots, but may be contacted by a three-dimensional metal layer with a predetermined spacing between interconnects. Furthermore, the controller 110 may be configured with respect to the multiple arrays according to any one or more possible layouts, including layouts that physically divide the controller 110 into two or more sub-controllers, or portions of the readout and / or control electronic circuitry that each control a predetermined group of arrays from the multiple arrays (while operating collectively as a single logical controller of the processor).

[0087] Coherent transmission of spin qubits

[0088] In isotopically enriched silicon, high-fidelity coherent transfer of electron spin qubits between quantum dots (known as “shuttling” of spin qubits) has been demonstrated (see Yoneda [4]). In a double quantum dot system, a single electron spin can be coherently transferred between a pair of metal oxide semiconductor (MOS) quantum dots.

[0089] Figure 2A A schematic cross-sectional view of a quantum bit device circuit 200 configured to achieve coherent spin transfer between corresponding quantum dot sites in Yoneda [4] is shown. A single electron is loaded into quantum dot site A and manipulated by gate voltage pulses applied to aluminum metal gates A and B. The single electron moves between sites A and B by biasing the voltage applied to the surface gate electrodes.

[0090] The gate voltage is swept along the detuning axis ε, which changes the energy difference between the states localized in the respective sites. Figure 2BThe stability diagram 210 of charge transfer in Yoneda [4] is shown. The charge configuration in the dot array is mapped by the SET current, and within the plotted region, there are two charge transition lines at sites A and one at sites B. The arrows define the gate voltage axis ε for qubit transfer. As ε increases, the site where the electron is located changes from A to B. Interdot transitions (ε = 0) are marked by circles. Spin initialization and readout are performed at the diamonds using spin-selective tunneling from site A to the reservoir combined with charge probing.

[0091] Spin polarization can be transferred between sites with high fidelity. By increasing the tunneling coupling above the Zeeman energy (approximately 28 GHz), spin-flip tunneling from site A to B (e.g., spin-orbit fields generated by electron migration or small site differences in spin quantization) can be avoided. Large tunneling coupling also suppresses state leakage caused by non-adiabatic tunneling.

[0092] The evaluation results in Yoneda [4] show that the transfer process can be viewed as a unitary phase rotation gate with an average gate fidelity of (99.36 ± 0.05)%. In the two-point system evaluated, the physical mechanisms that are expected to limit the transfer fidelity in longer links are essentially present. Extrapolating the observed coherence loss p of about 2% for transfers between adjacent sites corresponds to a spin transfer across about 50 sites or a distance of about 2 μm (assuming a site spacing of 40 nm) before the phase coherence decays to 1 / e. If only spin polarization is required, for example for qubit readout, electrons can be transferred over 2500 sites (or about 100 μm) before the polarization decays to 1 / e in the spin-up state.

[0093] In addition, the results show that due to the spin-orbit interaction, the qubit frequency is best fitted with the small spin dependence in the inter-point tunneling coupling. In addition, a detuning point appears at about ε = -7mV, where the competition between the Stark shift and the tunneling hybridization makes the qubit frequency first-order insensitive to the detuning fluctuations caused by charge noise. Additional methods for coherent transmission of spin qubits are described in International Patent Publication No. PCT / AU2021 / 050869, the contents of which are incorporated herein by reference. Nevertheless, qubit shuttling can be completed in a few nanoseconds that are several orders of magnitude faster than the dephasing time of the qubit. This provides an advantage for facilitating coherent electron shuttling in a fault-tolerant quantum computing architecture utilizing a 2×N array as described herein.

[0094] Quantum error correction in a 2×N array

[0095] A quantum processing architecture based on linear arrays of electron spin qubits, such as those formed from silicon metal oxide semiconductor (SiMOS) quantum dots, advantageously has long coherence times and can therefore be controlled to perform desired quantum logic operations. The linear structure also facilitates the ability to utilize qubit shuttling (i.e., coherently transporting spin qubits within the array) for long-range qubit interactions and can be implemented using densely packed gate configurations.

[0096] However, implementing quantum error correction on these linear architectures is challenging due to the constraints imposed on qubit geometry. The present disclosure provides a method for correcting errors in quantum processing by applying the coherent qubit transfer operation discussed above to map QECC onto the restricted geometry of a 2×N array.

[0097] Error correction of first-level logical qubits

[0098] Figure 3A A method 300 for implementing quantum error correction on a quantum processing device, such as a quantum processor, according to the architecture described herein is shown. At step 302, a QECC is determined for each of one or more bilinear quantum dot arrays of the device, wherein each array is configured to accommodate a plurality of spin qubits. Each array is configured as a 2×N array having N spin qubits. The QECC is a surface code having a distance d, such as Surface-17 (see Tomita [5]).

[0099] At step 304, the spin qubits in each 2×N array of the device are arranged according to a QECC such that the collective state of a subset of the spin qubits forms a first level (L1) logical qubit protected by the QECC. At step 306, a sequence of one or more entanglement operations is determined for performing on corresponding pairs of the plurality of spin qubits in each 2×N array. The arrangement of the qubits and the determination of the entanglement sequence (also referred to as "scheduling") enable the implementation of the syndrome extraction circuit in the geometry of the 2×N array (or "module"), as performed at step 308. The sequence of entanglement operations involves coherently transmitting one or more spin qubits from the plurality of spin qubits in each 2×N array.

[0100] At step 310, the syndrome obtained from the execution extraction circuit is passed through a decoder, which outputs a recovery operator. This operator is then applied to the code, returning it to code space (i.e., at step 312). In some embodiments, the steps of method 300 are performed entirely by a quantum processing device. In other embodiments, at least the decoding 310 and recovery 312 steps are performed by a classical processing device. For example, the classical processing device can be configured to instruct the quantum processing device to generate the syndrome, and to perform the decoding and recovery in response to transmitting the generated syndrome from the quantum computing device to the classical processing device.

[0101] Various embodiments of the method for implementing quantum error correction 300 using L1 logical qubits in the quantum processor 100 will be described below.

[0102] Surface code

[0103] A surface code is a topological QECC implemented on a 2D planar qubit layout with nearest neighbor interactions. A surface code encodes a single logical qubit in a number of physical qubits determined by the encoding distance d and the desired layout. A first-level QECC is applied to encode the collective state of spin qubits 101 in a 2×N array 102 into corresponding first-level (L1) logical qubits. In one example, the QECC determined at step 302 is a surface code, such as a Surface-17 code. Surface-17 is a distance d=3 QECC that requires N=17 physical qubits, such as Figure 1A and 1B shown.

[0104] Figure 4A A 2D abstract form of a Surface-17 code implemented on array 102 is shown, where nine data qubits (labeled 0 through 8) store the encoded logical information and eight auxiliary qubits (labeled 9 through 16) perform the projection measurements required for error correction.

[0105] Surface-17 stores a logical qubit whose logical X(Z) operator can be controlled at the physical level by performing X(Z) Pauli operations on a column of Pauli X (a row of Pauli Z operations). For example, the operation Apply Pauli operations to logical qubits. Figure 4B Schematically showing an arrangement 400 of stabilizers of the Surface-17 code, where the stabilizers are defined as the tensor product of the Pauli X (Pauli Z) operators around the corresponding data qubits. Specifically, the stabilizer groups of weight 4 and weight 2 are defined as:

[0106]

[0107] The coded state of QECC is defined as the +1 eigenstate of the stable subgroup. forms a group under multiplication. For example, Also stable encoding state: Surface-17's logical qubits is encoded so that: For the coding error process, Among them E i ∈{X,Y,Z} is the Pauli error on the i-th physical qubit.

[0108] Information about the parity of the errors that occurred can be obtained by measuring the eigenvalues ​​of the stabilizer. An eigenvalue of -1 indicates that there are an odd number of parity errors acting on the support of the stabilizer, i.e., the stabilizer acts non-trivially on the qubit (e.g., for These will be qubits 0, 1, 3, and 4.) The X-type (Z-type) stabilizer detects the odd-order parity of the Z(X) error.

[0109] To illustrate this, let ε = Z0 (phase flip on qubit 0, identity operation on the remaining qubits). will return an eigenvalue of -1, because although qubit 0 is and The stabilizer is part of both, but it is anticommutative with the former and commutative with the latter (using XZ=-ZX):

[0110]

[0111] and

[0112] ε=Z0

[0113] It commutes trivially with every other stabilizer, since it does not overlap with its support (e.g., does not act non-trivially on the data qubit 0). Therefore, the syndrome of the encoding is the set of -1 stabilizer readings. For ε = Z0, the syndrome is

[0114] Performing quantum error correction in method 300 involves measuring the stabilizer of the QECC to obtain the syndrome. However, the data qubit cannot be measured directly on the stabilizer's support because this would decoherent the stored quantum information. Instead, the measurement result is projected onto an auxiliary qubit and then read out. The sequence of operations required to extract the encoded stabilizer information via the auxiliary qubit is called a syndrome extraction circuit (SEC).

[0115] Gate scheduling and qubit arrangement

[0116] To perform SEC, the operations of a surface code such as Surface-17 are mapped into a 2×N array. First, the qubits in the QECC are formed in the first row 107 of the array, e.g. Figure 4A The qubits of Surface-17 are arranged in the first row 107 of array 102, and the second row 105 remains empty to shuttle the qubits and execute arbitrary non-local two-qubit gates. Scheduling refers to determining the sequence in which gates are executed to couple the spin qubits through corresponding shuttle operations of array 102.

[0117] Ancillary qubits 108 are initialized by tunneling electrons from a reservoir of immediately adjacent quantum dots placed around array 102. Nearest-neighbor and shuttled two-qubit gates can be performed one by one, shuttling using a second row 105 as necessary.

[0118] Due to the geometrically constrained architecture of the 2×N array, some operations cannot be performed in parallel. For example, to implement the first two CNOT gates in SEC (e.g., Figure 5 The shuttle paths required for the CNOT|0>|10> and CNOT|11>|1> (used in the example SEC 500) intersect within the array and must therefore be executed one by one in rounds. The total number of rounds required to execute a circuit is called the circuit depth. The longer the circuit execution time, the longer the spin qubits are idle and exposed to undesirable environmental decoherence.

[0119] This leads to an accumulation of errors that destroy the scheme's error correction capabilities. In the standard layout of Surface-17's qubits ( Figure 4B 2D arrangement 400 shown in FIG), the depth of the circuit is 6. Figure 4A In the naive permutation of , the depth of the circuit is 26, which is the worst possible depth for a circuit (i.e., one in which every operation is performed serially).

[0120] In method 300, qubits are instead selectively arranged to facilitate shuttling of one or more spin qubits in a plurality of spin qubits when performing error correction according to QECC. That is, for the described example, the qubits in first row 107 of array 102 are rearranged from their initial placement in a manner that enables multiple two-qubit gates to be performed simultaneously without crossing shuttling paths (i.e., so that at least some entanglement gate operations can be performed in parallel during SEC).

[0121] In the described embodiment, an arrangement of qubits in first row 107 of array 102 is determined to minimize the depth of the SEC or provide an approximation of this minimum depth. The qubit arrangement that minimizes the circuit depth can be approximated using techniques from simulated annealing and the Metropolis sampling algorithm.

[0122] Let σ denote a certain qubit arrangement in the first row 107 of array 102, and define E(σ) as the objective (energy) function to be minimized over it. In this case, this is the depth of the circuit, E(σ) = circuit depth(σ). Pseudocode for an algorithm for approximating this minimum-depth qubit arrangement is given below.

[0123]

[0124]

[0125] At each step of the algorithm (line 3), by swapping two adjacent qubits A new qubit configuration is proposed. If the energy of the new configuration is lower than the energy of the current configuration, E(σ′) < E(σ), then the new configuration is immediately accepted. Otherwise, the new configuration is accepted with probability p, which is given by the ratio of the Boltzmann factors of each configuration:

[0126] The algorithm starts at high temperature T = T high Sampling begins at 0. This means that initially, it's reasonable to accept suboptimal solutions (i.e., higher-energy qubit arrangements). This prevents the algorithm from getting stuck in metastable local minima. As the temperature slowly decreases, the probability of accepting worse configurations also decreases. Eventually, the temperature approaches zero, and the algorithm converges to a near-optimal configuration that minimizes the energy function.

[0127] There may be more than one possible qubit arrangement that minimizes the circuit depth. In some embodiments, step 304 involves selecting the qubit arrangement used to perform syndrome extraction as the one with the fewest number of shuttled two-qubit gates, as these gates are expected to be the worst performing gates in the circuit. That is, once the desired arrangement is determined at step 304, the sequence of two-gate entanglement operations is determined at step 306.

[0128] Figure 6The desired qubit arrangement for Surface-17 is shown, obtained by minimizing the depth and the total number of subsequently shuttled two-qubit gates. In some embodiments, processor 100 already knows the desired (i.e., optimal or near-optimal) arrangement, so that step 304 involves laying out the qubits according to the desired arrangement. In some embodiments, the sequence of (two-gate or other) entangling operations is determined before or concurrently with determining the desired arrangement (i.e., by performing step 306 before or in conjunction with step 304).

[0129] Optimization of arrangement

[0130] For the Surface-17 code, simulated annealing is performed from Figure 4A The naive qubit configuration shown was started. The minimum circuit depth achieved was 8, which was 2 rounds away from the optimal depth. As discussed below, this depth is sufficient to achieve adequate error correction performance on 2×N modules.

[0131] Among all possible qubit configurations that minimize the circuit depth, the one with the fewest number of shuttled two-qubit gates is chosen, since these gates are expected to be the worst performing gates in the circuit. Figure 5 As shown, the optimal qubit arrangement for Surface-17 is obtained by minimizing the depth and the total number of subsequent shuttled two-qubit gates.

[0132] Syndrome extraction

[0133] At step 308, a coded syndrome is determined by performing SEC. Figure 5 An exemplary syndrome extraction circuit 500 for Surface-17 QECC is shown. Quantum error correction is implemented through a series of one or more cycles, where the total number of cycles is given by the permuted circuit depth. To complete a full quantum error correction cycle, the syndrome is extracted and then decoded to form the output recovery operator, projecting the qubit back into the encoding space.

[0134] In the depicted example, apparatus 100 is configured to perform an error correction cycle on a 2×N array of L1 logical qubits (represented by QECC): (i) initializing one or more ancillary qubits of the QECC in the array according to a permutation, as determined at step 304; (ii) executing one or more two-qubit entanglement gates, each gate entangling one or more pairs of spin qubits of the QECC, as determined at step 306; and (iii) measuring the ancillary qubits.

[0135] Figure 6The paper shows the rounds of the error-correction cycle of the Surface-17 code using the desired qubit arrangement, where each circuit operation is explicitly shown on a 2×N array. The total number of rounds, i.e., the circuit depth, is 8 (which is 2 short of the optimal depth achieved in an unconstrained 2D architecture). The initial and final rounds involve the preparation and measurement of the auxiliary qubit, respectively.

[0136] In the first round, auxiliary qubits 9 to 16 are initialized in the corresponding basis of the stabilizer they measure. For example, auxiliary 11 is initialized in the +1 eigenstate |+> of the X basis, because it will extract the X-type stabilizer The measurement results.

[0137] The intermediate rounds (2 to 7) involve entanglement operations between auxiliary and data qubits. That is, the entangled qubits contain a data qubit associated with a stabilizer of the QECC and one or more corresponding auxiliary qubits of the QECC. The horizontal double arrows represent nearest-neighbor two-qubit gates, and the arrows passing through the holes in the top row of the array represent shuttled two-qubit gates. Figure 3B , the rows indicate the qubit pairs to be entangled. That is, auxiliary qubit 11 is entangled with data qubits 0, 1, 3, and 4.

[0138] The final turn (8) of the circuit consists of reading out the state of the auxiliary qubit in the appropriate basis. For auxiliary qubit 11, this is a measurement performed in the basis X. The observed reading of the auxiliary qubit (±1) is assumed to correspond to the measurement result of the corresponding stabilizer.

[0139] Figure 3B The SEC for performing step 308 to achieve a particular QECC of C is shown once its constituent operations have been scheduled optimally in a 2×N array using the method of steps 304 and 306. 2×N (C) The general process of execution. For example, Figure 6 SEC of Surface-17 is shown 2×N (C), as discussed above. At step 322, a qubit pair is selected for entanglement, the entangled qubit pair comprising a data qubit associated with a stabilizer of the QECC and a corresponding ancillary qubit of the QECC. The qubit pair is selected based on the gate scheduling and permutation in steps 306 and 304.

[0140] The entanglement operation depends on the relative locality of the qubits in array 102. At step 323, a check is performed to determine whether the qubits are adjacent qubits. If so, the qubits to be entangled are already located in adjacent spots, and entanglement of the qubits involves inducing direct local interactions between the qubits without shuttling either qubit. Otherwise, at step 324, entangling the spin qubit pair includes shuttling a selected spin qubit of the spin qubit pair from the first row of the array through the second row of the array; aligning the selected spin qubit with the other spin qubit; performing a two-qubit gate; and then shuttling at least the selected spin qubit back to the first row of the array.

[0141] At step 328, the entanglement operation is completed and a two-qubit gate is formed between the spin qubits of the selected pair. Repeating the process for at least one non-adjacent pair of spin qubits results in coherent transmission of spin qubits within the array as a way to relay quantum information between distant locations in the array.

[0142] Decoding and recovery

[0143] refer to Figure 3A After the syndrome extraction process at step 308, decoding is performed at step 310 to convert the encoded syndrome SEC 2×N (C) Mapping to the restoration operator D:S→R. The restoration operator specifies the Pauli operator to be applied to the encoded physical qubits. where R i ∈{X,Y,Z}, and has two purposes: (1) returning the encoding to the encoding space (i.e., after application, each stabilizer returns a +1 reading); and (2) returning the encoding to the original logical subspace (i.e., avoiding Pauli error strings by choosing the minimum weight correction operator consistent with the observed syndrome).

[0144] Targeting Syndrome SEC 2×N (C) The determined recovery operator may vary depending on the decoding process. Possible recovery operators include Or Z3. Both return to the initial encoding state ( and because is a stabilizer, and +1 eigenspace belonging to all stable subspaces), and returns to the same initial logical subspace (with no residual error strings connecting opposite boundaries).

[0145] The decoder implementation is related to the number of QECC stabilizer generators. For example, Surface-17 has only 4 X-type stabilizers. and 4 Z-type stabilizers In addition, X and Z stabilizers can be treated separately, where the X(Z) stabilizer S x (S z ) marks an odd number of Z(X) errors on its support, from which we can obtain a recovery operator consisting entirely of Z(X) errors.

[0146] In one example, due to the small number of coded stabilizers, decoding is performed by explicitly specifying the decoder mapping D:S→R. That is, the decoder mapping associates a recovery operator with each possible observed syndrome X (top) and syndrome Z (bottom), as determined by the best correction operator found for each observed syndrome. This is called exact maximum likelihood decoding. For example, for the observed syndrome Perform a lookup operation on the decoder map to retrieve the recovery operator:

[0147]

[0148] At step 312, the recovery operator Z1X2 is applied to the encoding, thereby returning it to the encoding space. In some embodiments, the syndrome decoding operation is performed by a classical computational processor device (e.g., using binary data as +1 or -1) and using a classical algorithm. The classical processor can be configured to receive information (e.g., syndrome values) from the quantum processor 100 via an electrical connection (e.g., hard wiring). In such embodiments, the classical processor operates as a decoding device that communicates with the quantum processor 100 and related components. This has the advantage that decoding can be performed off-chip relative to the quantum processor 100 while still achieving sufficiently fast computations to avoid spin qubit decoherence. The above-described table-based decoder runs in constant time O(1) and is therefore practically implemented using current classical technology.

[0149] Fault-tolerant circuit extraction

[0150] If the error correction of the code at distance d is fault-tolerant, then a single error in any component in the circuit propagates at most Errors. Since the encoding of distance d tolerates at most Errors are introduced by the error-correcting circuits, so fault tolerance requires that errors introduced by the error-correcting circuits do not lead to uncorrectable errors. Non-fault-tolerant circuits have limited practical use because they only perform operations that can corrupt the logical qubits stored in the code. That is, performing actual quantum error correction involves dealing with errors introduced from the environment, as well as errors introduced from the gates used to design the correction protocol.

[0151] For the example code with distance d=3 described in this paper, the error tolerance requirement is that a single error event in the SEC results in at most one output error. Surface-17's original SEC was designed to tolerate single error events on any of the single-qubit and two-qubit gates in the circuit, as well as during initialization.

[0152] An example of an error that destroys a stored logical qubit is ε′=Z0Z1. This error only leads to the stable quantum Marks an odd number of errors around it For this observed syndrome, the minimum weight correction is Once Z2 is applied, the state returns to the encoding space, but now the encoding is left with a string of Z operators (Z0Z1Z2), which is equivalent to a logical phase flip Such errors cannot be detected by measuring the stabilizer (in fact, it is part of the code space, created by construction). This is an example of a logical error.

[0153] Fault tolerance is achieved by ordering the two-qubit entangled gates in a specific way. For Surface-17, Figure 5 The two-qubit gates in the depicted SEC 500 are ordered in a way that propagates single-qubit errors into two-qubit errors. This is an unavoidable property of two-qubit gates, but only one of the two propagated errors is aligned in the direction of the logical operator. Therefore, the effective number of output errors aligned in directions that could cause a logical failure is one, satisfying fault tolerance. Because the optimization of operations in the 2×N array schedules them in different rounds without changing their relative ordering, fault tolerance for both single-qubit and two-qubit gate errors is maintained when executing SEC in the 2×N array.

[0154] Tolerance to measurement errors requires the ability to detect if one of the auxiliary qubits is read incorrectly. For example, if the qubit reads -1 instead of the correct +1. As long as the intensity of the measurement error is low enough, the measurement error can be tolerated by repeating the stabilizer measurement. This repetition performed by the circuit is only performed if the initial SEC does not return the trivial syndrome (i.e., each stabilizer gives a +1 reading). and provides protection against measurement errors.

[0155] After taking into account error tolerance, the final output of SEC encoding is the syndrome of encoding, that is, the stable sublist of -1 measurement results:

[0156] Other quantum error correction codes

[0157] In other embodiments, quantum error correction is performed using a QECC other than Surface-17 coding. For example, processor 100 may apply a QECC such as Shor coding (e.g., Shor6X2Z and Shor6Z2X; see Debroy [6]), Bacon-Shor-13 coding (see Bacon [7]), or XZZX-17 surface code (see Bonilla Ataides [8]). All of these codes have a distance d=3 and require no more than 20 physical qubits to implement. The following provides the properties of the syndrome extraction circuit when the above QECC is implemented in a 2×N array:

[0158]

[0159] ‘Qubits’ is the total number of physical spin qubits required for each scheme, ‘Circuit depth’ is the depth of the syndrome extraction circuit when implemented in a bilinear array, ‘Two-qubit gates’ is the number of two-qubit gates used in the circuit, and ‘Shuttled’ is the number of shuttled two-qubit gates required in the circuit.

[0160] These coded SECs are fault-tolerant and require measurements on the auxiliary qubit only at the end of the error correction round. This reduces the need for spin qubit measurements, which are slow operations. In the described embodiments, the error correction circuit is predetermined and remains constant throughout the quantum error correction cycle. In some embodiments, the execution of different parts of the circuit is conditioned based on the measurement results of the marker qubit.

[0161] Error correction performance evaluation

[0162] In order to evaluate the failure rate of the L1 logical qubits stored in the 2×N array of the processor 100 according to the method 300 proposed above, a Monte Carlo simulation was performed. Figure 7A A simulation model 700 is presented for evaluating the error correction performance in a 2×N array of SiMOS quantum dots. First, a QECCC is selected and its syndrome extraction circuit is decomposed to optimally fit into the 2×N array (using the method described above). During each operation of the circuit, errors are modeled according to the externally injected error model ε.

[0163] Syndrome Extraction Circuit SEC 2×N(C) is repeatedly conditioned when the measurement result of the auxiliary qubit is non-trivial to account for measurement errors. The final output of the circuit is a syndrome S, which is passed through a decoder D to form a recovery operator R. The recovery operator is applied back to the encoding, and the recovered encoding state is checked to determine whether a logical failure (i.e., a failure on the stored logical qubit of the encoding) has been recorded. Various aspects of the evaluation are described below.

[0164] Error modeling

[0165] Error events are modeled during initialization, single-qubit gates, two-qubit gates, shuttling, measurement, and qubit idle. The following diagram shows the eigenoperations in the circuit used for syndrome extraction and the associated errors modeled for each.

[0166]

[0167] 'Operation' is the intrinsic operation used in the extracted circuit. 'Error rate' is the probability that an error occurs in this operation in any given round. These error rates are given as multiples of the two-qubit error rate p. 'Structure' is the type of error modeled after each operation, assuming an error occurs first.

[0168] 1. Two-qubit gates: CNOT and CZ

[0169] The CZ gate is intrinsic to the physical architecture and is directly implemented by regulating the exchange interaction. Figure 7B Circuit identity 710 is shown representing a CNOT gate implemented based on a combination of a CZ gate and two Hadamard gates.

[0170] Error correction circuits primarily use CNOT gates, and occasionally CZ gates. Since CNOT and CZ can be correlated via two Hadamard gates, which have a fidelity an order of magnitude higher than that of the two-qubit gate, their fidelity is comparable. Therefore, the universal two-qubit error rate is defined as p 2q :

[0171] p:=p CNOT ≈p CZ ~1% (1)

[0172] The main error after the CZ gate is ZZ. The appropriate error channel used in the simulation is:

[0173] ε CZ (ρ)=(1-p)Ⅱ+p(ZZρZZ)

[0174] CZ gate can be CZ ~0.1μs. Since the Hadamard gate takes t H~1μs, so the time required to execute a CNOT gate is dominated by the time required to execute a Hadamard gate: t CNOT ~2μs.

[0175] 2. Single-qubit gates

[0176] The discussion focuses on the Hadamard gate, H, because it is the single-qubit gate primarily used in circuits. The fidelity of this gate is about 10 times that of the two-qubit gate:

[0177]

[0178] For a single-qubit gate, a depolarized Pauli channel is used, where X, Y, and Z errors occur at the same rate:

[0179]

[0180] The time required to execute a single-qubit gate is t 1q ~1μs.

[0181] 3. Initialization and measurement

[0182] In the evaluation case, the fidelity of initialization and measurement is comparable because they are related processes and each is approximately equal to the fidelity of the two-qubit gate. Let the error rates of initialization and measurement be p i and p m :

[0183] p i =p m =p(3)

[0184] Both initialization and measurement are modeled as assignment errors. For example, for the preparation of the state |0> (respectively |+>), with probability p i The state |1> (respectively |->) is incorrectly prepared. Similarly, if the expected measurement result is +1 (respectively -1), then with probability p m The output measurement result is -1 (respectively +1).

[0185] Initialization is assumed to involve moving qubits in from a reservoir placed on the left side of the array, and measurement involves moving qubits out of the array to the right. Under this assumption, the effective time for initialization and measurement (i.e., the time that other qubits will be idle) will be equal to the total time required to shuttle qubits in and out of the array. For a code requiring N total qubits, this time will be:

[0186] t i =t m =(N+1)t d ~2ns=0.002μs

[0187] For the codes evaluated, N~20 is used, where t d ~0.1ns is the time required to travel between points. It is assumed that the actual measurement of the auxiliary qubit, which would take much longer, can be performed separately and does not need to be performed until the very end of the circuit.

[0188] In other examples, if knowledge of auxiliary measurement results may be required before continuing with the quantum error correction cycle (e.g., for tag-based error correction), the initialization time remains unchanged, but the measurement time will be t′ m ~100μs.

[0189] 4. Shuttle

[0190] The evaluation considers two possible models for traversing multiple points. In the first model, the main error comes from the one-time cost of moving the spin and is then largely independent of the number of points traversed. In the second model, the error accumulates exponentially after each point jump. Let f d is the fidelity of shuttling at a single point, then the error rates associated with moving at n points in the exponential shuttling model and the one-time cost model are:

[0191]

[0192] Based on the experimental results on the shuttle on a single (see Yoneda [4]), f d = 99.4%. For these, the number of shuttled points for any two-qubit gate is rarely greater than 6, and so this number is considered a conservative representation of the number of shuttled two-qubit gates in general. Then and Indicates shuttling within a single 2×N module:

[0193]

[0194] In either shuttling model, the shuttled qubit will primarily experience dephasing errors. The noise deviation is quantified by the coefficient:

[0195]

[0196] The coefficient indicates how much more frequently Z errors occur compared to X and Y errors. The bias coefficient associated with shuttling is η ~ 10. The Pauli error channel for describing errors during shuttling then becomes:

[0197] ε(ρ)=(1-p Shtl )I+p h.r. ZρZ+p 1.r. (XρX+YρY) (6)

[0198] where p h.r. =p Shtl η / (1+η) and p l.r. =p Shtl / 2(1+η), and hr and lr represent high rate and low rate, respectively.

[0199] The shuttle time of each point is t d = 0.1ns. The time it takes to shuttle a two-qubit gate through n points is equal to the shuttling time plus the time required to execute the two-qubit gate. Since shuttling is several orders of magnitude faster than the two-qubit gate, the time it takes to shuttle a two-qubit gate is mainly determined by the time it takes for the two-qubit gate to complete. 2q given.

[0200] 5. Idle

[0201] The fidelity of the idle qubits is modeled as decaying exponentially with a lifetime constant given by the computation time T2. Define p Idl (t) is the probability that an idle qubit will have an error during the time period t:

[0202]

[0203] T2 can be as long as 2 ms, which has been experimentally achieved by continuously and resonantly driving spin qubits with an external field (see Hansen [9]). Although T2 is expected to increase in the future, T2 = 2 ms is currently considered an estimate of what can be achieved using spin qubits.

[0204] Idle is assigned a universal error rate that is a multiple of the two-qubit error rate p. To be conservative, the idle error rate is extracted using syndrome during the longest round in the circuit. This is the round implementing the CNOT gate (the longest two-qubit gate used in the circuit), where time is given by t CNOT =~2μs. To first order, shuttling will not affect the time of the two-qubit gate because it is very fast (0.1ns per point) and shuttling rarely occurs over a distance of more than 6 points. Therefore, regardless of whether the two-qubit gate is shuttled or not, the longest round time is ~2μs, and the associated idle error rate is: p Idl (2μs)=1-e -2μs / 2000μs ~p / 10. This general expression is used to model the idle error on each qubit that does not undergo an operation during each round of extraction of the circuit:

[0205]

[0206] Idle noise is also dominated by dephasing. For the physical implementation of the spin qubit of the present invention, a suitable deviation coefficient is η=1000, where the error channel is the same as in equation (6).

[0207] Circuit noise simulation

[0208] The error model is used to simulate the noise in each operation (including idle period) of the error correction circuit. Follow the steps below to perform SEC using the error model. 2×N (C):

[0209] (i) performing circuit operations;

[0210] (ii) propagating the current error state through the operation (e.g., through a gate); and

[0211] (iii) A new error associated with this operation (as specified by the error model) is introduced and merged with the propagated error.

[0212] The way Pauli errors propagate through the gates of a circuit depends on the explicit quantum operations that the gates perform. Figure 7C The propagation of Pauli errors in a CNOT gate is shown according to an example gate configuration 720. The Pauli Y error can be decomposed into Pauli X error and Pauli Z error, and these can be propagated separately.

[0213] Understanding how errors are introduced and propagated in the syndrome extraction circuit completes the description of circuit noise simulation. These errors propagate to the encoded qubits, and the decoder (e.g., a lookup decoder as described above) finds the appropriate recovery operator based on the extracted syndrome. A check is performed to determine whether physical errors have accumulated to the point of corrupting the logical qubits stored in the encoding. An exemplary process for performing such a logical state diagnostic is described below.

[0214] Logic status diagnosis

[0215] After completing a round of quantum error correction, the logical state of the QECC is verified to determine the recovered state. Is it the same as the initial state Encodes the same logical information, or whether a logical error has occurred. Determines the error status of the encoding is a binary vector: e=(x1,...,x n |z1,...,z n ), where if there is an X(Z) error on qubit i, then x i (z i ) is equal to +1, or 0 otherwise.

[0216] For Surface-17, the total number of data qubits in the encoding is n = 9. The recovery operator R is applied to the error state of the encoding and the recovered state is obtained. The recovery operator is given in binary vector form as: in is the binary XOR corresponding to modulo 2 addition. The coded stabilizers can be represented in the same binary vector format and stacked row by row to form the matrix S M Similar expressions can be used to encode logical operators to form the matrix L M For the Surface-17, these become:

[0217] as well as

[0218]

[0219] Then, perform the operation:

[0220]

[0221] in is the matrix L M The transpose of , and ⊙ is called the binary symplectic product. The output is a binary 1×2 vector If the encoding state and logic Oppose Yi, then is equal to +1, and equal to 0 otherwise. and Against Yi, this means:

[0222]

[0223] For example, if there is logic in the coding fail The coding state and logic Oppose easy and output occurs (according to ), which correctly establishes the logic according to the above rules The existence of errors.

[0224] Performance Evaluation

[0225] The error correction performance of the five QECCs mentioned above is evaluated in a 2×N array, where each is applied to protect the L1 logical qubits stored in a 2×N module. The error model described above is applied, where each error source is expressed as a multiple of a single parameter p that quantifies the noise strength.

[0226] Simulation of the syndrome extraction circuit (denoted as SEC) in a 2×N array with QECC and the associated 2×N (C)) is input and produces an output '1' if the stored logical qubit fails, or an output '0' if it remains intact. mAfter performing F simulations and observing F logical failures, the logical failure rate P of the stored qubits is estimated. There is an uncertainty (standard deviation) σP in the estimate, as given by the Monte Carlo estimate:

[0227]

[0228] Roughly speaking, if the failure rate of the encoded logical qubits in a 2×N module is However, a more comprehensive performance metric for evaluating small coding performance is the pseudothreshold. The pseudothreshold is the physical failure rate p pth , when below the pseudo threshold, the failure rate of the encoded logical qubits Drops below the failure rate P of an uncoded bare physical qubit unenc. That is, for p<p pth ,have

[0229] Therefore, the pseudo threshold is p pth The error correction scheme will only work if the physical noise on the quantum bit is small enough (less than p pth ) is successfully protected (i.e., the error rate of the qubit is reduced from its current value). If the noise on the qubit is higher than p pth , then using QECC to encode qubits becomes detrimental rather than beneficial, causing qubit failure rates to be higher than in their bare (unencoded) form. Consequently, effective error correction typically exhibits a high false threshold, allowing it to protect a larger number of noisy qubits.

[0230] Figure 8 The performance of QECC for L1 logical qubits encoded in a 2×N module (i.e., logical failure rate) is shown using 5 different QECCs and a single error model for shuttling. The pseudo threshold corresponds to the failure rate of the encoded qubits divided by the failure rate of the bare physical qubits without encoding. The x-axis values ​​(i.e., physical failure rates) are the intersections between the red dashed lines. The five QECCs are numbered 0 to 4, as indicated in the legend. The inset shows the slope of the best-fit line for all logical failure curves. The slope is equal to 2, which is consistent with the present invention's understanding of fault tolerance and error correction capability of the code with a distance d=3. The error bars for all data points are smaller than the size of the markers used.

[0231] The intersection of the logistic failure curves and the dashed lines for different encodings represents the pseudo threshold p for each encoding. pth For physical error rate p<p pth, the logical failure rate of qubits encoded with this encoding drops below that of bare physical qubits without the encoding. The table below presents the exact values ​​of the pseudo threshold for the different encodings used and for each of the two evaluated shuttling error models (i.e., single-shot errors and exponential accumulation errors).

[0232]

[0233] Figure 8 The linear trend and parallelism of the lines observed in the can be explained as follows. Sampling at low p values ​​(p ∼ 10 -4 -10 -3 (See Figure 5 The x-axis value of )) and the errors introduced into the encoding in each round of simulation are very small. Therefore, the logical failure is actually due to the minimum weight misconfiguration that the underlying encoding cannot correct. Since the distance of all encodings is d=3, it can successfully correct all weights A single error event can still cause a logic failure in the extraction circuit by cascading into errors of higher weights. However, this is prevented because all circuits are fault-tolerant, meaning that a weight-1 error can propagate into errors of weight at most 1.

[0234] Therefore, the next most likely number of errors that can cause a failure is a double error event. Two errors in a row can cause a logic failure. Therefore, at low values ​​of p for sampling, the logic failure rate is dominated by errors of weight 2. Since each error has a probability of occurring p, the logic failure rate caused by these double error events is given by: exist In the log-log plot against p, all codes are straight lines with a slope of 2. Figure 8 The inset of Figure 3 shows that the slope of the best-fit line for each of the encoded failure rate curves is equal to 2. This is consistent with the preservation of fault tolerance when executing the syndrome extraction circuit on a 2×N array.

[0235] In the case of a single shuttling error, the pseudo threshold is as high as p~O(10 -3 ). Even with exponential accumulation of shuttling errors, the pseudo threshold still reaches a maximum of 4×10 -4 (Shor-6X2Z). The physical failure rate used in the error correction simulation is equal to the two-qubit gate error rate p=p 2q (As shown above). Therefore, in order for error correction to succeed, the pseudo threshold is p=10 -3 The two-qubit gate fidelity is required to be 99.9%.

[0236] It is desirable to use QECC to significantly reduce the error rate of stored logical qubits compared to unencoded qubits. Figure 8It is shown that at p=10 -4 When the error rate of most QECC is about This sets a target for the required spin qubit fidelity to achieve an order of magnitude of error suppression using the QECC of the present invention.

[0237] Another evaluation metric of interest is the ability of the encoding to maintain the bias of the noise at the logical level (the degree of "logical bias"). This ensures that the encoded L1 logical qubits can be used for further QEEC (as discussed below). The tabulated results show the logical bias of the noise for each encoding, which is defined as the logical Z error rate relative to the logical X and Y error rates: Surface-17 is a code that minimizes noise bias. This can be attributed to the symmetrical layout of its stabilizers and logical operators, as well as the fact that the X and Z stabilizers and logical operators are disjoint (it is a CSS code). On the other hand, the XZZX surface code has stabilizers and logical operators that contain a mixture of X and Z operators. Therefore, a high rate of physical Z errors contributes to both logical X and logical Z failures, explaining the low logical bias observed for the XZZX code.

[0238] Based on these results, the proposed technique provides a general framework for decomposing the error correction circuitry of any QECC to fit within the geometric constraints of a 2×N bilinear array of quantum dots. In other words, if another code of interest emerges in the future, the presented method can be applied and evaluated using the metrics in this section to analyze its error correction capability relative to other codes.

[0239] Scalable fault-tolerant quantum processing

[0240] Scalable quantum error correction requires reducing the error rate of processed qubits to approximately 10 -15 , thereby executing efficient quantum algorithms. The above method protects multiple spin qubits as L1 logical qubits in a bilinear array. Fault tolerance is achieved by using a high pseudo threshold of ~10 -3 This is achieved by executing identity gates on L1 logical qubits. However, achieving the desired error rate on first-level (L1) logical qubits is challenging. This is because increasing the number of physical qubits N to increase the QECC distance increases the qubit shuttle distance, which weakens the protection provided by the error correction strategy.

[0241] It is desirable to use L1 logical qubit encodings in 2×N arrays according to the first level QECC as described above as high quality qubits in an architecture that provides fault tolerance while making error protection scalable. The proposed technique provides scalable quantum error protection by connecting multiple 2×N arrays so that second level qubit encoding can be implemented on a number of M>1 L1 logical qubits. The encoding applied to the second level (L2) logical qubits can be extended to achieve arbitrarily well protected logical qubits. The following describes a method for: (i) coupling multiple 2×N quantum dot arrays, and (ii) using the coupled arrays to implement a fault-tolerant quantum operation group, thereby enabling the L1 qubits to be treated as "base qubits" on which (second level) error protection is further applied.

[0242] Coupling multiple 2×N arrays

[0243] Figure 1C A portion of a quantum processor 100 is schematically illustrated, comprising a plurality of bilinear quantum dot arrays 102a, 102b, 102c, and 102d, wherein the arrays are arranged in a grid disposed between control circuitry portions 110a, 110b, and 110c. Control circuitry portions 110a, 110b, and 110c each include readout and control electronics, which collectively constitute or form part of a controller 110 of quantum processor 100. Controller 110 is configured to control the operation of quantum processor 100 by selectively coupling a first L1 logical qubit of a first bilinear array with a second L1 logical qubit of a second bilinear array at least via a coherent coupling mechanism, wherein the coupling occurs by transferring information encoded by the first L1 qubit to the second L1 qubit based on a long-range interaction. Based on this, controller 110 is configured to perform one or more fault-tolerant quantum processing operations on the L1 logical qubits of the plurality of bilinear arrays 102a-102d.

[0244] In the depicted embodiment, the coherent coupling mechanism includes a quantum transport structure 150 configured to connect multiple bilinear arrays according to an architecture. Referring to FIG1c , multiple 2×N quantum dot arrays 102a, 102b, 102c, and 102d are connected via multiple shuttle arrays 150a-150j of the quantum transport structure 150. Each shuttle array 150a-150j includes one or more quantum dots arranged in a linear configuration extending horizontally or vertically along a principal dimension relative to the orientation of the bilinear arrays. In the embodiment shown in FIG1c , the horizontally oriented shuttle array segments 150a, 150b, 150c, 150d, 150g, 150h, 150i, and 150j are directly connected to the ends of the respective bilinear arrays 102a, 102b, 102c, and 102d, while the vertically oriented arrays 150e and 150e form cross-segments with the horizontal segments.

[0245] In the described embodiment, Figure 1C As shown, each of the shuttle arrays 150a-150j spans a single quantum dot in a secondary dimension, thereby forming a 1×D array. That is, the primary dimension D of the shuttle array segments is scalable to connect the bilinear arrays 102a, 102b, 102c, 102d in a grid layout. In some embodiments, the shuttle arrays 150a-150j are configured with a secondary dimension greater than one (e.g., a 2×D array, a 3×D array, etc.) to provide redundancy in the shuttling capability of transferring qubits between the respective bilinear arrays 102a, 102b, 102c, 102d.

[0246] Figure 1D Shown Figure 1C An exemplary layout of a quantum processor 100, in which multiple bilinear arrays are organized according to the architecture depicted in FIG1c . Bilinear arrays, such as array 102a, are connected in a grid via arrays of vertical and horizontal shuttle gates. Sparse placement of the bilinear arrays allows for the dispersal of the readout and control electronics required to implement integrated control of the array of L1 qubits.

[0247] Figure 1D The geometry of the depicted layout has the advantage of allowing the gates that accumulate quantum dots to have a fan-out area while also accommodating the placement of control and measurement electronics. For example, the gates can be densely packed along a one-dimensional channel defined by the shuttle array, yet still contact a three-dimensional metal layer with wider spacing between interconnects.

[0248] like Figure 1D As shown, each 2x17 bilinear array (e.g., 102a, 102b, etc.) is configured to implement a surface code of distance 17 by coherently shuttling qubits across the shuttling rows 107, thereby facilitating long-range two-qubit interactions. Figure 1DIn this example, the qubits of each bilinear array are confined within an active silicon layer (nanowires) beneath multiple plunger gates. Multiple barrier gates are used to control the interactions between the qubits in the bilinear array and assist in the shuttling process. This allows each bilinear array to operate as an L1 logical qubit as described herein.

[0249] The readout and control electronics circuitry is collectively configured to selectively couple a first L1 logic qubit with a second L1 logic qubit by coherently transmitting one or more spin qubits between a first bilinear array (102a, 102b) and a second bilinear array (102c, 102d) connected to the first array. The selective coupling of the L1 logic qubits occurs by generating an entanglement operation between the one or more spin qubits in each array of L1 logic qubits, as described below in the context of performing quantum processing operations on the L1 qubits.

[0250] Figure 1E and 1F They were shown Figure 1D The invention relates to a quantum bit control and coherent transmission method for qubits in a quantum processor 100. Qubit control is achieved by applying an oscillating electromagnetic field 160 to rotate the qubit spin vector 161. Two-qubit coupling is achieved by applying a pulse 162 to one or more barrier gates to bring the qubits into close proximity for exchange interaction. Figure 1F , for interacting logical L1 qubits, the qubit array 102b of one L1 qubit can be shuttled to the shuttle row 107 of another L1 qubit 102a to perform cascade error correction code and create L2 logical qubits.

[0251] In other embodiments, quantum transport structure 150 can take different forms that can vary depending on the layout of the bilinear arrays and / or other components of the quantum processor. For example, structure 150 can include one or more quantum buses or pipelines configured to physically connect one or more of the bilinear arrays of the processor. In some embodiments, structure 150 includes one or more coupling devices, such as superconducting couplers.

[0252] Fault-tolerant logical operations

[0253] Using the L1 logical qubits in the corresponding 2×N array as physical qubits requires the ability to universally manipulate the logical qubits. For example, for processor 100, this enables controller 110 to perform arbitrary quantum operations on each L1 logical qubit stored in arrays 102a, 102b, 102c, 102d. The universal set of operations can be implemented as a discrete set:

[0254] G={PZ ,M Z ,H,T,CNOT}

[0255] Among them, P Z and M Z are the preparation and measurement in the Z basis, H and T are single-qubit gates, and CNOT is a two-qubit entanglement gate.

[0256] The following describes a method for implementing these operations, similarly defined on physical spin qubits in silicon quantum dots, on L1 logical qubits. The ability to implement accurate universal manipulation of L1 logical qubits enables processor 100 to process L1 qubits as logical qubits, thereby enabling the implementation of second-level QECC to encode the collective state of a set of M>1 L1 logical qubits. In this way, the lower error rate of L1 logical qubits (relative to spin qubits) is ~10 -4 -10 -5 Reduced to a further lower error rate of ~10 for L2 logical qubits -15 The L2 logical qubits thus provide high-quality qubits with an error rate sufficient for practical quantum computations.

[0257] Certain quantum processing operations can be performed in a similar manner across different QECCs, which are called transverse operations. Transverse operations are operations on logical qubits that can be implemented as a tensor product of operations on the encoded different physical qubits: Where n is the total number of physical qubits. For example, for all stable subcodes, the logical X is transverse. For Surface-17, this can be achieved by applying Achieve, otherwise And O i =I i (Notice ). Transverse operations are inherently fault-tolerant, as single error events do not propagate into higher-weight errors due to the disjoint nature of the operations. When implementing a general-purpose quantum processing operation set with a 2×N array, transverse operations are used whenever possible.

[0258] Initialization and measurement

[0259] Encoding a logical state using a stabilizer code can be performed by initializing all data qubits to an appropriate basis and performing the entanglement operation specified by the encoded stabilizer. However, instead of entangling data to ancillary qubits as in the syndrome extraction circuit, data is entangled to data qubits, thereby transforming the encoded state into the desired entangled logical state (which is in the +1 eigenspace of the stabilizer).

[0260] Figure 9A and 9B The logic used to initialize the corresponding states of Surface-17QECC is shown respectively. L AND Logic |+> L Fault-tolerant logic encoding circuits 900 and 910. Note that the entanglement operations in both circuits are performed between encoded data qubits, as these qubits will encode the logical states used for quantum computation.

[0261] This type of initialization is common to all stable subcodes. Z and X-based P X The main difference between the preparation (initialization) in the Z(X) basis and the initial preparation (initialization) in the Z(X) basis is that the data qubits are initially prepared in the |0> or |+> state. For any stable subcode, the measurement of the L1 logical qubit state can be done in a transverse manner, that is, by measuring the state of each data qubit. Then, classical error correction can be performed to identify the logical state with high probability. Logical measurement M in the Z(X) basis Z (M X ) requires transverse measurements of the data qubits in the Z(X) basis.

[0262] Single-qubit gates: H and T

[0263] H (Hadamard) gates are transverse for some codes, such as Steane codes, but not for many others. To implement H gates in other stable subcodes, code deformation techniques can be applied, such as weaving around lattice defects (see Fowler

[10] ) or lattice surgery (see Litinski

[11] ). Such techniques can be applied to logical qubits formed by a 2×N array, thereby decomposing the circuit as necessary using the methods discussed above.

[0264] For Surface-17, the H-gate is almost transverse. Applying the H-gate to all physical qubits results in the correct logical state (the X and Z logical operators are swapped), but the boundaries encoded therein are swapped. In some instances, the processor 100 implements the gate by executing a shuttle procedure to rearrange the qubits within the 2×N array so that the boundary qubits return to their natural positions. Alternatively, the controller 110 can be configured to keep track of the boundaries that have been swapped in all subsequent operations.

[0265] One of the most common uses of H-gates is to rotate between X and Z bases (e.g., to prepare a |+> state, an H-gate can be applied after preparing a |0> state). If this is the intended use of H in a particular circuit running the algorithm of interest, then no logical H-gate is required, as the logic state can be directly initialized and measured in each of the X and Z bases. In such instances, only initialization and measurement in the two bases are required, as well as H-gates at the physical level (see Figure 9A and 9B ), which can be realized with high fidelity using physical spin qubits.

[0266] For surface codes, logic T-gates can be implemented using magic state distillation, which involves using multiple faulty T-gates to produce a single high-quality 'distilled' T-gate (see Gidney

[12] ). These distillation protocols require a large number of physical qubits to produce a single high-quality logic T-gate.

[0267] It will be appreciated that implementing a single-qubit gate at the coded logic level can be one of the most resource-intensive operations, as it can require a large number of additional qubits. However, single-qubit gates do not necessarily require high-quality qubits. In fact, the noisiest operation, below which the qubit quality is set to the limit (i.e., pseudo-threshold) below which QECC can be successfully applied, is typically the CNOT gate.

[0268] Two-qubit gate: logical CNOT

[0269] The proposed architecture is able to implement logical CNOT gates (i.e., between L1 logical qubit pairs) while maintaining a high pseudo threshold. The implementation of CNOT gates is transversal for all codes whose X and Z stabilizers consist entirely of X and Z operators, respectively, including Surface-17 codes (referred to as "CSS codes").

[0270] Figure 10A and 10B is a pair of circuit diagrams for a logical CNOT gate between two L1 qubits of two coupled 2=N modules at the logical level 1000 and the physical level 1050. The logical qubit state encoded in one of the 2=N modules (control) is and is the logical qubit state encoded in another 2×N module (target). The data qubits controlling the 2=N modules are |q1>,|q2>,...,|q n >, its encoding And |Q1>,|Q2>,...,|Q n >For the target 2×N module, the data qubits are encoded

[0271] Controller 110 is configured to couple first and second L1 logical qubits encoded in two independent 2×N arrays (e.g., 102 a and 102 c or 102 b and 102 d). Coupling the L1 qubit pairs involves performing entanglement operations between the spin qubits of each array by transferring the spin qubits from one array in the pair to the other array in the pair and performing one or more entanglement operations between the transferred spin qubits.

[0272] Figure 11 A method 1100 performed by a controller 110 is shown for coupling (entangling) two logical qubits encoded in two independent 2×N arrays, such as for implementing a fault-tolerant CNOT gate between a control array in a plurality of bilinear arrays and a target array in a plurality of bilinear arrays.

[0273] At step 1102, qubits from the control array are shuttled via the shuttle array to the second row of empty points in the target array. At step 1104, nearest-neighbor CNOT gates are performed between the data qubits within the corresponding arrays. This generates logical CNOT gates between the L1 logical qubits encoded in each array. At step 1106, the shuttling process is reversed, with the qubits from the second row shuttled back to the first row of their original array. At step 1108, an error correction cycle is performed on each of the control and target arrays. This corrects any single error events that may have occurred during the entire entanglement process.

[0274] Figure 12 A schematic diagram 1200 is shown illustrating the coherent transmission of the underlying spin qubits during the formation of a CNOT gate on an L1 logical qubit pair according to method 1100. Note that only the data qubit (labeled |q i >,|Q i >) are entangled because these data qubits carry encoded logical information, while the auxiliary qubits (labeled |a i >,|A i >) is used in syndrome extraction circuits.

[0275] Evaluation of two-qubit logic gates

[0276] The fidelity of the lateral two-qubit gate to generate entangled logical Bell states was evaluated by simulation using Surface-17. The simulation involved initializing the control (target) logical qubit to a logical |0> using the encoding circuit in Figure 9. L (|+> L) state. The two logical qubits are entangled using a CNOT gate, as modeled in Figure 10. That is, according to the experiment, a logical CNOT gate is performed, and error correction rounds are performed before and after it. L To control and |0> L The effect of the target logical CNOT gate will be checked to see if the following logical Bell state is obtained:

[0277]

[0278] The state is represented by X1X2 and Z1Z2 (X1X2|φ + >=(+1)|φ + >=Z1Z2|Φ + >)Stable.

[0279] Therefore, if the logic of the final generated state and If the parity is trivial (equal to +1), the record is successfully generated as a logical Bell state; otherwise, it is recorded as a failure.

[0280] Circuit noise simulations were performed as presented for the evaluation of L1 logical qubit error rates (discussed above). However, in this simulation, errors were modeled at every error correction point, including at every operation of the encoding, during error correction rounds, and during the shuttling of qubits between different modules.

[0281] Figure 13 Demonstrates logic Failure rate of preparation |Φ + That is, the graph 1300 shows the inaccuracy of the Bell state preparation, which is also called the infidelity. It is observed that the pseudo threshold is p pth =8.1×10 -4 ~10 -3 That is, if the noise intensity of the physical qubit is lower than this value, the Bell state prepared for the encoded qubit is more accurate than the Bell state generated using two unencoded qubits. When using the shuttle error model where errors accumulate exponentially, the pseudo threshold of the logical CNOT is 4.5×10 -5 .

[0282] The results show that the strong error correction capability of QECC is maintained when performing one of the noisiest operations, namely logical CNOT, on L1 logical qubits stored in a 2×N array. This verifies the effectiveness of the proposed method in providing protection for idle L1 logical qubits and also for performing computational operations on stored L1 logical qubits while maintaining protection.

[0283] Scalable quantum error correction with second-level logical qubits

[0284] refer to Figure 13 , achieving an error rate of ~10 for physical spin quantum bits -4 Reduce the error rate of encoded L1 qubits to ~10 -5 Since the L1 logical qubits stored in the 2×N array can be universally manipulated, the L1 logical qubits can be processed with an error rate of ∼10 -5 high-quality quantum bits on which subsequent error correction can be performed.

[0285] A quantum processing architecture is presented, wherein a quantum processor 100 has a plurality of bilinear quantum dot arrays, each of the plurality of bilinear quantum dot arrays having at most N spin qubits, and a controller configured to: (i) control coherent transmission of one or more of the plurality of qubits within each array to implement first-level QECC, thereby encoding the collective state of the spin qubits of the array into corresponding first-level (L1) logical qubits; and (ii) selectively couple one or more pairs of L1 logical qubits in the plurality of bilinear arrays via a coherent coupling mechanism to implement second-level QECC, thereby encoding the collective state of a set of M>1 of the L1 logical qubits into corresponding second-level (L2) logical qubits. For an array pair, coupling is performed by transmitting information encoded by a first L1 qubit in the pair to a second L1 qubit in the pair based on long-range interactions (e.g., by qubit shuttling through a corresponding shuttle array, as described in the examples discussed herein).

[0286] This approach advantageously performs two levels of quantum error correction by applying two independent QECCs, such that the first level QECC reduces the error rate of the (physical) spin qubits to the lower error rate of the L1 logical qubits, and the second level QECC further reduces the lower error rate of the L1 logical qubits to the further lower error rate of the L2 logical qubits.

[0287] The general implementation of the proposed two-level quantum error correction method involves arranging an arbitrary number of M>1 L1 qubit sets to enable a larger surface code to be arranged on the L2 qubits. That is, a surface code with a distance greater than d=3 is applied to protect the L2 qubits. Since the error rate of the M L1 logical qubit set is ~10 -5 , and this error rate is below the threshold of the surface code family (about ~1%), so sufficiently large surface codes can be used to reduce the failure rate of encoded L2 logical qubits to any desired target.

[0288] The advantage of the proposed approach is that it allows a selective trade-off between resources (i.e., more qubits) and improved error protection. Specifically, the availability of sufficiently large surface codes enables the error rate of encoded L1 logical qubits to be reduced to ∼10 -15 , which is the value required to execute the desired quantum algorithm.

[0289] Furthermore, the proposed two-level qubit error correction method can be implemented, at least in part, using a classical decoding mechanism practical in current technology. In one example, the processor 100 includes a plurality of L2 logical qubits, each of which is generated by a total of M=10,000 high-quality (L1) qubits, each of which in turn is composed of N=17 physical qubits.

[0290] Those skilled in the art will appreciate that various changes and / or modifications may be made to the above embodiments without departing from the broad general scope of the present disclosure. Therefore, the present embodiments should be considered in all aspects as illustrative and not restrictive.

[0291] References

[0292] [1] Delfosse, Hierarchical decoding to reduce hardware requirements for quantum computing, 2020, arXiv:2001.11427

[0293] [2] Bluvstein, D. et al., “A quantum processor based on coherent transport of entangled atom arrays”, Nature, vol. 604, April 21, 2022, pp. 451–456.

[0294] [3] Mohiyaddin, FA et al., “Large-Scale 2D Spin-Based Quantum Processor with a Bi-Linear Architecture”, IEEE International Electron Devices Meeting, December 11-15, 2021, pp. 27.5.1-27.5.4.

[0295] [4] J. Yoneda et al., Nature Communications, 12, 10.1038 / s41467-021-24371-7 (2021).

[0296] [5] Y. Tomita and KM Svore, Physical Review A 90, 10.1103 / physreva.90.062320 (2014)

[0297] [6] D. M. Debroy, M. Li, S. Huang and K. R. Brown, Logical performance of 9-qubit compass codes in ion traps with crosstalk errors (2020), arXiv:1910.08495.

[0298] [7] D. Bacon, Physical Review A 73, 10.1103 / physreva.73.012340 (2006).

[0299] [8] JPBonilla Ataides, DKTuckett, SDBartlett, STIflammia and BJBrown, Nature Communications 12, 10.1038 / s41467-021-22274-1 (2021).

[0300] [9] I. Hansen et al. Implementation of the smart protocol for global qubit control in silicon (2021), arXiv:2108.00836.

[0301]

[10] A.G. Fowler et al., Physical Review A 86, 10.1103 / physreva.86.032324 (2012).

[0302]

[11] D. Litinski, Quantum, 3, 128, arXiv:1808.02892v3, (2019).

[0303]

[12] C. Gidney and A. G. Fowler, Quantum, 3, 135, arXiv:1812.01238v3, (2019).

Claims

1. A quantum processing device comprising: at least one bilinear quantum dot array, each array configured to accommodate a plurality of spin qubits; and A controller is configured to control coherent transmission of one or more qubits of the plurality of qubits within each array to implement a quantum error correction code (QECC), wherein the QECC encodes the collective state of the spin qubits of the corresponding array into corresponding first-level (L1) logical qubits.

2. The apparatus of claim 1 , wherein each bilinear array comprises: a first row of N quantum dots configured to accommodate at most N spin qubits; and a second row of N quantum dots configured to enable entanglement operations to be performed between corresponding qubits through the coherent transmission.

3. The apparatus of claim 2 , wherein the spin qubits are accommodated in the first row of the array according to an arrangement selected to facilitate the coherent transmission of the one or more spin qubits in the plurality of spin qubits to perform error correction according to the QECC.

4. The apparatus of claim 3 , wherein the apparatus is configured to perform a cycle of error correction on the L1 logical qubits of any one of the at least one bilinear arrays by: (i) initializing one or more ancillary qubits of the QECC in the array according to the arrangement; (ii) executing one or more two-qubit entanglement gates, each gate entangling one or more pairs of spin qubits of the QECC; and (iii) measuring the ancillary qubits.

5. The apparatus of claim 4, wherein the entangled qubits of the QECC comprise a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

6. An apparatus according to any one of claims 4 to 5, wherein the apparatus is configured to entangle two spin qubits in the array by: coherently transmitting a selected spin qubit of the spin qubit pair from the first row of the array through the second row of the array; aligning the selected spin qubit with the other spin qubit; performing a two-qubit gate; and then coherently transmitting at least the selected spin qubit back to the first row of the array.

7. The apparatus of any one of claims 4 to 5, wherein the apparatus is configured to entangle two spin qubits in the array by causing a direct local interaction between the qubits if the qubits to be entangled are already located in adjacent spots.

8. The apparatus of any one of claims 4 to 7, wherein the one or more two-qubit entanglement gates are scheduled according to the QECC and the geometry of the bilinear array.

9. The apparatus of any one of claims 3 to 8, wherein the arrangement of the qubits in the first row of the array is determined to minimize the depth of syndrome extraction circuitry.

10. The device of any one of claims 1 to 9, wherein each bilinear array is composed of silicon metal oxide semiconductor (SiMOS) quantum dots.

11. The apparatus according to any one of claims 1 to 10, wherein the QECC is a surface code.

12. A method for implementing quantum error correction on a quantum processing device, the method comprising: (i) arranging a plurality of spin qubits in a bilinear quantum dot array of the quantum processing device according to a quantum error correction code (QECC), wherein a collective state of a subset of the spin qubits forms a first level (L1) logical qubit protected by the QECC; (ii) determining a sequence of one or more entanglement operations for corresponding pairs of the plurality of spin qubits; (iii) executing a syndrome extraction circuit to determine a syndrome of the QECC for performing an error correction cycle by performing the sequence of entangling operations, Wherein performing the sequence of entanglement operations involves coherently transmitting one or more spin qubits among the plurality of spin qubits within the array.

13. The method of claim 12, wherein the bilinear array comprises: a first row of N quantum dots, the first row of N quantum dots being configured to accommodate up to N spin qubits; and a second row of N quantum dots, the second row of N quantum dots being configured to enable entanglement operations to be performed between corresponding qubits through the coherent transmission.

14. The method of claim 13, wherein an arrangement of the plurality of spin qubits in the first row is selected to facilitate the coherent transmission of the one or more spin qubits in the plurality of spin qubits to perform error correction according to the QECC.

15. The method of any one of claims 13 to 14, wherein executing the syndrome extraction circuit comprises: (i) initializing one or more ancillary qubits of the QECC in the array according to the arrangement; (ii) performing the determined sequence of entangling operations, each entangling operation entangling a pair of spin qubits of the QECC; and (iii) measuring the ancillary qubits.

16. The method of claim 15, wherein each entangled qubit pair comprises a data qubit associated with a stabilizer of the QECC and one or more corresponding ancillary qubits of the QECC.

17. The method of any one of claims 15 to 16, wherein entangling a spin qubit pair of the QECC comprises: coherently transmitting a selected spin qubit of the spin qubit pair from the first row of the array through the second row of the array; aligning the selected spin qubit with the other spin qubit of the pair; performing a two-qubit gate; and then coherently transmitting at least the selected spin qubit back to the first row of the array.

18. The method of any one of claims 15 to 16, wherein entangling a pair of spin qubits comprises causing direct local interactions between the qubits without coherently transmitting either of the qubits if the qubits to be entangled are already located in adjacent spots.

19. The method of any one of claims 12 to 18, wherein the disentanglement operation sequence of the syndrome extraction circuit is determined according to the QECC and the geometry of the bilinear array.

20. The method of any one of claims 12 to 19, wherein the arrangement of the qubits in the first row of the array is determined to minimize the depth of the syndrome extraction circuit.

21. The method according to any one of claims 12 to 20, further comprising: (iv) decoding the syndrome to obtain an output recovery operator; and (v) Applying the recovery operator to the QECC of the array.

22. The method of claim 21, wherein steps (iv) and (v) are performed by a classical processing device in response to transferring the syndrome from the quantum processing device to the classical processing device.

23. The device of any one of claims 1 to 11, wherein the device comprises a plurality of bilinear quantum dot arrays, and wherein the controller is further configured to: selectively coupling a first L1 logical qubit of a first bilinear array with a second L1 logical qubit of a second bilinear array via a coherent coupling mechanism, wherein the coupling occurs by transferring information encoded by the first L1 qubit into the second L1 qubit based on a long-range interaction; and One or more fault-tolerant quantum processing operations are performed on the L1 logical qubits of the plurality of bilinear arrays.

24. The apparatus of claim 23 , wherein the coherent coupling mechanism comprises a quantum transport structure configured to connect the plurality of bilinear arrays to enable the controller to selectively couple the first L1 logical qubit with the second L1 logical qubit by coherently transferring one or more spin qubits between the first bilinear array and a second bilinear array connected to the first array.

25. The device of claim 24, wherein the quantum transport structure comprises one or more quantum dot shuttle arrays, each shuttle array being disposed between the connected bilinear array pairs.

26. The apparatus of any one of claims 24 to 25, wherein the controller is further configured to couple the first L1 logical qubit with the second L1 logical qubit by creating an entanglement operation between one or more of the spin qubits in each array of the pair in the following manner: transferring the spin qubits from one array in the pair to the other array in the pair; and One or more entanglement operations are performed between the transferred spin qubits.

27. The apparatus of claim 26, wherein the controller is further configured to perform a fault-tolerant CNOT gate between a control array in the plurality of bilinear arrays and a target array in the plurality of bilinear arrays by: coherently transferring the spin qubits from the control array to the target array via the quantum transport structure; performing a nearest neighbor CNOT gate between pairs of one or more of the data qubits of the QECC; coherently transferring the spin qubits from the target array back to the control array; as well as An error correction cycle is performed on each of the control array and the target array.

28. The apparatus of claim 27, wherein the controller is further configured to apply second-level QECC to encode the collective state of the set of L1 logical qubits into corresponding second-level (L2) logical qubits.

29. The apparatus of claim 28, wherein the distance of the second-level QECC is arbitrarily scalable as the number M of the bilinear arrays of the apparatus is greater than 1.

30. A quantum processing device comprising: a plurality of bilinear quantum dot arrays, each array configured to accommodate a plurality of up to N spin qubits; A controller configured to: controlling coherent transmission of one or more qubits of the plurality of qubits within each array to implement first-level QECC to encode the collective state of the spin qubits of the array into corresponding first-level (L1) logical qubits; and selectively coupling one or more L1 logical qubit pairs of the plurality of bilinear arrays via a coherent coupling mechanism to implement a second-level QECC, thereby encoding a collective state of a set of M>1 of the L1 logical qubits into corresponding second-level (L2) logical qubits, wherein for each pair, the coupling is performed by transferring information encoded by a first L1 qubit in the pair to a second L1 qubit in the pair based on a long-range interaction, The first-level QECC reduces the error rate of the spin qubit to the lower error rate of the L1 logical qubit, and the second-level QECC further reduces the lower error rate of the L1 logical qubit to the further lower error rate of the L2 logical qubit.

31. The apparatus of claim 30 , wherein the coherent coupling mechanism comprises a quantum transport structure configured to connect the plurality of bilinear arrays to enable the controller to selectively couple the one or more L1 logic qubit pairs by, for each pair, coherently transferring one or more spin qubits between a first array in the pair and a second array in the pair connected to the first array.

32. The apparatus of claims 30-31, wherein the controller is further configured to perform a set of fault-tolerant quantum processing operations using one or more L2 logical qubits of the apparatus.

33. A method for performing a fault-tolerant quantum processing operation, the method being performed by the quantum processing apparatus according to claim 32, the method comprising: determining at least two connected bilinear arrays to perform a quantum processing operation; Select one or more pairs of the determined connected bilinear arrays, and for each selected pair comprising a first array and a second array: (i) coherently transferring at least a subset of the spin qubits from the first array to the second array; (ii) performing a separate entanglement operation between the spin qubits within the second array; (iii) performing the coherent transmission of step (i) in reverse; as well as (iv) performing an error correction cycle on each of the first array and the second array, wherein the error correction cycle is implemented by the method according to any one of claims 12 to 22.

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