Monitoring device data paths via analog data paths

Abstract

The invention relates to monitoring device data paths via analog data paths. In one embodiment, an apparatus may include a device having a data path associated therewith, an error check component coupled to the device and configured to receive data from the device via the data path, and a data path simulation circuitry, the data path analog circuitry is configured to switch between a first data set and a second data set to be provided from an analog data path to the error check component to monitor timing of the data path, and determining whether to provide data to the error check component from the data path or from the simulated data path based on a mode of operation of the device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to electronic devices, and more particularly to monitoring a device data path, such as a read data path, via an analog path. Background Art

[0002] Various types of electronic devices, such as digital logic circuits and memory systems, can store and process data. Digital logic circuits are electronic circuits that process digital signals or binary information that can take two possible values ​​(usually represented as 0 and 1). Digital logic circuits can use logic gates to manipulate and transform digital signals or binary information. Digital logic circuits can be used in a wide variety of electronic devices, including computers, calculators, digital clocks, and many other electronic devices that employ digital processing. Digital logic circuits can be designed to perform specific logical operations on digital inputs to generate digital outputs, and in some cases, can be combined to form more complex circuits to perform more complex operations. A memory device can include one or more memory devices that store data. A memory device can be, for example, a nonvolatile memory device and a volatile memory device. Generally speaking, a host system can utilize a memory system to store data at a memory device and retrieve data from the memory device. Summary of the Invention

[0003] According to one aspect of the present disclosure, an apparatus for monitoring a device data path is provided. The apparatus includes: a device having a data path associated therewith; an error checking component coupled to the device and configured to receive data from the device via the data path; and data path emulation circuitry configured to: switch between a first data set and a second data set to be provided to the error checking component from an emulated data path to monitor characteristics of the data path; and determine whether to provide data to the error checking component from the data path or from the emulated data path based on an operating mode of the device.

[0004] According to another aspect of the present disclosure, a method for monitoring a data path of a device is provided. The method includes providing a clock signal to a device having a data path associated therewith, the data path being associated with providing data from the device to an error checking component; providing the clock signal to data path simulation circuitry, the data path simulation circuitry being configured to monitor the timing of the data path by: providing the clock signal to a simulated data path; switching between at least a first data set and a second data set; and providing switching data to the error checking component based on the clock signal; and determining whether to provide data to the error checking component from the data path or from the simulated data path based on an operating mode of the device.

[0005] According to another aspect of the present disclosure, a system for monitoring a data path of a device is provided. The system includes: a device having a data path associated therewith; an error checking component coupled to the device and configured to receive data from the device via the data path; and a data path simulation circuit system configured to: determine an operating mode of the device; in response to the operating mode of the device being a non-read operating mode, provide a clock signal to an emulated data path; in response to the clock signal being provided to the emulated data path, switch between a first data set and a second data set; provide switching data from the emulated data path to the error checking component to monitor the timing of the data path; and determine whether the data provided to the error checking component is from the data path or from the emulated data path based on the operating mode of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example electronic system including a host, a controller, and a device according to various embodiments of the present disclosure is shown.

[0008] Figure 2 An example system including datapath simulation circuitry according to some embodiments of the present disclosure is shown.

[0009] Figure 3 is a flowchart corresponding to a method for monitoring a simulation path according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Various aspects of the present disclosure are directed to a data path monitor (e.g., a data path simulation circuit system, an error checking component, a data integrity component, etc.) for determining the timing and / or data integrity associated with an analog path (e.g., an analog data path, etc.), which includes a delay circuit system for simulating a data path of a device (e.g., a read path of a memory device). Many examples herein describe determining the timing of an analog path, however, an analog path can also be used to determine data integrity. The analog path can be an alternative data path that does not interfere with the data path being simulated. The determined timing associated with the analog path can be compared with the expected timing to determine when a timing violation associated with the device occurs. In this way, the data path simulation circuit system can be used to utilize the characteristics associated with the analog path (e.g., timing, data integrity, etc.) to determine aging, voltage drop, clock frequency swing, and other characteristics of the device. In some embodiments, the data path simulation circuit system can be used to trigger functional safety (FUSA) warnings related to voltage, circuit faults, and / or security threats (e.g., thermal attacks, power supply attacks, physical tampering, etc.). Although FUSA warnings are used as specific examples, other types of system warnings are also possible.

[0012] In some embodiments, the device path is a memory read data path. While the memory read data path is used as a specific example, other device paths include, but are not limited to, a memory write data path, a cache memory data path, a direct memory access (DMA) path, and / or an input / output (I / O) data path. The memory read data path may be critical for data flow between a processor and a memory unit, such as a random access memory (RAM). The device path may include multiple functions. For example, the memory read data path may include multiple functions, such as, but not limited to, address generation, address transmission, memory controller activation, data retrieval, data transfer, and / or data processing. In some embodiments, the memory read data path may include both memory access time and logic propagation.

[0013] In previous embodiments, it may be difficult to determine the timing of an entire bus (e.g., a data bus, etc.) associated with a memory device. For example, previous embodiments may utilize a number of representative bits from the memory data to check (e.g., monitor) the timing of the memory device. However, the number of representative bits may be relatively small and not representative of the entire bus. As used herein, a bus or data bus may refer to a device or system that transfers data between components of a computing device or between computing devices.

[0014] To address these and other deficiencies of current approaches, embodiments of the present disclosure allow for a simulated path representing a data read path or similar data path of a device, and for the timing of the simulated path to be determined to determine timing issues associated with the device's entire bus. In some embodiments, data path simulation circuitry can be used to determine the timing of the simulated path, where the simulated path includes delay circuitry for emulating a read data path of a memory device.

[0015] The data path simulation circuit system can be used to determine the timing of the simulation path when the memory device is not actively performing a read operation (e.g., non-read operation mode, etc.). For example, the data path simulation circuit system can determine the timing of the simulation path when the memory device is performing a write operation and / or when the memory device is in a non-read operation mode. As described herein, the device can be in a non-read operation mode and utilize the simulated data path to determine the timing of the simulation path. In some embodiments, the non-read operation mode is an operation mode when the device is not performing a read operation. In another embodiment, the non-read operation mode refers to an operation mode when the device is not utilizing a data bus to transmit data. That is, when utilizing the simulated data path to determine whether there is a timing violation associated with the device, the device can be in any number of operation modes other than the read mode (e.g., active read, etc.). When the memory device is not actively reading, the error checking component can receive switching data provided to the multiplexer via the simulated path. In this way, together with the delay circuit of the simulated path, the error checking component can determine the timing of the simulated path and compare the timing with the expected timing to determine whether the device is experiencing a violation (e.g., a timing violation, etc.).

[0016] Although some non-limiting examples herein are generally described with respect to applicability to memory systems and / or memory devices, the embodiments are not limited thereto, and aspects of the present disclosure may also be applied to systems on a chip, computing subsystems, data collection and processing, storage, networking, communications, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems / subsystems and / or devices. Accordingly, aspects of the present disclosure may be applied to these components to monitor device paths, as described herein. As used herein, a device path can be a path along which a device receives data and / or provides data. For example, a device path may include an input path and / or an output path.

[0017] Figure 1 An example electronic system 100 including a host 102 , a controller 104 , and a device 106 is shown, according to various embodiments of the present disclosure.

[0018] The electronic system 100 may be, for example, a desktop computer, a laptop computer, a television, a home theater system, a game console, a digital camera, a network router and / or switch, a printer, a scanner, a medical device, a GPS navigation device, a home device (e.g., a thermostat, a doorbell camera, a security camera, a smart lock, etc.), a wearable device, an industrial control system (e.g., an automated industrial and / or control device), a mobile computing device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., included in a vehicle, industrial equipment, or a networked commercial device), a system on a chip (SoC), a chipset (e.g., a collection of integrated circuits), a tile, a field programmable gate array (FPGA) structure (e.g., a segmented FPGA structure), or other such devices, or may be part of any of the above.

[0019] The electronic system 100 may be or may include a computing fabric. As used herein, the term "computing fabric" generally refers to a transmission, multiplexing, networking, computing, or communication topology in which components communicate data to each other via interconnecting switches, hubs, routers, multiplexers, buses, transmission lines and rings, cables, optical couplers and optical fibers, electromagnetic devices, or various other components. For example, a "computing fabric" may include various components (e.g., interconnects, crossbars, on-chip networks, token rings, etc.) within computing, memory, data storage and / or processing, networking and / or telecommunications, artificial intelligence, control and / or telemetry, digital entertainment, and / or other systems that facilitate intra-chip and / or inter-chip communication.

[0020] The electronic system 100 includes a host 102. The host 102 may include a processor chipset and a software stack executed by the processor chipset. For example, the host 102 may be or may include a central processing unit (CPU) or a CPU complex that may be configured to execute an operating system.

[0021] The host 102 may be coupled to the controller 104 via a physical and / or logical host interface that operates based on various communication protocols and provides control, address, data, and other signals to the controller 104 (e.g., to further enable the controller 104 to control the device 106). Examples of interfaces between the host 102 and the controller 104 may include, but are not limited to, a bus interface (e.g., a Serial Advanced Technology Attachment (SATA) interface, a Serial Attached SCSI (SAS) interface, a Small Computer System Interface (SCSI), a Peripheral Component Interconnect Express (PCIe) interface, an ISA, etc.), a memory interface (e.g., a Double Data Rate (DDR) interface, a Dual In-line Memory Module (DIMM) interface, an Open NAND Flash Interface (ONFI) interface, an NVM Express (NVMe) interface), a Fibre Channel, a UART interface, an I2C interface, a Serial Peripheral Interface (SPI), a Universal Serial Bus (USB) interface, an Ethernet interface, a General Purpose Input / Output (GIPO) interface, a custom interface, etc.

[0022] The controller 104 is communicatively coupled to one or more electronic devices 106 so that signaling can be exchanged therebetween. Non-limiting examples of devices 106 may include microcontrollers, microprocessors, digital logic circuits, analog circuits, light emitting diode (LED) displays, sensors, motors, actuators, audio amplifiers, radio frequency (RF) circuits, test and measurement instruments (e.g., oscilloscopes, multimeters, etc.), automotive electronics, medical devices, telecommunications equipment, memory devices (e.g., volatile and / or non-volatile memory devices), graphics processing units, processors / coprocessors, logic blocks, intellectual property (IP) cores, etc. As used herein, a "core" or "IP core" generally refers to one or more data and / or logic blocks that form a component of an application-specific integrated circuit or field-programmable gate array. A circuit portion may be designed, constructed, and / or otherwise configured to perform specific tasks and / or functions within the systems described herein.

[0023] like Figure 1 As shown in , controller 104 may include a processing device (e.g., processor 117) that can execute instructions stored in local memory 119 to perform the various operations described herein. Controller 104 may include various specialized circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that can perform the operations described herein. As an example, controller 104 may be a memory controller.

[0024] In various embodiments, one or more components of system 100 (e.g., host 102, controller 104, device 106, etc.) may be part of a SoC. In one example, device 106 itself may correspond to the SoC, while host 102 and controller 104 may be considered "outside" the SoC. In another example, host 102, controller 104, or both may be considered part of the SoC, along with device 106, whether internal or external to the SoC.

[0025] like Figure 1 As shown in , the controller 104 may include a data path monitor 113 (e.g., an error checking component and / or a data path simulation circuit system, etc.). The data path monitor 113 may reside on the controller 104. In other embodiments, the data path monitor 113 or a portion of the data path monitor 113 does not reside on the controller 104. For example, a portion of the simulation path associated with the data path monitor 113 may not reside on the controller 104. As used herein, the term "resides on..." refers to something being physically located on a particular component. For example, the data path monitor 113 "resides" on the controller 104, for example, refers to a situation where the hardware circuit system including the data path monitor 113 is physically located on the controller 104. The term "resides on..." may be used interchangeably herein with other terms such as "deployed on..." or "located on..." In some embodiments, the data path monitor 113 is part of the host 102, application, or operating system. Although Figure 1 Although not shown in order not to obscure the drawings, the data path monitor 113 may include various circuitry to facilitate aspects of the present disclosure described herein. For example, the data path monitor 113 may include various circuitry to facilitate determining the timing of the analog data path to identify potential timing violations of the memory device.

[0026] Figure 2 An example system 221 is shown that includes data path simulation circuitry 247, in accordance with some embodiments of the present disclosure. System 221 can be, for example, a system that can include device 224. Device 224 can be, for example, a memory device. In some embodiments, device 224 can have a data path associated therewith (e.g., a read data path and / or a write data path). System 221 can also include a clock controller 222, a clock tree 223, an error checking component 232, and / or reporting circuitry 235. As further described herein, system 221 can utilize a simulation path that includes one or more flip-flop circuits, one or more multiplexers, one or more delay circuits, and one or more gates to mimic the timing of the data path of device 224. In some embodiments, the data path is a read data path, and device 224 is a memory device.

[0027] Although device 224 is illustrated as static random access memory (SRAM), device 224 may be implemented as other types of memory or other types of devices. For example, device 224 may be a system on a chip, a computing subsystem, a data collection and processing device, a networking device, a communication device, a power supply device, an accelerator (e.g., an artificial intelligence accelerator, etc.), a control device, a telemetry device, a sensing and monitoring device, a digital entertainment device, an interface and / or structure, and other types of devices.

[0028] As used herein, clock controller 222 may include circuitry for generating or providing timing signals (e.g., clock pulses, etc.) that may be used to coordinate the operation of system 221. For example, the timing signals may be used to maintain the integrity of data transfer between a processor and device 224 or other type of memory device. As described herein, timing signals may be critical to data transfer. Even slight timing errors may cause malfunctions or errors in system 221. System 221 may include a clock tree 223 that may be used to maintain synchronized operation of various components of system 221.

[0029] In some embodiments, clock tree 223 may include multiple components to perform various functions. For example, clock tree 223 may include buffers to strengthen the clock signal received by clock controller 222, thereby creating different frequencies for different parts of system 221. In some embodiments, clock tree 223 may include other components such as (but not limited to): inverters, clock gates, multiplexers, level shifters, and / or other components used to strengthen the clock signal.

[0030] Clock tree 223 can distribute timing signals to device 224. As described herein, timing signals can be utilized by device 224 to perform a variety of different operations. For example, timing signals can be used to synchronize memory read operations, memory write operations, and other types of operations. In some embodiments, device 224 can provide signals to first multiplexer 231 and / or provide functional data 225 to other devices or systems.

[0031] In some embodiments, clock tree 223 may provide a timing signal to first flip-flop circuit 236. First flip-flop circuit 236 may be a device capable of changing state in response to an input signal. In some embodiments, first flip-flop circuit 236 may be coupled to first multiplexer 231 and NOT gate 244. As further described herein, first flip-flop circuit 236 may receive a signal identifying the state of device 224. In some embodiments, a signal from first flip-flop circuit 236 may be provided to indicate whether data from device 224 will be provided to error checking component 232 or whether data from the analog path will be provided to error checking component 232.

[0032] As further described herein, the emulation path may include multiple components to mimic the timing of the data path of device 224 or provide expected timing. For example, the emulation path may include multiple delay circuits 237, a clock gate 238, and / or a second multiplexer 243. In some embodiments, system 221 may include data path emulation circuitry 247, which may include portions of the emulation path including, but not limited to, NOT gate 228, OR gate 229, first flip-flop circuit 236, the multiple delay circuits 237, clock gate 238, second flip-flop circuit 239, second multiplexer 243, first multiplexer 231, and / or error checking component 232. In this manner, data path emulation circuitry 247 may be used to determine the timing of the emulation path of system 221 (e.g., when device 224 is not actively performing a read operation).

[0033] In some embodiments, the error checking component 232 can be coupled to the device 224 to receive data from the device 224 via a data path associated with the device 224. For example, when the device 224 is performing a read operation, the error checking component 232 can receive data from the device 224 via the first multiplexer 231. In these embodiments, the error checking component 232 can determine whether there are errors associated with the data. For example, the error checking component 232 can determine whether there are timing errors or data integrity errors (e.g., data accuracy errors, etc.) associated with the data received from the device 224. As an example, the error checking component 232 can be a single error correction double error detection (SECDED) decoder, but embodiments are not limited thereto.

[0034] In some embodiments, system 221 can utilize data path simulation circuitry 247 to determine characteristics of the simulated data path. As described herein, system 221 can utilize data path simulation circuitry 247 to determine the timing of the simulated data path of device 224 during a particular operating mode. For example, system 221 can determine whether device 224 is in a read mode or one of a non-read mode (e.g., a write mode, an idle mode, etc.).

[0035] As used herein, a read mode of device 224 refers to a mode in which device 224 is enabled / active and is performing a read operation, a write mode of device 224 refers to a mode in which device 224 is enabled / active and is performing a write operation, and an idle mode of device 224 refers to a mode in which device 224 is disabled / inactive such that it cannot perform a write or read operation. In some embodiments, the disabled / inactive mode may be referred to as an idle mode, which may include a power saving mode or other mode in which the device is not actively performing a read or write operation. Although specific operating modes are described, many other modes may also be utilized without departing from the present disclosure.

[0036] In some embodiments, system 221 is configured to provide data from the data path to error checking component 232 when device 224 is in read mode, and to provide data from the analog data path when device 224 is in non-read mode. In these embodiments, system 221 may utilize NOT gate 228 and / or OR gate 229 to determine the operating mode of device 224.

[0037] In some embodiments, a non-read operation may refer to an operating mode of device 224 in which data is not transferred via a data bus associated with device 224. For example, in some embodiments, system 221 may be configured to determine whether to provide data to error checking component 232 from the data path of device 224 or from an emulation path based on the operating mode of the data bus associated with device 224. For example, the operating mode of a data bus may refer to a data transfer operating state, a non-transfer operating state, and / or a plurality of other operating states. In these instances, the data transfer operating state may refer to the time when the data bus is being used to transfer data. In these instances, the non-transfer operating state may be a state when the data bus is not transferring data. In this manner, system 221 may provide switching data from an emulation path when the data bus is in the non-transfer operating state, and provide data from device 224 when the data bus is in the data transfer operating state.

[0038] In some embodiments, system 221 includes a memory enable (ME) signal 226 and a write enable (WE) signal 227. Conventionally, ME signal 226 is used to enable or disable device 224. In some embodiments, ME signal 226 is high (e.g., a signal "1," etc.) to activate device 224, and ME signal 226 is low (e.g., a signal "0," etc.) to deactivate device 224. In a similar manner, WE signal 227 can be used to indicate whether device 224 is in read mode or write mode. In some embodiments, WE signal 227 is high (e.g., a signal "1," etc.) to perform a write operation, and WE signal 227 is low (e.g., a signal "0," etc.) to perform a read operation.

[0039] In some embodiments, system 221 may include a NOT gate 228. As used herein, a NOT gate may be a logic gate. In some embodiments, NOT gate 228 may perform logic negation or logic inversion. For example, an input of a low signal (e.g., signal "0") may be inverted to a high signal (e.g., signal "1"). In some embodiments, ME signal 226 may be provided to the input of NOT gate 228. In this way, ME signal 226 may be inverted by NOT gate 228. Therefore, in these embodiments, NOT gate 228 may convert a valid high signal from ME signal 226 and invert it to a low signal. Similarly, NOT gate 228 may convert an invalid low signal from ME signal 226 and invert it to a high signal. The output signal from NOT gate 228 may be provided to OR gate 229. As used herein, OR gate 229 refers to a logic gate that can combine multiple binary conditions or signals. In some embodiments, OR gate 229 may be used to determine a logical "OR," wherein if one of the inputs is "true," the output of OR gate 229 will be true. For example, if one of the signals received by OR gate 229 is a high signal, the output of OR gate 229 will be a high signal.

[0040] In this example, a first input of OR gate 229 is received from the output of NOT gate 228, and a second input of OR gate 229 receives WE signal 227. In some embodiments, when either NOT gate 228 or WE signal 227 provides a high signal to OR gate 229, OR gate 229 will provide a high signal as an output. For example, WE signal 227 can be a high signal (e.g., a signal "1") provided to OR gate 229, and OR gate 229 can provide a high signal output. In a similar manner, when ME signal 226 is a low signal, NOT gate 228 can provide a high signal to OR gate 229. In this example, OR gate 229 can provide a high signal output in response to receiving a high signal from OR gate 229. Therefore, in some embodiments, when both WE signal 227 and NOT gate 228 are low signals, OR gate 229 can provide a low signal. In this manner, OR gate 229 may be used to provide a high signal when device 224 is disabled by ME signal 226 and / or when device 224 is enabled by WE signal 227 for a write operation.

[0041] In some embodiments, first flip-flop circuit 236 can be used to emulate a delay (e.g., memory read delay). In this way, first flip-flop circuit 236 can allow system 221 to implement a specific delay when switching from the data path of device 224 to the analog path. In some embodiments, additional flip-flop circuits can be utilized in addition to first flip-flop circuit 236. For example, the number of flip-flop circuits can depend on the time or clock count of the delay of system 221. For example, first flip-flop circuit 236 can provide a one-clock delay. In this example, additional flip-flop circuits can be added to system 221 to provide a two-clock delay.

[0042] As used herein, clock gate 238 may refer to an electrical device or circuit that can control the distribution of a clock signal. For example, clock gate 238 can be used to provide a timing signal to second flip-flop circuit 239 or prevent a timing signal from being provided to second flip-flop circuit 239. In some embodiments, clock gate 238 can be used to conserve power and / or performance of system 221 by deactivating the signal provided to second flip-flop circuit 239.

[0043] In some embodiments, a second flip-flop circuit 239 can be used to provide a select signal to a second multiplexer (MUX) 243. In some examples, the second flip-flop circuit 239 can perform switching to alternate the select signal provided to the second multiplexer 243. In these embodiments, the second flip-flop circuit 239 can provide a first select signal to the second multiplexer 243, causing the second multiplexer 243 to provide a first value from the first data set. For example, the second multiplexer 243 can receive the first select signal from the second flip-flop circuit 239, and the second multiplexer 243 can provide a first hexadecimal value "AA" 241 to the first multiplexer 231. In this example, the second multiplexer 243 can receive a second select signal from the second flip-flop circuit 239, and the second multiplexer 243 can provide a second hexadecimal value "55" 242 to the first multiplexer 231. In this manner, the second flip-flop circuit 239 and the second multiplexer 243 can provide the switched data set from the analog path to the error checking component 232 to monitor the timing of the analog path. Although a first data set and a second data set are described herein, additional data sets can be switched in a similar manner without departing from the present disclosure. Furthermore, although a first hexadecimal value "AA" 241 and a second hexadecimal value "55" are used as specific examples, other hexadecimal values ​​or data sets can be utilized.

[0044] The error checking component 232 can determine whether the received signal is correct (e.g., an "AA" 241 signal or a "55" 242 signal) to determine the timing of the analog path. For example, the error checking component 232 can identify a data signal that is expected to be received and determine whether the data signal is the correct signal. In some embodiments, the data signal can be used to determine the timing of the analog path, which can be used to determine the functionality of the data path of the device 224. As described herein, the timing of the analog path can refer to the amount of data timing of the analog path. For example, the timing of the analog path can be the amount of time between when the clock controller 222 generates a timing signal and when the data signal is received at the error checking component 232. In these embodiments, the error checking component 232 can determine the timing based on the determined time of the received data signal.

[0045] As described herein, error checking component 232 can receive an output signal from first multiplexer 231. In some embodiments, first multiplexer 231 can receive a signal from second multiplexer 243 or device 224. In some embodiments, the signal from device 224 received at first multiplexer 231 can be passed to error checking component 232 to determine the current timing of the signal processed by device 224. In this manner, error checking component 232 can determine the current timing of the data signal processed by device 224 in a manner similar to how error checking component 232 can determine the current timing of the data signal processed by the analog path. As described herein, the analog path can be configured to have the same or similar timing as the data path of device 224. However, in other embodiments, the analog path can be configured to have different timing than the data path of device 224. For example, the analog path can be configured to have a timing that is a ratio of the timing of device 224. In this manner, error checking component 232 can determine when the timing of an emulated path is outside of a threshold timing and utilize this determination to determine that a corresponding error associated with the data path of device 224 may exist.

[0046] In some embodiments, functional data 225 can be provided to an external system or device. As used herein, functional data 225 can be data read from device 224 via a read operation. In this manner, functional data 225 can be read data provided to a host device or host system in response to a read operation from the host device or host system.

[0047] In some embodiments, the error checking component 232 can provide a signal to the reporting circuit system 235. In some embodiments, the reporting circuit system 235 can generate a report associated with the device 224 and / or the analog path. In some instances, the reporting circuit system 235 can generate reports related to safe operation, error telemetry, dynamic voltage management system (DVFS), or other characteristics associated with the system 221. For example, the reporting circuit system 235 can be a FUSA reporting circuit system capable of generating notifications related to FUSA reports. Although FUSA reports are described herein, the present disclosure is not limited thereto. For example, the reporting circuit system 235 can generate a plurality of different reports that can describe the characteristics of the device 224 and / or the analog path. In some embodiments, the error checking component 232 and / or the reporting circuit system 235 can determine a fault based on a timing difference between the analog path and a threshold.

[0048] As described herein, timing violations of device 224 or timing violations of analog paths may be caused by a number of different issues associated with system 221. For example, when there is circuit system degradation or aging, the timing of the analog path may be below a threshold timing or slower than expected timing. In this manner, there may be possible circuit system degradation associated with device 224. In these embodiments, reporting circuitry 235 can be used to generate a number of different fault reports (e.g., FUSA reports, safety reports, power management reports, etc.) based on the timing at a specific time or the timing changes over a period of time.

[0049] Memories marked as FUSA are critical to the safe operation of the system. If these memories and / or paths fail or are damaged, the system is designed to identify the failure and take appropriate action to correct the error or enter a safe state to prevent further problems. FUSA may be indispensable for ensuring the reliability and safety of systems where failures may have serious consequences for memory devices. Device paths such as memory read data paths may be timing critical paths. That is, when there is a failure or damage to a particular device path, the particular device path may cause a serious failure. Device paths may become damaged due to security threats, aging, circuit failures, or other problems. A damaged device path may cause timing violations, which may harm the system that is utilizing the memory device. As described herein, a FUSA report is a specific instance of a report that can be generated by system 221. For example, other types of reports may be generated, such as (but not limited to) power management reports, security reports, or other system reports.

[0050] In some embodiments, system 221 may include an AND gate 245. AND gate 245 may include a first input from error checking component 232 and a second input from NOT gate 244. As described herein, NOT gate 244 may perform logical negation or inversion. For example, an input of a low signal (e.g., a signal "0") may be inverted to a high signal (e.g., a signal "1"). NOT gate 244 may receive a signal from first flip-flop circuit 236 that may indicate when the signal to device 224 includes one of ME signal 226, which is a low signal, or WE signal 227, which is a high signal provided to OR gate 229. In this manner, the signal to NOT gate 244 may be an indication of whether the data provided to first multiplexer 231 is functional data 225 or test data from an analog path through second multiplexer 243. In this manner, AND gate 245 may receive a low signal from NOT gate 244 when device 224 is not performing a read operation and a high signal from NOT gate 244 when device 224 is performing a read operation. This may allow AND gate 245 to determine that there is a functional error 234 to functional data 225 as compared to a timing error associated with the analog path through second multiplexer 243. As described herein, first flip-flop circuit 236 may also be used to account for data path delays.

[0051] In certain embodiments, system 221 may include an apparatus. As described herein, an apparatus may include a first flip-flop circuit to receive an indication signal that a memory device is in a particular state. In some embodiments, a first flip-flop circuit (e.g., first flip-flop circuit 236, etc.) may be configured to send a selection signal to a multiplexer (e.g., first multiplexer 231, etc.) when a memory device (e.g., device 224, etc.) is in a particular state. As described herein, first flip-flop circuit 236 may be configured to switch the multiplexer based on whether device 224 is performing a read operation.

[0052] As described herein, system 221 and / or apparatus may include a plurality of delay circuits 237 coupled to an analog path to provide timing that mimics the timing of a memory device or memory read operation of device 224. In some embodiments, device 224 may be designed to perform a specific operation (e.g., a read operation, etc.) within specific timing parameters. In this manner, the plurality of delay circuits 237 may be designed to mimic the specific timing parameters of device 224 when performing the specific operation. That is, the amount of time it takes device 224 to perform a read operation may be the same or similar to the time it takes a signal to pass through the analog path including the plurality of delay circuits 237. In other embodiments, delay circuits 237 may be used to mimic a specific timing operation that may differ from the read operation of device 224.

[0053] In some embodiments, the apparatus may include a second flip-flop circuit 239 to receive a timing signal in response to the memory device being in a particular state. As described herein, the second flip-flop circuit 239 may receive a timing signal from the clock gate 238 when the clock gate 238 determines that the device 224 is not performing a read operation.

[0054] In some embodiments, the apparatus may include a multiplexer (e.g., second multiplexer 243, etc.) to create a designated data signal (e.g., "AA" 241 and / or "55" 242, etc.) controlled by second flip-flop circuit 239 in response to receiving a timing signal from clock gate 238. As described herein, the designated data signal may be a switching data signal that can be used to identify the timing of the analog path.

[0055] In some embodiments, system 221 can be configured to generate a report when the timing of the analog path is outside of a threshold timing. As described herein, error checking component 232 can utilize a threshold timing associated with device 224. The threshold timing can be a range of timing values ​​within an acceptable timing range for a particular device. In this manner, error checking component 232 can determine when a timing violation is outside of a threshold and provide the timing violation to reporting circuitry 235. System 221 can also be configured to determine the timing of the analog path based on a received specified data signal. As described herein, the specified data can be switching data provided by second multiplexer 243 to allow error checking component 232 to identify sequentially received data signals.

[0056] In various specific embodiments, the system 221 may include a first flip-flop circuit 236 to receive an indication signal that a memory device (e.g., device 224, etc.) is in a write-enabled state, and a second flip-flop circuit 239 to receive a plurality of timing signals from an analog path in response to the memory device being in the write-enabled state. The plurality of timing signals may be utilized by the second flip-flop circuit 239 to provide a select signal to a second multiplexer 243 for providing switching data to the first multiplexer 231. As described herein, the designated data may switch between a first static data value (e.g., "AA" 241, etc.) and a second static data value (e.g., "55" 242, etc.).

[0057] In this particular embodiment, first flip-flop circuit 236 can be configured to send a signal to first multiplexer 231 to switch between providing functional data 225 from device 224 and providing a designated data signal from the analog path to a checking component (e.g., error checking component 232). In this particular embodiment, system 221 can include error checking component 232, which is configured to receive the corresponding designated data signal from first multiplexer 231 to determine the timing of the analog path and compare the timing of the analog path to a threshold timing associated with a memory device (e.g., device 224, etc.). As described herein, the threshold timing can be based on an expected timing of the analog path, which is based on the configuration of delay circuit 237 and / or other components of data path emulation circuitry 247.

[0058] Figure 3 is a flow chart corresponding to a method 360 for monitoring an analog path according to some embodiments of the present disclosure. The method 360 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 360 is performed by Figure 1 The data path monitor 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0059] Method 360 may be performed at step 361 to provide a clock signal to a device having a data path associated therewith that is associated with providing data from the device to an error checking component. In some embodiments, method 360 may utilize a clock controller (e.g., Figure 2 ), the clock controller may include circuitry for generating or providing timing signals (e.g., clock pulses, clock signals, etc.) that can be used to coordinate the operation of the device. For example, the timing signals can be used to maintain the integrity of data transfer between the processor and the device. As described herein, the timing signals can be critical to data transfer. Even slight timing errors can cause device malfunction or failure.

[0060] Method 360 may be performed at step 362 to provide a clock signal to data path simulation circuitry configured to monitor timing of the data path. In some embodiments, providing the clock signal to the data path simulation circuitry includes providing the clock signal to the simulation path, switching between at least a first data set and a second data set, and / or providing switching data to an error checking component based on the clock signal.

[0061] As used herein, an analog path may be an alternative path or electrical path that is not provided to a device having a data path. In this manner, an analog path may include multiple delay circuits (e.g., Figure 2 The signal may be a timing signal provided by a clock controller and / or a clock tree.

[0062] In some embodiments, when the operating mode of the device is a read operating mode, method 360 may be performed to prevent a clock signal from being provided to the analog path. As described herein, the data path simulation circuitry may determine when the device is in a read operating mode and provide functional data to the error correction circuitry instead of switching data from the analog path. As described herein, checking components (e.g., Figure 2 ) can be connected to a multiplexer (e.g., as shown in FIG. Figure 2 In some embodiments, activating the check component may refer to changing the check component from monitoring the functional data provided via the memory device to monitoring the functional data provided via the analog path (e.g., via the analog path). Figure 2 243, etc.). In this way, the inspection component can be notified when functional data is provided via the memory device and when non-functional data is provided via the analog path. By monitoring both functional and non-functional data, the inspection component can determine whether the timing of the memory device and / or the analog path has degraded over a period of time. In a similar manner, the inspection component can be used to inspect or monitor functional data and monitor the timing of signals passing through the analog path.

[0063] Method 360 may be performed at step 363 to determine whether to provide data to the error checking component from the data path or the emulation path based on the operating mode of the device. As described herein, method 360 may include providing data from the data path of the device to the error checking component when the device is in a read mode, and providing switching data from the emulation path to the error checking component when the device is in a non-read mode.

[0064] Method 360 can be performed to determine when the timing of a signal is outside a threshold. As described herein, when the timing of a signal provided via an analog path is outside a threshold timing, a checking component can generate a notification that a timing fault associated with the memory device exists. In this manner, a signal for determining a timing error is not provided via the memory device.

[0065] Figure 4 is a block diagram of an example computer system 490 in which embodiments of the present disclosure may operate. For example, Figure 4 An example machine is shown of a computer system 490 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 490 may correspond to a host system (e.g., Figure 1 102 ), the host system including, coupled to, or utilizing a memory system (e.g., Figure 2 system 221) or can be used to perform operations of the controller (for example, to execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a server or a client machine in a peer-to-peer (or distributed) network environment.

[0066] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0067] The example computer system 490 includes a processing device 491, a main memory 493 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 497 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 498, which communicate with each other via a bus 496.

[0068] Processing device 491 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 491 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 491 is configured to execute instructions 492 for performing the operations and steps discussed herein. Computer system 490 may further include a network interface device 494 for communicating via a network 495.

[0069] The data storage system 498 may include a machine-readable storage medium 499 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 492 or software embodying any one or more of the methods or functions described herein. The instructions 492 may also reside, completely or at least partially, within the main memory 493 and / or within the processing device 491 during execution by the computer system 490, with the main memory 493 and the processing device 491 also constituting machine-readable storage media. The machine-readable storage medium 499, the data storage system 498, and / or the main memory 493 may correspond to Figure 2 System 221.

[0070] In one embodiment, instructions 492 include instructions for implementing the corresponding syndrome calculation circuitry (e.g., Figure 1 13 ). Although the machine-readable storage medium 499 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding an instruction set for execution by a machine and causing the machine to perform any one or more methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but not be limited to) solid-state memory, optical media, and magnetic media.

[0071] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. These quantities are often, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0072] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the acts and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0073] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any other type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. Structures for a variety of these systems will be presented as described below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure described herein can be implemented using a variety of programming languages.

[0075] The present disclosure can be provided as a computer program product or software, which can include a machine-readable medium having instructions stored thereon, and the instructions can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0076] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. An apparatus for monitoring a data path of a device (224), comprising: a device (224) having a data path associated therewith; an error checking component (232) coupled to the device (224) and configured to receive data from the device (224) via the data path; as well as Data path simulation circuitry (247) configured to: switching between a first data set and a second data set to be provided from an analog data path to the error checking component (232) to monitor characteristics of the data path; as well as Whether data is provided to the error checking component (232) from the data path or from the emulated data path is determined based on an operating mode of the device (224).

2. The apparatus of claim 1 , wherein the analog data path comprises one or more flip-flop circuits, one or more multiplexers, one or more delay circuits, and one or more gates to emulate timing of the data path of the device. 3 . The apparatus of claim 1 , wherein when the device is a memory device and the characteristic is one of timing of a read data path or data integrity of the analog data path, the data path is the read data path.

4. An apparatus according to any one of claims 1 to 3, wherein the operating mode is one of a read mode and a non-read mode, and wherein the data path simulation circuit system is configured to provide data from the data path to the error checking component when the device is in the read mode, and to provide data from the simulated data path when the device is in the non-read mode.

5. The apparatus of any one of claims 1 to 3, wherein the data path emulation circuitry is configured to generate a signal when timing of the data provided from the emulated data path to the error checking component is outside a timing threshold.

6. The apparatus of any one of claims 1 to 3, wherein the data path emulation circuitry is configured to switch a multiplexer to provide data from the data path to the error checking component or to provide switched data from the emulated data path based on an operating mode of the device.

7. A method for monitoring a data path of a device, comprising: providing a clock signal to a device (224) having a data path associated therewith, the data path being associated with providing data from the device (224) to an error checking component (232); The clock signal is provided to data path simulation circuitry (247), which is configured to monitor the timing of the data path by: providing the clock signal to an analog data path; switching between at least a first data set and a second data set; as well as providing switching data to the error checking component (232) based on the clock signal; as well as Whether data is provided to the error checking component (232) from the data path or from the emulated data path is determined based on an operating mode of the device (224).

8. The method of claim 7, further comprising preventing the clock signal from being provided to the analog data path when the operating mode of the device is a read operating mode.

9. The method of any one of claims 7-8, wherein the analog data path is configured to provide the switching data to the error checking component within a threshold timing associated with the data path of the device.

10. The method of any one of claims 7 to 9, further comprising determining whether to provide data to the error checking component from the data path or from the simulated data path based on an operating mode of a data bus associated with the device, wherein the operating mode of the data bus includes a data transfer operating mode and a non-operating mode.

11. The method according to claim 7, further comprising: determining when a detected error is associated with data from the data path or switched data from the analog data path; as well as In response to determining that the timing of the simulated data path is outside of a timing threshold, an error is determined to be associated with the data path.

12. A system for monitoring a data path of a device, comprising: a device (224) having a data path associated therewith; an error checking component (232) coupled to the device (224) and configured to receive data from the device (224) via the data path; as well as Data path simulation circuitry (247) configured to: determining an operating mode of the device (224); providing a clock signal to an analog data path in response to the operating mode of the device (224) being a non-read operating mode; switching between a first data set and a second data set in response to the clock signal being provided to the analog data path; providing switching data from the analog data path to the error checking component (232) to monitor timing of the data path; as well as Whether data provided to the error checking component is from the data path or from the emulated data path is determined based on the operating mode of the device (224).

13. The system of claim 12, wherein the non-read operating mode is an operating mode in which the device is not performing a read operation using the data path.

14. The system of claim 12, wherein emulating a data path comprises delay circuitry to mimic timing of the data path based on a propagation time and a margin time of the data path.

15. The system of any one of claims 12 to 14, wherein the error checking component is further configured to: receiving the switching data from the analog data path to determine characteristics of the analog data path; and The timing of the simulated data path is compared to an expected timing, and a timing violation is generated when the timing of the simulated data path is outside a threshold of the expected timing.

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