System and method for processing different instructions on same assembly line

Abstract

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a system and method for processing different instructions on the same pipeline. Background Art

[0002] In the field of microelectronics, different processors typically process different instruction sets. For example, RISC processors process reduced instruction sets (RISC). RISC-V is the fifth generation of RISC, an open source instruction set architecture developed based on the reduced instruction set principle. DSP (digital signal processor) processors are designed for the DSP instruction set.

[0003] Processors generally use a pipeline approach to efficiently process instructions, splitting instruction execution into multiple stages (such as instruction fetch, decode, execute, memory access, and write back). Each stage represents a step the processor goes through when executing an instruction. This approach enables the processor to process multiple instructions at the same time and execute different stages of different instructions in parallel within each clock cycle.

[0004] The DSP pipeline can achieve multi-task parallelism and high execution efficiency. The power consumption when processing a task will be lower, and the overall power consumption will be small, but the main frequency of DSP is not high; the RISC-V pipeline is task serial. RISC-V's tasks are simple, the main frequency is high, and the single instruction execution speed is fast, but the overall efficiency is not as high as DSP.

[0005] In order to make the processor compatible with DSP and RISC-V instructions, a master-slave core method is currently used, where one core supports RISC-V and one core supports DSP. However, this method requires the hardware resources of two cores, which increases the hardware cost of the system and causes waste of resources. Summary of the Invention

[0006] The present invention provides a system and method for processing different instructions on the same pipeline, which solves the problem in the prior art that the processor requires many hardware resources, has high system hardware cost and causes waste of resources when being compatible with DSP and RISC instructions.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is to provide a system for processing different instructions on the same pipeline, comprising: a control unit and an operation unit, the control unit being electrically connected to the operation unit; the control unit comprising an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder, and a pipeline management subunit; the instruction register comprising a first instruction register and a second instruction register; the instruction acquisition subunit being configured to acquire computer instructions to be executed, wherein the encoding length and encoding rules of different types of computer instructions are the same, and the same encoding position of different types of computer instructions all contains an instruction type identifier; the instruction judgment subunit being configured to determine the type of the acquired computer instruction based on the instruction type identifier, and if the type of the computer instruction is the first instruction type, storing the computer instruction in the first instruction register; and if the type of the computer instruction is the second instruction type, storing the computer instruction in the second instruction register; the instruction decoder being configured to respectively decode the different types of computer instructions in the first instruction register and the second instruction register and generate corresponding operation tasks; the pipeline management subunit being configured to dispatch the operation tasks corresponding to the computer instructions to the operation unit; and the operation unit being configured to execute the operation tasks.

[0008] In some embodiments, the first instruction type comprises a RISC-V instruction type, and the second instruction type comprises a DSP instruction type.

[0009] In some embodiments, if the type of the computer instruction is the second instruction type, the instruction judgment subunit is also used to judge the execution method of the computer instruction based on the function of the computer instruction and the binary encoding rules, and combine multiple computer instructions that can be executed in parallel into a combined instruction and save them in the same row in the second instruction register.

[0010] In some embodiments, when the instruction decoder decodes the computer instruction in the first instruction register, it reads one of the computer instructions, identifies the operation information contained in the computer instruction, and generates the corresponding operation task based on the operation information; when the instruction decoder decodes the computer instruction in the second instruction register, it reads one of the combined instructions, splits the combined instruction into multiple second sub-instructions, respectively identifies the operation information contained in multiple second sub-instructions, and generates multiple corresponding operation tasks based on the operation information; wherein, the operation information includes an instruction category identifier, an opcode, an operand, and / or an immediate value.

[0011] In some embodiments, the pipeline management subunit sends the operation task generated according to the computer instruction in the first instruction register to the operation unit, and the operation task is executed serially in the operation unit; the pipeline management subunit sends multiple operation tasks generated according to the combined instruction in the second instruction register to the operation unit respectively, and multiple operation tasks are executed in parallel in the operation unit.

[0012] In some embodiments, the operation unit includes at least one of the following sub-units: a load-storage sub-unit, used to perform the operation tasks of loading and / or storing the computer instructions; a multiplication-addition sub-unit, used to perform the operation tasks of multiplication and / or accumulation operations of the computer instructions; an accumulator register sub-unit, used to perform the operation tasks of accumulation operations of the computer instructions; an arithmetic-logic sub-unit, used to perform the operation tasks of arithmetic and / or logic operations of the computer instructions; a digital signal processing operation sub-unit, used to perform the operation tasks of digital signal processing operations of the computer instructions; an accumulator register, used to store operands and / or operation results of arithmetic or logical operations; and a multiplication and quotient register, used to store operands and / or operation results of multiplication or division operations.

[0013] In some embodiments, a storage unit is also included, which is electrically connected to the control unit and the operation unit respectively, and is used to temporarily store the execution data generated when the operation unit performs the operation task. The storage unit includes: a first instruction storage unit, used to store the computer instructions of the first instruction type and / or their corresponding execution data; a second instruction storage unit, used to store the computer instructions of the second instruction type and / or their corresponding execution data; wherein, the second instruction storage unit includes multiple second instruction storage sub-units, each of the second instruction storage sub-units includes an independent data entrance and exit, so as to allow the operation unit to use the corresponding second instruction storage sub-unit at the same time when synchronously executing different operation tasks.

[0014] The present invention also provides a method for processing different instructions on the same pipeline, comprising the steps of: obtaining computer instructions to be executed, the encoding lengths and encoding rules of different types of computer instructions are the same, and the same encoding positions of different types of computer instructions all contain instruction category identifiers; judging the type of the obtained computer instructions based on the instruction category identifier; saving and reading the computer instructions of the first instruction type and the second instruction type respectively, decoding the different types of computer instructions, generating corresponding operation tasks, and executing the operation tasks after issuing them.

[0015] In some embodiments, the computer instruction is processed through an eight-stage pipeline, and the eight-stage pipeline is: F1 fetches instruction address, F2 fetches instruction content, D instruction decoding, R1 fetches operand address, R2 fetches operand, E1 first execution, E2 second execution and Wb write back.

[0016] In some embodiments, if the type of the computer instruction is a first instruction type, the computer instruction is decoded, the operation information contained in the computer instruction is identified, and a corresponding operation task is generated based on the operation information. The operation task is executed serially after being issued, and the execution status is synchronized; if the type of the computer instruction is a second instruction type, multiple computer instructions that can be executed in parallel are combined into a combined instruction and saved in the same line; a combined instruction is read, and the combined instruction is split into multiple second sub-instructions, the multiple second sub-instructions are decoded, the operation information contained in each second sub-instruction is identified respectively, and multiple corresponding operation tasks are generated based on the operation information. The multiple operation tasks are executed in parallel after being issued, and the execution status is synchronized.

[0017] The beneficial effects of the present invention are as follows: the present invention discloses a system and method for processing different instructions on the same pipeline. The system includes: a control unit and an arithmetic unit, the control unit being electrically connected to the arithmetic unit; the control unit including an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder, and a pipeline management subunit; the instruction register including a first instruction register and a second instruction register; the instruction acquisition subunit being used to acquire computer instructions to be executed, wherein the encoding length and encoding rules of different types of computer instructions are the same, and the same encoding position of different types of computer instructions all contains an instruction category identifier; the instruction judgment subunit being used to determine the type of the acquired computer instruction based on the instruction category identifier, and if the type of the computer instruction is the first instruction type, the computer instruction is stored in the first instruction register; if the type of the computer instruction is the second instruction type, the computer instruction is stored in the second instruction register; the instruction decoder being used to respectively decode different types of computer instructions in the first instruction register and the second instruction register and generate corresponding operation tasks; the pipeline management subunit being used to send the operation tasks corresponding to the computer instructions to the arithmetic unit; and the arithmetic unit being used to execute the operation tasks. The method includes the following steps: obtaining computer instructions to be executed, wherein the encoding lengths and encoding rules of different types of computer instructions are the same, and the same encoding positions of different types of computer instructions all contain instruction category identifiers; judging the type of the obtained computer instructions based on the instruction category identifiers; after respectively saving and reading computer instructions of a first instruction type and a second instruction type, decoding the different types of computer instructions, generating corresponding operation tasks, and issuing and executing the operation tasks. The present invention adopts instruction pipeline fusion for the two different types of instructions. The pipeline fusion enables the two different instructions to run on the same pipeline, thus ensuring that single-core hardware can mixedly process the two instructions on the same pipeline, saving hardware resources, and reducing the hardware cost required by the system; and at the same time, enabling the system to have the advantages of both fast instruction processing speed for the first instruction type and high efficiency for instruction processing for the second instruction type. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the composition of a system for processing different instructions on the same pipeline provided by the present application;

[0019] Figure 2 This is a schematic diagram of the composition of a system for processing different instructions on the same pipeline provided by the present application;

[0020] Figure 3 This is a pipeline diagram of a system that processes different instructions on the same pipeline provided by this application. Figure 1 ;

[0021] Figure 4 This is a pipeline diagram of a system that processes different instructions on the same pipeline provided by this application. Figure 2 ;

[0022] Figure 5 This is a flowchart of a method for processing different instructions on the same pipeline provided by this application. DETAILED DESCRIPTION

[0023] To facilitate understanding of the present invention, the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present invention.

[0024] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification are intended solely for the purpose of describing specific embodiments and are not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0025] like Figure 1 、 Figure 2 As shown, the present invention provides a system for processing different instructions on the same pipeline, including: a control unit 2 and an arithmetic unit 3. The control unit 2 is electrically connected to the arithmetic unit 3. The control unit 2 includes an instruction acquisition subunit 21, an instruction judgment subunit 22, an instruction register 23, an instruction decoder 24, and a pipeline management subunit 25; the instruction register 23 includes a first instruction register 231 and a second instruction register 232.

[0026] The instruction acquisition subunit 21 is used to acquire computer instructions to be executed. The encoding length and encoding rules of different types of computer instructions are the same, and the same encoding position of different types of computer instructions all contain an instruction category identifier. The instruction judgment subunit 22 is used to determine the type of the acquired computer instruction based on the instruction category identifier. If the computer instruction type is the first instruction type, the computer instruction is stored in the first instruction register 231; if the computer instruction type is the second instruction type, the computer instruction is stored in the second instruction register 232. The instruction decoder 24 is used to decode the different types of computer instructions in the first instruction register 231 and the second instruction register 232 respectively, and generate corresponding operation tasks. The pipeline management subunit 25 is used to send the operation tasks corresponding to the computer instructions to the operation unit 3. The operation unit 3 is used to execute the operation tasks.

[0027] The present invention adopts the fusion of instruction pipelines for two different types of instructions. The pipeline fusion enables the two different instructions to run on the same pipeline, which ensures that the single-core hardware can mix and process the two instructions on the same pipeline, saves hardware resources, and reduces the hardware cost required for the system; at the same time, it enables the system to have the advantages of fast instruction processing speed for the first instruction type and high instruction processing efficiency for the second instruction type.

[0028] The following combination Figures 1 to 5 , this application is described in detail with specific embodiments.

[0029] Figure 1 A schematic diagram of the system for processing different instructions on the same pipeline provided by an embodiment of the present application is shown, including: a control unit 2, an operation unit 3, and a storage unit 1. The control unit 2 is electrically connected to the operation unit 3 and the storage unit 1, respectively, and the operation unit 3 is also electrically connected to the storage unit 1.

[0030] The control unit 2 is the command and control center of the system, responsible for coordinating and controlling the execution of computer instructions by various computer components. Its basic functions are to retrieve, analyze, and execute computer instructions. The arithmetic unit 3 is the functional component in the system that processes data. Data processing primarily includes arithmetic operations on data and logical operations on logical data. Therefore, performing arithmetic and logical operations on data is the core function of the arithmetic unit 3. The storage unit 1 is used to temporarily store the execution data generated by the arithmetic unit 3 when performing operational tasks (i.e., processing data). This execution data includes intermediate operation data and operation results.

[0031] In this embodiment, the types of computer instructions include a first instruction type and a second instruction type. The first instruction type includes a RISC-V instruction type. RISC-V is the fifth generation RISC (Reduced Instruction Set Computer), which is an open source instruction set architecture developed based on the reduced instruction set principle. The second instruction type includes a DSP (digital signal processor) instruction type.

[0032] DSP instructions have a fixed-length and fixed-cycle characteristic: DSP instructions are typically fixed-length, meaning each computer instruction occupies the same number of bits. This design helps simplify the decoding and execution of computer instructions, thereby improving system efficiency and performance. With fixed-length instructions, the system can execute digital signal processing tasks more quickly, meet real-time requirements, and provide efficient performance. In many cases, the system executes DSP instructions at a fixed speed, meaning they execute one DSP instruction per machine cycle. This design facilitates real-time digital signal processing because timing can be precisely controlled, ensuring that the system processes input data and generates output on time. This fixed-cycle execution method is important for many digital signal processing tasks, as they often need to complete processing tasks within given time constraints.

[0033] RISC-V instructions also have the characteristics of fixed length and fixed cycle: RISC-V instructions are also fixed length, and the number of bits occupied by each computer instruction is the same.

[0034] DSP instructions, like RISC-V instructions, have fixed length and fixed cycle, so through pipeline fusion, one pipeline can support the processing of both DSP instructions and RISC instructions.

[0035] Further, such as Figure 2 As shown, the control unit 2 includes an instruction acquisition subunit 21, an instruction judgment subunit 22, an instruction register 23, an instruction decoder 24 and a pipeline management subunit 25; the instruction register 23 includes a first instruction register 231 and a second instruction register 232.

[0036] Specific, combined Figure 1 The instruction acquisition subunit 21 is used to acquire computer instructions to be executed. The encoding length and encoding rules of different types of computer instructions are the same, and the same encoding position of different types of computer instructions contains an instruction category identifier.

[0037] In this embodiment, before obtaining computer instructions, the two different types of computer instructions are binary-encoded and fused. This involves maintaining the length and encoding rules of RISC-V instructions while compressing the DSP instructions into 32-bit fixed-length instructions. Instruction category identifiers are placed at the same encoding position in the computer instructions to distinguish the types of computer instructions. The same encoding position can be either the first or last two digits of the computer instruction. Based on these two digits, it is possible to determine whether the computer instruction is a RISC-V instruction or a DSP instruction, thereby proceeding to the next step.

[0038] The computer instructions are encoded and fused so that two different types of computer instructions can use 32-bit fixed-length encoding and support the same decoding method. Therefore, the system can decode the two different types of computer instructions in a unified manner, further enabling the system to mix and process two different computer instructions on the same pipeline.

[0039] Furthermore, the instruction judgment subunit 22 is used to judge the type of the acquired computer instruction based on the instruction category identifier. If the type of the computer instruction is the first instruction type, the computer instruction is saved in the first instruction register 231; if the type of the computer instruction is the second instruction type, the computer instruction is saved in the second instruction register 232.

[0040] In this embodiment, the computer instruction type is determined to be a RISC-V instruction type or a DSP instruction type based on the two-bit instruction category identifier set for the computer instruction. If the computer instruction type is a RISC-V instruction type, the RISC-V instructions are saved one by one in the first instruction register 231. If the computer instruction type is a DSP instruction type, the instruction determination subunit 22 is further configured to determine the execution mode of multiple DSP instructions based on the functions and encoding rules of the DSP instructions, and to combine multiple DSP instructions that can be executed in parallel into a combined instruction, which is then stored in the same row of the second instruction register 232.

[0041] Among them, the first instruction register 231 is a 32-bit general instruction register, and each row can store one RISC-V instruction or DSP instruction; the second instruction register 232 is a 64-128-bit DSP instruction register, and each row can store multiple DSP instructions.

[0042] Furthermore, the instruction decoder 24 is used to decode different types of computer instructions in the first instruction register 231 and the second instruction register 232 respectively, and generate corresponding operation tasks.

[0043] Specifically, when the instruction decoder 24 decodes a computer instruction in the first instruction register 231, it reads a computer instruction, identifies the operation information contained in the computer instruction, and generates a corresponding operation task based on the operation information. When the instruction decoder 24 decodes a computer instruction in the second instruction register 232, it reads a combined instruction, splits the combined instruction into multiple second sub-instructions, identifies the operation information contained in each of the multiple second sub-instructions, and generates multiple corresponding operation tasks based on the operation information.

[0044] In this embodiment, when the instruction decoder 24 decodes a RISC-V instruction in the general instruction register, it reads a RISC-V instruction, identifies the operation information contained in the RISC-V instruction, generates a corresponding operation task based on the operation information, and assigns the RISC-V instruction and its operation task to the pipeline management subunit 25. When the instruction decoder 24 decodes a DSP instruction in the DSP instruction register, it reads a DSP combination instruction, splits the DSP combination instruction into multiple DSP sub-instructions, identifies the operation information contained in each of the multiple DSP sub-instructions, generates multiple corresponding operation tasks based on the operation information, and assigns the multiple DSP sub-instructions and their operation tasks to the pipeline management subunit 25.

[0045] Among them, the operation information includes the instruction category identifier, operation code, operand and / or immediate value. The operation code is the instruction sequence number, which is used to tell the system which computer instruction needs to be executed. Each computer instruction has an operation code, which indicates the nature of the operation that the computer instruction should perform. The operand is the entity on which the operator acts and is a component of the expression. It specifies the amount of digital calculation performed in the computer instruction. The operand indicates the source of the data required for the operation performed by the computer instruction. The immediate value usually refers to the number given in the immediate addressing mode instruction, which can be 8 bits, 16 bits or 32 bits. The value follows the operation code.

[0046] Furthermore, the pipeline management subunit 25 is used to send the operation task corresponding to the computer instruction to the operation unit 3.

[0047] Specifically, the pipeline management subunit 25 sends the operation task generated according to the computer instruction in the first instruction register 231 to the operation unit 3, and the operation task is executed serially in the operation unit 3. The pipeline management subunit 25 sends multiple operation tasks generated according to the combined instruction in the second instruction register 232 to the operation unit 3 respectively, and the multiple operation tasks are executed in parallel in the operation unit 3.

[0048] In this embodiment, the pipeline management subunit 25 sends a single RISC-V instruction and its operation task to the operation unit 3, which is executed step by step in the operation unit 3; and sends multiple DSP sub-instructions and their operation tasks to the operation unit 3, which are executed in parallel in the operation unit 3.

[0049] Further, such as Figure 2As shown, the operation unit 3 includes: a load-store unit 31 (LSU: Load-Store Unit), which is used to perform the operation tasks of loading and / or storing computer instructions; a multiply-accumulate unit 32 (MAC: Multiply-Accumulate), which is used to perform the operation tasks of multiplication and / or accumulation operations of computer instructions; an accumulator register unit 33 (ARU: Accumulator Register Unit), which is used to perform the operation tasks of accumulation operations of computer instructions; an arithmetic and logic unit 34 (ALU: Arithmetic and Logic Unit), which is used to perform the operation tasks of arithmetic and / or logic operations of computer instructions; a digital signal processing operation subunit 35 (DSP operation subunit), which is used to perform the operation tasks of digital signal processing operations of computer instructions; an accumulator register 36 (ACC: Accumulator register), which is used to store operands and / or operation results of arithmetic or logical operations; and a multiple-quotient register 37 (MQ: Multiple-Quotient Register), which is used to store operands and / or operation results of multiplication or division operations. In some other optional embodiments of the present application, the operation unit 3 includes at least one of the above sub-units.

[0050] In this embodiment, different components within the arithmetic unit 3 can simultaneously execute the operations of multiple DSP sub-instructions, while the operations of a single RISC-V instruction are executed by their corresponding components. After executing an operation task, the arithmetic unit 3 synchronizes the execution status of the operation task to the pipeline management sub-unit 25, interacts with the storage unit 1, and stores the generated execution data (intermediate operation data and operation results) in the storage unit 1.

[0051] Further, such as Figure 2 As shown, the storage unit 1 includes: a first instruction storage unit 11, used to store computer instructions of the first instruction type and / or their corresponding execution data; a second instruction storage unit 12, used to store computer instructions of the second instruction type and / or their corresponding execution data.

[0052] The second instruction storage unit 12 includes multiple second instruction storage subunits 121, each of which includes independent data entry and exit, allowing the operation unit 3 to use the corresponding second instruction storage subunit 121 simultaneously when executing different operation tasks synchronously.

[0053] In this embodiment, the first instruction storage unit 11 is a RISC-V register or a RISC-V memory, the second instruction storage unit 12 is a DSP register or a DSP memory, and the multiple second instruction storage sub-units 121 are multiple DSP register blocks or multiple DSP memory blocks. Each second instruction storage sub-unit 121 has a separate port. When in use, different components in the operation unit 3 can simultaneously call the corresponding second instruction storage sub-unit 121 through the corresponding port to complete the operation task synchronously, thereby ensuring the synchronous execution of the operation tasks of multiple DSP sub-instructions and improving the overall efficiency.

[0054] Further, such as Figure 3 As shown, in this embodiment, two different computer instructions are processed through the same eight-stage pipeline. The eight-stage pipeline is as follows: F1 fetches the instruction address, F2 fetches the instruction content, D decodes the instruction, R1 fetches the operand address, R2 fetches the operand, E1 executes the first instruction, E2 executes the second instruction, and Wb writes back.

[0055] In order to have a deeper understanding of the present invention, the following describes in detail the execution methods of two different types of computer instructions with reference to two specific examples.

[0056] Combine Figures 1 to 3 When the computer instruction is a RISC instruction, the corresponding operation task is executed serially on the eight-stage pipeline. The specific process of executing RISC-V instructions at each stage of the pipeline is as follows:

[0057] First level, F1 fetches instruction address: fetches a computer instruction address.

[0058] The second level, F2 fetches the instruction content: reads a 32-bit computer instruction according to the computer instruction address, and determines that the computer instruction is a RISC-V instruction based on the two-bit instruction category identifier, and saves the RISC-V instruction into the 32-bit general instruction register.

[0059] The third level, D instruction decoding: reads a RISC-V instruction from the 32-bit general instruction register, then directly decodes it, identifies the operation information contained in the RISC-V instruction, generates the corresponding operation task based on the operation information, and then sends the operation task to the next level of the pipeline (that is, R1 takes the operand address).

[0060] The fourth level, R1 takes the operand address: the operand address is taken out according to the source register address contained in the RISC-V instruction.

[0061] Level 5, R2 takes operands: takes out the operands according to the operand address and saves them to RISC-V registers or RISC-V memory.

[0062] The sixth stage, E1 first execution: executes the operation passed from the fifth stage of the pipeline, which can also be the operation distributed from the third stage of the pipeline.

[0063] The seventh stage, E2 second execution: executes the calculation operations passed from the sixth stage of the pipeline, which can also be the calculation operations distributed from the third stage of the pipeline.

[0064] Level 8, Wb write back: write the execution data back to the RISC-V register or RISC-V memory.

[0065] For each RISC-V instruction, the above eight-stage pipeline is executed sequentially.

[0066] Combine Figures 1 to 4 When the computer instruction is a DSP instruction, multiple operation tasks corresponding to multiple DSP sub-instructions are executed in parallel on the eight-stage pipeline. The specific process of executing DSP instructions at each stage of the pipeline is as follows:

[0067] First level, F1 fetches instruction address: fetches a computer instruction address.

[0068] In the second stage, F2 fetches the instruction content: it reads the 32-bit computer instruction according to the computer instruction address, and determines that the computer instruction is a DSP instruction based on the two-bit instruction category identifier. It then determines the execution modes of multiple DSP instructions respectively, and combines multiple DSP instructions that can be executed in parallel into a combined instruction, which is then stored in the same row of the second instruction register 232.

[0069] The third stage, D instruction decoding: reads a combined instruction from the 64-128-bit DSP instruction register, splits the combined instruction into multiple DSP sub-instructions, identifies the operation information contained in each of the multiple DSP sub-instructions, and generates multiple corresponding operation tasks based on this operation information. These operation tasks are simultaneously sent to the pipeline management sub-unit 25. The pipeline management sub-unit 25 synchronously sends these operation tasks to the corresponding different components of the operation unit 3 (for example, sending a load operation task to the fourth stage of the pipeline to be executed by the load-store sub-unit 31 in the operation unit 3; sending an addition operation task to the sixth stage of the pipeline to be executed by the multiplication-addition sub-unit 32 in the operation unit 3; sending a storage operation task to the seventh stage of the pipeline to be executed by the accumulation register 36 sub-unit in the operation unit 3).

[0070] The fourth stage, R1 takes the operand address: takes out the operand address according to the source register address contained in multiple DSP sub-instructions, and executes the load operation task distributed by the third stage of the pipeline.

[0071] The fifth stage, R2 takes the operand: executes the operation task sent by the third or fourth stage of the pipeline, and takes out the operand according to the operand address.

[0072] The sixth stage, E1 first execution: executes the addition operation task sent by the third stage of the pipeline, or the operation task sent by the fifth stage of the pipeline.

[0073] The seventh level, E2 second execution: executes the storage operation task sent by the third level of the pipeline, or the operation task sent by the sixth level of the pipeline.

[0074] Level 8, Wb write back: writes the execution data back to the DSP register or DSP memory, or executes the operation task passed from the seventh level of the pipeline.

[0075] The fourth to eighth levels correspond to multiple components in the arithmetic unit 3. To avoid conflicts such as data reading and writing, different components use different DSP register blocks or DSP memory blocks and their corresponding ports when executing a group of DSP operation tasks at the same time.

[0076] In summary, the system can execute two different computer instructions separately through the same pipeline, supporting the processing of both RISC-V and DSP instructions simultaneously through single-core hardware. This ensures the parallel processing of multiple DSP instruction operations while also enabling the rapid execution of individual RISC-V instructions. Through the integration of instruction set pipelines, the system combines the advantages of high efficiency and high speed in computer instruction processing while also conserving hardware resources and reducing system costs.

[0077] Corresponding to the system of the above embodiment for processing different instructions on the same pipeline, Figure 5 A flow chart of a method for processing different instructions on the same pipeline provided by an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0078] refer to Figure 5 , the method comprises the steps of:

[0079] S1: Obtain computer instructions to be executed. The encoding lengths and encoding rules of different types of computer instructions are the same, and the same encoding positions of different types of computer instructions all contain instruction category identifiers.

[0080] S2: Determine the type of the acquired computer instruction according to the instruction category identifier.

[0081] S3: After saving and reading computer instructions of the first instruction type and the second instruction type respectively, different types of computer instructions are decoded, and corresponding operation tasks are generated, and the operation tasks are issued and executed.

[0082] Among them, computer instructions are processed through an eight-stage pipeline, which is as follows: F1 fetches the instruction address, F2 fetches the instruction content, D decodes the instruction, R1 fetches the operand address, R2 fetches the operand, E1 first execution, E2 second execution and Wb writes back.

[0083] In S3, if the type of the computer instruction is the first instruction type, the computer instruction is decoded, the operation information contained in the computer instruction is identified, and a corresponding operation task is generated according to the operation information. After the operation task is issued, it is executed serially and the execution status is synchronized; if the type of the computer instruction is the second instruction type, multiple computer instructions that can be executed in parallel are combined into a combined instruction and saved in the same line; a combined instruction is read, and the combined instruction is split into multiple second sub-instructions, the multiple second sub-instructions are decoded, the operation information contained in each second sub-instruction is identified respectively, and multiple corresponding operation tasks are generated according to the operation information. After the multiple operation tasks are issued, they are executed in parallel respectively, and the execution status is synchronized.

[0084] It should be noted that the above-mentioned method of processing different instructions on the same pipeline is based on the same concept as the system of processing different instructions on the same pipeline in the present application. For details, please refer to the description of the embodiment shown in the above-mentioned system for processing different instructions on the same pipeline, and no further details will be given here.

[0085] Thus, the present invention discloses a system and method for processing different instructions on the same pipeline. The system includes: a control unit and an operation unit, the control unit being electrically connected to the operation unit; the control unit including an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder, and a pipeline management subunit; the instruction register including a first instruction register and a second instruction register; the instruction acquisition subunit is used to acquire computer instructions to be executed, the encoding length and encoding rules of different types of computer instructions are the same, and the same encoding position of different types of computer instructions all contains an instruction category identifier; the instruction judgment subunit is used to determine the type of the acquired computer instruction based on the instruction category identifier, if the type of the computer instruction is the first instruction type, the computer instruction is stored in the first instruction register, if the type of the computer instruction is the second instruction type, the computer instruction is stored in the second instruction register; the instruction decoder is used to decode different types of computer instructions in the first instruction register and the second instruction register respectively, and generate corresponding operation tasks; the pipeline management subunit is used to send the operation tasks corresponding to the computer instructions to the operation unit; the operation unit is used to execute the operation tasks. The method includes the following steps: obtaining computer instructions to be executed, wherein the encoding lengths and encoding rules of different types of computer instructions are the same, and the same encoding positions of different types of computer instructions all contain instruction category identifiers; judging the type of the obtained computer instructions based on the instruction category identifiers; after respectively saving and reading computer instructions of a first instruction type and a second instruction type, decoding the different types of computer instructions, generating corresponding operation tasks, and issuing and executing the operation tasks. The present invention adopts instruction pipeline fusion for the two different types of instructions. The pipeline fusion enables the two different instructions to run on the same pipeline, thus ensuring that single-core hardware can mixedly process the two instructions on the same pipeline, saving hardware resources, and reducing the hardware cost required by the system; and at the same time, enabling the system to have the advantages of both fast instruction processing speed for the first instruction type and high efficiency for instruction processing for the second instruction type.

[0086] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied to other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A system for processing different instructions on the same pipeline, characterized in that: include: a control unit and an arithmetic unit, wherein the control unit is electrically connected to the arithmetic unit; The control unit includes an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction register includes a first instruction register and a second instruction register; The instruction acquisition subunit is used to acquire computer instructions to be executed, the encoding length and encoding rules of different types of computer instructions are the same, and the same encoding position of different types of computer instructions contains an instruction category identifier; The instruction determination subunit is configured to determine a type of the acquired computer instruction according to the instruction category identifier, and if the type of the computer instruction is a first instruction type, store the computer instruction in the first instruction register; if the type of the computer instruction is a second instruction type, store the computer instruction in the second instruction register; The instruction decoder is used to decode different types of computer instructions in the first instruction register and the second instruction register respectively, and generate corresponding operation tasks; The pipeline management subunit is used to send the operation task corresponding to the computer instruction to the computing unit; The computing unit is used to execute the operation task.

2. The system for processing different instructions on the same pipeline according to claim 1, characterized in that: The first instruction type includes a RISC-V instruction type, and the second instruction type includes a DSP instruction type.

3. The system for processing different instructions on the same pipeline according to claim 1, characterized in that: If the type of the computer instruction is the second instruction type, the instruction judgment subunit is also used to judge the execution method of the computer instruction based on the function of the computer instruction and the binary encoding rules, and combine multiple computer instructions that can be executed in parallel into a combined instruction and save them in the same row in the second instruction register.

4. The system for processing different instructions on the same pipeline according to claim 3, characterized in that: When the instruction decoder decodes the computer instruction in the first instruction register, it reads one of the computer instructions, identifies the operation information contained in the computer instruction, and generates the corresponding operation task according to the operation information; When decoding the computer instruction in the second instruction register, the instruction decoder reads one of the combined instructions, splits the combined instruction into a plurality of second sub-instructions, identifies operation information contained in each of the plurality of second sub-instructions, and generates a plurality of corresponding operation tasks according to the operation information; The operation information includes an instruction type identifier, an operation code, an operand and / or an immediate value.

5. The system for processing different instructions on the same pipeline according to claim 4, characterized in that: The pipeline management subunit sends the operation task generated according to the computer instruction in the first instruction register to the operation unit, and the operation task is executed serially in the operation unit; The pipeline management subunit sends the multiple operation tasks generated according to the combined instruction in the second instruction register to the operation unit respectively, and the multiple operation tasks are executed in parallel in the operation unit.

6. The system for processing different instructions on the same pipeline according to claim 1, wherein: The computing unit includes at least one of the following subunits: A load-store subunit, configured to execute the operation tasks of loading and / or storing the computer instructions; a multiplication-accumulation subunit, configured to perform the multiplication and / or accumulation operations of the computer instructions; an accumulation register subunit, configured to perform the accumulation operation of the computer instruction; an arithmetic logic subunit, configured to perform the arithmetic and / or logical operations of the computer instructions; A digital signal processing operation subunit, configured to execute the digital signal processing operation task of the computer instruction; Accumulator register, used to store operands and / or results of arithmetic or logical operations; The multiplication and quotient register is used to store the operands and / or the results of multiplication or division operations.

7. The system for processing different instructions on the same pipeline according to claim 1, wherein: It also includes a storage unit, which is electrically connected to the control unit and the operation unit respectively, and is used to temporarily store execution data generated when the operation unit performs the operation task, and the storage unit includes: A first instruction storage unit, configured to store the computer instructions of a first instruction type and / or their corresponding execution data; A second instruction storage unit, configured to store the computer instructions of a second instruction type and / or their corresponding execution data; The second instruction storage unit includes a plurality of second instruction storage sub-units, and each second instruction storage sub-unit includes an independent data entry and exit to allow the operation unit to use the corresponding second instruction storage sub-unit simultaneously when executing different operation tasks synchronously.

8. A method for processing different instructions on the same pipeline, characterized in that: Including steps: Obtaining computer instructions to be executed, wherein the encoding length and encoding rules of different types of computer instructions are the same, and the same encoding position of the different types of computer instructions contains an instruction category identifier; Determining the type of the acquired computer instruction according to the instruction category identifier; After the computer instructions of the first instruction type and the second instruction type are saved and read respectively, the computer instructions of different types are decoded, and corresponding operation tasks are generated, and the operation tasks are executed after being issued.

9. The method for processing different instructions on the same pipeline according to claim 8, wherein: The computer instructions are processed through an eight-stage pipeline, which is: F1 fetches instruction address, F2 fetches instruction content, D instruction decoding, R1 fetches operand address, R2 fetches operand, E1 first execution, E2 second execution and Wb write back.

10. The method for processing different instructions on the same pipeline according to claim 9, characterized in that: If the type of the computer instruction is the first instruction type, decoding the computer instruction, identifying the operation information contained in the computer instruction, generating a corresponding operation task according to the operation information, issuing the operation task and executing it serially, and synchronizing the execution status; If the type of the computer instruction is the second instruction type, multiple computer instructions that can be executed in parallel are combined into a combined instruction and saved in the same line; read one combined instruction, and split the combined instruction into multiple second sub-instructions, decode the multiple second sub-instructions, identify the operation information contained in each second sub-instruction respectively, and generate multiple corresponding operation tasks according to the operation information, and execute the multiple operation tasks in parallel after issuing them, and synchronize the execution status.

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